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1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
28 */
29#include <linux/i2c.h>
30#include <linux/i2c-algo-bit.h>
31#include <linux/export.h>
32#include <drm/drmP.h>
33#include <drm/drm_hdcp.h>
34#include "intel_drv.h"
35#include <drm/i915_drm.h>
36#include "i915_drv.h"
37
38struct gmbus_pin {
39 const char *name;
40 i915_reg_t reg;
41};
42
43/* Map gmbus pin pairs to names and registers. */
44static const struct gmbus_pin gmbus_pins[] = {
45 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
46 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
47 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
48 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
49 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
50 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
51};
52
53static const struct gmbus_pin gmbus_pins_bdw[] = {
54 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
55 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
56 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
57 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
58};
59
60static const struct gmbus_pin gmbus_pins_skl[] = {
61 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
62 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
63 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
64};
65
66static const struct gmbus_pin gmbus_pins_bxt[] = {
67 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
68 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
69 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
70};
71
72static const struct gmbus_pin gmbus_pins_cnp[] = {
73 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
74 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
75 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
76 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
77};
78
79static const struct gmbus_pin gmbus_pins_icp[] = {
80 [GMBUS_PIN_1_BXT] = { "dpa", GPIOA },
81 [GMBUS_PIN_2_BXT] = { "dpb", GPIOB },
82 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOC },
83 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOD },
84 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOE },
85 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOF },
86};
87
88/* pin is expected to be valid */
89static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
90 unsigned int pin)
91{
92 if (HAS_PCH_ICP(dev_priv))
93 return &gmbus_pins_icp[pin];
94 else if (HAS_PCH_CNP(dev_priv))
95 return &gmbus_pins_cnp[pin];
96 else if (IS_GEN9_LP(dev_priv))
97 return &gmbus_pins_bxt[pin];
98 else if (IS_GEN9_BC(dev_priv))
99 return &gmbus_pins_skl[pin];
100 else if (IS_BROADWELL(dev_priv))
101 return &gmbus_pins_bdw[pin];
102 else
103 return &gmbus_pins[pin];
104}
105
106bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
107 unsigned int pin)
108{
109 unsigned int size;
110
111 if (HAS_PCH_ICP(dev_priv))
112 size = ARRAY_SIZE(gmbus_pins_icp);
113 else if (HAS_PCH_CNP(dev_priv))
114 size = ARRAY_SIZE(gmbus_pins_cnp);
115 else if (IS_GEN9_LP(dev_priv))
116 size = ARRAY_SIZE(gmbus_pins_bxt);
117 else if (IS_GEN9_BC(dev_priv))
118 size = ARRAY_SIZE(gmbus_pins_skl);
119 else if (IS_BROADWELL(dev_priv))
120 size = ARRAY_SIZE(gmbus_pins_bdw);
121 else
122 size = ARRAY_SIZE(gmbus_pins);
123
124 return pin < size &&
125 i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
126}
127
128/* Intel GPIO access functions */
129
130#define I2C_RISEFALL_TIME 10
131
132static inline struct intel_gmbus *
133to_intel_gmbus(struct i2c_adapter *i2c)
134{
135 return container_of(i2c, struct intel_gmbus, adapter);
136}
137
138void
139intel_i2c_reset(struct drm_i915_private *dev_priv)
140{
141 I915_WRITE(GMBUS0, 0);
142 I915_WRITE(GMBUS4, 0);
143}
144
145static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
146 bool enable)
147{
148 u32 val;
149
150 /* When using bit bashing for I2C, this bit needs to be set to 1 */
151 val = I915_READ(DSPCLK_GATE_D);
152 if (!enable)
153 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
154 else
155 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
156 I915_WRITE(DSPCLK_GATE_D, val);
157}
158
159static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
160 bool enable)
161{
162 u32 val;
163
164 val = I915_READ(SOUTH_DSPCLK_GATE_D);
165 if (!enable)
166 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
167 else
168 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
169 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
170}
171
172static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
173 bool enable)
174{
175 u32 val;
176
177 val = I915_READ(GEN9_CLKGATE_DIS_4);
178 if (!enable)
179 val |= BXT_GMBUS_GATING_DIS;
180 else
181 val &= ~BXT_GMBUS_GATING_DIS;
182 I915_WRITE(GEN9_CLKGATE_DIS_4, val);
183}
184
185static u32 get_reserved(struct intel_gmbus *bus)
186{
187 struct drm_i915_private *dev_priv = bus->dev_priv;
188 u32 reserved = 0;
189
190 /* On most chips, these bits must be preserved in software. */
191 if (!IS_I830(dev_priv) && !IS_I845G(dev_priv))
192 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
193 (GPIO_DATA_PULLUP_DISABLE |
194 GPIO_CLOCK_PULLUP_DISABLE);
195
196 return reserved;
197}
198
199static int get_clock(void *data)
200{
201 struct intel_gmbus *bus = data;
202 struct drm_i915_private *dev_priv = bus->dev_priv;
203 u32 reserved = get_reserved(bus);
204 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
205 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
206 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
207}
208
209static int get_data(void *data)
210{
211 struct intel_gmbus *bus = data;
212 struct drm_i915_private *dev_priv = bus->dev_priv;
213 u32 reserved = get_reserved(bus);
214 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
215 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
216 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
217}
218
219static void set_clock(void *data, int state_high)
220{
221 struct intel_gmbus *bus = data;
222 struct drm_i915_private *dev_priv = bus->dev_priv;
223 u32 reserved = get_reserved(bus);
224 u32 clock_bits;
225
226 if (state_high)
227 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
228 else
229 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
230 GPIO_CLOCK_VAL_MASK;
231
232 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
233 POSTING_READ(bus->gpio_reg);
234}
235
236static void set_data(void *data, int state_high)
237{
238 struct intel_gmbus *bus = data;
239 struct drm_i915_private *dev_priv = bus->dev_priv;
240 u32 reserved = get_reserved(bus);
241 u32 data_bits;
242
243 if (state_high)
244 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
245 else
246 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
247 GPIO_DATA_VAL_MASK;
248
249 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
250 POSTING_READ(bus->gpio_reg);
251}
252
253static int
254intel_gpio_pre_xfer(struct i2c_adapter *adapter)
255{
256 struct intel_gmbus *bus = container_of(adapter,
257 struct intel_gmbus,
258 adapter);
259 struct drm_i915_private *dev_priv = bus->dev_priv;
260
261 intel_i2c_reset(dev_priv);
262
263 if (IS_PINEVIEW(dev_priv))
264 pnv_gmbus_clock_gating(dev_priv, false);
265
266 set_data(bus, 1);
267 set_clock(bus, 1);
268 udelay(I2C_RISEFALL_TIME);
269 return 0;
270}
271
272static void
273intel_gpio_post_xfer(struct i2c_adapter *adapter)
274{
275 struct intel_gmbus *bus = container_of(adapter,
276 struct intel_gmbus,
277 adapter);
278 struct drm_i915_private *dev_priv = bus->dev_priv;
279
280 set_data(bus, 1);
281 set_clock(bus, 1);
282
283 if (IS_PINEVIEW(dev_priv))
284 pnv_gmbus_clock_gating(dev_priv, true);
285}
286
287static void
288intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
289{
290 struct drm_i915_private *dev_priv = bus->dev_priv;
291 struct i2c_algo_bit_data *algo;
292
293 algo = &bus->bit_algo;
294
295 bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
296 i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
297 bus->adapter.algo_data = algo;
298 algo->setsda = set_data;
299 algo->setscl = set_clock;
300 algo->getsda = get_data;
301 algo->getscl = get_clock;
302 algo->pre_xfer = intel_gpio_pre_xfer;
303 algo->post_xfer = intel_gpio_post_xfer;
304 algo->udelay = I2C_RISEFALL_TIME;
305 algo->timeout = usecs_to_jiffies(2200);
306 algo->data = bus;
307}
308
309static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
310{
311 DEFINE_WAIT(wait);
312 u32 gmbus2;
313 int ret;
314
315 /* Important: The hw handles only the first bit, so set only one! Since
316 * we also need to check for NAKs besides the hw ready/idle signal, we
317 * need to wake up periodically and check that ourselves.
318 */
319 if (!HAS_GMBUS_IRQ(dev_priv))
320 irq_en = 0;
321
322 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
323 I915_WRITE_FW(GMBUS4, irq_en);
324
325 status |= GMBUS_SATOER;
326 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);
327 if (ret)
328 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);
329
330 I915_WRITE_FW(GMBUS4, 0);
331 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
332
333 if (gmbus2 & GMBUS_SATOER)
334 return -ENXIO;
335
336 return ret;
337}
338
339static int
340gmbus_wait_idle(struct drm_i915_private *dev_priv)
341{
342 DEFINE_WAIT(wait);
343 u32 irq_enable;
344 int ret;
345
346 /* Important: The hw handles only the first bit, so set only one! */
347 irq_enable = 0;
348 if (HAS_GMBUS_IRQ(dev_priv))
349 irq_enable = GMBUS_IDLE_EN;
350
351 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
352 I915_WRITE_FW(GMBUS4, irq_enable);
353
354 ret = intel_wait_for_register_fw(dev_priv,
355 GMBUS2, GMBUS_ACTIVE, 0,
356 10);
357
358 I915_WRITE_FW(GMBUS4, 0);
359 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
360
361 return ret;
362}
363
364static int
365gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
366 unsigned short addr, u8 *buf, unsigned int len,
367 u32 gmbus1_index)
368{
369 I915_WRITE_FW(GMBUS1,
370 gmbus1_index |
371 GMBUS_CYCLE_WAIT |
372 (len << GMBUS_BYTE_COUNT_SHIFT) |
373 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
374 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
375 while (len) {
376 int ret;
377 u32 val, loop = 0;
378
379 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
380 if (ret)
381 return ret;
382
383 val = I915_READ_FW(GMBUS3);
384 do {
385 *buf++ = val & 0xff;
386 val >>= 8;
387 } while (--len && ++loop < 4);
388 }
389
390 return 0;
391}
392
393static int
394gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
395 u32 gmbus1_index)
396{
397 u8 *buf = msg->buf;
398 unsigned int rx_size = msg->len;
399 unsigned int len;
400 int ret;
401
402 do {
403 len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
404
405 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
406 buf, len, gmbus1_index);
407 if (ret)
408 return ret;
409
410 rx_size -= len;
411 buf += len;
412 } while (rx_size != 0);
413
414 return 0;
415}
416
417static int
418gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
419 unsigned short addr, u8 *buf, unsigned int len,
420 u32 gmbus1_index)
421{
422 unsigned int chunk_size = len;
423 u32 val, loop;
424
425 val = loop = 0;
426 while (len && loop < 4) {
427 val |= *buf++ << (8 * loop++);
428 len -= 1;
429 }
430
431 I915_WRITE_FW(GMBUS3, val);
432 I915_WRITE_FW(GMBUS1,
433 gmbus1_index | GMBUS_CYCLE_WAIT |
434 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
435 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
436 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
437 while (len) {
438 int ret;
439
440 val = loop = 0;
441 do {
442 val |= *buf++ << (8 * loop);
443 } while (--len && ++loop < 4);
444
445 I915_WRITE_FW(GMBUS3, val);
446
447 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
448 if (ret)
449 return ret;
450 }
451
452 return 0;
453}
454
455static int
456gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
457 u32 gmbus1_index)
458{
459 u8 *buf = msg->buf;
460 unsigned int tx_size = msg->len;
461 unsigned int len;
462 int ret;
463
464 do {
465 len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
466
467 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
468 gmbus1_index);
469 if (ret)
470 return ret;
471
472 buf += len;
473 tx_size -= len;
474 } while (tx_size != 0);
475
476 return 0;
477}
478
479/*
480 * The gmbus controller can combine a 1 or 2 byte write with another read/write
481 * that immediately follows it by using an "INDEX" cycle.
482 */
483static bool
484gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
485{
486 return (i + 1 < num &&
487 msgs[i].addr == msgs[i + 1].addr &&
488 !(msgs[i].flags & I2C_M_RD) &&
489 (msgs[i].len == 1 || msgs[i].len == 2) &&
490 msgs[i + 1].len > 0);
491}
492
493static int
494gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
495{
496 u32 gmbus1_index = 0;
497 u32 gmbus5 = 0;
498 int ret;
499
500 if (msgs[0].len == 2)
501 gmbus5 = GMBUS_2BYTE_INDEX_EN |
502 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
503 if (msgs[0].len == 1)
504 gmbus1_index = GMBUS_CYCLE_INDEX |
505 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
506
507 /* GMBUS5 holds 16-bit index */
508 if (gmbus5)
509 I915_WRITE_FW(GMBUS5, gmbus5);
510
511 if (msgs[1].flags & I2C_M_RD)
512 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
513 else
514 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
515
516 /* Clear GMBUS5 after each index transfer */
517 if (gmbus5)
518 I915_WRITE_FW(GMBUS5, 0);
519
520 return ret;
521}
522
523static int
524do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
525 u32 gmbus0_source)
526{
527 struct intel_gmbus *bus = container_of(adapter,
528 struct intel_gmbus,
529 adapter);
530 struct drm_i915_private *dev_priv = bus->dev_priv;
531 int i = 0, inc, try = 0;
532 int ret = 0;
533
534 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
535 if (IS_GEN9_LP(dev_priv))
536 bxt_gmbus_clock_gating(dev_priv, false);
537 else if (HAS_PCH_SPT(dev_priv) ||
538 HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
539 pch_gmbus_clock_gating(dev_priv, false);
540
541retry:
542 I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0);
543
544 for (; i < num; i += inc) {
545 inc = 1;
546 if (gmbus_is_index_xfer(msgs, i, num)) {
547 ret = gmbus_index_xfer(dev_priv, &msgs[i]);
548 inc = 2; /* an index transmission is two msgs */
549 } else if (msgs[i].flags & I2C_M_RD) {
550 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
551 } else {
552 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
553 }
554
555 if (!ret)
556 ret = gmbus_wait(dev_priv,
557 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
558 if (ret == -ETIMEDOUT)
559 goto timeout;
560 else if (ret)
561 goto clear_err;
562 }
563
564 /* Generate a STOP condition on the bus. Note that gmbus can't generata
565 * a STOP on the very first cycle. To simplify the code we
566 * unconditionally generate the STOP condition with an additional gmbus
567 * cycle. */
568 I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
569
570 /* Mark the GMBUS interface as disabled after waiting for idle.
571 * We will re-enable it at the start of the next xfer,
572 * till then let it sleep.
573 */
574 if (gmbus_wait_idle(dev_priv)) {
575 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
576 adapter->name);
577 ret = -ETIMEDOUT;
578 }
579 I915_WRITE_FW(GMBUS0, 0);
580 ret = ret ?: i;
581 goto out;
582
583clear_err:
584 /*
585 * Wait for bus to IDLE before clearing NAK.
586 * If we clear the NAK while bus is still active, then it will stay
587 * active and the next transaction may fail.
588 *
589 * If no ACK is received during the address phase of a transaction, the
590 * adapter must report -ENXIO. It is not clear what to return if no ACK
591 * is received at other times. But we have to be careful to not return
592 * spurious -ENXIO because that will prevent i2c and drm edid functions
593 * from retrying. So return -ENXIO only when gmbus properly quiescents -
594 * timing out seems to happen when there _is_ a ddc chip present, but
595 * it's slow responding and only answers on the 2nd retry.
596 */
597 ret = -ENXIO;
598 if (gmbus_wait_idle(dev_priv)) {
599 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
600 adapter->name);
601 ret = -ETIMEDOUT;
602 }
603
604 /* Toggle the Software Clear Interrupt bit. This has the effect
605 * of resetting the GMBUS controller and so clearing the
606 * BUS_ERROR raised by the slave's NAK.
607 */
608 I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
609 I915_WRITE_FW(GMBUS1, 0);
610 I915_WRITE_FW(GMBUS0, 0);
611
612 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
613 adapter->name, msgs[i].addr,
614 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
615
616 /*
617 * Passive adapters sometimes NAK the first probe. Retry the first
618 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
619 * has retries internally. See also the retry loop in
620 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
621 */
622 if (ret == -ENXIO && i == 0 && try++ == 0) {
623 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
624 adapter->name);
625 goto retry;
626 }
627
628 goto out;
629
630timeout:
631 DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
632 bus->adapter.name, bus->reg0 & 0xff);
633 I915_WRITE_FW(GMBUS0, 0);
634
635 /*
636 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
637 * instead. Use EAGAIN to have i2c core retry.
638 */
639 ret = -EAGAIN;
640
641out:
642 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
643 if (IS_GEN9_LP(dev_priv))
644 bxt_gmbus_clock_gating(dev_priv, true);
645 else if (HAS_PCH_SPT(dev_priv) ||
646 HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
647 pch_gmbus_clock_gating(dev_priv, true);
648
649 return ret;
650}
651
652static int
653gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
654{
655 struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus,
656 adapter);
657 struct drm_i915_private *dev_priv = bus->dev_priv;
658 int ret;
659
660 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
661
662 if (bus->force_bit) {
663 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
664 if (ret < 0)
665 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
666 } else {
667 ret = do_gmbus_xfer(adapter, msgs, num, 0);
668 if (ret == -EAGAIN)
669 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
670 }
671
672 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
673
674 return ret;
675}
676
677int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
678{
679 struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus,
680 adapter);
681 struct drm_i915_private *dev_priv = bus->dev_priv;
682 int ret;
683 u8 cmd = DRM_HDCP_DDC_AKSV;
684 u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
685 struct i2c_msg msgs[] = {
686 {
687 .addr = DRM_HDCP_DDC_ADDR,
688 .flags = 0,
689 .len = sizeof(cmd),
690 .buf = &cmd,
691 },
692 {
693 .addr = DRM_HDCP_DDC_ADDR,
694 .flags = 0,
695 .len = sizeof(buf),
696 .buf = buf,
697 }
698 };
699
700 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
701 mutex_lock(&dev_priv->gmbus_mutex);
702
703 /*
704 * In order to output Aksv to the receiver, use an indexed write to
705 * pass the i2c command, and tell GMBUS to use the HW-provided value
706 * instead of sourcing GMBUS3 for the data.
707 */
708 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
709
710 mutex_unlock(&dev_priv->gmbus_mutex);
711 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
712
713 return ret;
714}
715
716static u32 gmbus_func(struct i2c_adapter *adapter)
717{
718 return i2c_bit_algo.functionality(adapter) &
719 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
720 /* I2C_FUNC_10BIT_ADDR | */
721 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
722 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
723}
724
725static const struct i2c_algorithm gmbus_algorithm = {
726 .master_xfer = gmbus_xfer,
727 .functionality = gmbus_func
728};
729
730static void gmbus_lock_bus(struct i2c_adapter *adapter,
731 unsigned int flags)
732{
733 struct intel_gmbus *bus = to_intel_gmbus(adapter);
734 struct drm_i915_private *dev_priv = bus->dev_priv;
735
736 mutex_lock(&dev_priv->gmbus_mutex);
737}
738
739static int gmbus_trylock_bus(struct i2c_adapter *adapter,
740 unsigned int flags)
741{
742 struct intel_gmbus *bus = to_intel_gmbus(adapter);
743 struct drm_i915_private *dev_priv = bus->dev_priv;
744
745 return mutex_trylock(&dev_priv->gmbus_mutex);
746}
747
748static void gmbus_unlock_bus(struct i2c_adapter *adapter,
749 unsigned int flags)
750{
751 struct intel_gmbus *bus = to_intel_gmbus(adapter);
752 struct drm_i915_private *dev_priv = bus->dev_priv;
753
754 mutex_unlock(&dev_priv->gmbus_mutex);
755}
756
757static const struct i2c_lock_operations gmbus_lock_ops = {
758 .lock_bus = gmbus_lock_bus,
759 .trylock_bus = gmbus_trylock_bus,
760 .unlock_bus = gmbus_unlock_bus,
761};
762
763/**
764 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
765 * @dev_priv: i915 device private
766 */
767int intel_setup_gmbus(struct drm_i915_private *dev_priv)
768{
769 struct pci_dev *pdev = dev_priv->drm.pdev;
770 struct intel_gmbus *bus;
771 unsigned int pin;
772 int ret;
773
774 if (HAS_PCH_NOP(dev_priv))
775 return 0;
776
777 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
778 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
779 else if (!HAS_GMCH_DISPLAY(dev_priv))
780 dev_priv->gpio_mmio_base =
781 i915_mmio_reg_offset(PCH_GPIOA) -
782 i915_mmio_reg_offset(GPIOA);
783
784 mutex_init(&dev_priv->gmbus_mutex);
785 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
786
787 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
788 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
789 continue;
790
791 bus = &dev_priv->gmbus[pin];
792
793 bus->adapter.owner = THIS_MODULE;
794 bus->adapter.class = I2C_CLASS_DDC;
795 snprintf(bus->adapter.name,
796 sizeof(bus->adapter.name),
797 "i915 gmbus %s",
798 get_gmbus_pin(dev_priv, pin)->name);
799
800 bus->adapter.dev.parent = &pdev->dev;
801 bus->dev_priv = dev_priv;
802
803 bus->adapter.algo = &gmbus_algorithm;
804 bus->adapter.lock_ops = &gmbus_lock_ops;
805
806 /*
807 * We wish to retry with bit banging
808 * after a timed out GMBUS attempt.
809 */
810 bus->adapter.retries = 1;
811
812 /* By default use a conservative clock rate */
813 bus->reg0 = pin | GMBUS_RATE_100KHZ;
814
815 /* gmbus seems to be broken on i830 */
816 if (IS_I830(dev_priv))
817 bus->force_bit = 1;
818
819 intel_gpio_setup(bus, pin);
820
821 ret = i2c_add_adapter(&bus->adapter);
822 if (ret)
823 goto err;
824 }
825
826 intel_i2c_reset(dev_priv);
827
828 return 0;
829
830err:
831 while (pin--) {
832 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
833 continue;
834
835 bus = &dev_priv->gmbus[pin];
836 i2c_del_adapter(&bus->adapter);
837 }
838 return ret;
839}
840
841struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
842 unsigned int pin)
843{
844 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
845 return NULL;
846
847 return &dev_priv->gmbus[pin].adapter;
848}
849
850void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
851{
852 struct intel_gmbus *bus = to_intel_gmbus(adapter);
853
854 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
855}
856
857void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
858{
859 struct intel_gmbus *bus = to_intel_gmbus(adapter);
860 struct drm_i915_private *dev_priv = bus->dev_priv;
861
862 mutex_lock(&dev_priv->gmbus_mutex);
863
864 bus->force_bit += force_bit ? 1 : -1;
865 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
866 force_bit ? "en" : "dis", adapter->name,
867 bus->force_bit);
868
869 mutex_unlock(&dev_priv->gmbus_mutex);
870}
871
872void intel_teardown_gmbus(struct drm_i915_private *dev_priv)
873{
874 struct intel_gmbus *bus;
875 unsigned int pin;
876
877 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
878 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
879 continue;
880
881 bus = &dev_priv->gmbus[pin];
882 i2c_del_adapter(&bus->adapter);
883 }
884}