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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Technologic Systems TS-73xx SBC FPGA loader
4 *
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
8 * TS-7300, heavily based on load_fpga.c in their vendor tree.
9 */
10
11#include <linux/delay.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/string.h>
16#include <linux/iopoll.h>
17#include <linux/fpga/fpga-mgr.h>
18
19#define TS73XX_FPGA_DATA_REG 0
20#define TS73XX_FPGA_CONFIG_REG 1
21
22#define TS73XX_FPGA_WRITE_DONE 0x1
23#define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000 /* us */
24#define TS73XX_FPGA_RESET 0x2
25#define TS73XX_FPGA_RESET_LOW_DELAY 30 /* us */
26#define TS73XX_FPGA_RESET_HIGH_DELAY 80 /* us */
27#define TS73XX_FPGA_LOAD_OK 0x4
28#define TS73XX_FPGA_CONFIG_LOAD 0x8
29
30struct ts73xx_fpga_priv {
31 void __iomem *io_base;
32 struct device *dev;
33};
34
35static int ts73xx_fpga_write_init(struct fpga_manager *mgr,
36 struct fpga_image_info *info,
37 const char *buf, size_t count)
38{
39 struct ts73xx_fpga_priv *priv = mgr->priv;
40
41 /* Reset the FPGA */
42 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
43 udelay(TS73XX_FPGA_RESET_LOW_DELAY);
44 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
45 udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
46
47 return 0;
48}
49
50static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
51 size_t count)
52{
53 struct ts73xx_fpga_priv *priv = mgr->priv;
54 size_t i = 0;
55 int ret;
56 u8 reg;
57
58 while (count--) {
59 ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
60 reg, !(reg & TS73XX_FPGA_WRITE_DONE),
61 1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
62 if (ret < 0)
63 return ret;
64
65 writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
66 i++;
67 }
68
69 return 0;
70}
71
72static int ts73xx_fpga_write_complete(struct fpga_manager *mgr,
73 struct fpga_image_info *info)
74{
75 struct ts73xx_fpga_priv *priv = mgr->priv;
76 u8 reg;
77
78 usleep_range(1000, 2000);
79 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
80 reg |= TS73XX_FPGA_CONFIG_LOAD;
81 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
82
83 usleep_range(1000, 2000);
84 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
85 reg &= ~TS73XX_FPGA_CONFIG_LOAD;
86 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
87
88 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
89 if ((reg & TS73XX_FPGA_LOAD_OK) != TS73XX_FPGA_LOAD_OK)
90 return -ETIMEDOUT;
91
92 return 0;
93}
94
95static const struct fpga_manager_ops ts73xx_fpga_ops = {
96 .write_init = ts73xx_fpga_write_init,
97 .write = ts73xx_fpga_write,
98 .write_complete = ts73xx_fpga_write_complete,
99};
100
101static int ts73xx_fpga_probe(struct platform_device *pdev)
102{
103 struct device *kdev = &pdev->dev;
104 struct ts73xx_fpga_priv *priv;
105 struct fpga_manager *mgr;
106 struct resource *res;
107
108 priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
109 if (!priv)
110 return -ENOMEM;
111
112 priv->dev = kdev;
113
114 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
115 priv->io_base = devm_ioremap_resource(kdev, res);
116 if (IS_ERR(priv->io_base))
117 return PTR_ERR(priv->io_base);
118
119 mgr = devm_fpga_mgr_register(kdev, "TS-73xx FPGA Manager",
120 &ts73xx_fpga_ops, priv);
121 return PTR_ERR_OR_ZERO(mgr);
122}
123
124static struct platform_driver ts73xx_fpga_driver = {
125 .driver = {
126 .name = "ts73xx-fpga-mgr",
127 },
128 .probe = ts73xx_fpga_probe,
129};
130module_platform_driver(ts73xx_fpga_driver);
131
132MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
133MODULE_DESCRIPTION("TS-73xx FPGA Manager driver");
134MODULE_LICENSE("GPL v2");
1/*
2 * Technologic Systems TS-73xx SBC FPGA loader
3 *
4 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
5 *
6 * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
7 * TS-7300, heavily based on load_fpga.c in their vendor tree.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/delay.h>
20#include <linux/io.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/string.h>
24#include <linux/iopoll.h>
25#include <linux/fpga/fpga-mgr.h>
26
27#define TS73XX_FPGA_DATA_REG 0
28#define TS73XX_FPGA_CONFIG_REG 1
29
30#define TS73XX_FPGA_WRITE_DONE 0x1
31#define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000 /* us */
32#define TS73XX_FPGA_RESET 0x2
33#define TS73XX_FPGA_RESET_LOW_DELAY 30 /* us */
34#define TS73XX_FPGA_RESET_HIGH_DELAY 80 /* us */
35#define TS73XX_FPGA_LOAD_OK 0x4
36#define TS73XX_FPGA_CONFIG_LOAD 0x8
37
38struct ts73xx_fpga_priv {
39 void __iomem *io_base;
40 struct device *dev;
41};
42
43static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr)
44{
45 return FPGA_MGR_STATE_UNKNOWN;
46}
47
48static int ts73xx_fpga_write_init(struct fpga_manager *mgr,
49 struct fpga_image_info *info,
50 const char *buf, size_t count)
51{
52 struct ts73xx_fpga_priv *priv = mgr->priv;
53
54 /* Reset the FPGA */
55 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
56 udelay(TS73XX_FPGA_RESET_LOW_DELAY);
57 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
58 udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
59
60 return 0;
61}
62
63static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
64 size_t count)
65{
66 struct ts73xx_fpga_priv *priv = mgr->priv;
67 size_t i = 0;
68 int ret;
69 u8 reg;
70
71 while (count--) {
72 ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
73 reg, !(reg & TS73XX_FPGA_WRITE_DONE),
74 1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
75 if (ret < 0)
76 return ret;
77
78 writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
79 i++;
80 }
81
82 return 0;
83}
84
85static int ts73xx_fpga_write_complete(struct fpga_manager *mgr,
86 struct fpga_image_info *info)
87{
88 struct ts73xx_fpga_priv *priv = mgr->priv;
89 u8 reg;
90
91 usleep_range(1000, 2000);
92 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
93 reg |= TS73XX_FPGA_CONFIG_LOAD;
94 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
95
96 usleep_range(1000, 2000);
97 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
98 reg &= ~TS73XX_FPGA_CONFIG_LOAD;
99 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
100
101 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
102 if ((reg & TS73XX_FPGA_LOAD_OK) != TS73XX_FPGA_LOAD_OK)
103 return -ETIMEDOUT;
104
105 return 0;
106}
107
108static const struct fpga_manager_ops ts73xx_fpga_ops = {
109 .state = ts73xx_fpga_state,
110 .write_init = ts73xx_fpga_write_init,
111 .write = ts73xx_fpga_write,
112 .write_complete = ts73xx_fpga_write_complete,
113};
114
115static int ts73xx_fpga_probe(struct platform_device *pdev)
116{
117 struct device *kdev = &pdev->dev;
118 struct ts73xx_fpga_priv *priv;
119 struct resource *res;
120
121 priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
122 if (!priv)
123 return -ENOMEM;
124
125 priv->dev = kdev;
126
127 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
128 priv->io_base = devm_ioremap_resource(kdev, res);
129 if (IS_ERR(priv->io_base)) {
130 dev_err(kdev, "unable to remap registers\n");
131 return PTR_ERR(priv->io_base);
132 }
133
134 return fpga_mgr_register(kdev, "TS-73xx FPGA Manager",
135 &ts73xx_fpga_ops, priv);
136}
137
138static int ts73xx_fpga_remove(struct platform_device *pdev)
139{
140 fpga_mgr_unregister(&pdev->dev);
141
142 return 0;
143}
144
145static struct platform_driver ts73xx_fpga_driver = {
146 .driver = {
147 .name = "ts73xx-fpga-mgr",
148 },
149 .probe = ts73xx_fpga_probe,
150 .remove = ts73xx_fpga_remove,
151};
152module_platform_driver(ts73xx_fpga_driver);
153
154MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
155MODULE_DESCRIPTION("TS-73xx FPGA Manager driver");
156MODULE_LICENSE("GPL v2");