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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * FPGA to/from HPS Bridge Driver for Altera SoCFPGA Devices
4 *
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
6 *
7 * Includes this patch from the mailing list:
8 * fpga: altera-hps2fpga: fix HPS2FPGA bridge visibility to L3 masters
9 * Signed-off-by: Anatolij Gustschin <agust@denx.de>
10 */
11
12/*
13 * This driver manages bridges on a Altera SOCFPGA between the ARM host
14 * processor system (HPS) and the embedded FPGA.
15 *
16 * This driver supports enabling and disabling of the configured ports, which
17 * allows for safe reprogramming of the FPGA, assuming that the new FPGA image
18 * uses the same port configuration. Bridges must be disabled before
19 * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
20 */
21
22#include <linux/clk.h>
23#include <linux/fpga/fpga-bridge.h>
24#include <linux/kernel.h>
25#include <linux/mfd/syscon.h>
26#include <linux/module.h>
27#include <linux/of_platform.h>
28#include <linux/regmap.h>
29#include <linux/reset.h>
30#include <linux/spinlock.h>
31
32#define ALT_L3_REMAP_OFST 0x0
33#define ALT_L3_REMAP_MPUZERO_MSK 0x00000001
34#define ALT_L3_REMAP_H2F_MSK 0x00000008
35#define ALT_L3_REMAP_LWH2F_MSK 0x00000010
36
37#define HPS2FPGA_BRIDGE_NAME "hps2fpga"
38#define LWHPS2FPGA_BRIDGE_NAME "lwhps2fpga"
39#define FPGA2HPS_BRIDGE_NAME "fpga2hps"
40
41struct altera_hps2fpga_data {
42 const char *name;
43 struct reset_control *bridge_reset;
44 struct regmap *l3reg;
45 unsigned int remap_mask;
46 struct clk *clk;
47};
48
49static int alt_hps2fpga_enable_show(struct fpga_bridge *bridge)
50{
51 struct altera_hps2fpga_data *priv = bridge->priv;
52
53 return reset_control_status(priv->bridge_reset);
54}
55
56/* The L3 REMAP register is write only, so keep a cached value. */
57static unsigned int l3_remap_shadow;
58static DEFINE_SPINLOCK(l3_remap_lock);
59
60static int _alt_hps2fpga_enable_set(struct altera_hps2fpga_data *priv,
61 bool enable)
62{
63 unsigned long flags;
64 int ret;
65
66 /* bring bridge out of reset */
67 if (enable)
68 ret = reset_control_deassert(priv->bridge_reset);
69 else
70 ret = reset_control_assert(priv->bridge_reset);
71 if (ret)
72 return ret;
73
74 /* Allow bridge to be visible to L3 masters or not */
75 if (priv->remap_mask) {
76 spin_lock_irqsave(&l3_remap_lock, flags);
77 l3_remap_shadow |= ALT_L3_REMAP_MPUZERO_MSK;
78
79 if (enable)
80 l3_remap_shadow |= priv->remap_mask;
81 else
82 l3_remap_shadow &= ~priv->remap_mask;
83
84 ret = regmap_write(priv->l3reg, ALT_L3_REMAP_OFST,
85 l3_remap_shadow);
86 spin_unlock_irqrestore(&l3_remap_lock, flags);
87 }
88
89 return ret;
90}
91
92static int alt_hps2fpga_enable_set(struct fpga_bridge *bridge, bool enable)
93{
94 return _alt_hps2fpga_enable_set(bridge->priv, enable);
95}
96
97static const struct fpga_bridge_ops altera_hps2fpga_br_ops = {
98 .enable_set = alt_hps2fpga_enable_set,
99 .enable_show = alt_hps2fpga_enable_show,
100};
101
102static struct altera_hps2fpga_data hps2fpga_data = {
103 .name = HPS2FPGA_BRIDGE_NAME,
104 .remap_mask = ALT_L3_REMAP_H2F_MSK,
105};
106
107static struct altera_hps2fpga_data lwhps2fpga_data = {
108 .name = LWHPS2FPGA_BRIDGE_NAME,
109 .remap_mask = ALT_L3_REMAP_LWH2F_MSK,
110};
111
112static struct altera_hps2fpga_data fpga2hps_data = {
113 .name = FPGA2HPS_BRIDGE_NAME,
114};
115
116static const struct of_device_id altera_fpga_of_match[] = {
117 { .compatible = "altr,socfpga-hps2fpga-bridge",
118 .data = &hps2fpga_data },
119 { .compatible = "altr,socfpga-lwhps2fpga-bridge",
120 .data = &lwhps2fpga_data },
121 { .compatible = "altr,socfpga-fpga2hps-bridge",
122 .data = &fpga2hps_data },
123 {},
124};
125
126static int alt_fpga_bridge_probe(struct platform_device *pdev)
127{
128 struct device *dev = &pdev->dev;
129 struct altera_hps2fpga_data *priv;
130 const struct of_device_id *of_id;
131 struct fpga_bridge *br;
132 u32 enable;
133 int ret;
134
135 of_id = of_match_device(altera_fpga_of_match, dev);
136 if (!of_id) {
137 dev_err(dev, "failed to match device\n");
138 return -ENODEV;
139 }
140
141 priv = (struct altera_hps2fpga_data *)of_id->data;
142
143 priv->bridge_reset = of_reset_control_get_exclusive_by_index(dev->of_node,
144 0);
145 if (IS_ERR(priv->bridge_reset)) {
146 dev_err(dev, "Could not get %s reset control\n", priv->name);
147 return PTR_ERR(priv->bridge_reset);
148 }
149
150 if (priv->remap_mask) {
151 priv->l3reg = syscon_regmap_lookup_by_compatible("altr,l3regs");
152 if (IS_ERR(priv->l3reg)) {
153 dev_err(dev, "regmap for altr,l3regs lookup failed\n");
154 return PTR_ERR(priv->l3reg);
155 }
156 }
157
158 priv->clk = devm_clk_get(dev, NULL);
159 if (IS_ERR(priv->clk)) {
160 dev_err(dev, "no clock specified\n");
161 return PTR_ERR(priv->clk);
162 }
163
164 ret = clk_prepare_enable(priv->clk);
165 if (ret) {
166 dev_err(dev, "could not enable clock\n");
167 return -EBUSY;
168 }
169
170 if (!of_property_read_u32(dev->of_node, "bridge-enable", &enable)) {
171 if (enable > 1) {
172 dev_warn(dev, "invalid bridge-enable %u > 1\n", enable);
173 } else {
174 dev_info(dev, "%s bridge\n",
175 (enable ? "enabling" : "disabling"));
176
177 ret = _alt_hps2fpga_enable_set(priv, enable);
178 if (ret)
179 goto err;
180 }
181 }
182
183 br = fpga_bridge_register(dev, priv->name,
184 &altera_hps2fpga_br_ops, priv);
185 if (IS_ERR(br)) {
186 ret = PTR_ERR(br);
187 goto err;
188 }
189
190 platform_set_drvdata(pdev, br);
191
192 return 0;
193
194err:
195 clk_disable_unprepare(priv->clk);
196
197 return ret;
198}
199
200static int alt_fpga_bridge_remove(struct platform_device *pdev)
201{
202 struct fpga_bridge *bridge = platform_get_drvdata(pdev);
203 struct altera_hps2fpga_data *priv = bridge->priv;
204
205 fpga_bridge_unregister(bridge);
206
207 clk_disable_unprepare(priv->clk);
208
209 return 0;
210}
211
212MODULE_DEVICE_TABLE(of, altera_fpga_of_match);
213
214static struct platform_driver alt_fpga_bridge_driver = {
215 .probe = alt_fpga_bridge_probe,
216 .remove = alt_fpga_bridge_remove,
217 .driver = {
218 .name = "altera_hps2fpga_bridge",
219 .of_match_table = of_match_ptr(altera_fpga_of_match),
220 },
221};
222
223module_platform_driver(alt_fpga_bridge_driver);
224
225MODULE_DESCRIPTION("Altera SoCFPGA HPS to FPGA Bridge");
226MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
227MODULE_LICENSE("GPL v2");
1/*
2 * FPGA to/from HPS Bridge Driver for Altera SoCFPGA Devices
3 *
4 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
5 *
6 * Includes this patch from the mailing list:
7 * fpga: altera-hps2fpga: fix HPS2FPGA bridge visibility to L3 masters
8 * Signed-off-by: Anatolij Gustschin <agust@denx.de>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23/*
24 * This driver manages bridges on a Altera SOCFPGA between the ARM host
25 * processor system (HPS) and the embedded FPGA.
26 *
27 * This driver supports enabling and disabling of the configured ports, which
28 * allows for safe reprogramming of the FPGA, assuming that the new FPGA image
29 * uses the same port configuration. Bridges must be disabled before
30 * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
31 */
32
33#include <linux/clk.h>
34#include <linux/fpga/fpga-bridge.h>
35#include <linux/kernel.h>
36#include <linux/mfd/syscon.h>
37#include <linux/module.h>
38#include <linux/of_platform.h>
39#include <linux/regmap.h>
40#include <linux/reset.h>
41#include <linux/spinlock.h>
42
43#define ALT_L3_REMAP_OFST 0x0
44#define ALT_L3_REMAP_MPUZERO_MSK 0x00000001
45#define ALT_L3_REMAP_H2F_MSK 0x00000008
46#define ALT_L3_REMAP_LWH2F_MSK 0x00000010
47
48#define HPS2FPGA_BRIDGE_NAME "hps2fpga"
49#define LWHPS2FPGA_BRIDGE_NAME "lwhps2fpga"
50#define FPGA2HPS_BRIDGE_NAME "fpga2hps"
51
52struct altera_hps2fpga_data {
53 const char *name;
54 struct reset_control *bridge_reset;
55 struct regmap *l3reg;
56 unsigned int remap_mask;
57 struct clk *clk;
58};
59
60static int alt_hps2fpga_enable_show(struct fpga_bridge *bridge)
61{
62 struct altera_hps2fpga_data *priv = bridge->priv;
63
64 return reset_control_status(priv->bridge_reset);
65}
66
67/* The L3 REMAP register is write only, so keep a cached value. */
68static unsigned int l3_remap_shadow;
69static DEFINE_SPINLOCK(l3_remap_lock);
70
71static int _alt_hps2fpga_enable_set(struct altera_hps2fpga_data *priv,
72 bool enable)
73{
74 unsigned long flags;
75 int ret;
76
77 /* bring bridge out of reset */
78 if (enable)
79 ret = reset_control_deassert(priv->bridge_reset);
80 else
81 ret = reset_control_assert(priv->bridge_reset);
82 if (ret)
83 return ret;
84
85 /* Allow bridge to be visible to L3 masters or not */
86 if (priv->remap_mask) {
87 spin_lock_irqsave(&l3_remap_lock, flags);
88 l3_remap_shadow |= ALT_L3_REMAP_MPUZERO_MSK;
89
90 if (enable)
91 l3_remap_shadow |= priv->remap_mask;
92 else
93 l3_remap_shadow &= ~priv->remap_mask;
94
95 ret = regmap_write(priv->l3reg, ALT_L3_REMAP_OFST,
96 l3_remap_shadow);
97 spin_unlock_irqrestore(&l3_remap_lock, flags);
98 }
99
100 return ret;
101}
102
103static int alt_hps2fpga_enable_set(struct fpga_bridge *bridge, bool enable)
104{
105 return _alt_hps2fpga_enable_set(bridge->priv, enable);
106}
107
108static const struct fpga_bridge_ops altera_hps2fpga_br_ops = {
109 .enable_set = alt_hps2fpga_enable_set,
110 .enable_show = alt_hps2fpga_enable_show,
111};
112
113static struct altera_hps2fpga_data hps2fpga_data = {
114 .name = HPS2FPGA_BRIDGE_NAME,
115 .remap_mask = ALT_L3_REMAP_H2F_MSK,
116};
117
118static struct altera_hps2fpga_data lwhps2fpga_data = {
119 .name = LWHPS2FPGA_BRIDGE_NAME,
120 .remap_mask = ALT_L3_REMAP_LWH2F_MSK,
121};
122
123static struct altera_hps2fpga_data fpga2hps_data = {
124 .name = FPGA2HPS_BRIDGE_NAME,
125};
126
127static const struct of_device_id altera_fpga_of_match[] = {
128 { .compatible = "altr,socfpga-hps2fpga-bridge",
129 .data = &hps2fpga_data },
130 { .compatible = "altr,socfpga-lwhps2fpga-bridge",
131 .data = &lwhps2fpga_data },
132 { .compatible = "altr,socfpga-fpga2hps-bridge",
133 .data = &fpga2hps_data },
134 {},
135};
136
137static int alt_fpga_bridge_probe(struct platform_device *pdev)
138{
139 struct device *dev = &pdev->dev;
140 struct altera_hps2fpga_data *priv;
141 const struct of_device_id *of_id;
142 u32 enable;
143 int ret;
144
145 of_id = of_match_device(altera_fpga_of_match, dev);
146 if (!of_id) {
147 dev_err(dev, "failed to match device\n");
148 return -ENODEV;
149 }
150
151 priv = (struct altera_hps2fpga_data *)of_id->data;
152
153 priv->bridge_reset = of_reset_control_get_exclusive_by_index(dev->of_node,
154 0);
155 if (IS_ERR(priv->bridge_reset)) {
156 dev_err(dev, "Could not get %s reset control\n", priv->name);
157 return PTR_ERR(priv->bridge_reset);
158 }
159
160 if (priv->remap_mask) {
161 priv->l3reg = syscon_regmap_lookup_by_compatible("altr,l3regs");
162 if (IS_ERR(priv->l3reg)) {
163 dev_err(dev, "regmap for altr,l3regs lookup failed\n");
164 return PTR_ERR(priv->l3reg);
165 }
166 }
167
168 priv->clk = devm_clk_get(dev, NULL);
169 if (IS_ERR(priv->clk)) {
170 dev_err(dev, "no clock specified\n");
171 return PTR_ERR(priv->clk);
172 }
173
174 ret = clk_prepare_enable(priv->clk);
175 if (ret) {
176 dev_err(dev, "could not enable clock\n");
177 return -EBUSY;
178 }
179
180 if (!of_property_read_u32(dev->of_node, "bridge-enable", &enable)) {
181 if (enable > 1) {
182 dev_warn(dev, "invalid bridge-enable %u > 1\n", enable);
183 } else {
184 dev_info(dev, "%s bridge\n",
185 (enable ? "enabling" : "disabling"));
186
187 ret = _alt_hps2fpga_enable_set(priv, enable);
188 if (ret)
189 goto err;
190 }
191 }
192
193 ret = fpga_bridge_register(dev, priv->name, &altera_hps2fpga_br_ops,
194 priv);
195err:
196 if (ret)
197 clk_disable_unprepare(priv->clk);
198
199 return ret;
200}
201
202static int alt_fpga_bridge_remove(struct platform_device *pdev)
203{
204 struct fpga_bridge *bridge = platform_get_drvdata(pdev);
205 struct altera_hps2fpga_data *priv = bridge->priv;
206
207 fpga_bridge_unregister(&pdev->dev);
208
209 clk_disable_unprepare(priv->clk);
210
211 return 0;
212}
213
214MODULE_DEVICE_TABLE(of, altera_fpga_of_match);
215
216static struct platform_driver alt_fpga_bridge_driver = {
217 .probe = alt_fpga_bridge_probe,
218 .remove = alt_fpga_bridge_remove,
219 .driver = {
220 .name = "altera_hps2fpga_bridge",
221 .of_match_table = of_match_ptr(altera_fpga_of_match),
222 },
223};
224
225module_platform_driver(alt_fpga_bridge_driver);
226
227MODULE_DESCRIPTION("Altera SoCFPGA HPS to FPGA Bridge");
228MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
229MODULE_LICENSE("GPL v2");