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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * FPGA Freeze Bridge Controller
4 *
5 * Copyright (C) 2016 Altera Corporation. All rights reserved.
6 */
7#include <linux/delay.h>
8#include <linux/io.h>
9#include <linux/kernel.h>
10#include <linux/of_device.h>
11#include <linux/module.h>
12#include <linux/fpga/fpga-bridge.h>
13
14#define FREEZE_CSR_STATUS_OFFSET 0
15#define FREEZE_CSR_CTRL_OFFSET 4
16#define FREEZE_CSR_ILLEGAL_REQ_OFFSET 8
17#define FREEZE_CSR_REG_VERSION 12
18
19#define FREEZE_CSR_SUPPORTED_VERSION 2
20#define FREEZE_CSR_OFFICIAL_VERSION 0xad000003
21
22#define FREEZE_CSR_STATUS_FREEZE_REQ_DONE BIT(0)
23#define FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE BIT(1)
24
25#define FREEZE_CSR_CTRL_FREEZE_REQ BIT(0)
26#define FREEZE_CSR_CTRL_RESET_REQ BIT(1)
27#define FREEZE_CSR_CTRL_UNFREEZE_REQ BIT(2)
28
29#define FREEZE_BRIDGE_NAME "freeze"
30
31struct altera_freeze_br_data {
32 struct device *dev;
33 void __iomem *base_addr;
34 bool enable;
35};
36
37/*
38 * Poll status until status bit is set or we have a timeout.
39 */
40static int altera_freeze_br_req_ack(struct altera_freeze_br_data *priv,
41 u32 timeout, u32 req_ack)
42{
43 struct device *dev = priv->dev;
44 void __iomem *csr_illegal_req_addr = priv->base_addr +
45 FREEZE_CSR_ILLEGAL_REQ_OFFSET;
46 u32 status, illegal, ctrl;
47 int ret = -ETIMEDOUT;
48
49 do {
50 illegal = readl(csr_illegal_req_addr);
51 if (illegal) {
52 dev_err(dev, "illegal request detected 0x%x", illegal);
53
54 writel(1, csr_illegal_req_addr);
55
56 illegal = readl(csr_illegal_req_addr);
57 if (illegal)
58 dev_err(dev, "illegal request not cleared 0x%x",
59 illegal);
60
61 ret = -EINVAL;
62 break;
63 }
64
65 status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
66 dev_dbg(dev, "%s %x %x\n", __func__, status, req_ack);
67 status &= req_ack;
68 if (status) {
69 ctrl = readl(priv->base_addr + FREEZE_CSR_CTRL_OFFSET);
70 dev_dbg(dev, "%s request %x acknowledged %x %x\n",
71 __func__, req_ack, status, ctrl);
72 ret = 0;
73 break;
74 }
75
76 udelay(1);
77 } while (timeout--);
78
79 if (ret == -ETIMEDOUT)
80 dev_err(dev, "%s timeout waiting for 0x%x\n",
81 __func__, req_ack);
82
83 return ret;
84}
85
86static int altera_freeze_br_do_freeze(struct altera_freeze_br_data *priv,
87 u32 timeout)
88{
89 struct device *dev = priv->dev;
90 void __iomem *csr_ctrl_addr = priv->base_addr +
91 FREEZE_CSR_CTRL_OFFSET;
92 u32 status;
93 int ret;
94
95 status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
96
97 dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
98
99 if (status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE) {
100 dev_dbg(dev, "%s bridge already disabled %d\n",
101 __func__, status);
102 return 0;
103 } else if (!(status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)) {
104 dev_err(dev, "%s bridge not enabled %d\n", __func__, status);
105 return -EINVAL;
106 }
107
108 writel(FREEZE_CSR_CTRL_FREEZE_REQ, csr_ctrl_addr);
109
110 ret = altera_freeze_br_req_ack(priv, timeout,
111 FREEZE_CSR_STATUS_FREEZE_REQ_DONE);
112
113 if (ret)
114 writel(0, csr_ctrl_addr);
115 else
116 writel(FREEZE_CSR_CTRL_RESET_REQ, csr_ctrl_addr);
117
118 return ret;
119}
120
121static int altera_freeze_br_do_unfreeze(struct altera_freeze_br_data *priv,
122 u32 timeout)
123{
124 struct device *dev = priv->dev;
125 void __iomem *csr_ctrl_addr = priv->base_addr +
126 FREEZE_CSR_CTRL_OFFSET;
127 u32 status;
128 int ret;
129
130 writel(0, csr_ctrl_addr);
131
132 status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
133
134 dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
135
136 if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE) {
137 dev_dbg(dev, "%s bridge already enabled %d\n",
138 __func__, status);
139 return 0;
140 } else if (!(status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE)) {
141 dev_err(dev, "%s bridge not frozen %d\n", __func__, status);
142 return -EINVAL;
143 }
144
145 writel(FREEZE_CSR_CTRL_UNFREEZE_REQ, csr_ctrl_addr);
146
147 ret = altera_freeze_br_req_ack(priv, timeout,
148 FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE);
149
150 status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
151
152 dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
153
154 writel(0, csr_ctrl_addr);
155
156 return ret;
157}
158
159/*
160 * enable = 1 : allow traffic through the bridge
161 * enable = 0 : disable traffic through the bridge
162 */
163static int altera_freeze_br_enable_set(struct fpga_bridge *bridge,
164 bool enable)
165{
166 struct altera_freeze_br_data *priv = bridge->priv;
167 struct fpga_image_info *info = bridge->info;
168 u32 timeout = 0;
169 int ret;
170
171 if (enable) {
172 if (info)
173 timeout = info->enable_timeout_us;
174
175 ret = altera_freeze_br_do_unfreeze(bridge->priv, timeout);
176 } else {
177 if (info)
178 timeout = info->disable_timeout_us;
179
180 ret = altera_freeze_br_do_freeze(bridge->priv, timeout);
181 }
182
183 if (!ret)
184 priv->enable = enable;
185
186 return ret;
187}
188
189static int altera_freeze_br_enable_show(struct fpga_bridge *bridge)
190{
191 struct altera_freeze_br_data *priv = bridge->priv;
192
193 return priv->enable;
194}
195
196static const struct fpga_bridge_ops altera_freeze_br_br_ops = {
197 .enable_set = altera_freeze_br_enable_set,
198 .enable_show = altera_freeze_br_enable_show,
199};
200
201#ifdef CONFIG_OF
202static const struct of_device_id altera_freeze_br_of_match[] = {
203 { .compatible = "altr,freeze-bridge-controller", },
204 {},
205};
206MODULE_DEVICE_TABLE(of, altera_freeze_br_of_match);
207#endif
208
209static int altera_freeze_br_probe(struct platform_device *pdev)
210{
211 struct device *dev = &pdev->dev;
212 struct device_node *np = pdev->dev.of_node;
213 void __iomem *base_addr;
214 struct altera_freeze_br_data *priv;
215 struct fpga_bridge *br;
216 struct resource *res;
217 u32 status, revision;
218
219 if (!np)
220 return -ENODEV;
221
222 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
223 base_addr = devm_ioremap_resource(dev, res);
224 if (IS_ERR(base_addr))
225 return PTR_ERR(base_addr);
226
227 revision = readl(base_addr + FREEZE_CSR_REG_VERSION);
228 if ((revision != FREEZE_CSR_SUPPORTED_VERSION) &&
229 (revision != FREEZE_CSR_OFFICIAL_VERSION)) {
230 dev_err(dev,
231 "%s unexpected revision 0x%x != 0x%x != 0x%x\n",
232 __func__, revision, FREEZE_CSR_SUPPORTED_VERSION,
233 FREEZE_CSR_OFFICIAL_VERSION);
234 return -EINVAL;
235 }
236
237 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
238 if (!priv)
239 return -ENOMEM;
240
241 priv->dev = dev;
242
243 status = readl(base_addr + FREEZE_CSR_STATUS_OFFSET);
244 if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)
245 priv->enable = 1;
246
247 priv->base_addr = base_addr;
248
249 br = fpga_bridge_register(dev, FREEZE_BRIDGE_NAME,
250 &altera_freeze_br_br_ops, priv);
251 if (IS_ERR(br))
252 return PTR_ERR(br);
253
254 platform_set_drvdata(pdev, br);
255
256 return 0;
257}
258
259static int altera_freeze_br_remove(struct platform_device *pdev)
260{
261 struct fpga_bridge *br = platform_get_drvdata(pdev);
262
263 fpga_bridge_unregister(br);
264
265 return 0;
266}
267
268static struct platform_driver altera_freeze_br_driver = {
269 .probe = altera_freeze_br_probe,
270 .remove = altera_freeze_br_remove,
271 .driver = {
272 .name = "altera_freeze_br",
273 .of_match_table = of_match_ptr(altera_freeze_br_of_match),
274 },
275};
276
277module_platform_driver(altera_freeze_br_driver);
278
279MODULE_DESCRIPTION("Altera Freeze Bridge");
280MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
281MODULE_LICENSE("GPL v2");
1/*
2 * FPGA Freeze Bridge Controller
3 *
4 * Copyright (C) 2016 Altera Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18#include <linux/delay.h>
19#include <linux/io.h>
20#include <linux/kernel.h>
21#include <linux/of_device.h>
22#include <linux/module.h>
23#include <linux/fpga/fpga-bridge.h>
24
25#define FREEZE_CSR_STATUS_OFFSET 0
26#define FREEZE_CSR_CTRL_OFFSET 4
27#define FREEZE_CSR_ILLEGAL_REQ_OFFSET 8
28#define FREEZE_CSR_REG_VERSION 12
29
30#define FREEZE_CSR_SUPPORTED_VERSION 2
31#define FREEZE_CSR_OFFICIAL_VERSION 0xad000003
32
33#define FREEZE_CSR_STATUS_FREEZE_REQ_DONE BIT(0)
34#define FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE BIT(1)
35
36#define FREEZE_CSR_CTRL_FREEZE_REQ BIT(0)
37#define FREEZE_CSR_CTRL_RESET_REQ BIT(1)
38#define FREEZE_CSR_CTRL_UNFREEZE_REQ BIT(2)
39
40#define FREEZE_BRIDGE_NAME "freeze"
41
42struct altera_freeze_br_data {
43 struct device *dev;
44 void __iomem *base_addr;
45 bool enable;
46};
47
48/*
49 * Poll status until status bit is set or we have a timeout.
50 */
51static int altera_freeze_br_req_ack(struct altera_freeze_br_data *priv,
52 u32 timeout, u32 req_ack)
53{
54 struct device *dev = priv->dev;
55 void __iomem *csr_illegal_req_addr = priv->base_addr +
56 FREEZE_CSR_ILLEGAL_REQ_OFFSET;
57 u32 status, illegal, ctrl;
58 int ret = -ETIMEDOUT;
59
60 do {
61 illegal = readl(csr_illegal_req_addr);
62 if (illegal) {
63 dev_err(dev, "illegal request detected 0x%x", illegal);
64
65 writel(1, csr_illegal_req_addr);
66
67 illegal = readl(csr_illegal_req_addr);
68 if (illegal)
69 dev_err(dev, "illegal request not cleared 0x%x",
70 illegal);
71
72 ret = -EINVAL;
73 break;
74 }
75
76 status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
77 dev_dbg(dev, "%s %x %x\n", __func__, status, req_ack);
78 status &= req_ack;
79 if (status) {
80 ctrl = readl(priv->base_addr + FREEZE_CSR_CTRL_OFFSET);
81 dev_dbg(dev, "%s request %x acknowledged %x %x\n",
82 __func__, req_ack, status, ctrl);
83 ret = 0;
84 break;
85 }
86
87 udelay(1);
88 } while (timeout--);
89
90 if (ret == -ETIMEDOUT)
91 dev_err(dev, "%s timeout waiting for 0x%x\n",
92 __func__, req_ack);
93
94 return ret;
95}
96
97static int altera_freeze_br_do_freeze(struct altera_freeze_br_data *priv,
98 u32 timeout)
99{
100 struct device *dev = priv->dev;
101 void __iomem *csr_ctrl_addr = priv->base_addr +
102 FREEZE_CSR_CTRL_OFFSET;
103 u32 status;
104 int ret;
105
106 status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
107
108 dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
109
110 if (status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE) {
111 dev_dbg(dev, "%s bridge already disabled %d\n",
112 __func__, status);
113 return 0;
114 } else if (!(status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)) {
115 dev_err(dev, "%s bridge not enabled %d\n", __func__, status);
116 return -EINVAL;
117 }
118
119 writel(FREEZE_CSR_CTRL_FREEZE_REQ, csr_ctrl_addr);
120
121 ret = altera_freeze_br_req_ack(priv, timeout,
122 FREEZE_CSR_STATUS_FREEZE_REQ_DONE);
123
124 if (ret)
125 writel(0, csr_ctrl_addr);
126 else
127 writel(FREEZE_CSR_CTRL_RESET_REQ, csr_ctrl_addr);
128
129 return ret;
130}
131
132static int altera_freeze_br_do_unfreeze(struct altera_freeze_br_data *priv,
133 u32 timeout)
134{
135 struct device *dev = priv->dev;
136 void __iomem *csr_ctrl_addr = priv->base_addr +
137 FREEZE_CSR_CTRL_OFFSET;
138 u32 status;
139 int ret;
140
141 writel(0, csr_ctrl_addr);
142
143 status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
144
145 dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
146
147 if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE) {
148 dev_dbg(dev, "%s bridge already enabled %d\n",
149 __func__, status);
150 return 0;
151 } else if (!(status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE)) {
152 dev_err(dev, "%s bridge not frozen %d\n", __func__, status);
153 return -EINVAL;
154 }
155
156 writel(FREEZE_CSR_CTRL_UNFREEZE_REQ, csr_ctrl_addr);
157
158 ret = altera_freeze_br_req_ack(priv, timeout,
159 FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE);
160
161 status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
162
163 dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
164
165 writel(0, csr_ctrl_addr);
166
167 return ret;
168}
169
170/*
171 * enable = 1 : allow traffic through the bridge
172 * enable = 0 : disable traffic through the bridge
173 */
174static int altera_freeze_br_enable_set(struct fpga_bridge *bridge,
175 bool enable)
176{
177 struct altera_freeze_br_data *priv = bridge->priv;
178 struct fpga_image_info *info = bridge->info;
179 u32 timeout = 0;
180 int ret;
181
182 if (enable) {
183 if (info)
184 timeout = info->enable_timeout_us;
185
186 ret = altera_freeze_br_do_unfreeze(bridge->priv, timeout);
187 } else {
188 if (info)
189 timeout = info->disable_timeout_us;
190
191 ret = altera_freeze_br_do_freeze(bridge->priv, timeout);
192 }
193
194 if (!ret)
195 priv->enable = enable;
196
197 return ret;
198}
199
200static int altera_freeze_br_enable_show(struct fpga_bridge *bridge)
201{
202 struct altera_freeze_br_data *priv = bridge->priv;
203
204 return priv->enable;
205}
206
207static const struct fpga_bridge_ops altera_freeze_br_br_ops = {
208 .enable_set = altera_freeze_br_enable_set,
209 .enable_show = altera_freeze_br_enable_show,
210};
211
212static const struct of_device_id altera_freeze_br_of_match[] = {
213 { .compatible = "altr,freeze-bridge-controller", },
214 {},
215};
216MODULE_DEVICE_TABLE(of, altera_freeze_br_of_match);
217
218static int altera_freeze_br_probe(struct platform_device *pdev)
219{
220 struct device *dev = &pdev->dev;
221 struct device_node *np = pdev->dev.of_node;
222 void __iomem *base_addr;
223 struct altera_freeze_br_data *priv;
224 struct resource *res;
225 u32 status, revision;
226
227 if (!np)
228 return -ENODEV;
229
230 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
231 base_addr = devm_ioremap_resource(dev, res);
232 if (IS_ERR(base_addr))
233 return PTR_ERR(base_addr);
234
235 revision = readl(base_addr + FREEZE_CSR_REG_VERSION);
236 if ((revision != FREEZE_CSR_SUPPORTED_VERSION) &&
237 (revision != FREEZE_CSR_OFFICIAL_VERSION)) {
238 dev_err(dev,
239 "%s unexpected revision 0x%x != 0x%x != 0x%x\n",
240 __func__, revision, FREEZE_CSR_SUPPORTED_VERSION,
241 FREEZE_CSR_OFFICIAL_VERSION);
242 return -EINVAL;
243 }
244
245 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
246 if (!priv)
247 return -ENOMEM;
248
249 priv->dev = dev;
250
251 status = readl(base_addr + FREEZE_CSR_STATUS_OFFSET);
252 if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)
253 priv->enable = 1;
254
255 priv->base_addr = base_addr;
256
257 return fpga_bridge_register(dev, FREEZE_BRIDGE_NAME,
258 &altera_freeze_br_br_ops, priv);
259}
260
261static int altera_freeze_br_remove(struct platform_device *pdev)
262{
263 fpga_bridge_unregister(&pdev->dev);
264
265 return 0;
266}
267
268static struct platform_driver altera_freeze_br_driver = {
269 .probe = altera_freeze_br_probe,
270 .remove = altera_freeze_br_remove,
271 .driver = {
272 .name = "altera_freeze_br",
273 .of_match_table = of_match_ptr(altera_freeze_br_of_match),
274 },
275};
276
277module_platform_driver(altera_freeze_br_driver);
278
279MODULE_DESCRIPTION("Altera Freeze Bridge");
280MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
281MODULE_LICENSE("GPL v2");