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1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (C) 2017 Broadcom
3
4/*
5 * Broadcom SBA RAID Driver
6 *
7 * The Broadcom stream buffer accelerator (SBA) provides offloading
8 * capabilities for RAID operations. The SBA offload engine is accessible
9 * via Broadcom SoC specific ring manager. Two or more offload engines
10 * can share same Broadcom SoC specific ring manager due to this Broadcom
11 * SoC specific ring manager driver is implemented as a mailbox controller
12 * driver and offload engine drivers are implemented as mallbox clients.
13 *
14 * Typically, Broadcom SoC specific ring manager will implement larger
15 * number of hardware rings over one or more SBA hardware devices. By
16 * design, the internal buffer size of SBA hardware device is limited
17 * but all offload operations supported by SBA can be broken down into
18 * multiple small size requests and executed parallely on multiple SBA
19 * hardware devices for achieving high through-put.
20 *
21 * The Broadcom SBA RAID driver does not require any register programming
22 * except submitting request to SBA hardware device via mailbox channels.
23 * This driver implements a DMA device with one DMA channel using a single
24 * mailbox channel provided by Broadcom SoC specific ring manager driver.
25 * For having more SBA DMA channels, we can create more SBA device nodes
26 * in Broadcom SoC specific DTS based on number of hardware rings supported
27 * by Broadcom SoC ring manager.
28 */
29
30#include <linux/bitops.h>
31#include <linux/debugfs.h>
32#include <linux/dma-mapping.h>
33#include <linux/dmaengine.h>
34#include <linux/list.h>
35#include <linux/mailbox_client.h>
36#include <linux/mailbox/brcm-message.h>
37#include <linux/module.h>
38#include <linux/of_device.h>
39#include <linux/slab.h>
40#include <linux/raid/pq.h>
41
42#include "dmaengine.h"
43
44/* ====== Driver macros and defines ===== */
45
46#define SBA_TYPE_SHIFT 48
47#define SBA_TYPE_MASK GENMASK(1, 0)
48#define SBA_TYPE_A 0x0
49#define SBA_TYPE_B 0x2
50#define SBA_TYPE_C 0x3
51#define SBA_USER_DEF_SHIFT 32
52#define SBA_USER_DEF_MASK GENMASK(15, 0)
53#define SBA_R_MDATA_SHIFT 24
54#define SBA_R_MDATA_MASK GENMASK(7, 0)
55#define SBA_C_MDATA_MS_SHIFT 18
56#define SBA_C_MDATA_MS_MASK GENMASK(1, 0)
57#define SBA_INT_SHIFT 17
58#define SBA_INT_MASK BIT(0)
59#define SBA_RESP_SHIFT 16
60#define SBA_RESP_MASK BIT(0)
61#define SBA_C_MDATA_SHIFT 8
62#define SBA_C_MDATA_MASK GENMASK(7, 0)
63#define SBA_C_MDATA_BNUMx_SHIFT(__bnum) (2 * (__bnum))
64#define SBA_C_MDATA_BNUMx_MASK GENMASK(1, 0)
65#define SBA_C_MDATA_DNUM_SHIFT 5
66#define SBA_C_MDATA_DNUM_MASK GENMASK(4, 0)
67#define SBA_C_MDATA_LS(__v) ((__v) & 0xff)
68#define SBA_C_MDATA_MS(__v) (((__v) >> 8) & 0x3)
69#define SBA_CMD_SHIFT 0
70#define SBA_CMD_MASK GENMASK(3, 0)
71#define SBA_CMD_ZERO_BUFFER 0x4
72#define SBA_CMD_ZERO_ALL_BUFFERS 0x8
73#define SBA_CMD_LOAD_BUFFER 0x9
74#define SBA_CMD_XOR 0xa
75#define SBA_CMD_GALOIS_XOR 0xb
76#define SBA_CMD_WRITE_BUFFER 0xc
77#define SBA_CMD_GALOIS 0xe
78
79#define SBA_MAX_REQ_PER_MBOX_CHANNEL 8192
80#define SBA_MAX_MSG_SEND_PER_MBOX_CHANNEL 8
81
82/* Driver helper macros */
83#define to_sba_request(tx) \
84 container_of(tx, struct sba_request, tx)
85#define to_sba_device(dchan) \
86 container_of(dchan, struct sba_device, dma_chan)
87
88/* ===== Driver data structures ===== */
89
90enum sba_request_flags {
91 SBA_REQUEST_STATE_FREE = 0x001,
92 SBA_REQUEST_STATE_ALLOCED = 0x002,
93 SBA_REQUEST_STATE_PENDING = 0x004,
94 SBA_REQUEST_STATE_ACTIVE = 0x008,
95 SBA_REQUEST_STATE_ABORTED = 0x010,
96 SBA_REQUEST_STATE_MASK = 0x0ff,
97 SBA_REQUEST_FENCE = 0x100,
98};
99
100struct sba_request {
101 /* Global state */
102 struct list_head node;
103 struct sba_device *sba;
104 u32 flags;
105 /* Chained requests management */
106 struct sba_request *first;
107 struct list_head next;
108 atomic_t next_pending_count;
109 /* BRCM message data */
110 struct brcm_message msg;
111 struct dma_async_tx_descriptor tx;
112 /* SBA commands */
113 struct brcm_sba_command cmds[];
114};
115
116enum sba_version {
117 SBA_VER_1 = 0,
118 SBA_VER_2
119};
120
121struct sba_device {
122 /* Underlying device */
123 struct device *dev;
124 /* DT configuration parameters */
125 enum sba_version ver;
126 /* Derived configuration parameters */
127 u32 max_req;
128 u32 hw_buf_size;
129 u32 hw_resp_size;
130 u32 max_pq_coefs;
131 u32 max_pq_srcs;
132 u32 max_cmd_per_req;
133 u32 max_xor_srcs;
134 u32 max_resp_pool_size;
135 u32 max_cmds_pool_size;
136 /* Maibox client and Mailbox channels */
137 struct mbox_client client;
138 struct mbox_chan *mchan;
139 struct device *mbox_dev;
140 /* DMA device and DMA channel */
141 struct dma_device dma_dev;
142 struct dma_chan dma_chan;
143 /* DMA channel resources */
144 void *resp_base;
145 dma_addr_t resp_dma_base;
146 void *cmds_base;
147 dma_addr_t cmds_dma_base;
148 spinlock_t reqs_lock;
149 bool reqs_fence;
150 struct list_head reqs_alloc_list;
151 struct list_head reqs_pending_list;
152 struct list_head reqs_active_list;
153 struct list_head reqs_aborted_list;
154 struct list_head reqs_free_list;
155 /* DebugFS directory entries */
156 struct dentry *root;
157};
158
159/* ====== Command helper routines ===== */
160
161static inline u64 __pure sba_cmd_enc(u64 cmd, u32 val, u32 shift, u32 mask)
162{
163 cmd &= ~((u64)mask << shift);
164 cmd |= ((u64)(val & mask) << shift);
165 return cmd;
166}
167
168static inline u32 __pure sba_cmd_load_c_mdata(u32 b0)
169{
170 return b0 & SBA_C_MDATA_BNUMx_MASK;
171}
172
173static inline u32 __pure sba_cmd_write_c_mdata(u32 b0)
174{
175 return b0 & SBA_C_MDATA_BNUMx_MASK;
176}
177
178static inline u32 __pure sba_cmd_xor_c_mdata(u32 b1, u32 b0)
179{
180 return (b0 & SBA_C_MDATA_BNUMx_MASK) |
181 ((b1 & SBA_C_MDATA_BNUMx_MASK) << SBA_C_MDATA_BNUMx_SHIFT(1));
182}
183
184static inline u32 __pure sba_cmd_pq_c_mdata(u32 d, u32 b1, u32 b0)
185{
186 return (b0 & SBA_C_MDATA_BNUMx_MASK) |
187 ((b1 & SBA_C_MDATA_BNUMx_MASK) << SBA_C_MDATA_BNUMx_SHIFT(1)) |
188 ((d & SBA_C_MDATA_DNUM_MASK) << SBA_C_MDATA_DNUM_SHIFT);
189}
190
191/* ====== General helper routines ===== */
192
193static struct sba_request *sba_alloc_request(struct sba_device *sba)
194{
195 bool found = false;
196 unsigned long flags;
197 struct sba_request *req = NULL;
198
199 spin_lock_irqsave(&sba->reqs_lock, flags);
200 list_for_each_entry(req, &sba->reqs_free_list, node) {
201 if (async_tx_test_ack(&req->tx)) {
202 list_move_tail(&req->node, &sba->reqs_alloc_list);
203 found = true;
204 break;
205 }
206 }
207 spin_unlock_irqrestore(&sba->reqs_lock, flags);
208
209 if (!found) {
210 /*
211 * We have no more free requests so, we peek
212 * mailbox channels hoping few active requests
213 * would have completed which will create more
214 * room for new requests.
215 */
216 mbox_client_peek_data(sba->mchan);
217 return NULL;
218 }
219
220 req->flags = SBA_REQUEST_STATE_ALLOCED;
221 req->first = req;
222 INIT_LIST_HEAD(&req->next);
223 atomic_set(&req->next_pending_count, 1);
224
225 dma_async_tx_descriptor_init(&req->tx, &sba->dma_chan);
226 async_tx_ack(&req->tx);
227
228 return req;
229}
230
231/* Note: Must be called with sba->reqs_lock held */
232static void _sba_pending_request(struct sba_device *sba,
233 struct sba_request *req)
234{
235 lockdep_assert_held(&sba->reqs_lock);
236 req->flags &= ~SBA_REQUEST_STATE_MASK;
237 req->flags |= SBA_REQUEST_STATE_PENDING;
238 list_move_tail(&req->node, &sba->reqs_pending_list);
239 if (list_empty(&sba->reqs_active_list))
240 sba->reqs_fence = false;
241}
242
243/* Note: Must be called with sba->reqs_lock held */
244static bool _sba_active_request(struct sba_device *sba,
245 struct sba_request *req)
246{
247 lockdep_assert_held(&sba->reqs_lock);
248 if (list_empty(&sba->reqs_active_list))
249 sba->reqs_fence = false;
250 if (sba->reqs_fence)
251 return false;
252 req->flags &= ~SBA_REQUEST_STATE_MASK;
253 req->flags |= SBA_REQUEST_STATE_ACTIVE;
254 list_move_tail(&req->node, &sba->reqs_active_list);
255 if (req->flags & SBA_REQUEST_FENCE)
256 sba->reqs_fence = true;
257 return true;
258}
259
260/* Note: Must be called with sba->reqs_lock held */
261static void _sba_abort_request(struct sba_device *sba,
262 struct sba_request *req)
263{
264 lockdep_assert_held(&sba->reqs_lock);
265 req->flags &= ~SBA_REQUEST_STATE_MASK;
266 req->flags |= SBA_REQUEST_STATE_ABORTED;
267 list_move_tail(&req->node, &sba->reqs_aborted_list);
268 if (list_empty(&sba->reqs_active_list))
269 sba->reqs_fence = false;
270}
271
272/* Note: Must be called with sba->reqs_lock held */
273static void _sba_free_request(struct sba_device *sba,
274 struct sba_request *req)
275{
276 lockdep_assert_held(&sba->reqs_lock);
277 req->flags &= ~SBA_REQUEST_STATE_MASK;
278 req->flags |= SBA_REQUEST_STATE_FREE;
279 list_move_tail(&req->node, &sba->reqs_free_list);
280 if (list_empty(&sba->reqs_active_list))
281 sba->reqs_fence = false;
282}
283
284static void sba_free_chained_requests(struct sba_request *req)
285{
286 unsigned long flags;
287 struct sba_request *nreq;
288 struct sba_device *sba = req->sba;
289
290 spin_lock_irqsave(&sba->reqs_lock, flags);
291
292 _sba_free_request(sba, req);
293 list_for_each_entry(nreq, &req->next, next)
294 _sba_free_request(sba, nreq);
295
296 spin_unlock_irqrestore(&sba->reqs_lock, flags);
297}
298
299static void sba_chain_request(struct sba_request *first,
300 struct sba_request *req)
301{
302 unsigned long flags;
303 struct sba_device *sba = req->sba;
304
305 spin_lock_irqsave(&sba->reqs_lock, flags);
306
307 list_add_tail(&req->next, &first->next);
308 req->first = first;
309 atomic_inc(&first->next_pending_count);
310
311 spin_unlock_irqrestore(&sba->reqs_lock, flags);
312}
313
314static void sba_cleanup_nonpending_requests(struct sba_device *sba)
315{
316 unsigned long flags;
317 struct sba_request *req, *req1;
318
319 spin_lock_irqsave(&sba->reqs_lock, flags);
320
321 /* Freeup all alloced request */
322 list_for_each_entry_safe(req, req1, &sba->reqs_alloc_list, node)
323 _sba_free_request(sba, req);
324
325 /* Set all active requests as aborted */
326 list_for_each_entry_safe(req, req1, &sba->reqs_active_list, node)
327 _sba_abort_request(sba, req);
328
329 /*
330 * Note: We expect that aborted request will be eventually
331 * freed by sba_receive_message()
332 */
333
334 spin_unlock_irqrestore(&sba->reqs_lock, flags);
335}
336
337static void sba_cleanup_pending_requests(struct sba_device *sba)
338{
339 unsigned long flags;
340 struct sba_request *req, *req1;
341
342 spin_lock_irqsave(&sba->reqs_lock, flags);
343
344 /* Freeup all pending request */
345 list_for_each_entry_safe(req, req1, &sba->reqs_pending_list, node)
346 _sba_free_request(sba, req);
347
348 spin_unlock_irqrestore(&sba->reqs_lock, flags);
349}
350
351static int sba_send_mbox_request(struct sba_device *sba,
352 struct sba_request *req)
353{
354 int ret = 0;
355
356 /* Send message for the request */
357 req->msg.error = 0;
358 ret = mbox_send_message(sba->mchan, &req->msg);
359 if (ret < 0) {
360 dev_err(sba->dev, "send message failed with error %d", ret);
361 return ret;
362 }
363
364 /* Check error returned by mailbox controller */
365 ret = req->msg.error;
366 if (ret < 0) {
367 dev_err(sba->dev, "message error %d", ret);
368 }
369
370 /* Signal txdone for mailbox channel */
371 mbox_client_txdone(sba->mchan, ret);
372
373 return ret;
374}
375
376/* Note: Must be called with sba->reqs_lock held */
377static void _sba_process_pending_requests(struct sba_device *sba)
378{
379 int ret;
380 u32 count;
381 struct sba_request *req;
382
383 /* Process few pending requests */
384 count = SBA_MAX_MSG_SEND_PER_MBOX_CHANNEL;
385 while (!list_empty(&sba->reqs_pending_list) && count) {
386 /* Get the first pending request */
387 req = list_first_entry(&sba->reqs_pending_list,
388 struct sba_request, node);
389
390 /* Try to make request active */
391 if (!_sba_active_request(sba, req))
392 break;
393
394 /* Send request to mailbox channel */
395 ret = sba_send_mbox_request(sba, req);
396 if (ret < 0) {
397 _sba_pending_request(sba, req);
398 break;
399 }
400
401 count--;
402 }
403}
404
405static void sba_process_received_request(struct sba_device *sba,
406 struct sba_request *req)
407{
408 unsigned long flags;
409 struct dma_async_tx_descriptor *tx;
410 struct sba_request *nreq, *first = req->first;
411
412 /* Process only after all chained requests are received */
413 if (!atomic_dec_return(&first->next_pending_count)) {
414 tx = &first->tx;
415
416 WARN_ON(tx->cookie < 0);
417 if (tx->cookie > 0) {
418 spin_lock_irqsave(&sba->reqs_lock, flags);
419 dma_cookie_complete(tx);
420 spin_unlock_irqrestore(&sba->reqs_lock, flags);
421 dmaengine_desc_get_callback_invoke(tx, NULL);
422 dma_descriptor_unmap(tx);
423 tx->callback = NULL;
424 tx->callback_result = NULL;
425 }
426
427 dma_run_dependencies(tx);
428
429 spin_lock_irqsave(&sba->reqs_lock, flags);
430
431 /* Free all requests chained to first request */
432 list_for_each_entry(nreq, &first->next, next)
433 _sba_free_request(sba, nreq);
434 INIT_LIST_HEAD(&first->next);
435
436 /* Free the first request */
437 _sba_free_request(sba, first);
438
439 /* Process pending requests */
440 _sba_process_pending_requests(sba);
441
442 spin_unlock_irqrestore(&sba->reqs_lock, flags);
443 }
444}
445
446static void sba_write_stats_in_seqfile(struct sba_device *sba,
447 struct seq_file *file)
448{
449 unsigned long flags;
450 struct sba_request *req;
451 u32 free_count = 0, alloced_count = 0;
452 u32 pending_count = 0, active_count = 0, aborted_count = 0;
453
454 spin_lock_irqsave(&sba->reqs_lock, flags);
455
456 list_for_each_entry(req, &sba->reqs_free_list, node)
457 if (async_tx_test_ack(&req->tx))
458 free_count++;
459
460 list_for_each_entry(req, &sba->reqs_alloc_list, node)
461 alloced_count++;
462
463 list_for_each_entry(req, &sba->reqs_pending_list, node)
464 pending_count++;
465
466 list_for_each_entry(req, &sba->reqs_active_list, node)
467 active_count++;
468
469 list_for_each_entry(req, &sba->reqs_aborted_list, node)
470 aborted_count++;
471
472 spin_unlock_irqrestore(&sba->reqs_lock, flags);
473
474 seq_printf(file, "maximum requests = %d\n", sba->max_req);
475 seq_printf(file, "free requests = %d\n", free_count);
476 seq_printf(file, "alloced requests = %d\n", alloced_count);
477 seq_printf(file, "pending requests = %d\n", pending_count);
478 seq_printf(file, "active requests = %d\n", active_count);
479 seq_printf(file, "aborted requests = %d\n", aborted_count);
480}
481
482/* ====== DMAENGINE callbacks ===== */
483
484static void sba_free_chan_resources(struct dma_chan *dchan)
485{
486 /*
487 * Channel resources are pre-alloced so we just free-up
488 * whatever we can so that we can re-use pre-alloced
489 * channel resources next time.
490 */
491 sba_cleanup_nonpending_requests(to_sba_device(dchan));
492}
493
494static int sba_device_terminate_all(struct dma_chan *dchan)
495{
496 /* Cleanup all pending requests */
497 sba_cleanup_pending_requests(to_sba_device(dchan));
498
499 return 0;
500}
501
502static void sba_issue_pending(struct dma_chan *dchan)
503{
504 unsigned long flags;
505 struct sba_device *sba = to_sba_device(dchan);
506
507 /* Process pending requests */
508 spin_lock_irqsave(&sba->reqs_lock, flags);
509 _sba_process_pending_requests(sba);
510 spin_unlock_irqrestore(&sba->reqs_lock, flags);
511}
512
513static dma_cookie_t sba_tx_submit(struct dma_async_tx_descriptor *tx)
514{
515 unsigned long flags;
516 dma_cookie_t cookie;
517 struct sba_device *sba;
518 struct sba_request *req, *nreq;
519
520 if (unlikely(!tx))
521 return -EINVAL;
522
523 sba = to_sba_device(tx->chan);
524 req = to_sba_request(tx);
525
526 /* Assign cookie and mark all chained requests pending */
527 spin_lock_irqsave(&sba->reqs_lock, flags);
528 cookie = dma_cookie_assign(tx);
529 _sba_pending_request(sba, req);
530 list_for_each_entry(nreq, &req->next, next)
531 _sba_pending_request(sba, nreq);
532 spin_unlock_irqrestore(&sba->reqs_lock, flags);
533
534 return cookie;
535}
536
537static enum dma_status sba_tx_status(struct dma_chan *dchan,
538 dma_cookie_t cookie,
539 struct dma_tx_state *txstate)
540{
541 enum dma_status ret;
542 struct sba_device *sba = to_sba_device(dchan);
543
544 ret = dma_cookie_status(dchan, cookie, txstate);
545 if (ret == DMA_COMPLETE)
546 return ret;
547
548 mbox_client_peek_data(sba->mchan);
549
550 return dma_cookie_status(dchan, cookie, txstate);
551}
552
553static void sba_fillup_interrupt_msg(struct sba_request *req,
554 struct brcm_sba_command *cmds,
555 struct brcm_message *msg)
556{
557 u64 cmd;
558 u32 c_mdata;
559 dma_addr_t resp_dma = req->tx.phys;
560 struct brcm_sba_command *cmdsp = cmds;
561
562 /* Type-B command to load dummy data into buf0 */
563 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
564 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
565 cmd = sba_cmd_enc(cmd, req->sba->hw_resp_size,
566 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
567 c_mdata = sba_cmd_load_c_mdata(0);
568 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
569 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
570 cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
571 SBA_CMD_SHIFT, SBA_CMD_MASK);
572 cmdsp->cmd = cmd;
573 *cmdsp->cmd_dma = cpu_to_le64(cmd);
574 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
575 cmdsp->data = resp_dma;
576 cmdsp->data_len = req->sba->hw_resp_size;
577 cmdsp++;
578
579 /* Type-A command to write buf0 to dummy location */
580 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
581 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
582 cmd = sba_cmd_enc(cmd, req->sba->hw_resp_size,
583 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
584 cmd = sba_cmd_enc(cmd, 0x1,
585 SBA_RESP_SHIFT, SBA_RESP_MASK);
586 c_mdata = sba_cmd_write_c_mdata(0);
587 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
588 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
589 cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
590 SBA_CMD_SHIFT, SBA_CMD_MASK);
591 cmdsp->cmd = cmd;
592 *cmdsp->cmd_dma = cpu_to_le64(cmd);
593 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
594 if (req->sba->hw_resp_size) {
595 cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
596 cmdsp->resp = resp_dma;
597 cmdsp->resp_len = req->sba->hw_resp_size;
598 }
599 cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
600 cmdsp->data = resp_dma;
601 cmdsp->data_len = req->sba->hw_resp_size;
602 cmdsp++;
603
604 /* Fillup brcm_message */
605 msg->type = BRCM_MESSAGE_SBA;
606 msg->sba.cmds = cmds;
607 msg->sba.cmds_count = cmdsp - cmds;
608 msg->ctx = req;
609 msg->error = 0;
610}
611
612static struct dma_async_tx_descriptor *
613sba_prep_dma_interrupt(struct dma_chan *dchan, unsigned long flags)
614{
615 struct sba_request *req = NULL;
616 struct sba_device *sba = to_sba_device(dchan);
617
618 /* Alloc new request */
619 req = sba_alloc_request(sba);
620 if (!req)
621 return NULL;
622
623 /*
624 * Force fence so that no requests are submitted
625 * until DMA callback for this request is invoked.
626 */
627 req->flags |= SBA_REQUEST_FENCE;
628
629 /* Fillup request message */
630 sba_fillup_interrupt_msg(req, req->cmds, &req->msg);
631
632 /* Init async_tx descriptor */
633 req->tx.flags = flags;
634 req->tx.cookie = -EBUSY;
635
636 return &req->tx;
637}
638
639static void sba_fillup_memcpy_msg(struct sba_request *req,
640 struct brcm_sba_command *cmds,
641 struct brcm_message *msg,
642 dma_addr_t msg_offset, size_t msg_len,
643 dma_addr_t dst, dma_addr_t src)
644{
645 u64 cmd;
646 u32 c_mdata;
647 dma_addr_t resp_dma = req->tx.phys;
648 struct brcm_sba_command *cmdsp = cmds;
649
650 /* Type-B command to load data into buf0 */
651 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
652 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
653 cmd = sba_cmd_enc(cmd, msg_len,
654 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
655 c_mdata = sba_cmd_load_c_mdata(0);
656 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
657 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
658 cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
659 SBA_CMD_SHIFT, SBA_CMD_MASK);
660 cmdsp->cmd = cmd;
661 *cmdsp->cmd_dma = cpu_to_le64(cmd);
662 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
663 cmdsp->data = src + msg_offset;
664 cmdsp->data_len = msg_len;
665 cmdsp++;
666
667 /* Type-A command to write buf0 */
668 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
669 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
670 cmd = sba_cmd_enc(cmd, msg_len,
671 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
672 cmd = sba_cmd_enc(cmd, 0x1,
673 SBA_RESP_SHIFT, SBA_RESP_MASK);
674 c_mdata = sba_cmd_write_c_mdata(0);
675 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
676 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
677 cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
678 SBA_CMD_SHIFT, SBA_CMD_MASK);
679 cmdsp->cmd = cmd;
680 *cmdsp->cmd_dma = cpu_to_le64(cmd);
681 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
682 if (req->sba->hw_resp_size) {
683 cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
684 cmdsp->resp = resp_dma;
685 cmdsp->resp_len = req->sba->hw_resp_size;
686 }
687 cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
688 cmdsp->data = dst + msg_offset;
689 cmdsp->data_len = msg_len;
690 cmdsp++;
691
692 /* Fillup brcm_message */
693 msg->type = BRCM_MESSAGE_SBA;
694 msg->sba.cmds = cmds;
695 msg->sba.cmds_count = cmdsp - cmds;
696 msg->ctx = req;
697 msg->error = 0;
698}
699
700static struct sba_request *
701sba_prep_dma_memcpy_req(struct sba_device *sba,
702 dma_addr_t off, dma_addr_t dst, dma_addr_t src,
703 size_t len, unsigned long flags)
704{
705 struct sba_request *req = NULL;
706
707 /* Alloc new request */
708 req = sba_alloc_request(sba);
709 if (!req)
710 return NULL;
711 if (flags & DMA_PREP_FENCE)
712 req->flags |= SBA_REQUEST_FENCE;
713
714 /* Fillup request message */
715 sba_fillup_memcpy_msg(req, req->cmds, &req->msg,
716 off, len, dst, src);
717
718 /* Init async_tx descriptor */
719 req->tx.flags = flags;
720 req->tx.cookie = -EBUSY;
721
722 return req;
723}
724
725static struct dma_async_tx_descriptor *
726sba_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src,
727 size_t len, unsigned long flags)
728{
729 size_t req_len;
730 dma_addr_t off = 0;
731 struct sba_device *sba = to_sba_device(dchan);
732 struct sba_request *first = NULL, *req;
733
734 /* Create chained requests where each request is upto hw_buf_size */
735 while (len) {
736 req_len = (len < sba->hw_buf_size) ? len : sba->hw_buf_size;
737
738 req = sba_prep_dma_memcpy_req(sba, off, dst, src,
739 req_len, flags);
740 if (!req) {
741 if (first)
742 sba_free_chained_requests(first);
743 return NULL;
744 }
745
746 if (first)
747 sba_chain_request(first, req);
748 else
749 first = req;
750
751 off += req_len;
752 len -= req_len;
753 }
754
755 return (first) ? &first->tx : NULL;
756}
757
758static void sba_fillup_xor_msg(struct sba_request *req,
759 struct brcm_sba_command *cmds,
760 struct brcm_message *msg,
761 dma_addr_t msg_offset, size_t msg_len,
762 dma_addr_t dst, dma_addr_t *src, u32 src_cnt)
763{
764 u64 cmd;
765 u32 c_mdata;
766 unsigned int i;
767 dma_addr_t resp_dma = req->tx.phys;
768 struct brcm_sba_command *cmdsp = cmds;
769
770 /* Type-B command to load data into buf0 */
771 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
772 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
773 cmd = sba_cmd_enc(cmd, msg_len,
774 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
775 c_mdata = sba_cmd_load_c_mdata(0);
776 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
777 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
778 cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
779 SBA_CMD_SHIFT, SBA_CMD_MASK);
780 cmdsp->cmd = cmd;
781 *cmdsp->cmd_dma = cpu_to_le64(cmd);
782 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
783 cmdsp->data = src[0] + msg_offset;
784 cmdsp->data_len = msg_len;
785 cmdsp++;
786
787 /* Type-B commands to xor data with buf0 and put it back in buf0 */
788 for (i = 1; i < src_cnt; i++) {
789 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
790 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
791 cmd = sba_cmd_enc(cmd, msg_len,
792 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
793 c_mdata = sba_cmd_xor_c_mdata(0, 0);
794 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
795 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
796 cmd = sba_cmd_enc(cmd, SBA_CMD_XOR,
797 SBA_CMD_SHIFT, SBA_CMD_MASK);
798 cmdsp->cmd = cmd;
799 *cmdsp->cmd_dma = cpu_to_le64(cmd);
800 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
801 cmdsp->data = src[i] + msg_offset;
802 cmdsp->data_len = msg_len;
803 cmdsp++;
804 }
805
806 /* Type-A command to write buf0 */
807 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
808 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
809 cmd = sba_cmd_enc(cmd, msg_len,
810 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
811 cmd = sba_cmd_enc(cmd, 0x1,
812 SBA_RESP_SHIFT, SBA_RESP_MASK);
813 c_mdata = sba_cmd_write_c_mdata(0);
814 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
815 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
816 cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
817 SBA_CMD_SHIFT, SBA_CMD_MASK);
818 cmdsp->cmd = cmd;
819 *cmdsp->cmd_dma = cpu_to_le64(cmd);
820 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
821 if (req->sba->hw_resp_size) {
822 cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
823 cmdsp->resp = resp_dma;
824 cmdsp->resp_len = req->sba->hw_resp_size;
825 }
826 cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
827 cmdsp->data = dst + msg_offset;
828 cmdsp->data_len = msg_len;
829 cmdsp++;
830
831 /* Fillup brcm_message */
832 msg->type = BRCM_MESSAGE_SBA;
833 msg->sba.cmds = cmds;
834 msg->sba.cmds_count = cmdsp - cmds;
835 msg->ctx = req;
836 msg->error = 0;
837}
838
839static struct sba_request *
840sba_prep_dma_xor_req(struct sba_device *sba,
841 dma_addr_t off, dma_addr_t dst, dma_addr_t *src,
842 u32 src_cnt, size_t len, unsigned long flags)
843{
844 struct sba_request *req = NULL;
845
846 /* Alloc new request */
847 req = sba_alloc_request(sba);
848 if (!req)
849 return NULL;
850 if (flags & DMA_PREP_FENCE)
851 req->flags |= SBA_REQUEST_FENCE;
852
853 /* Fillup request message */
854 sba_fillup_xor_msg(req, req->cmds, &req->msg,
855 off, len, dst, src, src_cnt);
856
857 /* Init async_tx descriptor */
858 req->tx.flags = flags;
859 req->tx.cookie = -EBUSY;
860
861 return req;
862}
863
864static struct dma_async_tx_descriptor *
865sba_prep_dma_xor(struct dma_chan *dchan, dma_addr_t dst, dma_addr_t *src,
866 u32 src_cnt, size_t len, unsigned long flags)
867{
868 size_t req_len;
869 dma_addr_t off = 0;
870 struct sba_device *sba = to_sba_device(dchan);
871 struct sba_request *first = NULL, *req;
872
873 /* Sanity checks */
874 if (unlikely(src_cnt > sba->max_xor_srcs))
875 return NULL;
876
877 /* Create chained requests where each request is upto hw_buf_size */
878 while (len) {
879 req_len = (len < sba->hw_buf_size) ? len : sba->hw_buf_size;
880
881 req = sba_prep_dma_xor_req(sba, off, dst, src, src_cnt,
882 req_len, flags);
883 if (!req) {
884 if (first)
885 sba_free_chained_requests(first);
886 return NULL;
887 }
888
889 if (first)
890 sba_chain_request(first, req);
891 else
892 first = req;
893
894 off += req_len;
895 len -= req_len;
896 }
897
898 return (first) ? &first->tx : NULL;
899}
900
901static void sba_fillup_pq_msg(struct sba_request *req,
902 bool pq_continue,
903 struct brcm_sba_command *cmds,
904 struct brcm_message *msg,
905 dma_addr_t msg_offset, size_t msg_len,
906 dma_addr_t *dst_p, dma_addr_t *dst_q,
907 const u8 *scf, dma_addr_t *src, u32 src_cnt)
908{
909 u64 cmd;
910 u32 c_mdata;
911 unsigned int i;
912 dma_addr_t resp_dma = req->tx.phys;
913 struct brcm_sba_command *cmdsp = cmds;
914
915 if (pq_continue) {
916 /* Type-B command to load old P into buf0 */
917 if (dst_p) {
918 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
919 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
920 cmd = sba_cmd_enc(cmd, msg_len,
921 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
922 c_mdata = sba_cmd_load_c_mdata(0);
923 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
924 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
925 cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
926 SBA_CMD_SHIFT, SBA_CMD_MASK);
927 cmdsp->cmd = cmd;
928 *cmdsp->cmd_dma = cpu_to_le64(cmd);
929 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
930 cmdsp->data = *dst_p + msg_offset;
931 cmdsp->data_len = msg_len;
932 cmdsp++;
933 }
934
935 /* Type-B command to load old Q into buf1 */
936 if (dst_q) {
937 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
938 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
939 cmd = sba_cmd_enc(cmd, msg_len,
940 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
941 c_mdata = sba_cmd_load_c_mdata(1);
942 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
943 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
944 cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
945 SBA_CMD_SHIFT, SBA_CMD_MASK);
946 cmdsp->cmd = cmd;
947 *cmdsp->cmd_dma = cpu_to_le64(cmd);
948 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
949 cmdsp->data = *dst_q + msg_offset;
950 cmdsp->data_len = msg_len;
951 cmdsp++;
952 }
953 } else {
954 /* Type-A command to zero all buffers */
955 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
956 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
957 cmd = sba_cmd_enc(cmd, msg_len,
958 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
959 cmd = sba_cmd_enc(cmd, SBA_CMD_ZERO_ALL_BUFFERS,
960 SBA_CMD_SHIFT, SBA_CMD_MASK);
961 cmdsp->cmd = cmd;
962 *cmdsp->cmd_dma = cpu_to_le64(cmd);
963 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
964 cmdsp++;
965 }
966
967 /* Type-B commands for generate P onto buf0 and Q onto buf1 */
968 for (i = 0; i < src_cnt; i++) {
969 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
970 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
971 cmd = sba_cmd_enc(cmd, msg_len,
972 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
973 c_mdata = sba_cmd_pq_c_mdata(raid6_gflog[scf[i]], 1, 0);
974 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
975 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
976 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_MS(c_mdata),
977 SBA_C_MDATA_MS_SHIFT, SBA_C_MDATA_MS_MASK);
978 cmd = sba_cmd_enc(cmd, SBA_CMD_GALOIS_XOR,
979 SBA_CMD_SHIFT, SBA_CMD_MASK);
980 cmdsp->cmd = cmd;
981 *cmdsp->cmd_dma = cpu_to_le64(cmd);
982 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
983 cmdsp->data = src[i] + msg_offset;
984 cmdsp->data_len = msg_len;
985 cmdsp++;
986 }
987
988 /* Type-A command to write buf0 */
989 if (dst_p) {
990 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
991 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
992 cmd = sba_cmd_enc(cmd, msg_len,
993 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
994 cmd = sba_cmd_enc(cmd, 0x1,
995 SBA_RESP_SHIFT, SBA_RESP_MASK);
996 c_mdata = sba_cmd_write_c_mdata(0);
997 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
998 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
999 cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
1000 SBA_CMD_SHIFT, SBA_CMD_MASK);
1001 cmdsp->cmd = cmd;
1002 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1003 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1004 if (req->sba->hw_resp_size) {
1005 cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
1006 cmdsp->resp = resp_dma;
1007 cmdsp->resp_len = req->sba->hw_resp_size;
1008 }
1009 cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
1010 cmdsp->data = *dst_p + msg_offset;
1011 cmdsp->data_len = msg_len;
1012 cmdsp++;
1013 }
1014
1015 /* Type-A command to write buf1 */
1016 if (dst_q) {
1017 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1018 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1019 cmd = sba_cmd_enc(cmd, msg_len,
1020 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1021 cmd = sba_cmd_enc(cmd, 0x1,
1022 SBA_RESP_SHIFT, SBA_RESP_MASK);
1023 c_mdata = sba_cmd_write_c_mdata(1);
1024 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1025 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1026 cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
1027 SBA_CMD_SHIFT, SBA_CMD_MASK);
1028 cmdsp->cmd = cmd;
1029 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1030 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1031 if (req->sba->hw_resp_size) {
1032 cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
1033 cmdsp->resp = resp_dma;
1034 cmdsp->resp_len = req->sba->hw_resp_size;
1035 }
1036 cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
1037 cmdsp->data = *dst_q + msg_offset;
1038 cmdsp->data_len = msg_len;
1039 cmdsp++;
1040 }
1041
1042 /* Fillup brcm_message */
1043 msg->type = BRCM_MESSAGE_SBA;
1044 msg->sba.cmds = cmds;
1045 msg->sba.cmds_count = cmdsp - cmds;
1046 msg->ctx = req;
1047 msg->error = 0;
1048}
1049
1050static struct sba_request *
1051sba_prep_dma_pq_req(struct sba_device *sba, dma_addr_t off,
1052 dma_addr_t *dst_p, dma_addr_t *dst_q, dma_addr_t *src,
1053 u32 src_cnt, const u8 *scf, size_t len, unsigned long flags)
1054{
1055 struct sba_request *req = NULL;
1056
1057 /* Alloc new request */
1058 req = sba_alloc_request(sba);
1059 if (!req)
1060 return NULL;
1061 if (flags & DMA_PREP_FENCE)
1062 req->flags |= SBA_REQUEST_FENCE;
1063
1064 /* Fillup request messages */
1065 sba_fillup_pq_msg(req, dmaf_continue(flags),
1066 req->cmds, &req->msg,
1067 off, len, dst_p, dst_q, scf, src, src_cnt);
1068
1069 /* Init async_tx descriptor */
1070 req->tx.flags = flags;
1071 req->tx.cookie = -EBUSY;
1072
1073 return req;
1074}
1075
1076static void sba_fillup_pq_single_msg(struct sba_request *req,
1077 bool pq_continue,
1078 struct brcm_sba_command *cmds,
1079 struct brcm_message *msg,
1080 dma_addr_t msg_offset, size_t msg_len,
1081 dma_addr_t *dst_p, dma_addr_t *dst_q,
1082 dma_addr_t src, u8 scf)
1083{
1084 u64 cmd;
1085 u32 c_mdata;
1086 u8 pos, dpos = raid6_gflog[scf];
1087 dma_addr_t resp_dma = req->tx.phys;
1088 struct brcm_sba_command *cmdsp = cmds;
1089
1090 if (!dst_p)
1091 goto skip_p;
1092
1093 if (pq_continue) {
1094 /* Type-B command to load old P into buf0 */
1095 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1096 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1097 cmd = sba_cmd_enc(cmd, msg_len,
1098 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1099 c_mdata = sba_cmd_load_c_mdata(0);
1100 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1101 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1102 cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
1103 SBA_CMD_SHIFT, SBA_CMD_MASK);
1104 cmdsp->cmd = cmd;
1105 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1106 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1107 cmdsp->data = *dst_p + msg_offset;
1108 cmdsp->data_len = msg_len;
1109 cmdsp++;
1110
1111 /*
1112 * Type-B commands to xor data with buf0 and put it
1113 * back in buf0
1114 */
1115 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1116 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1117 cmd = sba_cmd_enc(cmd, msg_len,
1118 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1119 c_mdata = sba_cmd_xor_c_mdata(0, 0);
1120 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1121 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1122 cmd = sba_cmd_enc(cmd, SBA_CMD_XOR,
1123 SBA_CMD_SHIFT, SBA_CMD_MASK);
1124 cmdsp->cmd = cmd;
1125 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1126 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1127 cmdsp->data = src + msg_offset;
1128 cmdsp->data_len = msg_len;
1129 cmdsp++;
1130 } else {
1131 /* Type-B command to load old P into buf0 */
1132 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1133 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1134 cmd = sba_cmd_enc(cmd, msg_len,
1135 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1136 c_mdata = sba_cmd_load_c_mdata(0);
1137 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1138 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1139 cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
1140 SBA_CMD_SHIFT, SBA_CMD_MASK);
1141 cmdsp->cmd = cmd;
1142 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1143 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1144 cmdsp->data = src + msg_offset;
1145 cmdsp->data_len = msg_len;
1146 cmdsp++;
1147 }
1148
1149 /* Type-A command to write buf0 */
1150 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1151 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1152 cmd = sba_cmd_enc(cmd, msg_len,
1153 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1154 cmd = sba_cmd_enc(cmd, 0x1,
1155 SBA_RESP_SHIFT, SBA_RESP_MASK);
1156 c_mdata = sba_cmd_write_c_mdata(0);
1157 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1158 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1159 cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
1160 SBA_CMD_SHIFT, SBA_CMD_MASK);
1161 cmdsp->cmd = cmd;
1162 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1163 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1164 if (req->sba->hw_resp_size) {
1165 cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
1166 cmdsp->resp = resp_dma;
1167 cmdsp->resp_len = req->sba->hw_resp_size;
1168 }
1169 cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
1170 cmdsp->data = *dst_p + msg_offset;
1171 cmdsp->data_len = msg_len;
1172 cmdsp++;
1173
1174skip_p:
1175 if (!dst_q)
1176 goto skip_q;
1177
1178 /* Type-A command to zero all buffers */
1179 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1180 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1181 cmd = sba_cmd_enc(cmd, msg_len,
1182 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1183 cmd = sba_cmd_enc(cmd, SBA_CMD_ZERO_ALL_BUFFERS,
1184 SBA_CMD_SHIFT, SBA_CMD_MASK);
1185 cmdsp->cmd = cmd;
1186 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1187 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1188 cmdsp++;
1189
1190 if (dpos == 255)
1191 goto skip_q_computation;
1192 pos = (dpos < req->sba->max_pq_coefs) ?
1193 dpos : (req->sba->max_pq_coefs - 1);
1194
1195 /*
1196 * Type-B command to generate initial Q from data
1197 * and store output into buf0
1198 */
1199 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1200 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1201 cmd = sba_cmd_enc(cmd, msg_len,
1202 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1203 c_mdata = sba_cmd_pq_c_mdata(pos, 0, 0);
1204 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1205 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1206 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_MS(c_mdata),
1207 SBA_C_MDATA_MS_SHIFT, SBA_C_MDATA_MS_MASK);
1208 cmd = sba_cmd_enc(cmd, SBA_CMD_GALOIS,
1209 SBA_CMD_SHIFT, SBA_CMD_MASK);
1210 cmdsp->cmd = cmd;
1211 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1212 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1213 cmdsp->data = src + msg_offset;
1214 cmdsp->data_len = msg_len;
1215 cmdsp++;
1216
1217 dpos -= pos;
1218
1219 /* Multiple Type-A command to generate final Q */
1220 while (dpos) {
1221 pos = (dpos < req->sba->max_pq_coefs) ?
1222 dpos : (req->sba->max_pq_coefs - 1);
1223
1224 /*
1225 * Type-A command to generate Q with buf0 and
1226 * buf1 store result in buf0
1227 */
1228 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1229 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1230 cmd = sba_cmd_enc(cmd, msg_len,
1231 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1232 c_mdata = sba_cmd_pq_c_mdata(pos, 0, 1);
1233 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1234 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1235 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_MS(c_mdata),
1236 SBA_C_MDATA_MS_SHIFT, SBA_C_MDATA_MS_MASK);
1237 cmd = sba_cmd_enc(cmd, SBA_CMD_GALOIS,
1238 SBA_CMD_SHIFT, SBA_CMD_MASK);
1239 cmdsp->cmd = cmd;
1240 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1241 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1242 cmdsp++;
1243
1244 dpos -= pos;
1245 }
1246
1247skip_q_computation:
1248 if (pq_continue) {
1249 /*
1250 * Type-B command to XOR previous output with
1251 * buf0 and write it into buf0
1252 */
1253 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1254 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1255 cmd = sba_cmd_enc(cmd, msg_len,
1256 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1257 c_mdata = sba_cmd_xor_c_mdata(0, 0);
1258 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1259 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1260 cmd = sba_cmd_enc(cmd, SBA_CMD_XOR,
1261 SBA_CMD_SHIFT, SBA_CMD_MASK);
1262 cmdsp->cmd = cmd;
1263 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1264 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1265 cmdsp->data = *dst_q + msg_offset;
1266 cmdsp->data_len = msg_len;
1267 cmdsp++;
1268 }
1269
1270 /* Type-A command to write buf0 */
1271 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1272 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1273 cmd = sba_cmd_enc(cmd, msg_len,
1274 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1275 cmd = sba_cmd_enc(cmd, 0x1,
1276 SBA_RESP_SHIFT, SBA_RESP_MASK);
1277 c_mdata = sba_cmd_write_c_mdata(0);
1278 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1279 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1280 cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
1281 SBA_CMD_SHIFT, SBA_CMD_MASK);
1282 cmdsp->cmd = cmd;
1283 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1284 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1285 if (req->sba->hw_resp_size) {
1286 cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
1287 cmdsp->resp = resp_dma;
1288 cmdsp->resp_len = req->sba->hw_resp_size;
1289 }
1290 cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
1291 cmdsp->data = *dst_q + msg_offset;
1292 cmdsp->data_len = msg_len;
1293 cmdsp++;
1294
1295skip_q:
1296 /* Fillup brcm_message */
1297 msg->type = BRCM_MESSAGE_SBA;
1298 msg->sba.cmds = cmds;
1299 msg->sba.cmds_count = cmdsp - cmds;
1300 msg->ctx = req;
1301 msg->error = 0;
1302}
1303
1304static struct sba_request *
1305sba_prep_dma_pq_single_req(struct sba_device *sba, dma_addr_t off,
1306 dma_addr_t *dst_p, dma_addr_t *dst_q,
1307 dma_addr_t src, u8 scf, size_t len,
1308 unsigned long flags)
1309{
1310 struct sba_request *req = NULL;
1311
1312 /* Alloc new request */
1313 req = sba_alloc_request(sba);
1314 if (!req)
1315 return NULL;
1316 if (flags & DMA_PREP_FENCE)
1317 req->flags |= SBA_REQUEST_FENCE;
1318
1319 /* Fillup request messages */
1320 sba_fillup_pq_single_msg(req, dmaf_continue(flags),
1321 req->cmds, &req->msg, off, len,
1322 dst_p, dst_q, src, scf);
1323
1324 /* Init async_tx descriptor */
1325 req->tx.flags = flags;
1326 req->tx.cookie = -EBUSY;
1327
1328 return req;
1329}
1330
1331static struct dma_async_tx_descriptor *
1332sba_prep_dma_pq(struct dma_chan *dchan, dma_addr_t *dst, dma_addr_t *src,
1333 u32 src_cnt, const u8 *scf, size_t len, unsigned long flags)
1334{
1335 u32 i, dst_q_index;
1336 size_t req_len;
1337 bool slow = false;
1338 dma_addr_t off = 0;
1339 dma_addr_t *dst_p = NULL, *dst_q = NULL;
1340 struct sba_device *sba = to_sba_device(dchan);
1341 struct sba_request *first = NULL, *req;
1342
1343 /* Sanity checks */
1344 if (unlikely(src_cnt > sba->max_pq_srcs))
1345 return NULL;
1346 for (i = 0; i < src_cnt; i++)
1347 if (sba->max_pq_coefs <= raid6_gflog[scf[i]])
1348 slow = true;
1349
1350 /* Figure-out P and Q destination addresses */
1351 if (!(flags & DMA_PREP_PQ_DISABLE_P))
1352 dst_p = &dst[0];
1353 if (!(flags & DMA_PREP_PQ_DISABLE_Q))
1354 dst_q = &dst[1];
1355
1356 /* Create chained requests where each request is upto hw_buf_size */
1357 while (len) {
1358 req_len = (len < sba->hw_buf_size) ? len : sba->hw_buf_size;
1359
1360 if (slow) {
1361 dst_q_index = src_cnt;
1362
1363 if (dst_q) {
1364 for (i = 0; i < src_cnt; i++) {
1365 if (*dst_q == src[i]) {
1366 dst_q_index = i;
1367 break;
1368 }
1369 }
1370 }
1371
1372 if (dst_q_index < src_cnt) {
1373 i = dst_q_index;
1374 req = sba_prep_dma_pq_single_req(sba,
1375 off, dst_p, dst_q, src[i], scf[i],
1376 req_len, flags | DMA_PREP_FENCE);
1377 if (!req)
1378 goto fail;
1379
1380 if (first)
1381 sba_chain_request(first, req);
1382 else
1383 first = req;
1384
1385 flags |= DMA_PREP_CONTINUE;
1386 }
1387
1388 for (i = 0; i < src_cnt; i++) {
1389 if (dst_q_index == i)
1390 continue;
1391
1392 req = sba_prep_dma_pq_single_req(sba,
1393 off, dst_p, dst_q, src[i], scf[i],
1394 req_len, flags | DMA_PREP_FENCE);
1395 if (!req)
1396 goto fail;
1397
1398 if (first)
1399 sba_chain_request(first, req);
1400 else
1401 first = req;
1402
1403 flags |= DMA_PREP_CONTINUE;
1404 }
1405 } else {
1406 req = sba_prep_dma_pq_req(sba, off,
1407 dst_p, dst_q, src, src_cnt,
1408 scf, req_len, flags);
1409 if (!req)
1410 goto fail;
1411
1412 if (first)
1413 sba_chain_request(first, req);
1414 else
1415 first = req;
1416 }
1417
1418 off += req_len;
1419 len -= req_len;
1420 }
1421
1422 return (first) ? &first->tx : NULL;
1423
1424fail:
1425 if (first)
1426 sba_free_chained_requests(first);
1427 return NULL;
1428}
1429
1430/* ====== Mailbox callbacks ===== */
1431
1432static void sba_receive_message(struct mbox_client *cl, void *msg)
1433{
1434 struct brcm_message *m = msg;
1435 struct sba_request *req = m->ctx;
1436 struct sba_device *sba = req->sba;
1437
1438 /* Error count if message has error */
1439 if (m->error < 0)
1440 dev_err(sba->dev, "%s got message with error %d",
1441 dma_chan_name(&sba->dma_chan), m->error);
1442
1443 /* Process received request */
1444 sba_process_received_request(sba, req);
1445}
1446
1447/* ====== Debugfs callbacks ====== */
1448
1449static int sba_debugfs_stats_show(struct seq_file *file, void *offset)
1450{
1451 struct sba_device *sba = dev_get_drvdata(file->private);
1452
1453 /* Write stats in file */
1454 sba_write_stats_in_seqfile(sba, file);
1455
1456 return 0;
1457}
1458
1459/* ====== Platform driver routines ===== */
1460
1461static int sba_prealloc_channel_resources(struct sba_device *sba)
1462{
1463 int i, j, ret = 0;
1464 struct sba_request *req = NULL;
1465
1466 sba->resp_base = dma_alloc_coherent(sba->mbox_dev,
1467 sba->max_resp_pool_size,
1468 &sba->resp_dma_base, GFP_KERNEL);
1469 if (!sba->resp_base)
1470 return -ENOMEM;
1471
1472 sba->cmds_base = dma_alloc_coherent(sba->mbox_dev,
1473 sba->max_cmds_pool_size,
1474 &sba->cmds_dma_base, GFP_KERNEL);
1475 if (!sba->cmds_base) {
1476 ret = -ENOMEM;
1477 goto fail_free_resp_pool;
1478 }
1479
1480 spin_lock_init(&sba->reqs_lock);
1481 sba->reqs_fence = false;
1482 INIT_LIST_HEAD(&sba->reqs_alloc_list);
1483 INIT_LIST_HEAD(&sba->reqs_pending_list);
1484 INIT_LIST_HEAD(&sba->reqs_active_list);
1485 INIT_LIST_HEAD(&sba->reqs_aborted_list);
1486 INIT_LIST_HEAD(&sba->reqs_free_list);
1487
1488 for (i = 0; i < sba->max_req; i++) {
1489 req = devm_kzalloc(sba->dev,
1490 struct_size(req, cmds, sba->max_cmd_per_req),
1491 GFP_KERNEL);
1492 if (!req) {
1493 ret = -ENOMEM;
1494 goto fail_free_cmds_pool;
1495 }
1496 INIT_LIST_HEAD(&req->node);
1497 req->sba = sba;
1498 req->flags = SBA_REQUEST_STATE_FREE;
1499 INIT_LIST_HEAD(&req->next);
1500 atomic_set(&req->next_pending_count, 0);
1501 for (j = 0; j < sba->max_cmd_per_req; j++) {
1502 req->cmds[j].cmd = 0;
1503 req->cmds[j].cmd_dma = sba->cmds_base +
1504 (i * sba->max_cmd_per_req + j) * sizeof(u64);
1505 req->cmds[j].cmd_dma_addr = sba->cmds_dma_base +
1506 (i * sba->max_cmd_per_req + j) * sizeof(u64);
1507 req->cmds[j].flags = 0;
1508 }
1509 memset(&req->msg, 0, sizeof(req->msg));
1510 dma_async_tx_descriptor_init(&req->tx, &sba->dma_chan);
1511 async_tx_ack(&req->tx);
1512 req->tx.tx_submit = sba_tx_submit;
1513 req->tx.phys = sba->resp_dma_base + i * sba->hw_resp_size;
1514 list_add_tail(&req->node, &sba->reqs_free_list);
1515 }
1516
1517 return 0;
1518
1519fail_free_cmds_pool:
1520 dma_free_coherent(sba->mbox_dev,
1521 sba->max_cmds_pool_size,
1522 sba->cmds_base, sba->cmds_dma_base);
1523fail_free_resp_pool:
1524 dma_free_coherent(sba->mbox_dev,
1525 sba->max_resp_pool_size,
1526 sba->resp_base, sba->resp_dma_base);
1527 return ret;
1528}
1529
1530static void sba_freeup_channel_resources(struct sba_device *sba)
1531{
1532 dmaengine_terminate_all(&sba->dma_chan);
1533 dma_free_coherent(sba->mbox_dev, sba->max_cmds_pool_size,
1534 sba->cmds_base, sba->cmds_dma_base);
1535 dma_free_coherent(sba->mbox_dev, sba->max_resp_pool_size,
1536 sba->resp_base, sba->resp_dma_base);
1537 sba->resp_base = NULL;
1538 sba->resp_dma_base = 0;
1539}
1540
1541static int sba_async_register(struct sba_device *sba)
1542{
1543 int ret;
1544 struct dma_device *dma_dev = &sba->dma_dev;
1545
1546 /* Initialize DMA channel cookie */
1547 sba->dma_chan.device = dma_dev;
1548 dma_cookie_init(&sba->dma_chan);
1549
1550 /* Initialize DMA device capability mask */
1551 dma_cap_zero(dma_dev->cap_mask);
1552 dma_cap_set(DMA_INTERRUPT, dma_dev->cap_mask);
1553 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
1554 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1555 dma_cap_set(DMA_PQ, dma_dev->cap_mask);
1556
1557 /*
1558 * Set mailbox channel device as the base device of
1559 * our dma_device because the actual memory accesses
1560 * will be done by mailbox controller
1561 */
1562 dma_dev->dev = sba->mbox_dev;
1563
1564 /* Set base prep routines */
1565 dma_dev->device_free_chan_resources = sba_free_chan_resources;
1566 dma_dev->device_terminate_all = sba_device_terminate_all;
1567 dma_dev->device_issue_pending = sba_issue_pending;
1568 dma_dev->device_tx_status = sba_tx_status;
1569
1570 /* Set interrupt routine */
1571 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1572 dma_dev->device_prep_dma_interrupt = sba_prep_dma_interrupt;
1573
1574 /* Set memcpy routine */
1575 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1576 dma_dev->device_prep_dma_memcpy = sba_prep_dma_memcpy;
1577
1578 /* Set xor routine and capability */
1579 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1580 dma_dev->device_prep_dma_xor = sba_prep_dma_xor;
1581 dma_dev->max_xor = sba->max_xor_srcs;
1582 }
1583
1584 /* Set pq routine and capability */
1585 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1586 dma_dev->device_prep_dma_pq = sba_prep_dma_pq;
1587 dma_set_maxpq(dma_dev, sba->max_pq_srcs, 0);
1588 }
1589
1590 /* Initialize DMA device channel list */
1591 INIT_LIST_HEAD(&dma_dev->channels);
1592 list_add_tail(&sba->dma_chan.device_node, &dma_dev->channels);
1593
1594 /* Register with Linux async DMA framework*/
1595 ret = dma_async_device_register(dma_dev);
1596 if (ret) {
1597 dev_err(sba->dev, "async device register error %d", ret);
1598 return ret;
1599 }
1600
1601 dev_info(sba->dev, "%s capabilities: %s%s%s%s\n",
1602 dma_chan_name(&sba->dma_chan),
1603 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "interrupt " : "",
1604 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "memcpy " : "",
1605 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1606 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "");
1607
1608 return 0;
1609}
1610
1611static int sba_probe(struct platform_device *pdev)
1612{
1613 int ret = 0;
1614 struct sba_device *sba;
1615 struct platform_device *mbox_pdev;
1616 struct of_phandle_args args;
1617
1618 /* Allocate main SBA struct */
1619 sba = devm_kzalloc(&pdev->dev, sizeof(*sba), GFP_KERNEL);
1620 if (!sba)
1621 return -ENOMEM;
1622
1623 sba->dev = &pdev->dev;
1624 platform_set_drvdata(pdev, sba);
1625
1626 /* Number of mailbox channels should be atleast 1 */
1627 ret = of_count_phandle_with_args(pdev->dev.of_node,
1628 "mboxes", "#mbox-cells");
1629 if (ret <= 0)
1630 return -ENODEV;
1631
1632 /* Determine SBA version from DT compatible string */
1633 if (of_device_is_compatible(sba->dev->of_node, "brcm,iproc-sba"))
1634 sba->ver = SBA_VER_1;
1635 else if (of_device_is_compatible(sba->dev->of_node,
1636 "brcm,iproc-sba-v2"))
1637 sba->ver = SBA_VER_2;
1638 else
1639 return -ENODEV;
1640
1641 /* Derived Configuration parameters */
1642 switch (sba->ver) {
1643 case SBA_VER_1:
1644 sba->hw_buf_size = 4096;
1645 sba->hw_resp_size = 8;
1646 sba->max_pq_coefs = 6;
1647 sba->max_pq_srcs = 6;
1648 break;
1649 case SBA_VER_2:
1650 sba->hw_buf_size = 4096;
1651 sba->hw_resp_size = 8;
1652 sba->max_pq_coefs = 30;
1653 /*
1654 * We can support max_pq_srcs == max_pq_coefs because
1655 * we are limited by number of SBA commands that we can
1656 * fit in one message for underlying ring manager HW.
1657 */
1658 sba->max_pq_srcs = 12;
1659 break;
1660 default:
1661 return -EINVAL;
1662 }
1663 sba->max_req = SBA_MAX_REQ_PER_MBOX_CHANNEL;
1664 sba->max_cmd_per_req = sba->max_pq_srcs + 3;
1665 sba->max_xor_srcs = sba->max_cmd_per_req - 1;
1666 sba->max_resp_pool_size = sba->max_req * sba->hw_resp_size;
1667 sba->max_cmds_pool_size = sba->max_req *
1668 sba->max_cmd_per_req * sizeof(u64);
1669
1670 /* Setup mailbox client */
1671 sba->client.dev = &pdev->dev;
1672 sba->client.rx_callback = sba_receive_message;
1673 sba->client.tx_block = false;
1674 sba->client.knows_txdone = true;
1675 sba->client.tx_tout = 0;
1676
1677 /* Request mailbox channel */
1678 sba->mchan = mbox_request_channel(&sba->client, 0);
1679 if (IS_ERR(sba->mchan)) {
1680 ret = PTR_ERR(sba->mchan);
1681 goto fail_free_mchan;
1682 }
1683
1684 /* Find-out underlying mailbox device */
1685 ret = of_parse_phandle_with_args(pdev->dev.of_node,
1686 "mboxes", "#mbox-cells", 0, &args);
1687 if (ret)
1688 goto fail_free_mchan;
1689 mbox_pdev = of_find_device_by_node(args.np);
1690 of_node_put(args.np);
1691 if (!mbox_pdev) {
1692 ret = -ENODEV;
1693 goto fail_free_mchan;
1694 }
1695 sba->mbox_dev = &mbox_pdev->dev;
1696
1697 /* Prealloc channel resource */
1698 ret = sba_prealloc_channel_resources(sba);
1699 if (ret)
1700 goto fail_free_mchan;
1701
1702 /* Check availability of debugfs */
1703 if (!debugfs_initialized())
1704 goto skip_debugfs;
1705
1706 /* Create debugfs root entry */
1707 sba->root = debugfs_create_dir(dev_name(sba->dev), NULL);
1708
1709 /* Create debugfs stats entry */
1710 debugfs_create_devm_seqfile(sba->dev, "stats", sba->root,
1711 sba_debugfs_stats_show);
1712
1713skip_debugfs:
1714
1715 /* Register DMA device with Linux async framework */
1716 ret = sba_async_register(sba);
1717 if (ret)
1718 goto fail_free_resources;
1719
1720 /* Print device info */
1721 dev_info(sba->dev, "%s using SBAv%d mailbox channel from %s",
1722 dma_chan_name(&sba->dma_chan), sba->ver+1,
1723 dev_name(sba->mbox_dev));
1724
1725 return 0;
1726
1727fail_free_resources:
1728 debugfs_remove_recursive(sba->root);
1729 sba_freeup_channel_resources(sba);
1730fail_free_mchan:
1731 mbox_free_channel(sba->mchan);
1732 return ret;
1733}
1734
1735static int sba_remove(struct platform_device *pdev)
1736{
1737 struct sba_device *sba = platform_get_drvdata(pdev);
1738
1739 dma_async_device_unregister(&sba->dma_dev);
1740
1741 debugfs_remove_recursive(sba->root);
1742
1743 sba_freeup_channel_resources(sba);
1744
1745 mbox_free_channel(sba->mchan);
1746
1747 return 0;
1748}
1749
1750static const struct of_device_id sba_of_match[] = {
1751 { .compatible = "brcm,iproc-sba", },
1752 { .compatible = "brcm,iproc-sba-v2", },
1753 {},
1754};
1755MODULE_DEVICE_TABLE(of, sba_of_match);
1756
1757static struct platform_driver sba_driver = {
1758 .probe = sba_probe,
1759 .remove = sba_remove,
1760 .driver = {
1761 .name = "bcm-sba-raid",
1762 .of_match_table = sba_of_match,
1763 },
1764};
1765module_platform_driver(sba_driver);
1766
1767MODULE_DESCRIPTION("Broadcom SBA RAID driver");
1768MODULE_AUTHOR("Anup Patel <anup.patel@broadcom.com>");
1769MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (C) 2017 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/*
15 * Broadcom SBA RAID Driver
16 *
17 * The Broadcom stream buffer accelerator (SBA) provides offloading
18 * capabilities for RAID operations. The SBA offload engine is accessible
19 * via Broadcom SoC specific ring manager. Two or more offload engines
20 * can share same Broadcom SoC specific ring manager due to this Broadcom
21 * SoC specific ring manager driver is implemented as a mailbox controller
22 * driver and offload engine drivers are implemented as mallbox clients.
23 *
24 * Typically, Broadcom SoC specific ring manager will implement larger
25 * number of hardware rings over one or more SBA hardware devices. By
26 * design, the internal buffer size of SBA hardware device is limited
27 * but all offload operations supported by SBA can be broken down into
28 * multiple small size requests and executed parallely on multiple SBA
29 * hardware devices for achieving high through-put.
30 *
31 * The Broadcom SBA RAID driver does not require any register programming
32 * except submitting request to SBA hardware device via mailbox channels.
33 * This driver implements a DMA device with one DMA channel using a single
34 * mailbox channel provided by Broadcom SoC specific ring manager driver.
35 * For having more SBA DMA channels, we can create more SBA device nodes
36 * in Broadcom SoC specific DTS based on number of hardware rings supported
37 * by Broadcom SoC ring manager.
38 */
39
40#include <linux/bitops.h>
41#include <linux/debugfs.h>
42#include <linux/dma-mapping.h>
43#include <linux/dmaengine.h>
44#include <linux/list.h>
45#include <linux/mailbox_client.h>
46#include <linux/mailbox/brcm-message.h>
47#include <linux/module.h>
48#include <linux/of_device.h>
49#include <linux/slab.h>
50#include <linux/raid/pq.h>
51
52#include "dmaengine.h"
53
54/* ====== Driver macros and defines ===== */
55
56#define SBA_TYPE_SHIFT 48
57#define SBA_TYPE_MASK GENMASK(1, 0)
58#define SBA_TYPE_A 0x0
59#define SBA_TYPE_B 0x2
60#define SBA_TYPE_C 0x3
61#define SBA_USER_DEF_SHIFT 32
62#define SBA_USER_DEF_MASK GENMASK(15, 0)
63#define SBA_R_MDATA_SHIFT 24
64#define SBA_R_MDATA_MASK GENMASK(7, 0)
65#define SBA_C_MDATA_MS_SHIFT 18
66#define SBA_C_MDATA_MS_MASK GENMASK(1, 0)
67#define SBA_INT_SHIFT 17
68#define SBA_INT_MASK BIT(0)
69#define SBA_RESP_SHIFT 16
70#define SBA_RESP_MASK BIT(0)
71#define SBA_C_MDATA_SHIFT 8
72#define SBA_C_MDATA_MASK GENMASK(7, 0)
73#define SBA_C_MDATA_BNUMx_SHIFT(__bnum) (2 * (__bnum))
74#define SBA_C_MDATA_BNUMx_MASK GENMASK(1, 0)
75#define SBA_C_MDATA_DNUM_SHIFT 5
76#define SBA_C_MDATA_DNUM_MASK GENMASK(4, 0)
77#define SBA_C_MDATA_LS(__v) ((__v) & 0xff)
78#define SBA_C_MDATA_MS(__v) (((__v) >> 8) & 0x3)
79#define SBA_CMD_SHIFT 0
80#define SBA_CMD_MASK GENMASK(3, 0)
81#define SBA_CMD_ZERO_BUFFER 0x4
82#define SBA_CMD_ZERO_ALL_BUFFERS 0x8
83#define SBA_CMD_LOAD_BUFFER 0x9
84#define SBA_CMD_XOR 0xa
85#define SBA_CMD_GALOIS_XOR 0xb
86#define SBA_CMD_WRITE_BUFFER 0xc
87#define SBA_CMD_GALOIS 0xe
88
89#define SBA_MAX_REQ_PER_MBOX_CHANNEL 8192
90#define SBA_MAX_MSG_SEND_PER_MBOX_CHANNEL 8
91
92/* Driver helper macros */
93#define to_sba_request(tx) \
94 container_of(tx, struct sba_request, tx)
95#define to_sba_device(dchan) \
96 container_of(dchan, struct sba_device, dma_chan)
97
98/* ===== Driver data structures ===== */
99
100enum sba_request_flags {
101 SBA_REQUEST_STATE_FREE = 0x001,
102 SBA_REQUEST_STATE_ALLOCED = 0x002,
103 SBA_REQUEST_STATE_PENDING = 0x004,
104 SBA_REQUEST_STATE_ACTIVE = 0x008,
105 SBA_REQUEST_STATE_ABORTED = 0x010,
106 SBA_REQUEST_STATE_MASK = 0x0ff,
107 SBA_REQUEST_FENCE = 0x100,
108};
109
110struct sba_request {
111 /* Global state */
112 struct list_head node;
113 struct sba_device *sba;
114 u32 flags;
115 /* Chained requests management */
116 struct sba_request *first;
117 struct list_head next;
118 atomic_t next_pending_count;
119 /* BRCM message data */
120 struct brcm_message msg;
121 struct dma_async_tx_descriptor tx;
122 /* SBA commands */
123 struct brcm_sba_command cmds[0];
124};
125
126enum sba_version {
127 SBA_VER_1 = 0,
128 SBA_VER_2
129};
130
131struct sba_device {
132 /* Underlying device */
133 struct device *dev;
134 /* DT configuration parameters */
135 enum sba_version ver;
136 /* Derived configuration parameters */
137 u32 max_req;
138 u32 hw_buf_size;
139 u32 hw_resp_size;
140 u32 max_pq_coefs;
141 u32 max_pq_srcs;
142 u32 max_cmd_per_req;
143 u32 max_xor_srcs;
144 u32 max_resp_pool_size;
145 u32 max_cmds_pool_size;
146 /* Maibox client and Mailbox channels */
147 struct mbox_client client;
148 struct mbox_chan *mchan;
149 struct device *mbox_dev;
150 /* DMA device and DMA channel */
151 struct dma_device dma_dev;
152 struct dma_chan dma_chan;
153 /* DMA channel resources */
154 void *resp_base;
155 dma_addr_t resp_dma_base;
156 void *cmds_base;
157 dma_addr_t cmds_dma_base;
158 spinlock_t reqs_lock;
159 bool reqs_fence;
160 struct list_head reqs_alloc_list;
161 struct list_head reqs_pending_list;
162 struct list_head reqs_active_list;
163 struct list_head reqs_aborted_list;
164 struct list_head reqs_free_list;
165 /* DebugFS directory entries */
166 struct dentry *root;
167 struct dentry *stats;
168};
169
170/* ====== Command helper routines ===== */
171
172static inline u64 __pure sba_cmd_enc(u64 cmd, u32 val, u32 shift, u32 mask)
173{
174 cmd &= ~((u64)mask << shift);
175 cmd |= ((u64)(val & mask) << shift);
176 return cmd;
177}
178
179static inline u32 __pure sba_cmd_load_c_mdata(u32 b0)
180{
181 return b0 & SBA_C_MDATA_BNUMx_MASK;
182}
183
184static inline u32 __pure sba_cmd_write_c_mdata(u32 b0)
185{
186 return b0 & SBA_C_MDATA_BNUMx_MASK;
187}
188
189static inline u32 __pure sba_cmd_xor_c_mdata(u32 b1, u32 b0)
190{
191 return (b0 & SBA_C_MDATA_BNUMx_MASK) |
192 ((b1 & SBA_C_MDATA_BNUMx_MASK) << SBA_C_MDATA_BNUMx_SHIFT(1));
193}
194
195static inline u32 __pure sba_cmd_pq_c_mdata(u32 d, u32 b1, u32 b0)
196{
197 return (b0 & SBA_C_MDATA_BNUMx_MASK) |
198 ((b1 & SBA_C_MDATA_BNUMx_MASK) << SBA_C_MDATA_BNUMx_SHIFT(1)) |
199 ((d & SBA_C_MDATA_DNUM_MASK) << SBA_C_MDATA_DNUM_SHIFT);
200}
201
202/* ====== General helper routines ===== */
203
204static struct sba_request *sba_alloc_request(struct sba_device *sba)
205{
206 bool found = false;
207 unsigned long flags;
208 struct sba_request *req = NULL;
209
210 spin_lock_irqsave(&sba->reqs_lock, flags);
211 list_for_each_entry(req, &sba->reqs_free_list, node) {
212 if (async_tx_test_ack(&req->tx)) {
213 list_move_tail(&req->node, &sba->reqs_alloc_list);
214 found = true;
215 break;
216 }
217 }
218 spin_unlock_irqrestore(&sba->reqs_lock, flags);
219
220 if (!found) {
221 /*
222 * We have no more free requests so, we peek
223 * mailbox channels hoping few active requests
224 * would have completed which will create more
225 * room for new requests.
226 */
227 mbox_client_peek_data(sba->mchan);
228 return NULL;
229 }
230
231 req->flags = SBA_REQUEST_STATE_ALLOCED;
232 req->first = req;
233 INIT_LIST_HEAD(&req->next);
234 atomic_set(&req->next_pending_count, 1);
235
236 dma_async_tx_descriptor_init(&req->tx, &sba->dma_chan);
237 async_tx_ack(&req->tx);
238
239 return req;
240}
241
242/* Note: Must be called with sba->reqs_lock held */
243static void _sba_pending_request(struct sba_device *sba,
244 struct sba_request *req)
245{
246 lockdep_assert_held(&sba->reqs_lock);
247 req->flags &= ~SBA_REQUEST_STATE_MASK;
248 req->flags |= SBA_REQUEST_STATE_PENDING;
249 list_move_tail(&req->node, &sba->reqs_pending_list);
250 if (list_empty(&sba->reqs_active_list))
251 sba->reqs_fence = false;
252}
253
254/* Note: Must be called with sba->reqs_lock held */
255static bool _sba_active_request(struct sba_device *sba,
256 struct sba_request *req)
257{
258 lockdep_assert_held(&sba->reqs_lock);
259 if (list_empty(&sba->reqs_active_list))
260 sba->reqs_fence = false;
261 if (sba->reqs_fence)
262 return false;
263 req->flags &= ~SBA_REQUEST_STATE_MASK;
264 req->flags |= SBA_REQUEST_STATE_ACTIVE;
265 list_move_tail(&req->node, &sba->reqs_active_list);
266 if (req->flags & SBA_REQUEST_FENCE)
267 sba->reqs_fence = true;
268 return true;
269}
270
271/* Note: Must be called with sba->reqs_lock held */
272static void _sba_abort_request(struct sba_device *sba,
273 struct sba_request *req)
274{
275 lockdep_assert_held(&sba->reqs_lock);
276 req->flags &= ~SBA_REQUEST_STATE_MASK;
277 req->flags |= SBA_REQUEST_STATE_ABORTED;
278 list_move_tail(&req->node, &sba->reqs_aborted_list);
279 if (list_empty(&sba->reqs_active_list))
280 sba->reqs_fence = false;
281}
282
283/* Note: Must be called with sba->reqs_lock held */
284static void _sba_free_request(struct sba_device *sba,
285 struct sba_request *req)
286{
287 lockdep_assert_held(&sba->reqs_lock);
288 req->flags &= ~SBA_REQUEST_STATE_MASK;
289 req->flags |= SBA_REQUEST_STATE_FREE;
290 list_move_tail(&req->node, &sba->reqs_free_list);
291 if (list_empty(&sba->reqs_active_list))
292 sba->reqs_fence = false;
293}
294
295static void sba_free_chained_requests(struct sba_request *req)
296{
297 unsigned long flags;
298 struct sba_request *nreq;
299 struct sba_device *sba = req->sba;
300
301 spin_lock_irqsave(&sba->reqs_lock, flags);
302
303 _sba_free_request(sba, req);
304 list_for_each_entry(nreq, &req->next, next)
305 _sba_free_request(sba, nreq);
306
307 spin_unlock_irqrestore(&sba->reqs_lock, flags);
308}
309
310static void sba_chain_request(struct sba_request *first,
311 struct sba_request *req)
312{
313 unsigned long flags;
314 struct sba_device *sba = req->sba;
315
316 spin_lock_irqsave(&sba->reqs_lock, flags);
317
318 list_add_tail(&req->next, &first->next);
319 req->first = first;
320 atomic_inc(&first->next_pending_count);
321
322 spin_unlock_irqrestore(&sba->reqs_lock, flags);
323}
324
325static void sba_cleanup_nonpending_requests(struct sba_device *sba)
326{
327 unsigned long flags;
328 struct sba_request *req, *req1;
329
330 spin_lock_irqsave(&sba->reqs_lock, flags);
331
332 /* Freeup all alloced request */
333 list_for_each_entry_safe(req, req1, &sba->reqs_alloc_list, node)
334 _sba_free_request(sba, req);
335
336 /* Set all active requests as aborted */
337 list_for_each_entry_safe(req, req1, &sba->reqs_active_list, node)
338 _sba_abort_request(sba, req);
339
340 /*
341 * Note: We expect that aborted request will be eventually
342 * freed by sba_receive_message()
343 */
344
345 spin_unlock_irqrestore(&sba->reqs_lock, flags);
346}
347
348static void sba_cleanup_pending_requests(struct sba_device *sba)
349{
350 unsigned long flags;
351 struct sba_request *req, *req1;
352
353 spin_lock_irqsave(&sba->reqs_lock, flags);
354
355 /* Freeup all pending request */
356 list_for_each_entry_safe(req, req1, &sba->reqs_pending_list, node)
357 _sba_free_request(sba, req);
358
359 spin_unlock_irqrestore(&sba->reqs_lock, flags);
360}
361
362static int sba_send_mbox_request(struct sba_device *sba,
363 struct sba_request *req)
364{
365 int ret = 0;
366
367 /* Send message for the request */
368 req->msg.error = 0;
369 ret = mbox_send_message(sba->mchan, &req->msg);
370 if (ret < 0) {
371 dev_err(sba->dev, "send message failed with error %d", ret);
372 return ret;
373 }
374
375 /* Check error returned by mailbox controller */
376 ret = req->msg.error;
377 if (ret < 0) {
378 dev_err(sba->dev, "message error %d", ret);
379 }
380
381 /* Signal txdone for mailbox channel */
382 mbox_client_txdone(sba->mchan, ret);
383
384 return ret;
385}
386
387/* Note: Must be called with sba->reqs_lock held */
388static void _sba_process_pending_requests(struct sba_device *sba)
389{
390 int ret;
391 u32 count;
392 struct sba_request *req;
393
394 /* Process few pending requests */
395 count = SBA_MAX_MSG_SEND_PER_MBOX_CHANNEL;
396 while (!list_empty(&sba->reqs_pending_list) && count) {
397 /* Get the first pending request */
398 req = list_first_entry(&sba->reqs_pending_list,
399 struct sba_request, node);
400
401 /* Try to make request active */
402 if (!_sba_active_request(sba, req))
403 break;
404
405 /* Send request to mailbox channel */
406 ret = sba_send_mbox_request(sba, req);
407 if (ret < 0) {
408 _sba_pending_request(sba, req);
409 break;
410 }
411
412 count--;
413 }
414}
415
416static void sba_process_received_request(struct sba_device *sba,
417 struct sba_request *req)
418{
419 unsigned long flags;
420 struct dma_async_tx_descriptor *tx;
421 struct sba_request *nreq, *first = req->first;
422
423 /* Process only after all chained requests are received */
424 if (!atomic_dec_return(&first->next_pending_count)) {
425 tx = &first->tx;
426
427 WARN_ON(tx->cookie < 0);
428 if (tx->cookie > 0) {
429 spin_lock_irqsave(&sba->reqs_lock, flags);
430 dma_cookie_complete(tx);
431 spin_unlock_irqrestore(&sba->reqs_lock, flags);
432 dmaengine_desc_get_callback_invoke(tx, NULL);
433 dma_descriptor_unmap(tx);
434 tx->callback = NULL;
435 tx->callback_result = NULL;
436 }
437
438 dma_run_dependencies(tx);
439
440 spin_lock_irqsave(&sba->reqs_lock, flags);
441
442 /* Free all requests chained to first request */
443 list_for_each_entry(nreq, &first->next, next)
444 _sba_free_request(sba, nreq);
445 INIT_LIST_HEAD(&first->next);
446
447 /* Free the first request */
448 _sba_free_request(sba, first);
449
450 /* Process pending requests */
451 _sba_process_pending_requests(sba);
452
453 spin_unlock_irqrestore(&sba->reqs_lock, flags);
454 }
455}
456
457static void sba_write_stats_in_seqfile(struct sba_device *sba,
458 struct seq_file *file)
459{
460 unsigned long flags;
461 struct sba_request *req;
462 u32 free_count = 0, alloced_count = 0;
463 u32 pending_count = 0, active_count = 0, aborted_count = 0;
464
465 spin_lock_irqsave(&sba->reqs_lock, flags);
466
467 list_for_each_entry(req, &sba->reqs_free_list, node)
468 if (async_tx_test_ack(&req->tx))
469 free_count++;
470
471 list_for_each_entry(req, &sba->reqs_alloc_list, node)
472 alloced_count++;
473
474 list_for_each_entry(req, &sba->reqs_pending_list, node)
475 pending_count++;
476
477 list_for_each_entry(req, &sba->reqs_active_list, node)
478 active_count++;
479
480 list_for_each_entry(req, &sba->reqs_aborted_list, node)
481 aborted_count++;
482
483 spin_unlock_irqrestore(&sba->reqs_lock, flags);
484
485 seq_printf(file, "maximum requests = %d\n", sba->max_req);
486 seq_printf(file, "free requests = %d\n", free_count);
487 seq_printf(file, "alloced requests = %d\n", alloced_count);
488 seq_printf(file, "pending requests = %d\n", pending_count);
489 seq_printf(file, "active requests = %d\n", active_count);
490 seq_printf(file, "aborted requests = %d\n", aborted_count);
491}
492
493/* ====== DMAENGINE callbacks ===== */
494
495static void sba_free_chan_resources(struct dma_chan *dchan)
496{
497 /*
498 * Channel resources are pre-alloced so we just free-up
499 * whatever we can so that we can re-use pre-alloced
500 * channel resources next time.
501 */
502 sba_cleanup_nonpending_requests(to_sba_device(dchan));
503}
504
505static int sba_device_terminate_all(struct dma_chan *dchan)
506{
507 /* Cleanup all pending requests */
508 sba_cleanup_pending_requests(to_sba_device(dchan));
509
510 return 0;
511}
512
513static void sba_issue_pending(struct dma_chan *dchan)
514{
515 unsigned long flags;
516 struct sba_device *sba = to_sba_device(dchan);
517
518 /* Process pending requests */
519 spin_lock_irqsave(&sba->reqs_lock, flags);
520 _sba_process_pending_requests(sba);
521 spin_unlock_irqrestore(&sba->reqs_lock, flags);
522}
523
524static dma_cookie_t sba_tx_submit(struct dma_async_tx_descriptor *tx)
525{
526 unsigned long flags;
527 dma_cookie_t cookie;
528 struct sba_device *sba;
529 struct sba_request *req, *nreq;
530
531 if (unlikely(!tx))
532 return -EINVAL;
533
534 sba = to_sba_device(tx->chan);
535 req = to_sba_request(tx);
536
537 /* Assign cookie and mark all chained requests pending */
538 spin_lock_irqsave(&sba->reqs_lock, flags);
539 cookie = dma_cookie_assign(tx);
540 _sba_pending_request(sba, req);
541 list_for_each_entry(nreq, &req->next, next)
542 _sba_pending_request(sba, nreq);
543 spin_unlock_irqrestore(&sba->reqs_lock, flags);
544
545 return cookie;
546}
547
548static enum dma_status sba_tx_status(struct dma_chan *dchan,
549 dma_cookie_t cookie,
550 struct dma_tx_state *txstate)
551{
552 enum dma_status ret;
553 struct sba_device *sba = to_sba_device(dchan);
554
555 ret = dma_cookie_status(dchan, cookie, txstate);
556 if (ret == DMA_COMPLETE)
557 return ret;
558
559 mbox_client_peek_data(sba->mchan);
560
561 return dma_cookie_status(dchan, cookie, txstate);
562}
563
564static void sba_fillup_interrupt_msg(struct sba_request *req,
565 struct brcm_sba_command *cmds,
566 struct brcm_message *msg)
567{
568 u64 cmd;
569 u32 c_mdata;
570 dma_addr_t resp_dma = req->tx.phys;
571 struct brcm_sba_command *cmdsp = cmds;
572
573 /* Type-B command to load dummy data into buf0 */
574 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
575 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
576 cmd = sba_cmd_enc(cmd, req->sba->hw_resp_size,
577 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
578 c_mdata = sba_cmd_load_c_mdata(0);
579 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
580 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
581 cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
582 SBA_CMD_SHIFT, SBA_CMD_MASK);
583 cmdsp->cmd = cmd;
584 *cmdsp->cmd_dma = cpu_to_le64(cmd);
585 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
586 cmdsp->data = resp_dma;
587 cmdsp->data_len = req->sba->hw_resp_size;
588 cmdsp++;
589
590 /* Type-A command to write buf0 to dummy location */
591 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
592 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
593 cmd = sba_cmd_enc(cmd, req->sba->hw_resp_size,
594 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
595 cmd = sba_cmd_enc(cmd, 0x1,
596 SBA_RESP_SHIFT, SBA_RESP_MASK);
597 c_mdata = sba_cmd_write_c_mdata(0);
598 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
599 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
600 cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
601 SBA_CMD_SHIFT, SBA_CMD_MASK);
602 cmdsp->cmd = cmd;
603 *cmdsp->cmd_dma = cpu_to_le64(cmd);
604 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
605 if (req->sba->hw_resp_size) {
606 cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
607 cmdsp->resp = resp_dma;
608 cmdsp->resp_len = req->sba->hw_resp_size;
609 }
610 cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
611 cmdsp->data = resp_dma;
612 cmdsp->data_len = req->sba->hw_resp_size;
613 cmdsp++;
614
615 /* Fillup brcm_message */
616 msg->type = BRCM_MESSAGE_SBA;
617 msg->sba.cmds = cmds;
618 msg->sba.cmds_count = cmdsp - cmds;
619 msg->ctx = req;
620 msg->error = 0;
621}
622
623static struct dma_async_tx_descriptor *
624sba_prep_dma_interrupt(struct dma_chan *dchan, unsigned long flags)
625{
626 struct sba_request *req = NULL;
627 struct sba_device *sba = to_sba_device(dchan);
628
629 /* Alloc new request */
630 req = sba_alloc_request(sba);
631 if (!req)
632 return NULL;
633
634 /*
635 * Force fence so that no requests are submitted
636 * until DMA callback for this request is invoked.
637 */
638 req->flags |= SBA_REQUEST_FENCE;
639
640 /* Fillup request message */
641 sba_fillup_interrupt_msg(req, req->cmds, &req->msg);
642
643 /* Init async_tx descriptor */
644 req->tx.flags = flags;
645 req->tx.cookie = -EBUSY;
646
647 return &req->tx;
648}
649
650static void sba_fillup_memcpy_msg(struct sba_request *req,
651 struct brcm_sba_command *cmds,
652 struct brcm_message *msg,
653 dma_addr_t msg_offset, size_t msg_len,
654 dma_addr_t dst, dma_addr_t src)
655{
656 u64 cmd;
657 u32 c_mdata;
658 dma_addr_t resp_dma = req->tx.phys;
659 struct brcm_sba_command *cmdsp = cmds;
660
661 /* Type-B command to load data into buf0 */
662 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
663 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
664 cmd = sba_cmd_enc(cmd, msg_len,
665 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
666 c_mdata = sba_cmd_load_c_mdata(0);
667 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
668 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
669 cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
670 SBA_CMD_SHIFT, SBA_CMD_MASK);
671 cmdsp->cmd = cmd;
672 *cmdsp->cmd_dma = cpu_to_le64(cmd);
673 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
674 cmdsp->data = src + msg_offset;
675 cmdsp->data_len = msg_len;
676 cmdsp++;
677
678 /* Type-A command to write buf0 */
679 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
680 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
681 cmd = sba_cmd_enc(cmd, msg_len,
682 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
683 cmd = sba_cmd_enc(cmd, 0x1,
684 SBA_RESP_SHIFT, SBA_RESP_MASK);
685 c_mdata = sba_cmd_write_c_mdata(0);
686 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
687 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
688 cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
689 SBA_CMD_SHIFT, SBA_CMD_MASK);
690 cmdsp->cmd = cmd;
691 *cmdsp->cmd_dma = cpu_to_le64(cmd);
692 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
693 if (req->sba->hw_resp_size) {
694 cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
695 cmdsp->resp = resp_dma;
696 cmdsp->resp_len = req->sba->hw_resp_size;
697 }
698 cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
699 cmdsp->data = dst + msg_offset;
700 cmdsp->data_len = msg_len;
701 cmdsp++;
702
703 /* Fillup brcm_message */
704 msg->type = BRCM_MESSAGE_SBA;
705 msg->sba.cmds = cmds;
706 msg->sba.cmds_count = cmdsp - cmds;
707 msg->ctx = req;
708 msg->error = 0;
709}
710
711static struct sba_request *
712sba_prep_dma_memcpy_req(struct sba_device *sba,
713 dma_addr_t off, dma_addr_t dst, dma_addr_t src,
714 size_t len, unsigned long flags)
715{
716 struct sba_request *req = NULL;
717
718 /* Alloc new request */
719 req = sba_alloc_request(sba);
720 if (!req)
721 return NULL;
722 if (flags & DMA_PREP_FENCE)
723 req->flags |= SBA_REQUEST_FENCE;
724
725 /* Fillup request message */
726 sba_fillup_memcpy_msg(req, req->cmds, &req->msg,
727 off, len, dst, src);
728
729 /* Init async_tx descriptor */
730 req->tx.flags = flags;
731 req->tx.cookie = -EBUSY;
732
733 return req;
734}
735
736static struct dma_async_tx_descriptor *
737sba_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src,
738 size_t len, unsigned long flags)
739{
740 size_t req_len;
741 dma_addr_t off = 0;
742 struct sba_device *sba = to_sba_device(dchan);
743 struct sba_request *first = NULL, *req;
744
745 /* Create chained requests where each request is upto hw_buf_size */
746 while (len) {
747 req_len = (len < sba->hw_buf_size) ? len : sba->hw_buf_size;
748
749 req = sba_prep_dma_memcpy_req(sba, off, dst, src,
750 req_len, flags);
751 if (!req) {
752 if (first)
753 sba_free_chained_requests(first);
754 return NULL;
755 }
756
757 if (first)
758 sba_chain_request(first, req);
759 else
760 first = req;
761
762 off += req_len;
763 len -= req_len;
764 }
765
766 return (first) ? &first->tx : NULL;
767}
768
769static void sba_fillup_xor_msg(struct sba_request *req,
770 struct brcm_sba_command *cmds,
771 struct brcm_message *msg,
772 dma_addr_t msg_offset, size_t msg_len,
773 dma_addr_t dst, dma_addr_t *src, u32 src_cnt)
774{
775 u64 cmd;
776 u32 c_mdata;
777 unsigned int i;
778 dma_addr_t resp_dma = req->tx.phys;
779 struct brcm_sba_command *cmdsp = cmds;
780
781 /* Type-B command to load data into buf0 */
782 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
783 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
784 cmd = sba_cmd_enc(cmd, msg_len,
785 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
786 c_mdata = sba_cmd_load_c_mdata(0);
787 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
788 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
789 cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
790 SBA_CMD_SHIFT, SBA_CMD_MASK);
791 cmdsp->cmd = cmd;
792 *cmdsp->cmd_dma = cpu_to_le64(cmd);
793 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
794 cmdsp->data = src[0] + msg_offset;
795 cmdsp->data_len = msg_len;
796 cmdsp++;
797
798 /* Type-B commands to xor data with buf0 and put it back in buf0 */
799 for (i = 1; i < src_cnt; i++) {
800 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
801 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
802 cmd = sba_cmd_enc(cmd, msg_len,
803 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
804 c_mdata = sba_cmd_xor_c_mdata(0, 0);
805 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
806 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
807 cmd = sba_cmd_enc(cmd, SBA_CMD_XOR,
808 SBA_CMD_SHIFT, SBA_CMD_MASK);
809 cmdsp->cmd = cmd;
810 *cmdsp->cmd_dma = cpu_to_le64(cmd);
811 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
812 cmdsp->data = src[i] + msg_offset;
813 cmdsp->data_len = msg_len;
814 cmdsp++;
815 }
816
817 /* Type-A command to write buf0 */
818 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
819 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
820 cmd = sba_cmd_enc(cmd, msg_len,
821 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
822 cmd = sba_cmd_enc(cmd, 0x1,
823 SBA_RESP_SHIFT, SBA_RESP_MASK);
824 c_mdata = sba_cmd_write_c_mdata(0);
825 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
826 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
827 cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
828 SBA_CMD_SHIFT, SBA_CMD_MASK);
829 cmdsp->cmd = cmd;
830 *cmdsp->cmd_dma = cpu_to_le64(cmd);
831 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
832 if (req->sba->hw_resp_size) {
833 cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
834 cmdsp->resp = resp_dma;
835 cmdsp->resp_len = req->sba->hw_resp_size;
836 }
837 cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
838 cmdsp->data = dst + msg_offset;
839 cmdsp->data_len = msg_len;
840 cmdsp++;
841
842 /* Fillup brcm_message */
843 msg->type = BRCM_MESSAGE_SBA;
844 msg->sba.cmds = cmds;
845 msg->sba.cmds_count = cmdsp - cmds;
846 msg->ctx = req;
847 msg->error = 0;
848}
849
850static struct sba_request *
851sba_prep_dma_xor_req(struct sba_device *sba,
852 dma_addr_t off, dma_addr_t dst, dma_addr_t *src,
853 u32 src_cnt, size_t len, unsigned long flags)
854{
855 struct sba_request *req = NULL;
856
857 /* Alloc new request */
858 req = sba_alloc_request(sba);
859 if (!req)
860 return NULL;
861 if (flags & DMA_PREP_FENCE)
862 req->flags |= SBA_REQUEST_FENCE;
863
864 /* Fillup request message */
865 sba_fillup_xor_msg(req, req->cmds, &req->msg,
866 off, len, dst, src, src_cnt);
867
868 /* Init async_tx descriptor */
869 req->tx.flags = flags;
870 req->tx.cookie = -EBUSY;
871
872 return req;
873}
874
875static struct dma_async_tx_descriptor *
876sba_prep_dma_xor(struct dma_chan *dchan, dma_addr_t dst, dma_addr_t *src,
877 u32 src_cnt, size_t len, unsigned long flags)
878{
879 size_t req_len;
880 dma_addr_t off = 0;
881 struct sba_device *sba = to_sba_device(dchan);
882 struct sba_request *first = NULL, *req;
883
884 /* Sanity checks */
885 if (unlikely(src_cnt > sba->max_xor_srcs))
886 return NULL;
887
888 /* Create chained requests where each request is upto hw_buf_size */
889 while (len) {
890 req_len = (len < sba->hw_buf_size) ? len : sba->hw_buf_size;
891
892 req = sba_prep_dma_xor_req(sba, off, dst, src, src_cnt,
893 req_len, flags);
894 if (!req) {
895 if (first)
896 sba_free_chained_requests(first);
897 return NULL;
898 }
899
900 if (first)
901 sba_chain_request(first, req);
902 else
903 first = req;
904
905 off += req_len;
906 len -= req_len;
907 }
908
909 return (first) ? &first->tx : NULL;
910}
911
912static void sba_fillup_pq_msg(struct sba_request *req,
913 bool pq_continue,
914 struct brcm_sba_command *cmds,
915 struct brcm_message *msg,
916 dma_addr_t msg_offset, size_t msg_len,
917 dma_addr_t *dst_p, dma_addr_t *dst_q,
918 const u8 *scf, dma_addr_t *src, u32 src_cnt)
919{
920 u64 cmd;
921 u32 c_mdata;
922 unsigned int i;
923 dma_addr_t resp_dma = req->tx.phys;
924 struct brcm_sba_command *cmdsp = cmds;
925
926 if (pq_continue) {
927 /* Type-B command to load old P into buf0 */
928 if (dst_p) {
929 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
930 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
931 cmd = sba_cmd_enc(cmd, msg_len,
932 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
933 c_mdata = sba_cmd_load_c_mdata(0);
934 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
935 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
936 cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
937 SBA_CMD_SHIFT, SBA_CMD_MASK);
938 cmdsp->cmd = cmd;
939 *cmdsp->cmd_dma = cpu_to_le64(cmd);
940 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
941 cmdsp->data = *dst_p + msg_offset;
942 cmdsp->data_len = msg_len;
943 cmdsp++;
944 }
945
946 /* Type-B command to load old Q into buf1 */
947 if (dst_q) {
948 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
949 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
950 cmd = sba_cmd_enc(cmd, msg_len,
951 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
952 c_mdata = sba_cmd_load_c_mdata(1);
953 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
954 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
955 cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
956 SBA_CMD_SHIFT, SBA_CMD_MASK);
957 cmdsp->cmd = cmd;
958 *cmdsp->cmd_dma = cpu_to_le64(cmd);
959 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
960 cmdsp->data = *dst_q + msg_offset;
961 cmdsp->data_len = msg_len;
962 cmdsp++;
963 }
964 } else {
965 /* Type-A command to zero all buffers */
966 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
967 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
968 cmd = sba_cmd_enc(cmd, msg_len,
969 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
970 cmd = sba_cmd_enc(cmd, SBA_CMD_ZERO_ALL_BUFFERS,
971 SBA_CMD_SHIFT, SBA_CMD_MASK);
972 cmdsp->cmd = cmd;
973 *cmdsp->cmd_dma = cpu_to_le64(cmd);
974 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
975 cmdsp++;
976 }
977
978 /* Type-B commands for generate P onto buf0 and Q onto buf1 */
979 for (i = 0; i < src_cnt; i++) {
980 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
981 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
982 cmd = sba_cmd_enc(cmd, msg_len,
983 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
984 c_mdata = sba_cmd_pq_c_mdata(raid6_gflog[scf[i]], 1, 0);
985 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
986 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
987 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_MS(c_mdata),
988 SBA_C_MDATA_MS_SHIFT, SBA_C_MDATA_MS_MASK);
989 cmd = sba_cmd_enc(cmd, SBA_CMD_GALOIS_XOR,
990 SBA_CMD_SHIFT, SBA_CMD_MASK);
991 cmdsp->cmd = cmd;
992 *cmdsp->cmd_dma = cpu_to_le64(cmd);
993 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
994 cmdsp->data = src[i] + msg_offset;
995 cmdsp->data_len = msg_len;
996 cmdsp++;
997 }
998
999 /* Type-A command to write buf0 */
1000 if (dst_p) {
1001 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1002 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1003 cmd = sba_cmd_enc(cmd, msg_len,
1004 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1005 cmd = sba_cmd_enc(cmd, 0x1,
1006 SBA_RESP_SHIFT, SBA_RESP_MASK);
1007 c_mdata = sba_cmd_write_c_mdata(0);
1008 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1009 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1010 cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
1011 SBA_CMD_SHIFT, SBA_CMD_MASK);
1012 cmdsp->cmd = cmd;
1013 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1014 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1015 if (req->sba->hw_resp_size) {
1016 cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
1017 cmdsp->resp = resp_dma;
1018 cmdsp->resp_len = req->sba->hw_resp_size;
1019 }
1020 cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
1021 cmdsp->data = *dst_p + msg_offset;
1022 cmdsp->data_len = msg_len;
1023 cmdsp++;
1024 }
1025
1026 /* Type-A command to write buf1 */
1027 if (dst_q) {
1028 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1029 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1030 cmd = sba_cmd_enc(cmd, msg_len,
1031 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1032 cmd = sba_cmd_enc(cmd, 0x1,
1033 SBA_RESP_SHIFT, SBA_RESP_MASK);
1034 c_mdata = sba_cmd_write_c_mdata(1);
1035 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1036 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1037 cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
1038 SBA_CMD_SHIFT, SBA_CMD_MASK);
1039 cmdsp->cmd = cmd;
1040 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1041 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1042 if (req->sba->hw_resp_size) {
1043 cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
1044 cmdsp->resp = resp_dma;
1045 cmdsp->resp_len = req->sba->hw_resp_size;
1046 }
1047 cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
1048 cmdsp->data = *dst_q + msg_offset;
1049 cmdsp->data_len = msg_len;
1050 cmdsp++;
1051 }
1052
1053 /* Fillup brcm_message */
1054 msg->type = BRCM_MESSAGE_SBA;
1055 msg->sba.cmds = cmds;
1056 msg->sba.cmds_count = cmdsp - cmds;
1057 msg->ctx = req;
1058 msg->error = 0;
1059}
1060
1061static struct sba_request *
1062sba_prep_dma_pq_req(struct sba_device *sba, dma_addr_t off,
1063 dma_addr_t *dst_p, dma_addr_t *dst_q, dma_addr_t *src,
1064 u32 src_cnt, const u8 *scf, size_t len, unsigned long flags)
1065{
1066 struct sba_request *req = NULL;
1067
1068 /* Alloc new request */
1069 req = sba_alloc_request(sba);
1070 if (!req)
1071 return NULL;
1072 if (flags & DMA_PREP_FENCE)
1073 req->flags |= SBA_REQUEST_FENCE;
1074
1075 /* Fillup request messages */
1076 sba_fillup_pq_msg(req, dmaf_continue(flags),
1077 req->cmds, &req->msg,
1078 off, len, dst_p, dst_q, scf, src, src_cnt);
1079
1080 /* Init async_tx descriptor */
1081 req->tx.flags = flags;
1082 req->tx.cookie = -EBUSY;
1083
1084 return req;
1085}
1086
1087static void sba_fillup_pq_single_msg(struct sba_request *req,
1088 bool pq_continue,
1089 struct brcm_sba_command *cmds,
1090 struct brcm_message *msg,
1091 dma_addr_t msg_offset, size_t msg_len,
1092 dma_addr_t *dst_p, dma_addr_t *dst_q,
1093 dma_addr_t src, u8 scf)
1094{
1095 u64 cmd;
1096 u32 c_mdata;
1097 u8 pos, dpos = raid6_gflog[scf];
1098 dma_addr_t resp_dma = req->tx.phys;
1099 struct brcm_sba_command *cmdsp = cmds;
1100
1101 if (!dst_p)
1102 goto skip_p;
1103
1104 if (pq_continue) {
1105 /* Type-B command to load old P into buf0 */
1106 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1107 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1108 cmd = sba_cmd_enc(cmd, msg_len,
1109 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1110 c_mdata = sba_cmd_load_c_mdata(0);
1111 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1112 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1113 cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
1114 SBA_CMD_SHIFT, SBA_CMD_MASK);
1115 cmdsp->cmd = cmd;
1116 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1117 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1118 cmdsp->data = *dst_p + msg_offset;
1119 cmdsp->data_len = msg_len;
1120 cmdsp++;
1121
1122 /*
1123 * Type-B commands to xor data with buf0 and put it
1124 * back in buf0
1125 */
1126 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1127 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1128 cmd = sba_cmd_enc(cmd, msg_len,
1129 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1130 c_mdata = sba_cmd_xor_c_mdata(0, 0);
1131 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1132 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1133 cmd = sba_cmd_enc(cmd, SBA_CMD_XOR,
1134 SBA_CMD_SHIFT, SBA_CMD_MASK);
1135 cmdsp->cmd = cmd;
1136 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1137 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1138 cmdsp->data = src + msg_offset;
1139 cmdsp->data_len = msg_len;
1140 cmdsp++;
1141 } else {
1142 /* Type-B command to load old P into buf0 */
1143 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1144 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1145 cmd = sba_cmd_enc(cmd, msg_len,
1146 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1147 c_mdata = sba_cmd_load_c_mdata(0);
1148 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1149 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1150 cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
1151 SBA_CMD_SHIFT, SBA_CMD_MASK);
1152 cmdsp->cmd = cmd;
1153 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1154 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1155 cmdsp->data = src + msg_offset;
1156 cmdsp->data_len = msg_len;
1157 cmdsp++;
1158 }
1159
1160 /* Type-A command to write buf0 */
1161 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1162 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1163 cmd = sba_cmd_enc(cmd, msg_len,
1164 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1165 cmd = sba_cmd_enc(cmd, 0x1,
1166 SBA_RESP_SHIFT, SBA_RESP_MASK);
1167 c_mdata = sba_cmd_write_c_mdata(0);
1168 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1169 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1170 cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
1171 SBA_CMD_SHIFT, SBA_CMD_MASK);
1172 cmdsp->cmd = cmd;
1173 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1174 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1175 if (req->sba->hw_resp_size) {
1176 cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
1177 cmdsp->resp = resp_dma;
1178 cmdsp->resp_len = req->sba->hw_resp_size;
1179 }
1180 cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
1181 cmdsp->data = *dst_p + msg_offset;
1182 cmdsp->data_len = msg_len;
1183 cmdsp++;
1184
1185skip_p:
1186 if (!dst_q)
1187 goto skip_q;
1188
1189 /* Type-A command to zero all buffers */
1190 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1191 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1192 cmd = sba_cmd_enc(cmd, msg_len,
1193 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1194 cmd = sba_cmd_enc(cmd, SBA_CMD_ZERO_ALL_BUFFERS,
1195 SBA_CMD_SHIFT, SBA_CMD_MASK);
1196 cmdsp->cmd = cmd;
1197 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1198 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1199 cmdsp++;
1200
1201 if (dpos == 255)
1202 goto skip_q_computation;
1203 pos = (dpos < req->sba->max_pq_coefs) ?
1204 dpos : (req->sba->max_pq_coefs - 1);
1205
1206 /*
1207 * Type-B command to generate initial Q from data
1208 * and store output into buf0
1209 */
1210 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1211 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1212 cmd = sba_cmd_enc(cmd, msg_len,
1213 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1214 c_mdata = sba_cmd_pq_c_mdata(pos, 0, 0);
1215 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1216 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1217 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_MS(c_mdata),
1218 SBA_C_MDATA_MS_SHIFT, SBA_C_MDATA_MS_MASK);
1219 cmd = sba_cmd_enc(cmd, SBA_CMD_GALOIS,
1220 SBA_CMD_SHIFT, SBA_CMD_MASK);
1221 cmdsp->cmd = cmd;
1222 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1223 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1224 cmdsp->data = src + msg_offset;
1225 cmdsp->data_len = msg_len;
1226 cmdsp++;
1227
1228 dpos -= pos;
1229
1230 /* Multiple Type-A command to generate final Q */
1231 while (dpos) {
1232 pos = (dpos < req->sba->max_pq_coefs) ?
1233 dpos : (req->sba->max_pq_coefs - 1);
1234
1235 /*
1236 * Type-A command to generate Q with buf0 and
1237 * buf1 store result in buf0
1238 */
1239 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1240 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1241 cmd = sba_cmd_enc(cmd, msg_len,
1242 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1243 c_mdata = sba_cmd_pq_c_mdata(pos, 0, 1);
1244 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1245 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1246 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_MS(c_mdata),
1247 SBA_C_MDATA_MS_SHIFT, SBA_C_MDATA_MS_MASK);
1248 cmd = sba_cmd_enc(cmd, SBA_CMD_GALOIS,
1249 SBA_CMD_SHIFT, SBA_CMD_MASK);
1250 cmdsp->cmd = cmd;
1251 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1252 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1253 cmdsp++;
1254
1255 dpos -= pos;
1256 }
1257
1258skip_q_computation:
1259 if (pq_continue) {
1260 /*
1261 * Type-B command to XOR previous output with
1262 * buf0 and write it into buf0
1263 */
1264 cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1265 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1266 cmd = sba_cmd_enc(cmd, msg_len,
1267 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1268 c_mdata = sba_cmd_xor_c_mdata(0, 0);
1269 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1270 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1271 cmd = sba_cmd_enc(cmd, SBA_CMD_XOR,
1272 SBA_CMD_SHIFT, SBA_CMD_MASK);
1273 cmdsp->cmd = cmd;
1274 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1275 cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1276 cmdsp->data = *dst_q + msg_offset;
1277 cmdsp->data_len = msg_len;
1278 cmdsp++;
1279 }
1280
1281 /* Type-A command to write buf0 */
1282 cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1283 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1284 cmd = sba_cmd_enc(cmd, msg_len,
1285 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1286 cmd = sba_cmd_enc(cmd, 0x1,
1287 SBA_RESP_SHIFT, SBA_RESP_MASK);
1288 c_mdata = sba_cmd_write_c_mdata(0);
1289 cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1290 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1291 cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
1292 SBA_CMD_SHIFT, SBA_CMD_MASK);
1293 cmdsp->cmd = cmd;
1294 *cmdsp->cmd_dma = cpu_to_le64(cmd);
1295 cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1296 if (req->sba->hw_resp_size) {
1297 cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
1298 cmdsp->resp = resp_dma;
1299 cmdsp->resp_len = req->sba->hw_resp_size;
1300 }
1301 cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
1302 cmdsp->data = *dst_q + msg_offset;
1303 cmdsp->data_len = msg_len;
1304 cmdsp++;
1305
1306skip_q:
1307 /* Fillup brcm_message */
1308 msg->type = BRCM_MESSAGE_SBA;
1309 msg->sba.cmds = cmds;
1310 msg->sba.cmds_count = cmdsp - cmds;
1311 msg->ctx = req;
1312 msg->error = 0;
1313}
1314
1315static struct sba_request *
1316sba_prep_dma_pq_single_req(struct sba_device *sba, dma_addr_t off,
1317 dma_addr_t *dst_p, dma_addr_t *dst_q,
1318 dma_addr_t src, u8 scf, size_t len,
1319 unsigned long flags)
1320{
1321 struct sba_request *req = NULL;
1322
1323 /* Alloc new request */
1324 req = sba_alloc_request(sba);
1325 if (!req)
1326 return NULL;
1327 if (flags & DMA_PREP_FENCE)
1328 req->flags |= SBA_REQUEST_FENCE;
1329
1330 /* Fillup request messages */
1331 sba_fillup_pq_single_msg(req, dmaf_continue(flags),
1332 req->cmds, &req->msg, off, len,
1333 dst_p, dst_q, src, scf);
1334
1335 /* Init async_tx descriptor */
1336 req->tx.flags = flags;
1337 req->tx.cookie = -EBUSY;
1338
1339 return req;
1340}
1341
1342static struct dma_async_tx_descriptor *
1343sba_prep_dma_pq(struct dma_chan *dchan, dma_addr_t *dst, dma_addr_t *src,
1344 u32 src_cnt, const u8 *scf, size_t len, unsigned long flags)
1345{
1346 u32 i, dst_q_index;
1347 size_t req_len;
1348 bool slow = false;
1349 dma_addr_t off = 0;
1350 dma_addr_t *dst_p = NULL, *dst_q = NULL;
1351 struct sba_device *sba = to_sba_device(dchan);
1352 struct sba_request *first = NULL, *req;
1353
1354 /* Sanity checks */
1355 if (unlikely(src_cnt > sba->max_pq_srcs))
1356 return NULL;
1357 for (i = 0; i < src_cnt; i++)
1358 if (sba->max_pq_coefs <= raid6_gflog[scf[i]])
1359 slow = true;
1360
1361 /* Figure-out P and Q destination addresses */
1362 if (!(flags & DMA_PREP_PQ_DISABLE_P))
1363 dst_p = &dst[0];
1364 if (!(flags & DMA_PREP_PQ_DISABLE_Q))
1365 dst_q = &dst[1];
1366
1367 /* Create chained requests where each request is upto hw_buf_size */
1368 while (len) {
1369 req_len = (len < sba->hw_buf_size) ? len : sba->hw_buf_size;
1370
1371 if (slow) {
1372 dst_q_index = src_cnt;
1373
1374 if (dst_q) {
1375 for (i = 0; i < src_cnt; i++) {
1376 if (*dst_q == src[i]) {
1377 dst_q_index = i;
1378 break;
1379 }
1380 }
1381 }
1382
1383 if (dst_q_index < src_cnt) {
1384 i = dst_q_index;
1385 req = sba_prep_dma_pq_single_req(sba,
1386 off, dst_p, dst_q, src[i], scf[i],
1387 req_len, flags | DMA_PREP_FENCE);
1388 if (!req)
1389 goto fail;
1390
1391 if (first)
1392 sba_chain_request(first, req);
1393 else
1394 first = req;
1395
1396 flags |= DMA_PREP_CONTINUE;
1397 }
1398
1399 for (i = 0; i < src_cnt; i++) {
1400 if (dst_q_index == i)
1401 continue;
1402
1403 req = sba_prep_dma_pq_single_req(sba,
1404 off, dst_p, dst_q, src[i], scf[i],
1405 req_len, flags | DMA_PREP_FENCE);
1406 if (!req)
1407 goto fail;
1408
1409 if (first)
1410 sba_chain_request(first, req);
1411 else
1412 first = req;
1413
1414 flags |= DMA_PREP_CONTINUE;
1415 }
1416 } else {
1417 req = sba_prep_dma_pq_req(sba, off,
1418 dst_p, dst_q, src, src_cnt,
1419 scf, req_len, flags);
1420 if (!req)
1421 goto fail;
1422
1423 if (first)
1424 sba_chain_request(first, req);
1425 else
1426 first = req;
1427 }
1428
1429 off += req_len;
1430 len -= req_len;
1431 }
1432
1433 return (first) ? &first->tx : NULL;
1434
1435fail:
1436 if (first)
1437 sba_free_chained_requests(first);
1438 return NULL;
1439}
1440
1441/* ====== Mailbox callbacks ===== */
1442
1443static void sba_receive_message(struct mbox_client *cl, void *msg)
1444{
1445 struct brcm_message *m = msg;
1446 struct sba_request *req = m->ctx;
1447 struct sba_device *sba = req->sba;
1448
1449 /* Error count if message has error */
1450 if (m->error < 0)
1451 dev_err(sba->dev, "%s got message with error %d",
1452 dma_chan_name(&sba->dma_chan), m->error);
1453
1454 /* Process received request */
1455 sba_process_received_request(sba, req);
1456}
1457
1458/* ====== Debugfs callbacks ====== */
1459
1460static int sba_debugfs_stats_show(struct seq_file *file, void *offset)
1461{
1462 struct platform_device *pdev = to_platform_device(file->private);
1463 struct sba_device *sba = platform_get_drvdata(pdev);
1464
1465 /* Write stats in file */
1466 sba_write_stats_in_seqfile(sba, file);
1467
1468 return 0;
1469}
1470
1471/* ====== Platform driver routines ===== */
1472
1473static int sba_prealloc_channel_resources(struct sba_device *sba)
1474{
1475 int i, j, ret = 0;
1476 struct sba_request *req = NULL;
1477
1478 sba->resp_base = dma_alloc_coherent(sba->mbox_dev,
1479 sba->max_resp_pool_size,
1480 &sba->resp_dma_base, GFP_KERNEL);
1481 if (!sba->resp_base)
1482 return -ENOMEM;
1483
1484 sba->cmds_base = dma_alloc_coherent(sba->mbox_dev,
1485 sba->max_cmds_pool_size,
1486 &sba->cmds_dma_base, GFP_KERNEL);
1487 if (!sba->cmds_base) {
1488 ret = -ENOMEM;
1489 goto fail_free_resp_pool;
1490 }
1491
1492 spin_lock_init(&sba->reqs_lock);
1493 sba->reqs_fence = false;
1494 INIT_LIST_HEAD(&sba->reqs_alloc_list);
1495 INIT_LIST_HEAD(&sba->reqs_pending_list);
1496 INIT_LIST_HEAD(&sba->reqs_active_list);
1497 INIT_LIST_HEAD(&sba->reqs_aborted_list);
1498 INIT_LIST_HEAD(&sba->reqs_free_list);
1499
1500 for (i = 0; i < sba->max_req; i++) {
1501 req = devm_kzalloc(sba->dev,
1502 sizeof(*req) +
1503 sba->max_cmd_per_req * sizeof(req->cmds[0]),
1504 GFP_KERNEL);
1505 if (!req) {
1506 ret = -ENOMEM;
1507 goto fail_free_cmds_pool;
1508 }
1509 INIT_LIST_HEAD(&req->node);
1510 req->sba = sba;
1511 req->flags = SBA_REQUEST_STATE_FREE;
1512 INIT_LIST_HEAD(&req->next);
1513 atomic_set(&req->next_pending_count, 0);
1514 for (j = 0; j < sba->max_cmd_per_req; j++) {
1515 req->cmds[j].cmd = 0;
1516 req->cmds[j].cmd_dma = sba->cmds_base +
1517 (i * sba->max_cmd_per_req + j) * sizeof(u64);
1518 req->cmds[j].cmd_dma_addr = sba->cmds_dma_base +
1519 (i * sba->max_cmd_per_req + j) * sizeof(u64);
1520 req->cmds[j].flags = 0;
1521 }
1522 memset(&req->msg, 0, sizeof(req->msg));
1523 dma_async_tx_descriptor_init(&req->tx, &sba->dma_chan);
1524 async_tx_ack(&req->tx);
1525 req->tx.tx_submit = sba_tx_submit;
1526 req->tx.phys = sba->resp_dma_base + i * sba->hw_resp_size;
1527 list_add_tail(&req->node, &sba->reqs_free_list);
1528 }
1529
1530 return 0;
1531
1532fail_free_cmds_pool:
1533 dma_free_coherent(sba->mbox_dev,
1534 sba->max_cmds_pool_size,
1535 sba->cmds_base, sba->cmds_dma_base);
1536fail_free_resp_pool:
1537 dma_free_coherent(sba->mbox_dev,
1538 sba->max_resp_pool_size,
1539 sba->resp_base, sba->resp_dma_base);
1540 return ret;
1541}
1542
1543static void sba_freeup_channel_resources(struct sba_device *sba)
1544{
1545 dmaengine_terminate_all(&sba->dma_chan);
1546 dma_free_coherent(sba->mbox_dev, sba->max_cmds_pool_size,
1547 sba->cmds_base, sba->cmds_dma_base);
1548 dma_free_coherent(sba->mbox_dev, sba->max_resp_pool_size,
1549 sba->resp_base, sba->resp_dma_base);
1550 sba->resp_base = NULL;
1551 sba->resp_dma_base = 0;
1552}
1553
1554static int sba_async_register(struct sba_device *sba)
1555{
1556 int ret;
1557 struct dma_device *dma_dev = &sba->dma_dev;
1558
1559 /* Initialize DMA channel cookie */
1560 sba->dma_chan.device = dma_dev;
1561 dma_cookie_init(&sba->dma_chan);
1562
1563 /* Initialize DMA device capability mask */
1564 dma_cap_zero(dma_dev->cap_mask);
1565 dma_cap_set(DMA_INTERRUPT, dma_dev->cap_mask);
1566 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
1567 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1568 dma_cap_set(DMA_PQ, dma_dev->cap_mask);
1569
1570 /*
1571 * Set mailbox channel device as the base device of
1572 * our dma_device because the actual memory accesses
1573 * will be done by mailbox controller
1574 */
1575 dma_dev->dev = sba->mbox_dev;
1576
1577 /* Set base prep routines */
1578 dma_dev->device_free_chan_resources = sba_free_chan_resources;
1579 dma_dev->device_terminate_all = sba_device_terminate_all;
1580 dma_dev->device_issue_pending = sba_issue_pending;
1581 dma_dev->device_tx_status = sba_tx_status;
1582
1583 /* Set interrupt routine */
1584 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1585 dma_dev->device_prep_dma_interrupt = sba_prep_dma_interrupt;
1586
1587 /* Set memcpy routine */
1588 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1589 dma_dev->device_prep_dma_memcpy = sba_prep_dma_memcpy;
1590
1591 /* Set xor routine and capability */
1592 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1593 dma_dev->device_prep_dma_xor = sba_prep_dma_xor;
1594 dma_dev->max_xor = sba->max_xor_srcs;
1595 }
1596
1597 /* Set pq routine and capability */
1598 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1599 dma_dev->device_prep_dma_pq = sba_prep_dma_pq;
1600 dma_set_maxpq(dma_dev, sba->max_pq_srcs, 0);
1601 }
1602
1603 /* Initialize DMA device channel list */
1604 INIT_LIST_HEAD(&dma_dev->channels);
1605 list_add_tail(&sba->dma_chan.device_node, &dma_dev->channels);
1606
1607 /* Register with Linux async DMA framework*/
1608 ret = dma_async_device_register(dma_dev);
1609 if (ret) {
1610 dev_err(sba->dev, "async device register error %d", ret);
1611 return ret;
1612 }
1613
1614 dev_info(sba->dev, "%s capabilities: %s%s%s%s\n",
1615 dma_chan_name(&sba->dma_chan),
1616 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "interrupt " : "",
1617 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "memcpy " : "",
1618 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1619 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "");
1620
1621 return 0;
1622}
1623
1624static int sba_probe(struct platform_device *pdev)
1625{
1626 int ret = 0;
1627 struct sba_device *sba;
1628 struct platform_device *mbox_pdev;
1629 struct of_phandle_args args;
1630
1631 /* Allocate main SBA struct */
1632 sba = devm_kzalloc(&pdev->dev, sizeof(*sba), GFP_KERNEL);
1633 if (!sba)
1634 return -ENOMEM;
1635
1636 sba->dev = &pdev->dev;
1637 platform_set_drvdata(pdev, sba);
1638
1639 /* Number of mailbox channels should be atleast 1 */
1640 ret = of_count_phandle_with_args(pdev->dev.of_node,
1641 "mboxes", "#mbox-cells");
1642 if (ret <= 0)
1643 return -ENODEV;
1644
1645 /* Determine SBA version from DT compatible string */
1646 if (of_device_is_compatible(sba->dev->of_node, "brcm,iproc-sba"))
1647 sba->ver = SBA_VER_1;
1648 else if (of_device_is_compatible(sba->dev->of_node,
1649 "brcm,iproc-sba-v2"))
1650 sba->ver = SBA_VER_2;
1651 else
1652 return -ENODEV;
1653
1654 /* Derived Configuration parameters */
1655 switch (sba->ver) {
1656 case SBA_VER_1:
1657 sba->hw_buf_size = 4096;
1658 sba->hw_resp_size = 8;
1659 sba->max_pq_coefs = 6;
1660 sba->max_pq_srcs = 6;
1661 break;
1662 case SBA_VER_2:
1663 sba->hw_buf_size = 4096;
1664 sba->hw_resp_size = 8;
1665 sba->max_pq_coefs = 30;
1666 /*
1667 * We can support max_pq_srcs == max_pq_coefs because
1668 * we are limited by number of SBA commands that we can
1669 * fit in one message for underlying ring manager HW.
1670 */
1671 sba->max_pq_srcs = 12;
1672 break;
1673 default:
1674 return -EINVAL;
1675 }
1676 sba->max_req = SBA_MAX_REQ_PER_MBOX_CHANNEL;
1677 sba->max_cmd_per_req = sba->max_pq_srcs + 3;
1678 sba->max_xor_srcs = sba->max_cmd_per_req - 1;
1679 sba->max_resp_pool_size = sba->max_req * sba->hw_resp_size;
1680 sba->max_cmds_pool_size = sba->max_req *
1681 sba->max_cmd_per_req * sizeof(u64);
1682
1683 /* Setup mailbox client */
1684 sba->client.dev = &pdev->dev;
1685 sba->client.rx_callback = sba_receive_message;
1686 sba->client.tx_block = false;
1687 sba->client.knows_txdone = true;
1688 sba->client.tx_tout = 0;
1689
1690 /* Request mailbox channel */
1691 sba->mchan = mbox_request_channel(&sba->client, 0);
1692 if (IS_ERR(sba->mchan)) {
1693 ret = PTR_ERR(sba->mchan);
1694 goto fail_free_mchan;
1695 }
1696
1697 /* Find-out underlying mailbox device */
1698 ret = of_parse_phandle_with_args(pdev->dev.of_node,
1699 "mboxes", "#mbox-cells", 0, &args);
1700 if (ret)
1701 goto fail_free_mchan;
1702 mbox_pdev = of_find_device_by_node(args.np);
1703 of_node_put(args.np);
1704 if (!mbox_pdev) {
1705 ret = -ENODEV;
1706 goto fail_free_mchan;
1707 }
1708 sba->mbox_dev = &mbox_pdev->dev;
1709
1710 /* Prealloc channel resource */
1711 ret = sba_prealloc_channel_resources(sba);
1712 if (ret)
1713 goto fail_free_mchan;
1714
1715 /* Check availability of debugfs */
1716 if (!debugfs_initialized())
1717 goto skip_debugfs;
1718
1719 /* Create debugfs root entry */
1720 sba->root = debugfs_create_dir(dev_name(sba->dev), NULL);
1721 if (IS_ERR_OR_NULL(sba->root)) {
1722 dev_err(sba->dev, "failed to create debugfs root entry\n");
1723 sba->root = NULL;
1724 goto skip_debugfs;
1725 }
1726
1727 /* Create debugfs stats entry */
1728 sba->stats = debugfs_create_devm_seqfile(sba->dev, "stats", sba->root,
1729 sba_debugfs_stats_show);
1730 if (IS_ERR_OR_NULL(sba->stats))
1731 dev_err(sba->dev, "failed to create debugfs stats file\n");
1732skip_debugfs:
1733
1734 /* Register DMA device with Linux async framework */
1735 ret = sba_async_register(sba);
1736 if (ret)
1737 goto fail_free_resources;
1738
1739 /* Print device info */
1740 dev_info(sba->dev, "%s using SBAv%d mailbox channel from %s",
1741 dma_chan_name(&sba->dma_chan), sba->ver+1,
1742 dev_name(sba->mbox_dev));
1743
1744 return 0;
1745
1746fail_free_resources:
1747 debugfs_remove_recursive(sba->root);
1748 sba_freeup_channel_resources(sba);
1749fail_free_mchan:
1750 mbox_free_channel(sba->mchan);
1751 return ret;
1752}
1753
1754static int sba_remove(struct platform_device *pdev)
1755{
1756 struct sba_device *sba = platform_get_drvdata(pdev);
1757
1758 dma_async_device_unregister(&sba->dma_dev);
1759
1760 debugfs_remove_recursive(sba->root);
1761
1762 sba_freeup_channel_resources(sba);
1763
1764 mbox_free_channel(sba->mchan);
1765
1766 return 0;
1767}
1768
1769static const struct of_device_id sba_of_match[] = {
1770 { .compatible = "brcm,iproc-sba", },
1771 { .compatible = "brcm,iproc-sba-v2", },
1772 {},
1773};
1774MODULE_DEVICE_TABLE(of, sba_of_match);
1775
1776static struct platform_driver sba_driver = {
1777 .probe = sba_probe,
1778 .remove = sba_remove,
1779 .driver = {
1780 .name = "bcm-sba-raid",
1781 .of_match_table = sba_of_match,
1782 },
1783};
1784module_platform_driver(sba_driver);
1785
1786MODULE_DESCRIPTION("Broadcom SBA RAID driver");
1787MODULE_AUTHOR("Anup Patel <anup.patel@broadcom.com>");
1788MODULE_LICENSE("GPL v2");