1/* SPDX-License-Identifier: GPL-2.0-or-later */
 2/*
 3 * Copyright (C) 2016 Imagination Technologies
 4 * Author: Marcin Nowakowski <marcin.nowakowski@mips.com>
 
 
 
 
 
 5 */
 6
 7#ifndef __PROBES_COMMON_H
 8#define __PROBES_COMMON_H
 9
10#include <asm/inst.h>
11
12int __insn_is_compact_branch(union mips_instruction insn);
13
14static inline int __insn_has_delay_slot(const union mips_instruction insn)
15{
16	switch (insn.i_format.opcode) {
17	/*
18	 * jr and jalr are in r_format format.
19	 */
20	case spec_op:
21		switch (insn.r_format.func) {
22		case jalr_op:
23		case jr_op:
24			return 1;
25		}
26		break;
27
28	/*
29	 * This group contains:
30	 * bltz_op, bgez_op, bltzl_op, bgezl_op,
31	 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
32	 */
33	case bcond_op:
34		switch (insn.i_format.rt) {
35		case bltz_op:
36		case bltzl_op:
37		case bgez_op:
38		case bgezl_op:
39		case bltzal_op:
40		case bltzall_op:
41		case bgezal_op:
42		case bgezall_op:
43		case bposge32_op:
44			return 1;
45		}
46		break;
47
48	/*
49	 * These are unconditional and in j_format.
50	 */
51	case jal_op:
52	case j_op:
53	case beq_op:
54	case beql_op:
55	case bne_op:
56	case bnel_op:
57	case blez_op: /* not really i_format */
58	case blezl_op:
59	case bgtz_op:
60	case bgtzl_op:
61		return 1;
62
63	/*
64	 * And now the FPA/cp1 branch instructions.
65	 */
66	case cop1_op:
67#ifdef CONFIG_CPU_CAVIUM_OCTEON
68	case lwc2_op: /* This is bbit0 on Octeon */
69	case ldc2_op: /* This is bbit032 on Octeon */
70	case swc2_op: /* This is bbit1 on Octeon */
71	case sdc2_op: /* This is bbit132 on Octeon */
72#endif
73		return 1;
74	}
75
76	return 0;
77}
78
79#endif  /* __PROBES_COMMON_H */

 
 1/*
 2 * Copyright (C) 2016 Imagination Technologies
 3 * Author: Marcin Nowakowski <marcin.nowakowski@mips.com>
 4 *
 5 * This program is free software; you can redistribute it and/or modify it
 6 * under the terms of the GNU General Public License as published by the
 7 * Free Software Foundation; either version 2 of the License, or (at your
 8 * option) any later version.
 9 */
10
11#ifndef __PROBES_COMMON_H
12#define __PROBES_COMMON_H
13
14#include <asm/inst.h>
15
16int __insn_is_compact_branch(union mips_instruction insn);
17
18static inline int __insn_has_delay_slot(const union mips_instruction insn)
19{
20	switch (insn.i_format.opcode) {
21	/*
22	 * jr and jalr are in r_format format.
23	 */
24	case spec_op:
25		switch (insn.r_format.func) {
26		case jalr_op:
27		case jr_op:
28			return 1;
29		}
30		break;
31
32	/*
33	 * This group contains:
34	 * bltz_op, bgez_op, bltzl_op, bgezl_op,
35	 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
36	 */
37	case bcond_op:
38		switch (insn.i_format.rt) {
39		case bltz_op:
40		case bltzl_op:
41		case bgez_op:
42		case bgezl_op:
43		case bltzal_op:
44		case bltzall_op:
45		case bgezal_op:
46		case bgezall_op:
47		case bposge32_op:
48			return 1;
49		}
50		break;
51
52	/*
53	 * These are unconditional and in j_format.
54	 */
55	case jal_op:
56	case j_op:
57	case beq_op:
58	case beql_op:
59	case bne_op:
60	case bnel_op:
61	case blez_op: /* not really i_format */
62	case blezl_op:
63	case bgtz_op:
64	case bgtzl_op:
65		return 1;
66
67	/*
68	 * And now the FPA/cp1 branch instructions.
69	 */
70	case cop1_op:
71#ifdef CONFIG_CPU_CAVIUM_OCTEON
72	case lwc2_op: /* This is bbit0 on Octeon */
73	case ldc2_op: /* This is bbit032 on Octeon */
74	case swc2_op: /* This is bbit1 on Octeon */
75	case sdc2_op: /* This is bbit132 on Octeon */
76#endif
77		return 1;
78	}
79
80	return 0;
81}
82
83#endif  /* __PROBES_COMMON_H */