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1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier Pro4 SoC
4//
5// Copyright (C) 2015-2016 Socionext Inc.
6// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8#include <dt-bindings/gpio/uniphier-gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12 compatible = "socionext,uniphier-pro4";
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a9";
23 reg = <0>;
24 enable-method = "psci";
25 next-level-cache = <&l2>;
26 };
27
28 cpu@1 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a9";
31 reg = <1>;
32 enable-method = "psci";
33 next-level-cache = <&l2>;
34 };
35 };
36
37 psci {
38 compatible = "arm,psci-0.2";
39 method = "smc";
40 };
41
42 clocks {
43 refclk: ref {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <25000000>;
47 };
48
49 arm_timer_clk: arm-timer {
50 #clock-cells = <0>;
51 compatible = "fixed-clock";
52 clock-frequency = <50000000>;
53 };
54 };
55
56 soc {
57 compatible = "simple-bus";
58 #address-cells = <1>;
59 #size-cells = <1>;
60 ranges;
61 interrupt-parent = <&intc>;
62
63 l2: cache-controller@500c0000 {
64 compatible = "socionext,uniphier-system-cache";
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
66 <0x506c0000 0x400>;
67 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
69 cache-unified;
70 cache-size = <(768 * 1024)>;
71 cache-sets = <256>;
72 cache-line-size = <128>;
73 cache-level = <2>;
74 };
75
76 spi0: spi@54006000 {
77 compatible = "socionext,uniphier-scssi";
78 status = "disabled";
79 reg = <0x54006000 0x100>;
80 #address-cells = <1>;
81 #size-cells = <0>;
82 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_spi0>;
85 clocks = <&peri_clk 11>;
86 resets = <&peri_rst 11>;
87 };
88
89 serial0: serial@54006800 {
90 compatible = "socionext,uniphier-uart";
91 status = "disabled";
92 reg = <0x54006800 0x40>;
93 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_uart0>;
96 clocks = <&peri_clk 0>;
97 resets = <&peri_rst 0>;
98 };
99
100 serial1: serial@54006900 {
101 compatible = "socionext,uniphier-uart";
102 status = "disabled";
103 reg = <0x54006900 0x40>;
104 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_uart1>;
107 clocks = <&peri_clk 1>;
108 resets = <&peri_rst 1>;
109 };
110
111 serial2: serial@54006a00 {
112 compatible = "socionext,uniphier-uart";
113 status = "disabled";
114 reg = <0x54006a00 0x40>;
115 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_uart2>;
118 clocks = <&peri_clk 2>;
119 resets = <&peri_rst 2>;
120 };
121
122 serial3: serial@54006b00 {
123 compatible = "socionext,uniphier-uart";
124 status = "disabled";
125 reg = <0x54006b00 0x40>;
126 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_uart3>;
129 clocks = <&peri_clk 3>;
130 resets = <&peri_rst 3>;
131 };
132
133 gpio: gpio@55000000 {
134 compatible = "socionext,uniphier-gpio";
135 reg = <0x55000000 0x200>;
136 interrupt-parent = <&aidet>;
137 interrupt-controller;
138 #interrupt-cells = <2>;
139 gpio-controller;
140 #gpio-cells = <2>;
141 gpio-ranges = <&pinctrl 0 0 0>;
142 gpio-ranges-group-names = "gpio_range";
143 ngpios = <248>;
144 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
145 };
146
147 i2c0: i2c@58780000 {
148 compatible = "socionext,uniphier-fi2c";
149 status = "disabled";
150 reg = <0x58780000 0x80>;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c0>;
156 clocks = <&peri_clk 4>;
157 resets = <&peri_rst 4>;
158 clock-frequency = <100000>;
159 };
160
161 i2c1: i2c@58781000 {
162 compatible = "socionext,uniphier-fi2c";
163 status = "disabled";
164 reg = <0x58781000 0x80>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_i2c1>;
170 clocks = <&peri_clk 5>;
171 resets = <&peri_rst 5>;
172 clock-frequency = <100000>;
173 };
174
175 i2c2: i2c@58782000 {
176 compatible = "socionext,uniphier-fi2c";
177 status = "disabled";
178 reg = <0x58782000 0x80>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_i2c2>;
184 clocks = <&peri_clk 6>;
185 resets = <&peri_rst 6>;
186 clock-frequency = <100000>;
187 };
188
189 i2c3: i2c@58783000 {
190 compatible = "socionext,uniphier-fi2c";
191 status = "disabled";
192 reg = <0x58783000 0x80>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c3>;
198 clocks = <&peri_clk 7>;
199 resets = <&peri_rst 7>;
200 clock-frequency = <100000>;
201 };
202
203 /* i2c4 does not exist */
204
205 /* chip-internal connection for DMD */
206 i2c5: i2c@58785000 {
207 compatible = "socionext,uniphier-fi2c";
208 reg = <0x58785000 0x80>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&peri_clk 9>;
213 resets = <&peri_rst 9>;
214 clock-frequency = <400000>;
215 };
216
217 /* chip-internal connection for HDMI */
218 i2c6: i2c@58786000 {
219 compatible = "socionext,uniphier-fi2c";
220 reg = <0x58786000 0x80>;
221 #address-cells = <1>;
222 #size-cells = <0>;
223 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&peri_clk 10>;
225 resets = <&peri_rst 10>;
226 clock-frequency = <400000>;
227 };
228
229 system_bus: system-bus@58c00000 {
230 compatible = "socionext,uniphier-system-bus";
231 status = "disabled";
232 reg = <0x58c00000 0x400>;
233 #address-cells = <2>;
234 #size-cells = <1>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_system_bus>;
237 };
238
239 smpctrl@59801000 {
240 compatible = "socionext,uniphier-smpctrl";
241 reg = <0x59801000 0x400>;
242 };
243
244 mioctrl@59810000 {
245 compatible = "socionext,uniphier-pro4-mioctrl",
246 "simple-mfd", "syscon";
247 reg = <0x59810000 0x800>;
248
249 mio_clk: clock {
250 compatible = "socionext,uniphier-pro4-mio-clock";
251 #clock-cells = <1>;
252 };
253
254 mio_rst: reset {
255 compatible = "socionext,uniphier-pro4-mio-reset";
256 #reset-cells = <1>;
257 };
258 };
259
260 perictrl@59820000 {
261 compatible = "socionext,uniphier-pro4-perictrl",
262 "simple-mfd", "syscon";
263 reg = <0x59820000 0x200>;
264
265 peri_clk: clock {
266 compatible = "socionext,uniphier-pro4-peri-clock";
267 #clock-cells = <1>;
268 };
269
270 peri_rst: reset {
271 compatible = "socionext,uniphier-pro4-peri-reset";
272 #reset-cells = <1>;
273 };
274 };
275
276 dmac: dma-controller@5a000000 {
277 compatible = "socionext,uniphier-mio-dmac";
278 reg = <0x5a000000 0x1000>;
279 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&mio_clk 7>;
288 resets = <&mio_rst 7>;
289 #dma-cells = <1>;
290 };
291
292 sd: mmc@5a400000 {
293 compatible = "socionext,uniphier-sd-v2.91";
294 status = "disabled";
295 reg = <0x5a400000 0x200>;
296 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
297 pinctrl-names = "default", "uhs";
298 pinctrl-0 = <&pinctrl_sd>;
299 pinctrl-1 = <&pinctrl_sd_uhs>;
300 clocks = <&mio_clk 0>;
301 reset-names = "host", "bridge";
302 resets = <&mio_rst 0>, <&mio_rst 3>;
303 dma-names = "rx-tx";
304 dmas = <&dmac 4>;
305 bus-width = <4>;
306 cap-sd-highspeed;
307 sd-uhs-sdr12;
308 sd-uhs-sdr25;
309 sd-uhs-sdr50;
310 };
311
312 emmc: mmc@5a500000 {
313 compatible = "socionext,uniphier-sd-v2.91";
314 status = "disabled";
315 reg = <0x5a500000 0x200>;
316 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_emmc>;
319 clocks = <&mio_clk 1>;
320 reset-names = "host", "bridge", "hw";
321 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
322 dma-names = "rx-tx";
323 dmas = <&dmac 5>;
324 bus-width = <8>;
325 cap-mmc-highspeed;
326 cap-mmc-hw-reset;
327 non-removable;
328 };
329
330 sd1: mmc@5a600000 {
331 compatible = "socionext,uniphier-sd-v2.91";
332 status = "disabled";
333 reg = <0x5a600000 0x200>;
334 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_sd1>;
337 clocks = <&mio_clk 2>;
338 reset-names = "host", "bridge";
339 resets = <&mio_rst 2>, <&mio_rst 5>;
340 dma-names = "rx-tx";
341 dmas = <&dmac 6>;
342 bus-width = <4>;
343 cap-sd-highspeed;
344 };
345
346 usb2: usb@5a800100 {
347 compatible = "socionext,uniphier-ehci", "generic-ehci";
348 status = "disabled";
349 reg = <0x5a800100 0x100>;
350 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_usb2>;
353 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
354 <&mio_clk 12>;
355 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
356 <&mio_rst 12>;
357 phy-names = "usb";
358 phys = <&usb_phy0>;
359 has-transaction-translator;
360 };
361
362 usb3: usb@5a810100 {
363 compatible = "socionext,uniphier-ehci", "generic-ehci";
364 status = "disabled";
365 reg = <0x5a810100 0x100>;
366 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_usb3>;
369 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
370 <&mio_clk 13>;
371 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
372 <&mio_rst 13>;
373 phy-names = "usb";
374 phys = <&usb_phy1>;
375 has-transaction-translator;
376 };
377
378 soc_glue: soc-glue@5f800000 {
379 compatible = "socionext,uniphier-pro4-soc-glue",
380 "simple-mfd", "syscon";
381 reg = <0x5f800000 0x2000>;
382
383 pinctrl: pinctrl {
384 compatible = "socionext,uniphier-pro4-pinctrl";
385 };
386
387 usb-controller {
388 compatible = "socionext,uniphier-pro4-usb2-phy";
389 #address-cells = <1>;
390 #size-cells = <0>;
391
392 usb_phy0: phy@0 {
393 reg = <0>;
394 #phy-cells = <0>;
395 };
396
397 usb_phy1: phy@1 {
398 reg = <1>;
399 #phy-cells = <0>;
400 };
401
402 usb_phy2: phy@2 {
403 reg = <2>;
404 #phy-cells = <0>;
405 vbus-supply = <&usb0_vbus>;
406 };
407
408 usb_phy3: phy@3 {
409 reg = <3>;
410 #phy-cells = <0>;
411 vbus-supply = <&usb1_vbus>;
412 };
413 };
414
415 sg_clk: clock {
416 compatible = "socionext,uniphier-pro4-sg-clock";
417 #clock-cells = <1>;
418 };
419 };
420
421 soc-glue@5f900000 {
422 compatible = "socionext,uniphier-pro4-soc-glue-debug",
423 "simple-mfd";
424 #address-cells = <1>;
425 #size-cells = <1>;
426 ranges = <0 0x5f900000 0x2000>;
427
428 efuse@100 {
429 compatible = "socionext,uniphier-efuse";
430 reg = <0x100 0x28>;
431 };
432
433 efuse@130 {
434 compatible = "socionext,uniphier-efuse";
435 reg = <0x130 0x8>;
436 };
437
438 efuse@200 {
439 compatible = "socionext,uniphier-efuse";
440 reg = <0x200 0x14>;
441 };
442 };
443
444 xdmac: dma-controller@5fc10000 {
445 compatible = "socionext,uniphier-xdmac";
446 reg = <0x5fc10000 0x5300>;
447 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
448 dma-channels = <16>;
449 #dma-cells = <2>;
450 };
451
452 aidet: interrupt-controller@5fc20000 {
453 compatible = "socionext,uniphier-pro4-aidet";
454 reg = <0x5fc20000 0x200>;
455 interrupt-controller;
456 #interrupt-cells = <2>;
457 };
458
459 timer@60000200 {
460 compatible = "arm,cortex-a9-global-timer";
461 reg = <0x60000200 0x20>;
462 interrupts = <GIC_PPI 11
463 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
464 clocks = <&arm_timer_clk>;
465 };
466
467 timer@60000600 {
468 compatible = "arm,cortex-a9-twd-timer";
469 reg = <0x60000600 0x20>;
470 interrupts = <GIC_PPI 13
471 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
472 clocks = <&arm_timer_clk>;
473 };
474
475 intc: interrupt-controller@60001000 {
476 compatible = "arm,cortex-a9-gic";
477 reg = <0x60001000 0x1000>,
478 <0x60000100 0x100>;
479 #interrupt-cells = <3>;
480 interrupt-controller;
481 };
482
483 sysctrl@61840000 {
484 compatible = "socionext,uniphier-pro4-sysctrl",
485 "simple-mfd", "syscon";
486 reg = <0x61840000 0x10000>;
487
488 sys_clk: clock {
489 compatible = "socionext,uniphier-pro4-clock";
490 #clock-cells = <1>;
491 };
492
493 sys_rst: reset {
494 compatible = "socionext,uniphier-pro4-reset";
495 #reset-cells = <1>;
496 };
497 };
498
499 eth: ethernet@65000000 {
500 compatible = "socionext,uniphier-pro4-ave4";
501 status = "disabled";
502 reg = <0x65000000 0x8500>;
503 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_ether_rgmii>;
506 clock-names = "gio", "ether", "ether-gb", "ether-phy";
507 clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>,
508 <&sys_clk 10>;
509 reset-names = "gio", "ether";
510 resets = <&sys_rst 12>, <&sys_rst 6>;
511 phy-mode = "rgmii";
512 local-mac-address = [00 00 00 00 00 00];
513 socionext,syscon-phy-mode = <&soc_glue 0>;
514
515 mdio: mdio {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 };
519 };
520
521 ahci0: sata@65600000 {
522 compatible = "socionext,uniphier-pro4-ahci",
523 "generic-ahci";
524 status = "disabled";
525 reg = <0x65600000 0x10000>;
526 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&sys_clk 12>, <&sys_clk 28>;
528 resets = <&sys_rst 12>, <&sys_rst 28>, <&ahci0_rst 3>;
529 ports-implemented = <1>;
530 phys = <&ahci0_phy>;
531 assigned-clocks = <&sg_clk 0>;
532 assigned-clock-rates = <25000000>;
533 };
534
535 sata-controller@65700000 {
536 compatible = "socionext,uniphier-pxs2-ahci-glue",
537 "simple-mfd";
538 #address-cells = <1>;
539 #size-cells = <1>;
540 ranges = <0 0x65700000 0x100>;
541
542 ahci0_rst: reset-controller@0 {
543 compatible = "socionext,uniphier-pro4-ahci-reset";
544 reg = <0x0 0x4>;
545 clock-names = "gio", "link";
546 clocks = <&sys_clk 12>, <&sys_clk 28>;
547 reset-names = "gio", "link";
548 resets = <&sys_rst 12>, <&sys_rst 28>;
549 #reset-cells = <1>;
550 };
551
552 ahci0_phy: sata-phy@10 {
553 compatible = "socionext,uniphier-pro4-ahci-phy";
554 reg = <0x10 0x40>;
555 clock-names = "link", "gio";
556 clocks = <&sys_clk 28>, <&sys_clk 12>;
557 reset-names = "link", "gio", "phy",
558 "pm", "tx", "rx";
559 resets = <&sys_rst 28>, <&sys_rst 12>,
560 <&sys_rst 30>,
561 <&ahci0_rst 0>, <&ahci0_rst 1>,
562 <&ahci0_rst 2>;
563 #phy-cells = <0>;
564 };
565 };
566
567 ahci1: sata@65800000 {
568 compatible = "socionext,uniphier-pro4-ahci",
569 "generic-ahci";
570 status = "disabled";
571 reg = <0x65800000 0x10000>;
572 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&sys_clk 12>, <&sys_clk 29>;
574 resets = <&sys_rst 12>, <&sys_rst 29>, <&ahci1_rst 3>;
575 ports-implemented = <1>;
576 phys = <&ahci1_phy>;
577 assigned-clocks = <&sg_clk 0>;
578 assigned-clock-rates = <25000000>;
579 };
580
581 sata-controller@65900000 {
582 compatible = "socionext,uniphier-pro4-ahci-glue",
583 "simple-mfd";
584 #address-cells = <1>;
585 #size-cells = <1>;
586 ranges = <0 0x65900000 0x100>;
587
588 ahci1_rst: reset-controller@0 {
589 compatible = "socionext,uniphier-pro4-ahci-reset";
590 reg = <0x0 0x4>;
591 clock-names = "gio", "link";
592 clocks = <&sys_clk 12>, <&sys_clk 29>;
593 reset-names = "gio", "link";
594 resets = <&sys_rst 12>, <&sys_rst 29>;
595 #reset-cells = <1>;
596 };
597
598 ahci1_phy: sata-phy@10 {
599 compatible = "socionext,uniphier-pro4-ahci-phy";
600 reg = <0x10 0x40>;
601 clock-names = "link", "gio";
602 clocks = <&sys_clk 29>, <&sys_clk 12>;
603 reset-names = "link", "gio", "phy",
604 "pm", "tx", "rx";
605 resets = <&sys_rst 29>, <&sys_rst 12>,
606 <&sys_rst 30>,
607 <&ahci1_rst 0>, <&ahci1_rst 1>,
608 <&ahci1_rst 2>;
609 #phy-cells = <0>;
610 };
611 };
612
613 usb0: usb@65a00000 {
614 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
615 status = "disabled";
616 reg = <0x65a00000 0xcd00>;
617 interrupt-names = "host", "peripheral";
618 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&pinctrl_usb0>;
622 clock-names = "ref", "bus_early", "suspend";
623 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
624 resets = <&usb0_rst 4>;
625 phys = <&usb_phy2>, <&usb0_ssphy>;
626 dr_mode = "host";
627 };
628
629 usb-controller@65b00000 {
630 compatible = "socionext,uniphier-pro4-dwc3-glue",
631 "simple-mfd";
632 #address-cells = <1>;
633 #size-cells = <1>;
634 ranges = <0 0x65b00000 0x100>;
635
636 usb0_vbus: regulator@0 {
637 compatible = "socionext,uniphier-pro4-usb3-regulator";
638 reg = <0 0x10>;
639 clock-names = "gio", "link";
640 clocks = <&sys_clk 12>, <&sys_clk 14>;
641 reset-names = "gio", "link";
642 resets = <&sys_rst 12>, <&sys_rst 14>;
643 };
644
645 usb0_ssphy: ss-phy@10 {
646 compatible = "socionext,uniphier-pro4-usb3-ssphy";
647 reg = <0x10 0x10>;
648 #phy-cells = <0>;
649 clock-names = "gio", "link";
650 clocks = <&sys_clk 12>, <&sys_clk 14>;
651 reset-names = "gio", "link";
652 resets = <&sys_rst 12>, <&sys_rst 14>;
653 vbus-supply = <&usb0_vbus>;
654 };
655
656 usb0_rst: reset@40 {
657 compatible = "socionext,uniphier-pro4-usb3-reset";
658 reg = <0x40 0x4>;
659 #reset-cells = <1>;
660 clock-names = "gio", "link";
661 clocks = <&sys_clk 12>, <&sys_clk 14>;
662 reset-names = "gio", "link";
663 resets = <&sys_rst 12>, <&sys_rst 14>;
664 };
665 };
666
667 usb1: usb@65c00000 {
668 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
669 status = "disabled";
670 reg = <0x65c00000 0xcd00>;
671 interrupt-names = "host", "peripheral";
672 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
674 pinctrl-names = "default";
675 pinctrl-0 = <&pinctrl_usb1>;
676 clock-names = "ref", "bus_early", "suspend";
677 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
678 resets = <&usb1_rst 4>;
679 phys = <&usb_phy3>;
680 dr_mode = "host";
681 };
682
683 usb-controller@65d00000 {
684 compatible = "socionext,uniphier-pro4-dwc3-glue",
685 "simple-mfd";
686 #address-cells = <1>;
687 #size-cells = <1>;
688 ranges = <0 0x65d00000 0x100>;
689
690 usb1_vbus: regulator@0 {
691 compatible = "socionext,uniphier-pro4-usb3-regulator";
692 reg = <0 0x10>;
693 clock-names = "gio", "link";
694 clocks = <&sys_clk 12>, <&sys_clk 15>;
695 reset-names = "gio", "link";
696 resets = <&sys_rst 12>, <&sys_rst 15>;
697 };
698
699 usb1_rst: reset@40 {
700 compatible = "socionext,uniphier-pro4-usb3-reset";
701 reg = <0x40 0x4>;
702 #reset-cells = <1>;
703 clock-names = "gio", "link";
704 clocks = <&sys_clk 12>, <&sys_clk 15>;
705 reset-names = "gio", "link";
706 resets = <&sys_rst 12>, <&sys_rst 15>;
707 };
708 };
709
710 nand: nand-controller@68000000 {
711 compatible = "socionext,uniphier-denali-nand-v5a";
712 status = "disabled";
713 reg-names = "nand_data", "denali_reg";
714 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
715 #address-cells = <1>;
716 #size-cells = <0>;
717 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
718 pinctrl-names = "default";
719 pinctrl-0 = <&pinctrl_nand>;
720 clock-names = "nand", "nand_x", "ecc";
721 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
722 reset-names = "nand", "reg";
723 resets = <&sys_rst 2>, <&sys_rst 2>;
724 };
725 };
726};
727
728#include "uniphier-pinctrl.dtsi"
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier Pro4 SoC
4//
5// Copyright (C) 2015-2016 Socionext Inc.
6// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8#include <dt-bindings/gpio/uniphier-gpio.h>
9
10/ {
11 compatible = "socionext,uniphier-pro4";
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 reg = <0>;
23 enable-method = "psci";
24 next-level-cache = <&l2>;
25 };
26
27 cpu@1 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a9";
30 reg = <1>;
31 enable-method = "psci";
32 next-level-cache = <&l2>;
33 };
34 };
35
36 psci {
37 compatible = "arm,psci-0.2";
38 method = "smc";
39 };
40
41 clocks {
42 refclk: ref {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <25000000>;
46 };
47
48 arm_timer_clk: arm-timer {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <50000000>;
52 };
53 };
54
55 soc {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges;
60 interrupt-parent = <&intc>;
61
62 l2: l2-cache@500c0000 {
63 compatible = "socionext,uniphier-system-cache";
64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
65 <0x506c0000 0x400>;
66 interrupts = <0 174 4>, <0 175 4>;
67 cache-unified;
68 cache-size = <(768 * 1024)>;
69 cache-sets = <256>;
70 cache-line-size = <128>;
71 cache-level = <2>;
72 };
73
74 serial0: serial@54006800 {
75 compatible = "socionext,uniphier-uart";
76 status = "disabled";
77 reg = <0x54006800 0x40>;
78 interrupts = <0 33 4>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_uart0>;
81 clocks = <&peri_clk 0>;
82 resets = <&peri_rst 0>;
83 };
84
85 serial1: serial@54006900 {
86 compatible = "socionext,uniphier-uart";
87 status = "disabled";
88 reg = <0x54006900 0x40>;
89 interrupts = <0 35 4>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_uart1>;
92 clocks = <&peri_clk 1>;
93 resets = <&peri_rst 1>;
94 };
95
96 serial2: serial@54006a00 {
97 compatible = "socionext,uniphier-uart";
98 status = "disabled";
99 reg = <0x54006a00 0x40>;
100 interrupts = <0 37 4>;
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_uart2>;
103 clocks = <&peri_clk 2>;
104 resets = <&peri_rst 2>;
105 };
106
107 serial3: serial@54006b00 {
108 compatible = "socionext,uniphier-uart";
109 status = "disabled";
110 reg = <0x54006b00 0x40>;
111 interrupts = <0 177 4>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_uart3>;
114 clocks = <&peri_clk 3>;
115 resets = <&peri_rst 3>;
116 };
117
118 gpio: gpio@55000000 {
119 compatible = "socionext,uniphier-gpio";
120 reg = <0x55000000 0x200>;
121 interrupt-parent = <&aidet>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 gpio-controller;
125 #gpio-cells = <2>;
126 gpio-ranges = <&pinctrl 0 0 0>;
127 gpio-ranges-group-names = "gpio_range";
128 ngpios = <248>;
129 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
130 };
131
132 i2c0: i2c@58780000 {
133 compatible = "socionext,uniphier-fi2c";
134 status = "disabled";
135 reg = <0x58780000 0x80>;
136 #address-cells = <1>;
137 #size-cells = <0>;
138 interrupts = <0 41 4>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_i2c0>;
141 clocks = <&peri_clk 4>;
142 resets = <&peri_rst 4>;
143 clock-frequency = <100000>;
144 };
145
146 i2c1: i2c@58781000 {
147 compatible = "socionext,uniphier-fi2c";
148 status = "disabled";
149 reg = <0x58781000 0x80>;
150 #address-cells = <1>;
151 #size-cells = <0>;
152 interrupts = <0 42 4>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_i2c1>;
155 clocks = <&peri_clk 5>;
156 resets = <&peri_rst 5>;
157 clock-frequency = <100000>;
158 };
159
160 i2c2: i2c@58782000 {
161 compatible = "socionext,uniphier-fi2c";
162 status = "disabled";
163 reg = <0x58782000 0x80>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 interrupts = <0 43 4>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_i2c2>;
169 clocks = <&peri_clk 6>;
170 resets = <&peri_rst 6>;
171 clock-frequency = <100000>;
172 };
173
174 i2c3: i2c@58783000 {
175 compatible = "socionext,uniphier-fi2c";
176 status = "disabled";
177 reg = <0x58783000 0x80>;
178 #address-cells = <1>;
179 #size-cells = <0>;
180 interrupts = <0 44 4>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_i2c3>;
183 clocks = <&peri_clk 7>;
184 resets = <&peri_rst 7>;
185 clock-frequency = <100000>;
186 };
187
188 /* i2c4 does not exist */
189
190 /* chip-internal connection for DMD */
191 i2c5: i2c@58785000 {
192 compatible = "socionext,uniphier-fi2c";
193 reg = <0x58785000 0x80>;
194 #address-cells = <1>;
195 #size-cells = <0>;
196 interrupts = <0 25 4>;
197 clocks = <&peri_clk 9>;
198 resets = <&peri_rst 9>;
199 clock-frequency = <400000>;
200 };
201
202 /* chip-internal connection for HDMI */
203 i2c6: i2c@58786000 {
204 compatible = "socionext,uniphier-fi2c";
205 reg = <0x58786000 0x80>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 interrupts = <0 26 4>;
209 clocks = <&peri_clk 10>;
210 resets = <&peri_rst 10>;
211 clock-frequency = <400000>;
212 };
213
214 system_bus: system-bus@58c00000 {
215 compatible = "socionext,uniphier-system-bus";
216 status = "disabled";
217 reg = <0x58c00000 0x400>;
218 #address-cells = <2>;
219 #size-cells = <1>;
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_system_bus>;
222 };
223
224 smpctrl@59801000 {
225 compatible = "socionext,uniphier-smpctrl";
226 reg = <0x59801000 0x400>;
227 };
228
229 mioctrl@59810000 {
230 compatible = "socionext,uniphier-pro4-mioctrl",
231 "simple-mfd", "syscon";
232 reg = <0x59810000 0x800>;
233
234 mio_clk: clock {
235 compatible = "socionext,uniphier-pro4-mio-clock";
236 #clock-cells = <1>;
237 };
238
239 mio_rst: reset {
240 compatible = "socionext,uniphier-pro4-mio-reset";
241 #reset-cells = <1>;
242 };
243 };
244
245 perictrl@59820000 {
246 compatible = "socionext,uniphier-pro4-perictrl",
247 "simple-mfd", "syscon";
248 reg = <0x59820000 0x200>;
249
250 peri_clk: clock {
251 compatible = "socionext,uniphier-pro4-peri-clock";
252 #clock-cells = <1>;
253 };
254
255 peri_rst: reset {
256 compatible = "socionext,uniphier-pro4-peri-reset";
257 #reset-cells = <1>;
258 };
259 };
260
261 usb2: usb@5a800100 {
262 compatible = "socionext,uniphier-ehci", "generic-ehci";
263 status = "disabled";
264 reg = <0x5a800100 0x100>;
265 interrupts = <0 80 4>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_usb2>;
268 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
269 <&mio_clk 12>;
270 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
271 <&mio_rst 12>;
272 has-transaction-translator;
273 };
274
275 usb3: usb@5a810100 {
276 compatible = "socionext,uniphier-ehci", "generic-ehci";
277 status = "disabled";
278 reg = <0x5a810100 0x100>;
279 interrupts = <0 81 4>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_usb3>;
282 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
283 <&mio_clk 13>;
284 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
285 <&mio_rst 13>;
286 has-transaction-translator;
287 };
288
289 soc-glue@5f800000 {
290 compatible = "socionext,uniphier-pro4-soc-glue",
291 "simple-mfd", "syscon";
292 reg = <0x5f800000 0x2000>;
293
294 pinctrl: pinctrl {
295 compatible = "socionext,uniphier-pro4-pinctrl";
296 };
297 };
298
299 soc-glue@5f900000 {
300 compatible = "socionext,uniphier-pro4-soc-glue-debug",
301 "simple-mfd";
302 #address-cells = <1>;
303 #size-cells = <1>;
304 ranges = <0 0x5f900000 0x2000>;
305
306 efuse@100 {
307 compatible = "socionext,uniphier-efuse";
308 reg = <0x100 0x28>;
309 };
310
311 efuse@130 {
312 compatible = "socionext,uniphier-efuse";
313 reg = <0x130 0x8>;
314 };
315
316 efuse@200 {
317 compatible = "socionext,uniphier-efuse";
318 reg = <0x200 0x14>;
319 };
320 };
321
322 aidet: aidet@5fc20000 {
323 compatible = "socionext,uniphier-pro4-aidet";
324 reg = <0x5fc20000 0x200>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 };
328
329 timer@60000200 {
330 compatible = "arm,cortex-a9-global-timer";
331 reg = <0x60000200 0x20>;
332 interrupts = <1 11 0x304>;
333 clocks = <&arm_timer_clk>;
334 };
335
336 timer@60000600 {
337 compatible = "arm,cortex-a9-twd-timer";
338 reg = <0x60000600 0x20>;
339 interrupts = <1 13 0x304>;
340 clocks = <&arm_timer_clk>;
341 };
342
343 intc: interrupt-controller@60001000 {
344 compatible = "arm,cortex-a9-gic";
345 reg = <0x60001000 0x1000>,
346 <0x60000100 0x100>;
347 #interrupt-cells = <3>;
348 interrupt-controller;
349 };
350
351 sysctrl@61840000 {
352 compatible = "socionext,uniphier-pro4-sysctrl",
353 "simple-mfd", "syscon";
354 reg = <0x61840000 0x10000>;
355
356 sys_clk: clock {
357 compatible = "socionext,uniphier-pro4-clock";
358 #clock-cells = <1>;
359 };
360
361 sys_rst: reset {
362 compatible = "socionext,uniphier-pro4-reset";
363 #reset-cells = <1>;
364 };
365 };
366
367 eth: ethernet@65000000 {
368 compatible = "socionext,uniphier-pro4-ave4";
369 status = "disabled";
370 reg = <0x65000000 0x8500>;
371 interrupts = <0 66 4>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_ether_rgmii>;
374 clocks = <&sys_clk 6>;
375 resets = <&sys_rst 6>;
376 phy-mode = "rgmii";
377 local-mac-address = [00 00 00 00 00 00];
378
379 mdio: mdio {
380 #address-cells = <1>;
381 #size-cells = <0>;
382 };
383 };
384
385 nand: nand@68000000 {
386 compatible = "socionext,uniphier-denali-nand-v5a";
387 status = "disabled";
388 reg-names = "nand_data", "denali_reg";
389 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
390 interrupts = <0 65 4>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_nand>;
393 clocks = <&sys_clk 2>;
394 resets = <&sys_rst 2>;
395 };
396 };
397};
398
399#include "uniphier-pinctrl.dtsi"