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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
4 */
5
6/dts-v1/;
7#include "imx27.dtsi"
8
9/ {
10 model = "Eukrea CPUIMX27";
11 compatible = "eukrea,cpuimx27", "fsl,imx27";
12
13 memory@a0000000 {
14 device_type = "memory";
15 reg = <0xa0000000 0x04000000>;
16 };
17
18 clk14745600: clk-uart {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <14745600>;
22 };
23};
24
25&fec {
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_fec>;
28 status = "okay";
29};
30
31&i2c1 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_i2c1>;
34 status = "okay";
35
36 pcf8563@51 {
37 compatible = "nxp,pcf8563";
38 reg = <0x51>;
39 };
40};
41
42&nfc {
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_nfc>;
45 nand-bus-width = <8>;
46 nand-ecc-mode = "hw";
47 nand-on-flash-bbt;
48 status = "okay";
49};
50
51&owire {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_owire>;
54 status = "okay";
55};
56
57&sdhci2 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_sdhc2>;
60 bus-width = <4>;
61 non-removable;
62 status = "okay";
63};
64
65&uart4 {
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_uart4>;
68 uart-has-rtscts;
69 status = "okay";
70};
71
72&usbh2 {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_usbh2>;
75 dr_mode = "host";
76 phy_type = "ulpi";
77 disable-over-current;
78 status = "okay";
79};
80
81&usbotg {
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_usbotg>;
84 dr_mode = "otg";
85 phy_type = "ulpi";
86 disable-over-current;
87 status = "okay";
88};
89
90&weim {
91 status = "okay";
92
93 nor: nor@0,0 {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "cfi-flash";
97 reg = <0 0x00000000 0x04000000>;
98 bank-width = <2>;
99 linux,mtd-name = "physmap-flash.0";
100 fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>;
101 };
102
103 uart8250@3,200000 {
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_uart8250_1>;
106 compatible = "ns8250";
107 clocks = <&clk14745600>;
108 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
109 interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>;
110 reg = <3 0x200000 0x1000>;
111 reg-shift = <1>;
112 reg-io-width = <1>;
113 no-loopback-test;
114 };
115
116 uart8250@3,400000 {
117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_uart8250_2>;
119 compatible = "ns8250";
120 clocks = <&clk14745600>;
121 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
122 interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
123 reg = <3 0x400000 0x1000>;
124 reg-shift = <1>;
125 reg-io-width = <1>;
126 no-loopback-test;
127 };
128
129 uart8250@3,800000 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_uart8250_3>;
132 compatible = "ns8250";
133 clocks = <&clk14745600>;
134 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
135 interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>;
136 reg = <3 0x800000 0x1000>;
137 reg-shift = <1>;
138 reg-io-width = <1>;
139 no-loopback-test;
140 };
141
142 uart8250@3,1000000 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_uart8250_4>;
145 compatible = "ns8250";
146 clocks = <&clk14745600>;
147 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
148 interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>;
149 reg = <3 0x1000000 0x1000>;
150 reg-shift = <1>;
151 reg-io-width = <1>;
152 no-loopback-test;
153 };
154};
155
156&iomuxc {
157 imx27-eukrea-cpuimx27 {
158 pinctrl_fec: fecgrp {
159 fsl,pins = <
160 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
161 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
162 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
163 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
164 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
165 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
166 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
167 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
168 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
169 MX27_PAD_ATA_DATA7__FEC_MDC 0x0
170 MX27_PAD_ATA_DATA8__FEC_CRS 0x0
171 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
172 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
173 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
174 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
175 MX27_PAD_ATA_DATA13__FEC_COL 0x0
176 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
177 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
178 >;
179 };
180
181 pinctrl_i2c1: i2c1grp {
182 fsl,pins = <
183 MX27_PAD_I2C_DATA__I2C_DATA 0x0
184 MX27_PAD_I2C_CLK__I2C_CLK 0x0
185 >;
186 };
187
188 pinctrl_nfc: nfcgrp {
189 fsl,pins = <
190 MX27_PAD_NFRB__NFRB 0x0
191 MX27_PAD_NFCLE__NFCLE 0x0
192 MX27_PAD_NFWP_B__NFWP_B 0x0
193 MX27_PAD_NFCE_B__NFCE_B 0x0
194 MX27_PAD_NFALE__NFALE 0x0
195 MX27_PAD_NFRE_B__NFRE_B 0x0
196 MX27_PAD_NFWE_B__NFWE_B 0x0
197 >;
198 };
199
200 pinctrl_owire: owiregrp {
201 fsl,pins = <
202 MX27_PAD_RTCK__OWIRE 0x0
203 >;
204 };
205
206 pinctrl_sdhc2: sdhc2grp {
207 fsl,pins = <
208 MX27_PAD_SD2_CLK__SD2_CLK 0x0
209 MX27_PAD_SD2_CMD__SD2_CMD 0x0
210 MX27_PAD_SD2_D0__SD2_D0 0x0
211 MX27_PAD_SD2_D1__SD2_D1 0x0
212 MX27_PAD_SD2_D2__SD2_D2 0x0
213 MX27_PAD_SD2_D3__SD2_D3 0x0
214 >;
215 };
216
217 pinctrl_uart4: uart4grp {
218 fsl,pins = <
219 MX27_PAD_USBH1_TXDM__UART4_TXD 0x0
220 MX27_PAD_USBH1_RXDP__UART4_RXD 0x0
221 MX27_PAD_USBH1_TXDP__UART4_CTS 0x0
222 MX27_PAD_USBH1_FS__UART4_RTS 0x0
223 >;
224 };
225
226 pinctrl_uart8250_1: uart82501grp {
227 fsl,pins = <
228 MX27_PAD_USB_PWR__GPIO2_23 0x0
229 >;
230 };
231
232 pinctrl_uart8250_2: uart82502grp {
233 fsl,pins = <
234 MX27_PAD_USBH1_SUSP__GPIO2_22 0x0
235 >;
236 };
237
238 pinctrl_uart8250_3: uart82503grp {
239 fsl,pins = <
240 MX27_PAD_USBH1_OE_B__GPIO2_27 0x0
241 >;
242 };
243
244 pinctrl_uart8250_4: uart82504grp {
245 fsl,pins = <
246 MX27_PAD_USBH1_RXDM__GPIO2_30 0x0
247 >;
248 };
249
250 pinctrl_usbh2: usbh2grp {
251 fsl,pins = <
252 MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
253 MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
254 MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
255 MX27_PAD_USBH2_STP__USBH2_STP 0x0
256 MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
257 MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
258 MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
259 MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
260 MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
261 MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
262 MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
263 MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
264 >;
265 };
266
267 pinctrl_usbotg: usbotggrp {
268 fsl,pins = <
269 MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
270 MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
271 MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
272 MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
273 MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
274 MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
275 MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
276 MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
277 MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
278 MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
279 MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
280 MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
281 >;
282 };
283 };
284};
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx27.dtsi"
14
15/ {
16 model = "Eukrea CPUIMX27";
17 compatible = "eukrea,cpuimx27", "fsl,imx27";
18
19 memory@a0000000 {
20 reg = <0xa0000000 0x04000000>;
21 };
22
23 clk14745600: clk-uart {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <14745600>;
27 };
28};
29
30&fec {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_fec>;
33 status = "okay";
34};
35
36&i2c1 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_i2c1>;
39 status = "okay";
40
41 pcf8563@51 {
42 compatible = "nxp,pcf8563";
43 reg = <0x51>;
44 };
45};
46
47&nfc {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_nfc>;
50 nand-bus-width = <8>;
51 nand-ecc-mode = "hw";
52 nand-on-flash-bbt;
53 status = "okay";
54};
55
56&owire {
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_owire>;
59 status = "okay";
60};
61
62&sdhci2 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_sdhc2>;
65 bus-width = <4>;
66 non-removable;
67 status = "okay";
68};
69
70&uart4 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_uart4>;
73 uart-has-rtscts;
74 status = "okay";
75};
76
77&usbh2 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_usbh2>;
80 dr_mode = "host";
81 phy_type = "ulpi";
82 disable-over-current;
83 status = "okay";
84};
85
86&usbotg {
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_usbotg>;
89 dr_mode = "otg";
90 phy_type = "ulpi";
91 disable-over-current;
92 status = "okay";
93};
94
95&weim {
96 status = "okay";
97
98 nor: nor@0,0 {
99 #address-cells = <1>;
100 #size-cells = <1>;
101 compatible = "cfi-flash";
102 reg = <0 0x00000000 0x04000000>;
103 bank-width = <2>;
104 linux,mtd-name = "physmap-flash.0";
105 fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>;
106 };
107
108 uart8250@3,200000 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_uart8250_1>;
111 compatible = "ns8250";
112 clocks = <&clk14745600>;
113 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
114 interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>;
115 reg = <3 0x200000 0x1000>;
116 reg-shift = <1>;
117 reg-io-width = <1>;
118 no-loopback-test;
119 };
120
121 uart8250@3,400000 {
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_uart8250_2>;
124 compatible = "ns8250";
125 clocks = <&clk14745600>;
126 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
127 interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
128 reg = <3 0x400000 0x1000>;
129 reg-shift = <1>;
130 reg-io-width = <1>;
131 no-loopback-test;
132 };
133
134 uart8250@3,800000 {
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_uart8250_3>;
137 compatible = "ns8250";
138 clocks = <&clk14745600>;
139 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
140 interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>;
141 reg = <3 0x800000 0x1000>;
142 reg-shift = <1>;
143 reg-io-width = <1>;
144 no-loopback-test;
145 };
146
147 uart8250@3,1000000 {
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_uart8250_4>;
150 compatible = "ns8250";
151 clocks = <&clk14745600>;
152 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
153 interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>;
154 reg = <3 0x1000000 0x1000>;
155 reg-shift = <1>;
156 reg-io-width = <1>;
157 no-loopback-test;
158 };
159};
160
161&iomuxc {
162 imx27-eukrea-cpuimx27 {
163 pinctrl_fec: fecgrp {
164 fsl,pins = <
165 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
166 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
167 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
168 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
169 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
170 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
171 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
172 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
173 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
174 MX27_PAD_ATA_DATA7__FEC_MDC 0x0
175 MX27_PAD_ATA_DATA8__FEC_CRS 0x0
176 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
177 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
178 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
179 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
180 MX27_PAD_ATA_DATA13__FEC_COL 0x0
181 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
182 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
183 >;
184 };
185
186 pinctrl_i2c1: i2c1grp {
187 fsl,pins = <
188 MX27_PAD_I2C_DATA__I2C_DATA 0x0
189 MX27_PAD_I2C_CLK__I2C_CLK 0x0
190 >;
191 };
192
193 pinctrl_nfc: nfcgrp {
194 fsl,pins = <
195 MX27_PAD_NFRB__NFRB 0x0
196 MX27_PAD_NFCLE__NFCLE 0x0
197 MX27_PAD_NFWP_B__NFWP_B 0x0
198 MX27_PAD_NFCE_B__NFCE_B 0x0
199 MX27_PAD_NFALE__NFALE 0x0
200 MX27_PAD_NFRE_B__NFRE_B 0x0
201 MX27_PAD_NFWE_B__NFWE_B 0x0
202 >;
203 };
204
205 pinctrl_owire: owiregrp {
206 fsl,pins = <
207 MX27_PAD_RTCK__OWIRE 0x0
208 >;
209 };
210
211 pinctrl_sdhc2: sdhc2grp {
212 fsl,pins = <
213 MX27_PAD_SD2_CLK__SD2_CLK 0x0
214 MX27_PAD_SD2_CMD__SD2_CMD 0x0
215 MX27_PAD_SD2_D0__SD2_D0 0x0
216 MX27_PAD_SD2_D1__SD2_D1 0x0
217 MX27_PAD_SD2_D2__SD2_D2 0x0
218 MX27_PAD_SD2_D3__SD2_D3 0x0
219 >;
220 };
221
222 pinctrl_uart4: uart4grp {
223 fsl,pins = <
224 MX27_PAD_USBH1_TXDM__UART4_TXD 0x0
225 MX27_PAD_USBH1_RXDP__UART4_RXD 0x0
226 MX27_PAD_USBH1_TXDP__UART4_CTS 0x0
227 MX27_PAD_USBH1_FS__UART4_RTS 0x0
228 >;
229 };
230
231 pinctrl_uart8250_1: uart82501grp {
232 fsl,pins = <
233 MX27_PAD_USB_PWR__GPIO2_23 0x0
234 >;
235 };
236
237 pinctrl_uart8250_2: uart82502grp {
238 fsl,pins = <
239 MX27_PAD_USBH1_SUSP__GPIO2_22 0x0
240 >;
241 };
242
243 pinctrl_uart8250_3: uart82503grp {
244 fsl,pins = <
245 MX27_PAD_USBH1_OE_B__GPIO2_27 0x0
246 >;
247 };
248
249 pinctrl_uart8250_4: uart82504grp {
250 fsl,pins = <
251 MX27_PAD_USBH1_RXDM__GPIO2_30 0x0
252 >;
253 };
254
255 pinctrl_usbh2: usbh2grp {
256 fsl,pins = <
257 MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
258 MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
259 MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
260 MX27_PAD_USBH2_STP__USBH2_STP 0x0
261 MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
262 MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
263 MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
264 MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
265 MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
266 MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
267 MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
268 MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
269 >;
270 };
271
272 pinctrl_usbotg: usbotggrp {
273 fsl,pins = <
274 MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
275 MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
276 MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
277 MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
278 MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
279 MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
280 MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
281 MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
282 MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
283 MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
284 MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
285 MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
286 >;
287 };
288 };
289};