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1/*
2 * sun4i_can.c - CAN bus controller driver for Allwinner SUN4I&SUN7I based SoCs
3 *
4 * Copyright (C) 2013 Peter Chen
5 * Copyright (C) 2015 Gerhard Bertelsmann
6 * All rights reserved.
7 *
8 * Parts of this software are based on (derived from) the SJA1000 code by:
9 * Copyright (C) 2014 Oliver Hartkopp <oliver.hartkopp@volkswagen.de>
10 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
11 * Copyright (C) 2002-2007 Volkswagen Group Electronic Research
12 * Copyright (C) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33,
13 * 38106 Braunschweig, GERMANY
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. Neither the name of Volkswagen nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * Alternatively, provided that this notice is retained in full, this
28 * software may be distributed under the terms of the GNU General
29 * Public License ("GPL") version 2, in which case the provisions of the
30 * GPL apply INSTEAD OF those given above.
31 *
32 * The provided data structures and external interfaces from this code
33 * are not restricted to be used by modules with a GPL compatible license.
34 *
35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
38 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
40 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
41 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
42 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
43 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
44 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
45 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
46 * DAMAGE.
47 *
48 */
49
50#include <linux/netdevice.h>
51#include <linux/can.h>
52#include <linux/can/dev.h>
53#include <linux/can/error.h>
54#include <linux/clk.h>
55#include <linux/delay.h>
56#include <linux/ethtool.h>
57#include <linux/interrupt.h>
58#include <linux/init.h>
59#include <linux/io.h>
60#include <linux/module.h>
61#include <linux/of.h>
62#include <linux/of_device.h>
63#include <linux/platform_device.h>
64#include <linux/reset.h>
65
66#define DRV_NAME "sun4i_can"
67
68/* Registers address (physical base address 0x01C2BC00) */
69#define SUN4I_REG_MSEL_ADDR 0x0000 /* CAN Mode Select */
70#define SUN4I_REG_CMD_ADDR 0x0004 /* CAN Command */
71#define SUN4I_REG_STA_ADDR 0x0008 /* CAN Status */
72#define SUN4I_REG_INT_ADDR 0x000c /* CAN Interrupt Flag */
73#define SUN4I_REG_INTEN_ADDR 0x0010 /* CAN Interrupt Enable */
74#define SUN4I_REG_BTIME_ADDR 0x0014 /* CAN Bus Timing 0 */
75#define SUN4I_REG_TEWL_ADDR 0x0018 /* CAN Tx Error Warning Limit */
76#define SUN4I_REG_ERRC_ADDR 0x001c /* CAN Error Counter */
77#define SUN4I_REG_RMCNT_ADDR 0x0020 /* CAN Receive Message Counter */
78#define SUN4I_REG_RBUFSA_ADDR 0x0024 /* CAN Receive Buffer Start Address */
79#define SUN4I_REG_BUF0_ADDR 0x0040 /* CAN Tx/Rx Buffer 0 */
80#define SUN4I_REG_BUF1_ADDR 0x0044 /* CAN Tx/Rx Buffer 1 */
81#define SUN4I_REG_BUF2_ADDR 0x0048 /* CAN Tx/Rx Buffer 2 */
82#define SUN4I_REG_BUF3_ADDR 0x004c /* CAN Tx/Rx Buffer 3 */
83#define SUN4I_REG_BUF4_ADDR 0x0050 /* CAN Tx/Rx Buffer 4 */
84#define SUN4I_REG_BUF5_ADDR 0x0054 /* CAN Tx/Rx Buffer 5 */
85#define SUN4I_REG_BUF6_ADDR 0x0058 /* CAN Tx/Rx Buffer 6 */
86#define SUN4I_REG_BUF7_ADDR 0x005c /* CAN Tx/Rx Buffer 7 */
87#define SUN4I_REG_BUF8_ADDR 0x0060 /* CAN Tx/Rx Buffer 8 */
88#define SUN4I_REG_BUF9_ADDR 0x0064 /* CAN Tx/Rx Buffer 9 */
89#define SUN4I_REG_BUF10_ADDR 0x0068 /* CAN Tx/Rx Buffer 10 */
90#define SUN4I_REG_BUF11_ADDR 0x006c /* CAN Tx/Rx Buffer 11 */
91#define SUN4I_REG_BUF12_ADDR 0x0070 /* CAN Tx/Rx Buffer 12 */
92#define SUN4I_REG_ACPC_ADDR 0x0040 /* CAN Acceptance Code 0 */
93#define SUN4I_REG_ACPM_ADDR 0x0044 /* CAN Acceptance Mask 0 */
94#define SUN4I_REG_RBUF_RBACK_START_ADDR 0x0180 /* CAN transmit buffer start */
95#define SUN4I_REG_RBUF_RBACK_END_ADDR 0x01b0 /* CAN transmit buffer end */
96
97/* Controller Register Description */
98
99/* mode select register (r/w)
100 * offset:0x0000 default:0x0000_0001
101 */
102#define SUN4I_MSEL_SLEEP_MODE (0x01 << 4) /* write in reset mode */
103#define SUN4I_MSEL_WAKE_UP (0x00 << 4)
104#define SUN4I_MSEL_SINGLE_FILTER (0x01 << 3) /* write in reset mode */
105#define SUN4I_MSEL_DUAL_FILTERS (0x00 << 3)
106#define SUN4I_MSEL_LOOPBACK_MODE BIT(2)
107#define SUN4I_MSEL_LISTEN_ONLY_MODE BIT(1)
108#define SUN4I_MSEL_RESET_MODE BIT(0)
109
110/* command register (w)
111 * offset:0x0004 default:0x0000_0000
112 */
113#define SUN4I_CMD_BUS_OFF_REQ BIT(5)
114#define SUN4I_CMD_SELF_RCV_REQ BIT(4)
115#define SUN4I_CMD_CLEAR_OR_FLAG BIT(3)
116#define SUN4I_CMD_RELEASE_RBUF BIT(2)
117#define SUN4I_CMD_ABORT_REQ BIT(1)
118#define SUN4I_CMD_TRANS_REQ BIT(0)
119
120/* status register (r)
121 * offset:0x0008 default:0x0000_003c
122 */
123#define SUN4I_STA_BIT_ERR (0x00 << 22)
124#define SUN4I_STA_FORM_ERR (0x01 << 22)
125#define SUN4I_STA_STUFF_ERR (0x02 << 22)
126#define SUN4I_STA_OTHER_ERR (0x03 << 22)
127#define SUN4I_STA_MASK_ERR (0x03 << 22)
128#define SUN4I_STA_ERR_DIR BIT(21)
129#define SUN4I_STA_ERR_SEG_CODE (0x1f << 16)
130#define SUN4I_STA_START (0x03 << 16)
131#define SUN4I_STA_ID28_21 (0x02 << 16)
132#define SUN4I_STA_ID20_18 (0x06 << 16)
133#define SUN4I_STA_SRTR (0x04 << 16)
134#define SUN4I_STA_IDE (0x05 << 16)
135#define SUN4I_STA_ID17_13 (0x07 << 16)
136#define SUN4I_STA_ID12_5 (0x0f << 16)
137#define SUN4I_STA_ID4_0 (0x0e << 16)
138#define SUN4I_STA_RTR (0x0c << 16)
139#define SUN4I_STA_RB1 (0x0d << 16)
140#define SUN4I_STA_RB0 (0x09 << 16)
141#define SUN4I_STA_DLEN (0x0b << 16)
142#define SUN4I_STA_DATA_FIELD (0x0a << 16)
143#define SUN4I_STA_CRC_SEQUENCE (0x08 << 16)
144#define SUN4I_STA_CRC_DELIMITER (0x18 << 16)
145#define SUN4I_STA_ACK (0x19 << 16)
146#define SUN4I_STA_ACK_DELIMITER (0x1b << 16)
147#define SUN4I_STA_END (0x1a << 16)
148#define SUN4I_STA_INTERMISSION (0x12 << 16)
149#define SUN4I_STA_ACTIVE_ERROR (0x11 << 16)
150#define SUN4I_STA_PASSIVE_ERROR (0x16 << 16)
151#define SUN4I_STA_TOLERATE_DOMINANT_BITS (0x13 << 16)
152#define SUN4I_STA_ERROR_DELIMITER (0x17 << 16)
153#define SUN4I_STA_OVERLOAD (0x1c << 16)
154#define SUN4I_STA_BUS_OFF BIT(7)
155#define SUN4I_STA_ERR_STA BIT(6)
156#define SUN4I_STA_TRANS_BUSY BIT(5)
157#define SUN4I_STA_RCV_BUSY BIT(4)
158#define SUN4I_STA_TRANS_OVER BIT(3)
159#define SUN4I_STA_TBUF_RDY BIT(2)
160#define SUN4I_STA_DATA_ORUN BIT(1)
161#define SUN4I_STA_RBUF_RDY BIT(0)
162
163/* interrupt register (r)
164 * offset:0x000c default:0x0000_0000
165 */
166#define SUN4I_INT_BUS_ERR BIT(7)
167#define SUN4I_INT_ARB_LOST BIT(6)
168#define SUN4I_INT_ERR_PASSIVE BIT(5)
169#define SUN4I_INT_WAKEUP BIT(4)
170#define SUN4I_INT_DATA_OR BIT(3)
171#define SUN4I_INT_ERR_WRN BIT(2)
172#define SUN4I_INT_TBUF_VLD BIT(1)
173#define SUN4I_INT_RBUF_VLD BIT(0)
174
175/* interrupt enable register (r/w)
176 * offset:0x0010 default:0x0000_0000
177 */
178#define SUN4I_INTEN_BERR BIT(7)
179#define SUN4I_INTEN_ARB_LOST BIT(6)
180#define SUN4I_INTEN_ERR_PASSIVE BIT(5)
181#define SUN4I_INTEN_WAKEUP BIT(4)
182#define SUN4I_INTEN_OR BIT(3)
183#define SUN4I_INTEN_ERR_WRN BIT(2)
184#define SUN4I_INTEN_TX BIT(1)
185#define SUN4I_INTEN_RX BIT(0)
186
187/* error code */
188#define SUN4I_ERR_INRCV (0x1 << 5)
189#define SUN4I_ERR_INTRANS (0x0 << 5)
190
191/* filter mode */
192#define SUN4I_FILTER_CLOSE 0
193#define SUN4I_SINGLE_FLTER_MODE 1
194#define SUN4I_DUAL_FILTER_MODE 2
195
196/* message buffer flags */
197#define SUN4I_MSG_EFF_FLAG BIT(7)
198#define SUN4I_MSG_RTR_FLAG BIT(6)
199
200/* max. number of interrupts handled in ISR */
201#define SUN4I_CAN_MAX_IRQ 20
202#define SUN4I_MODE_MAX_RETRIES 100
203
204/**
205 * struct sun4ican_quirks - Differences between SoC variants.
206 *
207 * @has_reset: SoC needs reset deasserted.
208 */
209struct sun4ican_quirks {
210 bool has_reset;
211};
212
213struct sun4ican_priv {
214 struct can_priv can;
215 void __iomem *base;
216 struct clk *clk;
217 struct reset_control *reset;
218 spinlock_t cmdreg_lock; /* lock for concurrent cmd register writes */
219};
220
221static const struct can_bittiming_const sun4ican_bittiming_const = {
222 .name = DRV_NAME,
223 .tseg1_min = 1,
224 .tseg1_max = 16,
225 .tseg2_min = 1,
226 .tseg2_max = 8,
227 .sjw_max = 4,
228 .brp_min = 1,
229 .brp_max = 64,
230 .brp_inc = 1,
231};
232
233static void sun4i_can_write_cmdreg(struct sun4ican_priv *priv, u8 val)
234{
235 unsigned long flags;
236
237 spin_lock_irqsave(&priv->cmdreg_lock, flags);
238 writel(val, priv->base + SUN4I_REG_CMD_ADDR);
239 spin_unlock_irqrestore(&priv->cmdreg_lock, flags);
240}
241
242static int set_normal_mode(struct net_device *dev)
243{
244 struct sun4ican_priv *priv = netdev_priv(dev);
245 int retry = SUN4I_MODE_MAX_RETRIES;
246 u32 mod_reg_val = 0;
247
248 do {
249 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
250 mod_reg_val &= ~SUN4I_MSEL_RESET_MODE;
251 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
252 } while (retry-- && (mod_reg_val & SUN4I_MSEL_RESET_MODE));
253
254 if (readl(priv->base + SUN4I_REG_MSEL_ADDR) & SUN4I_MSEL_RESET_MODE) {
255 netdev_err(dev,
256 "setting controller into normal mode failed!\n");
257 return -ETIMEDOUT;
258 }
259
260 return 0;
261}
262
263static int set_reset_mode(struct net_device *dev)
264{
265 struct sun4ican_priv *priv = netdev_priv(dev);
266 int retry = SUN4I_MODE_MAX_RETRIES;
267 u32 mod_reg_val = 0;
268
269 do {
270 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
271 mod_reg_val |= SUN4I_MSEL_RESET_MODE;
272 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
273 } while (retry-- && !(mod_reg_val & SUN4I_MSEL_RESET_MODE));
274
275 if (!(readl(priv->base + SUN4I_REG_MSEL_ADDR) &
276 SUN4I_MSEL_RESET_MODE)) {
277 netdev_err(dev, "setting controller into reset mode failed!\n");
278 return -ETIMEDOUT;
279 }
280
281 return 0;
282}
283
284/* bittiming is called in reset_mode only */
285static int sun4ican_set_bittiming(struct net_device *dev)
286{
287 struct sun4ican_priv *priv = netdev_priv(dev);
288 struct can_bittiming *bt = &priv->can.bittiming;
289 u32 cfg;
290
291 cfg = ((bt->brp - 1) & 0x3FF) |
292 (((bt->sjw - 1) & 0x3) << 14) |
293 (((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) << 16) |
294 (((bt->phase_seg2 - 1) & 0x7) << 20);
295 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
296 cfg |= 0x800000;
297
298 netdev_dbg(dev, "setting BITTIMING=0x%08x\n", cfg);
299 writel(cfg, priv->base + SUN4I_REG_BTIME_ADDR);
300
301 return 0;
302}
303
304static int sun4ican_get_berr_counter(const struct net_device *dev,
305 struct can_berr_counter *bec)
306{
307 struct sun4ican_priv *priv = netdev_priv(dev);
308 u32 errors;
309 int err;
310
311 err = clk_prepare_enable(priv->clk);
312 if (err) {
313 netdev_err(dev, "could not enable clock\n");
314 return err;
315 }
316
317 errors = readl(priv->base + SUN4I_REG_ERRC_ADDR);
318
319 bec->txerr = errors & 0xFF;
320 bec->rxerr = (errors >> 16) & 0xFF;
321
322 clk_disable_unprepare(priv->clk);
323
324 return 0;
325}
326
327static int sun4i_can_start(struct net_device *dev)
328{
329 struct sun4ican_priv *priv = netdev_priv(dev);
330 int err;
331 u32 mod_reg_val;
332
333 /* we need to enter the reset mode */
334 err = set_reset_mode(dev);
335 if (err) {
336 netdev_err(dev, "could not enter reset mode\n");
337 return err;
338 }
339
340 /* set filters - we accept all */
341 writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR);
342 writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR);
343
344 /* clear error counters and error code capture */
345 writel(0, priv->base + SUN4I_REG_ERRC_ADDR);
346
347 /* enable interrupts */
348 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
349 writel(0xFF, priv->base + SUN4I_REG_INTEN_ADDR);
350 else
351 writel(0xFF & ~SUN4I_INTEN_BERR,
352 priv->base + SUN4I_REG_INTEN_ADDR);
353
354 /* enter the selected mode */
355 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
356 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
357 mod_reg_val |= SUN4I_MSEL_LOOPBACK_MODE;
358 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
359 mod_reg_val |= SUN4I_MSEL_LISTEN_ONLY_MODE;
360 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
361
362 err = sun4ican_set_bittiming(dev);
363 if (err)
364 return err;
365
366 /* we are ready to enter the normal mode */
367 err = set_normal_mode(dev);
368 if (err) {
369 netdev_err(dev, "could not enter normal mode\n");
370 return err;
371 }
372
373 priv->can.state = CAN_STATE_ERROR_ACTIVE;
374
375 return 0;
376}
377
378static int sun4i_can_stop(struct net_device *dev)
379{
380 struct sun4ican_priv *priv = netdev_priv(dev);
381 int err;
382
383 priv->can.state = CAN_STATE_STOPPED;
384 /* we need to enter reset mode */
385 err = set_reset_mode(dev);
386 if (err) {
387 netdev_err(dev, "could not enter reset mode\n");
388 return err;
389 }
390
391 /* disable all interrupts */
392 writel(0, priv->base + SUN4I_REG_INTEN_ADDR);
393
394 return 0;
395}
396
397static int sun4ican_set_mode(struct net_device *dev, enum can_mode mode)
398{
399 int err;
400
401 switch (mode) {
402 case CAN_MODE_START:
403 err = sun4i_can_start(dev);
404 if (err) {
405 netdev_err(dev, "starting CAN controller failed!\n");
406 return err;
407 }
408 if (netif_queue_stopped(dev))
409 netif_wake_queue(dev);
410 break;
411
412 default:
413 return -EOPNOTSUPP;
414 }
415 return 0;
416}
417
418/* transmit a CAN message
419 * message layout in the sk_buff should be like this:
420 * xx xx xx xx ff ll 00 11 22 33 44 55 66 77
421 * [ can_id ] [flags] [len] [can data (up to 8 bytes]
422 */
423static netdev_tx_t sun4ican_start_xmit(struct sk_buff *skb, struct net_device *dev)
424{
425 struct sun4ican_priv *priv = netdev_priv(dev);
426 struct can_frame *cf = (struct can_frame *)skb->data;
427 u8 dlc;
428 u32 dreg, msg_flag_n;
429 canid_t id;
430 int i;
431
432 if (can_dev_dropped_skb(dev, skb))
433 return NETDEV_TX_OK;
434
435 netif_stop_queue(dev);
436
437 id = cf->can_id;
438 dlc = cf->len;
439 msg_flag_n = dlc;
440
441 if (id & CAN_RTR_FLAG)
442 msg_flag_n |= SUN4I_MSG_RTR_FLAG;
443
444 if (id & CAN_EFF_FLAG) {
445 msg_flag_n |= SUN4I_MSG_EFF_FLAG;
446 dreg = SUN4I_REG_BUF5_ADDR;
447 writel((id >> 21) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR);
448 writel((id >> 13) & 0xFF, priv->base + SUN4I_REG_BUF2_ADDR);
449 writel((id >> 5) & 0xFF, priv->base + SUN4I_REG_BUF3_ADDR);
450 writel((id << 3) & 0xF8, priv->base + SUN4I_REG_BUF4_ADDR);
451 } else {
452 dreg = SUN4I_REG_BUF3_ADDR;
453 writel((id >> 3) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR);
454 writel((id << 5) & 0xE0, priv->base + SUN4I_REG_BUF2_ADDR);
455 }
456
457 for (i = 0; i < dlc; i++)
458 writel(cf->data[i], priv->base + (dreg + i * 4));
459
460 writel(msg_flag_n, priv->base + SUN4I_REG_BUF0_ADDR);
461
462 can_put_echo_skb(skb, dev, 0, 0);
463
464 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
465 sun4i_can_write_cmdreg(priv, SUN4I_CMD_SELF_RCV_REQ);
466 else
467 sun4i_can_write_cmdreg(priv, SUN4I_CMD_TRANS_REQ);
468
469 return NETDEV_TX_OK;
470}
471
472static void sun4i_can_rx(struct net_device *dev)
473{
474 struct sun4ican_priv *priv = netdev_priv(dev);
475 struct net_device_stats *stats = &dev->stats;
476 struct can_frame *cf;
477 struct sk_buff *skb;
478 u8 fi;
479 u32 dreg;
480 canid_t id;
481 int i;
482
483 /* create zero'ed CAN frame buffer */
484 skb = alloc_can_skb(dev, &cf);
485 if (!skb)
486 return;
487
488 fi = readl(priv->base + SUN4I_REG_BUF0_ADDR);
489 cf->len = can_cc_dlc2len(fi & 0x0F);
490 if (fi & SUN4I_MSG_EFF_FLAG) {
491 dreg = SUN4I_REG_BUF5_ADDR;
492 id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 21) |
493 (readl(priv->base + SUN4I_REG_BUF2_ADDR) << 13) |
494 (readl(priv->base + SUN4I_REG_BUF3_ADDR) << 5) |
495 ((readl(priv->base + SUN4I_REG_BUF4_ADDR) >> 3) & 0x1f);
496 id |= CAN_EFF_FLAG;
497 } else {
498 dreg = SUN4I_REG_BUF3_ADDR;
499 id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 3) |
500 ((readl(priv->base + SUN4I_REG_BUF2_ADDR) >> 5) & 0x7);
501 }
502
503 /* remote frame ? */
504 if (fi & SUN4I_MSG_RTR_FLAG) {
505 id |= CAN_RTR_FLAG;
506 } else {
507 for (i = 0; i < cf->len; i++)
508 cf->data[i] = readl(priv->base + dreg + i * 4);
509
510 stats->rx_bytes += cf->len;
511 }
512 stats->rx_packets++;
513
514 cf->can_id = id;
515
516 sun4i_can_write_cmdreg(priv, SUN4I_CMD_RELEASE_RBUF);
517
518 netif_rx(skb);
519}
520
521static int sun4i_can_err(struct net_device *dev, u8 isrc, u8 status)
522{
523 struct sun4ican_priv *priv = netdev_priv(dev);
524 struct net_device_stats *stats = &dev->stats;
525 struct can_frame *cf;
526 struct sk_buff *skb;
527 enum can_state state = priv->can.state;
528 enum can_state rx_state, tx_state;
529 unsigned int rxerr, txerr, errc;
530 u32 ecc, alc;
531
532 /* we don't skip if alloc fails because we want the stats anyhow */
533 skb = alloc_can_err_skb(dev, &cf);
534
535 errc = readl(priv->base + SUN4I_REG_ERRC_ADDR);
536 rxerr = (errc >> 16) & 0xFF;
537 txerr = errc & 0xFF;
538
539 if (isrc & SUN4I_INT_DATA_OR) {
540 /* data overrun interrupt */
541 netdev_dbg(dev, "data overrun interrupt\n");
542 if (likely(skb)) {
543 cf->can_id |= CAN_ERR_CRTL;
544 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
545 }
546 stats->rx_over_errors++;
547 stats->rx_errors++;
548
549 /* reset the CAN IP by entering reset mode
550 * ignoring timeout error
551 */
552 set_reset_mode(dev);
553 set_normal_mode(dev);
554
555 /* clear bit */
556 sun4i_can_write_cmdreg(priv, SUN4I_CMD_CLEAR_OR_FLAG);
557 }
558 if (isrc & SUN4I_INT_ERR_WRN) {
559 /* error warning interrupt */
560 netdev_dbg(dev, "error warning interrupt\n");
561
562 if (status & SUN4I_STA_BUS_OFF)
563 state = CAN_STATE_BUS_OFF;
564 else if (status & SUN4I_STA_ERR_STA)
565 state = CAN_STATE_ERROR_WARNING;
566 else
567 state = CAN_STATE_ERROR_ACTIVE;
568 }
569 if (skb && state != CAN_STATE_BUS_OFF) {
570 cf->can_id |= CAN_ERR_CNT;
571 cf->data[6] = txerr;
572 cf->data[7] = rxerr;
573 }
574 if (isrc & SUN4I_INT_BUS_ERR) {
575 /* bus error interrupt */
576 netdev_dbg(dev, "bus error interrupt\n");
577 priv->can.can_stats.bus_error++;
578 stats->rx_errors++;
579
580 if (likely(skb)) {
581 ecc = readl(priv->base + SUN4I_REG_STA_ADDR);
582
583 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
584
585 switch (ecc & SUN4I_STA_MASK_ERR) {
586 case SUN4I_STA_BIT_ERR:
587 cf->data[2] |= CAN_ERR_PROT_BIT;
588 break;
589 case SUN4I_STA_FORM_ERR:
590 cf->data[2] |= CAN_ERR_PROT_FORM;
591 break;
592 case SUN4I_STA_STUFF_ERR:
593 cf->data[2] |= CAN_ERR_PROT_STUFF;
594 break;
595 default:
596 cf->data[3] = (ecc & SUN4I_STA_ERR_SEG_CODE)
597 >> 16;
598 break;
599 }
600 /* error occurred during transmission? */
601 if ((ecc & SUN4I_STA_ERR_DIR) == 0)
602 cf->data[2] |= CAN_ERR_PROT_TX;
603 }
604 }
605 if (isrc & SUN4I_INT_ERR_PASSIVE) {
606 /* error passive interrupt */
607 netdev_dbg(dev, "error passive interrupt\n");
608 if (state == CAN_STATE_ERROR_PASSIVE)
609 state = CAN_STATE_ERROR_WARNING;
610 else
611 state = CAN_STATE_ERROR_PASSIVE;
612 }
613 if (isrc & SUN4I_INT_ARB_LOST) {
614 /* arbitration lost interrupt */
615 netdev_dbg(dev, "arbitration lost interrupt\n");
616 alc = readl(priv->base + SUN4I_REG_STA_ADDR);
617 priv->can.can_stats.arbitration_lost++;
618 if (likely(skb)) {
619 cf->can_id |= CAN_ERR_LOSTARB;
620 cf->data[0] = (alc >> 8) & 0x1f;
621 }
622 }
623
624 if (state != priv->can.state) {
625 tx_state = txerr >= rxerr ? state : 0;
626 rx_state = txerr <= rxerr ? state : 0;
627
628 if (likely(skb))
629 can_change_state(dev, cf, tx_state, rx_state);
630 else
631 priv->can.state = state;
632 if (state == CAN_STATE_BUS_OFF)
633 can_bus_off(dev);
634 }
635
636 if (likely(skb))
637 netif_rx(skb);
638 else
639 return -ENOMEM;
640
641 return 0;
642}
643
644static irqreturn_t sun4i_can_interrupt(int irq, void *dev_id)
645{
646 struct net_device *dev = (struct net_device *)dev_id;
647 struct sun4ican_priv *priv = netdev_priv(dev);
648 struct net_device_stats *stats = &dev->stats;
649 u8 isrc, status;
650 int n = 0;
651
652 while ((isrc = readl(priv->base + SUN4I_REG_INT_ADDR)) &&
653 (n < SUN4I_CAN_MAX_IRQ)) {
654 n++;
655 status = readl(priv->base + SUN4I_REG_STA_ADDR);
656
657 if (isrc & SUN4I_INT_WAKEUP)
658 netdev_warn(dev, "wakeup interrupt\n");
659
660 if (isrc & SUN4I_INT_TBUF_VLD) {
661 /* transmission complete interrupt */
662 stats->tx_bytes += can_get_echo_skb(dev, 0, NULL);
663 stats->tx_packets++;
664 netif_wake_queue(dev);
665 }
666 if ((isrc & SUN4I_INT_RBUF_VLD) &&
667 !(isrc & SUN4I_INT_DATA_OR)) {
668 /* receive interrupt - don't read if overrun occurred */
669 while (status & SUN4I_STA_RBUF_RDY) {
670 /* RX buffer is not empty */
671 sun4i_can_rx(dev);
672 status = readl(priv->base + SUN4I_REG_STA_ADDR);
673 }
674 }
675 if (isrc &
676 (SUN4I_INT_DATA_OR | SUN4I_INT_ERR_WRN | SUN4I_INT_BUS_ERR |
677 SUN4I_INT_ERR_PASSIVE | SUN4I_INT_ARB_LOST)) {
678 /* error interrupt */
679 if (sun4i_can_err(dev, isrc, status))
680 netdev_err(dev, "can't allocate buffer - clearing pending interrupts\n");
681 }
682 /* clear interrupts */
683 writel(isrc, priv->base + SUN4I_REG_INT_ADDR);
684 readl(priv->base + SUN4I_REG_INT_ADDR);
685 }
686 if (n >= SUN4I_CAN_MAX_IRQ)
687 netdev_dbg(dev, "%d messages handled in ISR", n);
688
689 return (n) ? IRQ_HANDLED : IRQ_NONE;
690}
691
692static int sun4ican_open(struct net_device *dev)
693{
694 struct sun4ican_priv *priv = netdev_priv(dev);
695 int err;
696
697 /* common open */
698 err = open_candev(dev);
699 if (err)
700 return err;
701
702 /* register interrupt handler */
703 err = request_irq(dev->irq, sun4i_can_interrupt, 0, dev->name, dev);
704 if (err) {
705 netdev_err(dev, "request_irq err: %d\n", err);
706 goto exit_irq;
707 }
708
709 /* software reset deassert */
710 err = reset_control_deassert(priv->reset);
711 if (err) {
712 netdev_err(dev, "could not deassert CAN reset\n");
713 goto exit_soft_reset;
714 }
715
716 /* turn on clocking for CAN peripheral block */
717 err = clk_prepare_enable(priv->clk);
718 if (err) {
719 netdev_err(dev, "could not enable CAN peripheral clock\n");
720 goto exit_clock;
721 }
722
723 err = sun4i_can_start(dev);
724 if (err) {
725 netdev_err(dev, "could not start CAN peripheral\n");
726 goto exit_can_start;
727 }
728
729 netif_start_queue(dev);
730
731 return 0;
732
733exit_can_start:
734 clk_disable_unprepare(priv->clk);
735exit_clock:
736 reset_control_assert(priv->reset);
737exit_soft_reset:
738 free_irq(dev->irq, dev);
739exit_irq:
740 close_candev(dev);
741 return err;
742}
743
744static int sun4ican_close(struct net_device *dev)
745{
746 struct sun4ican_priv *priv = netdev_priv(dev);
747
748 netif_stop_queue(dev);
749 sun4i_can_stop(dev);
750 clk_disable_unprepare(priv->clk);
751 reset_control_assert(priv->reset);
752
753 free_irq(dev->irq, dev);
754 close_candev(dev);
755
756 return 0;
757}
758
759static const struct net_device_ops sun4ican_netdev_ops = {
760 .ndo_open = sun4ican_open,
761 .ndo_stop = sun4ican_close,
762 .ndo_start_xmit = sun4ican_start_xmit,
763};
764
765static const struct ethtool_ops sun4ican_ethtool_ops = {
766 .get_ts_info = ethtool_op_get_ts_info,
767};
768
769static const struct sun4ican_quirks sun4ican_quirks_a10 = {
770 .has_reset = false,
771};
772
773static const struct sun4ican_quirks sun4ican_quirks_r40 = {
774 .has_reset = true,
775};
776
777static const struct of_device_id sun4ican_of_match[] = {
778 {
779 .compatible = "allwinner,sun4i-a10-can",
780 .data = &sun4ican_quirks_a10
781 }, {
782 .compatible = "allwinner,sun7i-a20-can",
783 .data = &sun4ican_quirks_a10
784 }, {
785 .compatible = "allwinner,sun8i-r40-can",
786 .data = &sun4ican_quirks_r40
787 }, {
788 /* sentinel */
789 },
790};
791
792MODULE_DEVICE_TABLE(of, sun4ican_of_match);
793
794static int sun4ican_remove(struct platform_device *pdev)
795{
796 struct net_device *dev = platform_get_drvdata(pdev);
797
798 unregister_netdev(dev);
799 free_candev(dev);
800
801 return 0;
802}
803
804static int sun4ican_probe(struct platform_device *pdev)
805{
806 struct device_node *np = pdev->dev.of_node;
807 struct clk *clk;
808 struct reset_control *reset = NULL;
809 void __iomem *addr;
810 int err, irq;
811 struct net_device *dev;
812 struct sun4ican_priv *priv;
813 const struct sun4ican_quirks *quirks;
814
815 quirks = of_device_get_match_data(&pdev->dev);
816 if (!quirks) {
817 dev_err(&pdev->dev, "failed to determine the quirks to use\n");
818 err = -ENODEV;
819 goto exit;
820 }
821
822 if (quirks->has_reset) {
823 reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
824 if (IS_ERR(reset)) {
825 dev_err(&pdev->dev, "unable to request reset\n");
826 err = PTR_ERR(reset);
827 goto exit;
828 }
829 }
830
831 clk = of_clk_get(np, 0);
832 if (IS_ERR(clk)) {
833 dev_err(&pdev->dev, "unable to request clock\n");
834 err = -ENODEV;
835 goto exit;
836 }
837
838 irq = platform_get_irq(pdev, 0);
839 if (irq < 0) {
840 err = -ENODEV;
841 goto exit;
842 }
843
844 addr = devm_platform_ioremap_resource(pdev, 0);
845 if (IS_ERR(addr)) {
846 err = PTR_ERR(addr);
847 goto exit;
848 }
849
850 dev = alloc_candev(sizeof(struct sun4ican_priv), 1);
851 if (!dev) {
852 dev_err(&pdev->dev,
853 "could not allocate memory for CAN device\n");
854 err = -ENOMEM;
855 goto exit;
856 }
857
858 dev->netdev_ops = &sun4ican_netdev_ops;
859 dev->ethtool_ops = &sun4ican_ethtool_ops;
860 dev->irq = irq;
861 dev->flags |= IFF_ECHO;
862
863 priv = netdev_priv(dev);
864 priv->can.clock.freq = clk_get_rate(clk);
865 priv->can.bittiming_const = &sun4ican_bittiming_const;
866 priv->can.do_set_mode = sun4ican_set_mode;
867 priv->can.do_get_berr_counter = sun4ican_get_berr_counter;
868 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
869 CAN_CTRLMODE_LISTENONLY |
870 CAN_CTRLMODE_LOOPBACK |
871 CAN_CTRLMODE_3_SAMPLES;
872 priv->base = addr;
873 priv->clk = clk;
874 priv->reset = reset;
875 spin_lock_init(&priv->cmdreg_lock);
876
877 platform_set_drvdata(pdev, dev);
878 SET_NETDEV_DEV(dev, &pdev->dev);
879
880 err = register_candev(dev);
881 if (err) {
882 dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
883 DRV_NAME, err);
884 goto exit_free;
885 }
886
887 dev_info(&pdev->dev, "device registered (base=%p, irq=%d)\n",
888 priv->base, dev->irq);
889
890 return 0;
891
892exit_free:
893 free_candev(dev);
894exit:
895 return err;
896}
897
898static struct platform_driver sun4i_can_driver = {
899 .driver = {
900 .name = DRV_NAME,
901 .of_match_table = sun4ican_of_match,
902 },
903 .probe = sun4ican_probe,
904 .remove = sun4ican_remove,
905};
906
907module_platform_driver(sun4i_can_driver);
908
909MODULE_AUTHOR("Peter Chen <xingkongcp@gmail.com>");
910MODULE_AUTHOR("Gerhard Bertelsmann <info@gerhard-bertelsmann.de>");
911MODULE_LICENSE("Dual BSD/GPL");
912MODULE_DESCRIPTION("CAN driver for Allwinner SoCs (A10/A20)");
1/*
2 * sun4i_can.c - CAN bus controller driver for Allwinner SUN4I&SUN7I based SoCs
3 *
4 * Copyright (C) 2013 Peter Chen
5 * Copyright (C) 2015 Gerhard Bertelsmann
6 * All rights reserved.
7 *
8 * Parts of this software are based on (derived from) the SJA1000 code by:
9 * Copyright (C) 2014 Oliver Hartkopp <oliver.hartkopp@volkswagen.de>
10 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
11 * Copyright (C) 2002-2007 Volkswagen Group Electronic Research
12 * Copyright (C) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33,
13 * 38106 Braunschweig, GERMANY
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. Neither the name of Volkswagen nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * Alternatively, provided that this notice is retained in full, this
28 * software may be distributed under the terms of the GNU General
29 * Public License ("GPL") version 2, in which case the provisions of the
30 * GPL apply INSTEAD OF those given above.
31 *
32 * The provided data structures and external interfaces from this code
33 * are not restricted to be used by modules with a GPL compatible license.
34 *
35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
38 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
40 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
41 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
42 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
43 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
44 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
45 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
46 * DAMAGE.
47 *
48 */
49
50#include <linux/netdevice.h>
51#include <linux/can.h>
52#include <linux/can/dev.h>
53#include <linux/can/error.h>
54#include <linux/can/led.h>
55#include <linux/clk.h>
56#include <linux/delay.h>
57#include <linux/interrupt.h>
58#include <linux/init.h>
59#include <linux/io.h>
60#include <linux/module.h>
61#include <linux/of.h>
62#include <linux/of_device.h>
63#include <linux/platform_device.h>
64
65#define DRV_NAME "sun4i_can"
66
67/* Registers address (physical base address 0x01C2BC00) */
68#define SUN4I_REG_MSEL_ADDR 0x0000 /* CAN Mode Select */
69#define SUN4I_REG_CMD_ADDR 0x0004 /* CAN Command */
70#define SUN4I_REG_STA_ADDR 0x0008 /* CAN Status */
71#define SUN4I_REG_INT_ADDR 0x000c /* CAN Interrupt Flag */
72#define SUN4I_REG_INTEN_ADDR 0x0010 /* CAN Interrupt Enable */
73#define SUN4I_REG_BTIME_ADDR 0x0014 /* CAN Bus Timing 0 */
74#define SUN4I_REG_TEWL_ADDR 0x0018 /* CAN Tx Error Warning Limit */
75#define SUN4I_REG_ERRC_ADDR 0x001c /* CAN Error Counter */
76#define SUN4I_REG_RMCNT_ADDR 0x0020 /* CAN Receive Message Counter */
77#define SUN4I_REG_RBUFSA_ADDR 0x0024 /* CAN Receive Buffer Start Address */
78#define SUN4I_REG_BUF0_ADDR 0x0040 /* CAN Tx/Rx Buffer 0 */
79#define SUN4I_REG_BUF1_ADDR 0x0044 /* CAN Tx/Rx Buffer 1 */
80#define SUN4I_REG_BUF2_ADDR 0x0048 /* CAN Tx/Rx Buffer 2 */
81#define SUN4I_REG_BUF3_ADDR 0x004c /* CAN Tx/Rx Buffer 3 */
82#define SUN4I_REG_BUF4_ADDR 0x0050 /* CAN Tx/Rx Buffer 4 */
83#define SUN4I_REG_BUF5_ADDR 0x0054 /* CAN Tx/Rx Buffer 5 */
84#define SUN4I_REG_BUF6_ADDR 0x0058 /* CAN Tx/Rx Buffer 6 */
85#define SUN4I_REG_BUF7_ADDR 0x005c /* CAN Tx/Rx Buffer 7 */
86#define SUN4I_REG_BUF8_ADDR 0x0060 /* CAN Tx/Rx Buffer 8 */
87#define SUN4I_REG_BUF9_ADDR 0x0064 /* CAN Tx/Rx Buffer 9 */
88#define SUN4I_REG_BUF10_ADDR 0x0068 /* CAN Tx/Rx Buffer 10 */
89#define SUN4I_REG_BUF11_ADDR 0x006c /* CAN Tx/Rx Buffer 11 */
90#define SUN4I_REG_BUF12_ADDR 0x0070 /* CAN Tx/Rx Buffer 12 */
91#define SUN4I_REG_ACPC_ADDR 0x0040 /* CAN Acceptance Code 0 */
92#define SUN4I_REG_ACPM_ADDR 0x0044 /* CAN Acceptance Mask 0 */
93#define SUN4I_REG_RBUF_RBACK_START_ADDR 0x0180 /* CAN transmit buffer start */
94#define SUN4I_REG_RBUF_RBACK_END_ADDR 0x01b0 /* CAN transmit buffer end */
95
96/* Controller Register Description */
97
98/* mode select register (r/w)
99 * offset:0x0000 default:0x0000_0001
100 */
101#define SUN4I_MSEL_SLEEP_MODE (0x01 << 4) /* write in reset mode */
102#define SUN4I_MSEL_WAKE_UP (0x00 << 4)
103#define SUN4I_MSEL_SINGLE_FILTER (0x01 << 3) /* write in reset mode */
104#define SUN4I_MSEL_DUAL_FILTERS (0x00 << 3)
105#define SUN4I_MSEL_LOOPBACK_MODE BIT(2)
106#define SUN4I_MSEL_LISTEN_ONLY_MODE BIT(1)
107#define SUN4I_MSEL_RESET_MODE BIT(0)
108
109/* command register (w)
110 * offset:0x0004 default:0x0000_0000
111 */
112#define SUN4I_CMD_BUS_OFF_REQ BIT(5)
113#define SUN4I_CMD_SELF_RCV_REQ BIT(4)
114#define SUN4I_CMD_CLEAR_OR_FLAG BIT(3)
115#define SUN4I_CMD_RELEASE_RBUF BIT(2)
116#define SUN4I_CMD_ABORT_REQ BIT(1)
117#define SUN4I_CMD_TRANS_REQ BIT(0)
118
119/* status register (r)
120 * offset:0x0008 default:0x0000_003c
121 */
122#define SUN4I_STA_BIT_ERR (0x00 << 22)
123#define SUN4I_STA_FORM_ERR (0x01 << 22)
124#define SUN4I_STA_STUFF_ERR (0x02 << 22)
125#define SUN4I_STA_OTHER_ERR (0x03 << 22)
126#define SUN4I_STA_MASK_ERR (0x03 << 22)
127#define SUN4I_STA_ERR_DIR BIT(21)
128#define SUN4I_STA_ERR_SEG_CODE (0x1f << 16)
129#define SUN4I_STA_START (0x03 << 16)
130#define SUN4I_STA_ID28_21 (0x02 << 16)
131#define SUN4I_STA_ID20_18 (0x06 << 16)
132#define SUN4I_STA_SRTR (0x04 << 16)
133#define SUN4I_STA_IDE (0x05 << 16)
134#define SUN4I_STA_ID17_13 (0x07 << 16)
135#define SUN4I_STA_ID12_5 (0x0f << 16)
136#define SUN4I_STA_ID4_0 (0x0e << 16)
137#define SUN4I_STA_RTR (0x0c << 16)
138#define SUN4I_STA_RB1 (0x0d << 16)
139#define SUN4I_STA_RB0 (0x09 << 16)
140#define SUN4I_STA_DLEN (0x0b << 16)
141#define SUN4I_STA_DATA_FIELD (0x0a << 16)
142#define SUN4I_STA_CRC_SEQUENCE (0x08 << 16)
143#define SUN4I_STA_CRC_DELIMITER (0x18 << 16)
144#define SUN4I_STA_ACK (0x19 << 16)
145#define SUN4I_STA_ACK_DELIMITER (0x1b << 16)
146#define SUN4I_STA_END (0x1a << 16)
147#define SUN4I_STA_INTERMISSION (0x12 << 16)
148#define SUN4I_STA_ACTIVE_ERROR (0x11 << 16)
149#define SUN4I_STA_PASSIVE_ERROR (0x16 << 16)
150#define SUN4I_STA_TOLERATE_DOMINANT_BITS (0x13 << 16)
151#define SUN4I_STA_ERROR_DELIMITER (0x17 << 16)
152#define SUN4I_STA_OVERLOAD (0x1c << 16)
153#define SUN4I_STA_BUS_OFF BIT(7)
154#define SUN4I_STA_ERR_STA BIT(6)
155#define SUN4I_STA_TRANS_BUSY BIT(5)
156#define SUN4I_STA_RCV_BUSY BIT(4)
157#define SUN4I_STA_TRANS_OVER BIT(3)
158#define SUN4I_STA_TBUF_RDY BIT(2)
159#define SUN4I_STA_DATA_ORUN BIT(1)
160#define SUN4I_STA_RBUF_RDY BIT(0)
161
162/* interrupt register (r)
163 * offset:0x000c default:0x0000_0000
164 */
165#define SUN4I_INT_BUS_ERR BIT(7)
166#define SUN4I_INT_ARB_LOST BIT(6)
167#define SUN4I_INT_ERR_PASSIVE BIT(5)
168#define SUN4I_INT_WAKEUP BIT(4)
169#define SUN4I_INT_DATA_OR BIT(3)
170#define SUN4I_INT_ERR_WRN BIT(2)
171#define SUN4I_INT_TBUF_VLD BIT(1)
172#define SUN4I_INT_RBUF_VLD BIT(0)
173
174/* interrupt enable register (r/w)
175 * offset:0x0010 default:0x0000_0000
176 */
177#define SUN4I_INTEN_BERR BIT(7)
178#define SUN4I_INTEN_ARB_LOST BIT(6)
179#define SUN4I_INTEN_ERR_PASSIVE BIT(5)
180#define SUN4I_INTEN_WAKEUP BIT(4)
181#define SUN4I_INTEN_OR BIT(3)
182#define SUN4I_INTEN_ERR_WRN BIT(2)
183#define SUN4I_INTEN_TX BIT(1)
184#define SUN4I_INTEN_RX BIT(0)
185
186/* error code */
187#define SUN4I_ERR_INRCV (0x1 << 5)
188#define SUN4I_ERR_INTRANS (0x0 << 5)
189
190/* filter mode */
191#define SUN4I_FILTER_CLOSE 0
192#define SUN4I_SINGLE_FLTER_MODE 1
193#define SUN4I_DUAL_FILTER_MODE 2
194
195/* message buffer flags */
196#define SUN4I_MSG_EFF_FLAG BIT(7)
197#define SUN4I_MSG_RTR_FLAG BIT(6)
198
199/* max. number of interrupts handled in ISR */
200#define SUN4I_CAN_MAX_IRQ 20
201#define SUN4I_MODE_MAX_RETRIES 100
202
203struct sun4ican_priv {
204 struct can_priv can;
205 void __iomem *base;
206 struct clk *clk;
207 spinlock_t cmdreg_lock; /* lock for concurrent cmd register writes */
208};
209
210static const struct can_bittiming_const sun4ican_bittiming_const = {
211 .name = DRV_NAME,
212 .tseg1_min = 1,
213 .tseg1_max = 16,
214 .tseg2_min = 1,
215 .tseg2_max = 8,
216 .sjw_max = 4,
217 .brp_min = 1,
218 .brp_max = 64,
219 .brp_inc = 1,
220};
221
222static void sun4i_can_write_cmdreg(struct sun4ican_priv *priv, u8 val)
223{
224 unsigned long flags;
225
226 spin_lock_irqsave(&priv->cmdreg_lock, flags);
227 writel(val, priv->base + SUN4I_REG_CMD_ADDR);
228 spin_unlock_irqrestore(&priv->cmdreg_lock, flags);
229}
230
231static int set_normal_mode(struct net_device *dev)
232{
233 struct sun4ican_priv *priv = netdev_priv(dev);
234 int retry = SUN4I_MODE_MAX_RETRIES;
235 u32 mod_reg_val = 0;
236
237 do {
238 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
239 mod_reg_val &= ~SUN4I_MSEL_RESET_MODE;
240 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
241 } while (retry-- && (mod_reg_val & SUN4I_MSEL_RESET_MODE));
242
243 if (readl(priv->base + SUN4I_REG_MSEL_ADDR) & SUN4I_MSEL_RESET_MODE) {
244 netdev_err(dev,
245 "setting controller into normal mode failed!\n");
246 return -ETIMEDOUT;
247 }
248
249 return 0;
250}
251
252static int set_reset_mode(struct net_device *dev)
253{
254 struct sun4ican_priv *priv = netdev_priv(dev);
255 int retry = SUN4I_MODE_MAX_RETRIES;
256 u32 mod_reg_val = 0;
257
258 do {
259 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
260 mod_reg_val |= SUN4I_MSEL_RESET_MODE;
261 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
262 } while (retry-- && !(mod_reg_val & SUN4I_MSEL_RESET_MODE));
263
264 if (!(readl(priv->base + SUN4I_REG_MSEL_ADDR) &
265 SUN4I_MSEL_RESET_MODE)) {
266 netdev_err(dev, "setting controller into reset mode failed!\n");
267 return -ETIMEDOUT;
268 }
269
270 return 0;
271}
272
273/* bittiming is called in reset_mode only */
274static int sun4ican_set_bittiming(struct net_device *dev)
275{
276 struct sun4ican_priv *priv = netdev_priv(dev);
277 struct can_bittiming *bt = &priv->can.bittiming;
278 u32 cfg;
279
280 cfg = ((bt->brp - 1) & 0x3FF) |
281 (((bt->sjw - 1) & 0x3) << 14) |
282 (((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) << 16) |
283 (((bt->phase_seg2 - 1) & 0x7) << 20);
284 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
285 cfg |= 0x800000;
286
287 netdev_dbg(dev, "setting BITTIMING=0x%08x\n", cfg);
288 writel(cfg, priv->base + SUN4I_REG_BTIME_ADDR);
289
290 return 0;
291}
292
293static int sun4ican_get_berr_counter(const struct net_device *dev,
294 struct can_berr_counter *bec)
295{
296 struct sun4ican_priv *priv = netdev_priv(dev);
297 u32 errors;
298 int err;
299
300 err = clk_prepare_enable(priv->clk);
301 if (err) {
302 netdev_err(dev, "could not enable clock\n");
303 return err;
304 }
305
306 errors = readl(priv->base + SUN4I_REG_ERRC_ADDR);
307
308 bec->txerr = errors & 0xFF;
309 bec->rxerr = (errors >> 16) & 0xFF;
310
311 clk_disable_unprepare(priv->clk);
312
313 return 0;
314}
315
316static int sun4i_can_start(struct net_device *dev)
317{
318 struct sun4ican_priv *priv = netdev_priv(dev);
319 int err;
320 u32 mod_reg_val;
321
322 /* we need to enter the reset mode */
323 err = set_reset_mode(dev);
324 if (err) {
325 netdev_err(dev, "could not enter reset mode\n");
326 return err;
327 }
328
329 /* set filters - we accept all */
330 writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR);
331 writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR);
332
333 /* clear error counters and error code capture */
334 writel(0, priv->base + SUN4I_REG_ERRC_ADDR);
335
336 /* enable interrupts */
337 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
338 writel(0xFF, priv->base + SUN4I_REG_INTEN_ADDR);
339 else
340 writel(0xFF & ~SUN4I_INTEN_BERR,
341 priv->base + SUN4I_REG_INTEN_ADDR);
342
343 /* enter the selected mode */
344 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
345 if (priv->can.ctrlmode & CAN_CTRLMODE_PRESUME_ACK)
346 mod_reg_val |= SUN4I_MSEL_LOOPBACK_MODE;
347 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
348 mod_reg_val |= SUN4I_MSEL_LISTEN_ONLY_MODE;
349 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
350
351 err = sun4ican_set_bittiming(dev);
352 if (err)
353 return err;
354
355 /* we are ready to enter the normal mode */
356 err = set_normal_mode(dev);
357 if (err) {
358 netdev_err(dev, "could not enter normal mode\n");
359 return err;
360 }
361
362 priv->can.state = CAN_STATE_ERROR_ACTIVE;
363
364 return 0;
365}
366
367static int sun4i_can_stop(struct net_device *dev)
368{
369 struct sun4ican_priv *priv = netdev_priv(dev);
370 int err;
371
372 priv->can.state = CAN_STATE_STOPPED;
373 /* we need to enter reset mode */
374 err = set_reset_mode(dev);
375 if (err) {
376 netdev_err(dev, "could not enter reset mode\n");
377 return err;
378 }
379
380 /* disable all interrupts */
381 writel(0, priv->base + SUN4I_REG_INTEN_ADDR);
382
383 return 0;
384}
385
386static int sun4ican_set_mode(struct net_device *dev, enum can_mode mode)
387{
388 int err;
389
390 switch (mode) {
391 case CAN_MODE_START:
392 err = sun4i_can_start(dev);
393 if (err) {
394 netdev_err(dev, "starting CAN controller failed!\n");
395 return err;
396 }
397 if (netif_queue_stopped(dev))
398 netif_wake_queue(dev);
399 break;
400
401 default:
402 return -EOPNOTSUPP;
403 }
404 return 0;
405}
406
407/* transmit a CAN message
408 * message layout in the sk_buff should be like this:
409 * xx xx xx xx ff ll 00 11 22 33 44 55 66 77
410 * [ can_id ] [flags] [len] [can data (up to 8 bytes]
411 */
412static int sun4ican_start_xmit(struct sk_buff *skb, struct net_device *dev)
413{
414 struct sun4ican_priv *priv = netdev_priv(dev);
415 struct can_frame *cf = (struct can_frame *)skb->data;
416 u8 dlc;
417 u32 dreg, msg_flag_n;
418 canid_t id;
419 int i;
420
421 if (can_dropped_invalid_skb(dev, skb))
422 return NETDEV_TX_OK;
423
424 netif_stop_queue(dev);
425
426 id = cf->can_id;
427 dlc = cf->can_dlc;
428 msg_flag_n = dlc;
429
430 if (id & CAN_RTR_FLAG)
431 msg_flag_n |= SUN4I_MSG_RTR_FLAG;
432
433 if (id & CAN_EFF_FLAG) {
434 msg_flag_n |= SUN4I_MSG_EFF_FLAG;
435 dreg = SUN4I_REG_BUF5_ADDR;
436 writel((id >> 21) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR);
437 writel((id >> 13) & 0xFF, priv->base + SUN4I_REG_BUF2_ADDR);
438 writel((id >> 5) & 0xFF, priv->base + SUN4I_REG_BUF3_ADDR);
439 writel((id << 3) & 0xF8, priv->base + SUN4I_REG_BUF4_ADDR);
440 } else {
441 dreg = SUN4I_REG_BUF3_ADDR;
442 writel((id >> 3) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR);
443 writel((id << 5) & 0xE0, priv->base + SUN4I_REG_BUF2_ADDR);
444 }
445
446 for (i = 0; i < dlc; i++)
447 writel(cf->data[i], priv->base + (dreg + i * 4));
448
449 writel(msg_flag_n, priv->base + SUN4I_REG_BUF0_ADDR);
450
451 can_put_echo_skb(skb, dev, 0);
452
453 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
454 sun4i_can_write_cmdreg(priv, SUN4I_CMD_SELF_RCV_REQ);
455 else
456 sun4i_can_write_cmdreg(priv, SUN4I_CMD_TRANS_REQ);
457
458 return NETDEV_TX_OK;
459}
460
461static void sun4i_can_rx(struct net_device *dev)
462{
463 struct sun4ican_priv *priv = netdev_priv(dev);
464 struct net_device_stats *stats = &dev->stats;
465 struct can_frame *cf;
466 struct sk_buff *skb;
467 u8 fi;
468 u32 dreg;
469 canid_t id;
470 int i;
471
472 /* create zero'ed CAN frame buffer */
473 skb = alloc_can_skb(dev, &cf);
474 if (!skb)
475 return;
476
477 fi = readl(priv->base + SUN4I_REG_BUF0_ADDR);
478 cf->can_dlc = get_can_dlc(fi & 0x0F);
479 if (fi & SUN4I_MSG_EFF_FLAG) {
480 dreg = SUN4I_REG_BUF5_ADDR;
481 id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 21) |
482 (readl(priv->base + SUN4I_REG_BUF2_ADDR) << 13) |
483 (readl(priv->base + SUN4I_REG_BUF3_ADDR) << 5) |
484 ((readl(priv->base + SUN4I_REG_BUF4_ADDR) >> 3) & 0x1f);
485 id |= CAN_EFF_FLAG;
486 } else {
487 dreg = SUN4I_REG_BUF3_ADDR;
488 id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 3) |
489 ((readl(priv->base + SUN4I_REG_BUF2_ADDR) >> 5) & 0x7);
490 }
491
492 /* remote frame ? */
493 if (fi & SUN4I_MSG_RTR_FLAG)
494 id |= CAN_RTR_FLAG;
495 else
496 for (i = 0; i < cf->can_dlc; i++)
497 cf->data[i] = readl(priv->base + dreg + i * 4);
498
499 cf->can_id = id;
500
501 sun4i_can_write_cmdreg(priv, SUN4I_CMD_RELEASE_RBUF);
502
503 stats->rx_packets++;
504 stats->rx_bytes += cf->can_dlc;
505 netif_rx(skb);
506
507 can_led_event(dev, CAN_LED_EVENT_RX);
508}
509
510static int sun4i_can_err(struct net_device *dev, u8 isrc, u8 status)
511{
512 struct sun4ican_priv *priv = netdev_priv(dev);
513 struct net_device_stats *stats = &dev->stats;
514 struct can_frame *cf;
515 struct sk_buff *skb;
516 enum can_state state = priv->can.state;
517 enum can_state rx_state, tx_state;
518 unsigned int rxerr, txerr, errc;
519 u32 ecc, alc;
520
521 /* we don't skip if alloc fails because we want the stats anyhow */
522 skb = alloc_can_err_skb(dev, &cf);
523
524 errc = readl(priv->base + SUN4I_REG_ERRC_ADDR);
525 rxerr = (errc >> 16) & 0xFF;
526 txerr = errc & 0xFF;
527
528 if (skb) {
529 cf->data[6] = txerr;
530 cf->data[7] = rxerr;
531 }
532
533 if (isrc & SUN4I_INT_DATA_OR) {
534 /* data overrun interrupt */
535 netdev_dbg(dev, "data overrun interrupt\n");
536 if (likely(skb)) {
537 cf->can_id |= CAN_ERR_CRTL;
538 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
539 }
540 stats->rx_over_errors++;
541 stats->rx_errors++;
542 /* clear bit */
543 sun4i_can_write_cmdreg(priv, SUN4I_CMD_CLEAR_OR_FLAG);
544 }
545 if (isrc & SUN4I_INT_ERR_WRN) {
546 /* error warning interrupt */
547 netdev_dbg(dev, "error warning interrupt\n");
548
549 if (status & SUN4I_STA_BUS_OFF)
550 state = CAN_STATE_BUS_OFF;
551 else if (status & SUN4I_STA_ERR_STA)
552 state = CAN_STATE_ERROR_WARNING;
553 else
554 state = CAN_STATE_ERROR_ACTIVE;
555 }
556 if (isrc & SUN4I_INT_BUS_ERR) {
557 /* bus error interrupt */
558 netdev_dbg(dev, "bus error interrupt\n");
559 priv->can.can_stats.bus_error++;
560 stats->rx_errors++;
561
562 if (likely(skb)) {
563 ecc = readl(priv->base + SUN4I_REG_STA_ADDR);
564
565 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
566
567 switch (ecc & SUN4I_STA_MASK_ERR) {
568 case SUN4I_STA_BIT_ERR:
569 cf->data[2] |= CAN_ERR_PROT_BIT;
570 break;
571 case SUN4I_STA_FORM_ERR:
572 cf->data[2] |= CAN_ERR_PROT_FORM;
573 break;
574 case SUN4I_STA_STUFF_ERR:
575 cf->data[2] |= CAN_ERR_PROT_STUFF;
576 break;
577 default:
578 cf->data[3] = (ecc & SUN4I_STA_ERR_SEG_CODE)
579 >> 16;
580 break;
581 }
582 /* error occurred during transmission? */
583 if ((ecc & SUN4I_STA_ERR_DIR) == 0)
584 cf->data[2] |= CAN_ERR_PROT_TX;
585 }
586 }
587 if (isrc & SUN4I_INT_ERR_PASSIVE) {
588 /* error passive interrupt */
589 netdev_dbg(dev, "error passive interrupt\n");
590 if (state == CAN_STATE_ERROR_PASSIVE)
591 state = CAN_STATE_ERROR_WARNING;
592 else
593 state = CAN_STATE_ERROR_PASSIVE;
594 }
595 if (isrc & SUN4I_INT_ARB_LOST) {
596 /* arbitration lost interrupt */
597 netdev_dbg(dev, "arbitration lost interrupt\n");
598 alc = readl(priv->base + SUN4I_REG_STA_ADDR);
599 priv->can.can_stats.arbitration_lost++;
600 stats->tx_errors++;
601 if (likely(skb)) {
602 cf->can_id |= CAN_ERR_LOSTARB;
603 cf->data[0] = (alc >> 8) & 0x1f;
604 }
605 }
606
607 if (state != priv->can.state) {
608 tx_state = txerr >= rxerr ? state : 0;
609 rx_state = txerr <= rxerr ? state : 0;
610
611 if (likely(skb))
612 can_change_state(dev, cf, tx_state, rx_state);
613 else
614 priv->can.state = state;
615 if (state == CAN_STATE_BUS_OFF)
616 can_bus_off(dev);
617 }
618
619 if (likely(skb)) {
620 stats->rx_packets++;
621 stats->rx_bytes += cf->can_dlc;
622 netif_rx(skb);
623 } else {
624 return -ENOMEM;
625 }
626
627 return 0;
628}
629
630static irqreturn_t sun4i_can_interrupt(int irq, void *dev_id)
631{
632 struct net_device *dev = (struct net_device *)dev_id;
633 struct sun4ican_priv *priv = netdev_priv(dev);
634 struct net_device_stats *stats = &dev->stats;
635 u8 isrc, status;
636 int n = 0;
637
638 while ((isrc = readl(priv->base + SUN4I_REG_INT_ADDR)) &&
639 (n < SUN4I_CAN_MAX_IRQ)) {
640 n++;
641 status = readl(priv->base + SUN4I_REG_STA_ADDR);
642
643 if (isrc & SUN4I_INT_WAKEUP)
644 netdev_warn(dev, "wakeup interrupt\n");
645
646 if (isrc & SUN4I_INT_TBUF_VLD) {
647 /* transmission complete interrupt */
648 stats->tx_bytes +=
649 readl(priv->base +
650 SUN4I_REG_RBUF_RBACK_START_ADDR) & 0xf;
651 stats->tx_packets++;
652 can_get_echo_skb(dev, 0);
653 netif_wake_queue(dev);
654 can_led_event(dev, CAN_LED_EVENT_TX);
655 }
656 if (isrc & SUN4I_INT_RBUF_VLD) {
657 /* receive interrupt */
658 while (status & SUN4I_STA_RBUF_RDY) {
659 /* RX buffer is not empty */
660 sun4i_can_rx(dev);
661 status = readl(priv->base + SUN4I_REG_STA_ADDR);
662 }
663 }
664 if (isrc &
665 (SUN4I_INT_DATA_OR | SUN4I_INT_ERR_WRN | SUN4I_INT_BUS_ERR |
666 SUN4I_INT_ERR_PASSIVE | SUN4I_INT_ARB_LOST)) {
667 /* error interrupt */
668 if (sun4i_can_err(dev, isrc, status))
669 netdev_err(dev, "can't allocate buffer - clearing pending interrupts\n");
670 }
671 /* clear interrupts */
672 writel(isrc, priv->base + SUN4I_REG_INT_ADDR);
673 readl(priv->base + SUN4I_REG_INT_ADDR);
674 }
675 if (n >= SUN4I_CAN_MAX_IRQ)
676 netdev_dbg(dev, "%d messages handled in ISR", n);
677
678 return (n) ? IRQ_HANDLED : IRQ_NONE;
679}
680
681static int sun4ican_open(struct net_device *dev)
682{
683 struct sun4ican_priv *priv = netdev_priv(dev);
684 int err;
685
686 /* common open */
687 err = open_candev(dev);
688 if (err)
689 return err;
690
691 /* register interrupt handler */
692 err = request_irq(dev->irq, sun4i_can_interrupt, 0, dev->name, dev);
693 if (err) {
694 netdev_err(dev, "request_irq err: %d\n", err);
695 goto exit_irq;
696 }
697
698 /* turn on clocking for CAN peripheral block */
699 err = clk_prepare_enable(priv->clk);
700 if (err) {
701 netdev_err(dev, "could not enable CAN peripheral clock\n");
702 goto exit_clock;
703 }
704
705 err = sun4i_can_start(dev);
706 if (err) {
707 netdev_err(dev, "could not start CAN peripheral\n");
708 goto exit_can_start;
709 }
710
711 can_led_event(dev, CAN_LED_EVENT_OPEN);
712 netif_start_queue(dev);
713
714 return 0;
715
716exit_can_start:
717 clk_disable_unprepare(priv->clk);
718exit_clock:
719 free_irq(dev->irq, dev);
720exit_irq:
721 close_candev(dev);
722 return err;
723}
724
725static int sun4ican_close(struct net_device *dev)
726{
727 struct sun4ican_priv *priv = netdev_priv(dev);
728
729 netif_stop_queue(dev);
730 sun4i_can_stop(dev);
731 clk_disable_unprepare(priv->clk);
732
733 free_irq(dev->irq, dev);
734 close_candev(dev);
735 can_led_event(dev, CAN_LED_EVENT_STOP);
736
737 return 0;
738}
739
740static const struct net_device_ops sun4ican_netdev_ops = {
741 .ndo_open = sun4ican_open,
742 .ndo_stop = sun4ican_close,
743 .ndo_start_xmit = sun4ican_start_xmit,
744};
745
746static const struct of_device_id sun4ican_of_match[] = {
747 {.compatible = "allwinner,sun4i-a10-can"},
748 {},
749};
750
751MODULE_DEVICE_TABLE(of, sun4ican_of_match);
752
753static int sun4ican_remove(struct platform_device *pdev)
754{
755 struct net_device *dev = platform_get_drvdata(pdev);
756
757 unregister_netdev(dev);
758 free_candev(dev);
759
760 return 0;
761}
762
763static int sun4ican_probe(struct platform_device *pdev)
764{
765 struct device_node *np = pdev->dev.of_node;
766 struct resource *mem;
767 struct clk *clk;
768 void __iomem *addr;
769 int err, irq;
770 struct net_device *dev;
771 struct sun4ican_priv *priv;
772
773 clk = of_clk_get(np, 0);
774 if (IS_ERR(clk)) {
775 dev_err(&pdev->dev, "unable to request clock\n");
776 err = -ENODEV;
777 goto exit;
778 }
779
780 irq = platform_get_irq(pdev, 0);
781 if (irq < 0) {
782 dev_err(&pdev->dev, "could not get a valid irq\n");
783 err = -ENODEV;
784 goto exit;
785 }
786
787 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
788 addr = devm_ioremap_resource(&pdev->dev, mem);
789 if (IS_ERR(addr)) {
790 err = -EBUSY;
791 goto exit;
792 }
793
794 dev = alloc_candev(sizeof(struct sun4ican_priv), 1);
795 if (!dev) {
796 dev_err(&pdev->dev,
797 "could not allocate memory for CAN device\n");
798 err = -ENOMEM;
799 goto exit;
800 }
801
802 dev->netdev_ops = &sun4ican_netdev_ops;
803 dev->irq = irq;
804 dev->flags |= IFF_ECHO;
805
806 priv = netdev_priv(dev);
807 priv->can.clock.freq = clk_get_rate(clk);
808 priv->can.bittiming_const = &sun4ican_bittiming_const;
809 priv->can.do_set_mode = sun4ican_set_mode;
810 priv->can.do_get_berr_counter = sun4ican_get_berr_counter;
811 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
812 CAN_CTRLMODE_LISTENONLY |
813 CAN_CTRLMODE_LOOPBACK |
814 CAN_CTRLMODE_PRESUME_ACK |
815 CAN_CTRLMODE_3_SAMPLES;
816 priv->base = addr;
817 priv->clk = clk;
818 spin_lock_init(&priv->cmdreg_lock);
819
820 platform_set_drvdata(pdev, dev);
821 SET_NETDEV_DEV(dev, &pdev->dev);
822
823 err = register_candev(dev);
824 if (err) {
825 dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
826 DRV_NAME, err);
827 goto exit_free;
828 }
829 devm_can_led_init(dev);
830
831 dev_info(&pdev->dev, "device registered (base=%p, irq=%d)\n",
832 priv->base, dev->irq);
833
834 return 0;
835
836exit_free:
837 free_candev(dev);
838exit:
839 return err;
840}
841
842static struct platform_driver sun4i_can_driver = {
843 .driver = {
844 .name = DRV_NAME,
845 .of_match_table = sun4ican_of_match,
846 },
847 .probe = sun4ican_probe,
848 .remove = sun4ican_remove,
849};
850
851module_platform_driver(sun4i_can_driver);
852
853MODULE_AUTHOR("Peter Chen <xingkongcp@gmail.com>");
854MODULE_AUTHOR("Gerhard Bertelsmann <info@gerhard-bertelsmann.de>");
855MODULE_LICENSE("Dual BSD/GPL");
856MODULE_DESCRIPTION("CAN driver for Allwinner SoCs (A10/A20)");