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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Arasan Secure Digital Host Controller Interface.
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
5 * Copyright (c) 2012 Wind River Systems, Inc.
6 * Copyright (C) 2013 Pengutronix e.K.
7 * Copyright (C) 2013 Xilinx Inc.
8 *
9 * Based on sdhci-of-esdhc.c
10 *
11 * Copyright (c) 2007 Freescale Semiconductor, Inc.
12 * Copyright (c) 2009 MontaVista Software, Inc.
13 *
14 * Authors: Xiaobo Xie <X.Xie@freescale.com>
15 * Anton Vorontsov <avorontsov@ru.mvista.com>
16 */
17
18#include <linux/clk-provider.h>
19#include <linux/mfd/syscon.h>
20#include <linux/module.h>
21#include <linux/of_device.h>
22#include <linux/phy/phy.h>
23#include <linux/regmap.h>
24#include <linux/reset.h>
25#include <linux/of.h>
26#include <linux/firmware/xlnx-zynqmp.h>
27
28#include "cqhci.h"
29#include "sdhci-cqhci.h"
30#include "sdhci-pltfm.h"
31
32#define SDHCI_ARASAN_VENDOR_REGISTER 0x78
33
34#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
35#define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF
36
37#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
38#define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F
39
40#define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
41#define VENDOR_ENHANCED_STROBE BIT(0)
42
43#define PHY_CLK_TOO_SLOW_HZ 400000
44
45#define SDHCI_ITAPDLY_CHGWIN 0x200
46#define SDHCI_ITAPDLY_ENABLE 0x100
47#define SDHCI_OTAPDLY_ENABLE 0x40
48
49/* Default settings for ZynqMP Clock Phases */
50#define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}
51#define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
52
53#define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0}
54#define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
55
56/*
57 * On some SoCs the syscon area has a feature where the upper 16-bits of
58 * each 32-bit register act as a write mask for the lower 16-bits. This allows
59 * atomic updates of the register without locking. This macro is used on SoCs
60 * that have that feature.
61 */
62#define HIWORD_UPDATE(val, mask, shift) \
63 ((val) << (shift) | (mask) << ((shift) + 16))
64
65/**
66 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
67 *
68 * @reg: Offset within the syscon of the register containing this field
69 * @width: Number of bits for this field
70 * @shift: Bit offset within @reg of this field (or -1 if not avail)
71 */
72struct sdhci_arasan_soc_ctl_field {
73 u32 reg;
74 u16 width;
75 s16 shift;
76};
77
78/**
79 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
80 *
81 * @baseclkfreq: Where to find corecfg_baseclkfreq
82 * @clockmultiplier: Where to find corecfg_clockmultiplier
83 * @support64b: Where to find SUPPORT64B bit
84 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
85 *
86 * It's up to the licensee of the Arsan IP block to make these available
87 * somewhere if needed. Presumably these will be scattered somewhere that's
88 * accessible via the syscon API.
89 */
90struct sdhci_arasan_soc_ctl_map {
91 struct sdhci_arasan_soc_ctl_field baseclkfreq;
92 struct sdhci_arasan_soc_ctl_field clockmultiplier;
93 struct sdhci_arasan_soc_ctl_field support64b;
94 bool hiword_update;
95};
96
97/**
98 * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
99 *
100 * @sdcardclk_ops: The output clock related operations
101 * @sampleclk_ops: The sample clock related operations
102 */
103struct sdhci_arasan_clk_ops {
104 const struct clk_ops *sdcardclk_ops;
105 const struct clk_ops *sampleclk_ops;
106};
107
108/**
109 * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
110 *
111 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
112 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
113 * @sampleclk_hw: Struct for the clock we might provide to a PHY.
114 * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw.
115 * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes
116 * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes
117 * @set_clk_delays: Function pointer for setting Clock Delays
118 * @clk_of_data: Platform specific runtime clock data storage pointer
119 */
120struct sdhci_arasan_clk_data {
121 struct clk_hw sdcardclk_hw;
122 struct clk *sdcardclk;
123 struct clk_hw sampleclk_hw;
124 struct clk *sampleclk;
125 int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
126 int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
127 void (*set_clk_delays)(struct sdhci_host *host);
128 void *clk_of_data;
129};
130
131/**
132 * struct sdhci_arasan_data - Arasan Controller Data
133 *
134 * @host: Pointer to the main SDHCI host structure.
135 * @clk_ahb: Pointer to the AHB clock
136 * @phy: Pointer to the generic phy
137 * @is_phy_on: True if the PHY is on; false if not.
138 * @has_cqe: True if controller has command queuing engine.
139 * @clk_data: Struct for the Arasan Controller Clock Data.
140 * @clk_ops: Struct for the Arasan Controller Clock Operations.
141 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
142 * @soc_ctl_map: Map to get offsets into soc_ctl registers.
143 * @quirks: Arasan deviations from spec.
144 */
145struct sdhci_arasan_data {
146 struct sdhci_host *host;
147 struct clk *clk_ahb;
148 struct phy *phy;
149 bool is_phy_on;
150
151 bool has_cqe;
152 struct sdhci_arasan_clk_data clk_data;
153 const struct sdhci_arasan_clk_ops *clk_ops;
154
155 struct regmap *soc_ctl_base;
156 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
157 unsigned int quirks;
158
159/* Controller does not have CD wired and will not function normally without */
160#define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
161/* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
162 * internal clock even when the clock isn't stable */
163#define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
164/*
165 * Some of the Arasan variations might not have timing requirements
166 * met at 25MHz for Default Speed mode, those controllers work at
167 * 19MHz instead
168 */
169#define SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN BIT(2)
170};
171
172struct sdhci_arasan_of_data {
173 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
174 const struct sdhci_pltfm_data *pdata;
175 const struct sdhci_arasan_clk_ops *clk_ops;
176};
177
178static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
179 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
180 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
181 .hiword_update = true,
182};
183
184static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
185 .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 },
186 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
187 .hiword_update = false,
188};
189
190static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
191 .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
192 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
193 .hiword_update = false,
194};
195
196static const struct sdhci_arasan_soc_ctl_map thunderbay_soc_ctl_map = {
197 .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
198 .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
199 .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
200 .hiword_update = false,
201};
202
203static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
204 .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
205 .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
206 .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
207 .hiword_update = false,
208};
209
210/**
211 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
212 *
213 * @host: The sdhci_host
214 * @fld: The field to write to
215 * @val: The value to write
216 *
217 * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
218 * Note that if a field is specified as not available (shift < 0) then
219 * this function will silently return an error code. It will be noisy
220 * and print errors for any other (unexpected) errors.
221 *
222 * Return: 0 on success and error value on error
223 */
224static int sdhci_arasan_syscon_write(struct sdhci_host *host,
225 const struct sdhci_arasan_soc_ctl_field *fld,
226 u32 val)
227{
228 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
229 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
230 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
231 u32 reg = fld->reg;
232 u16 width = fld->width;
233 s16 shift = fld->shift;
234 int ret;
235
236 /*
237 * Silently return errors for shift < 0 so caller doesn't have
238 * to check for fields which are optional. For fields that
239 * are required then caller needs to do something special
240 * anyway.
241 */
242 if (shift < 0)
243 return -EINVAL;
244
245 if (sdhci_arasan->soc_ctl_map->hiword_update)
246 ret = regmap_write(soc_ctl_base, reg,
247 HIWORD_UPDATE(val, GENMASK(width, 0),
248 shift));
249 else
250 ret = regmap_update_bits(soc_ctl_base, reg,
251 GENMASK(shift + width, shift),
252 val << shift);
253
254 /* Yell about (unexpected) regmap errors */
255 if (ret)
256 pr_warn("%s: Regmap write fail: %d\n",
257 mmc_hostname(host->mmc), ret);
258
259 return ret;
260}
261
262static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
263{
264 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
265 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
266 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
267 bool ctrl_phy = false;
268
269 if (!IS_ERR(sdhci_arasan->phy)) {
270 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
271 /*
272 * If PHY off, set clock to max speed and power PHY on.
273 *
274 * Although PHY docs apparently suggest power cycling
275 * when changing the clock the PHY doesn't like to be
276 * powered on while at low speeds like those used in ID
277 * mode. Even worse is powering the PHY on while the
278 * clock is off.
279 *
280 * To workaround the PHY limitations, the best we can
281 * do is to power it on at a faster speed and then slam
282 * through low speeds without power cycling.
283 */
284 sdhci_set_clock(host, host->max_clk);
285 if (phy_power_on(sdhci_arasan->phy)) {
286 pr_err("%s: Cannot power on phy.\n",
287 mmc_hostname(host->mmc));
288 return;
289 }
290
291 sdhci_arasan->is_phy_on = true;
292
293 /*
294 * We'll now fall through to the below case with
295 * ctrl_phy = false (so we won't turn off/on). The
296 * sdhci_set_clock() will set the real clock.
297 */
298 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
299 /*
300 * At higher clock speeds the PHY is fine being power
301 * cycled and docs say you _should_ power cycle when
302 * changing clock speeds.
303 */
304 ctrl_phy = true;
305 }
306 }
307
308 if (ctrl_phy && sdhci_arasan->is_phy_on) {
309 phy_power_off(sdhci_arasan->phy);
310 sdhci_arasan->is_phy_on = false;
311 }
312
313 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) {
314 /*
315 * Some of the Arasan variations might not have timing
316 * requirements met at 25MHz for Default Speed mode,
317 * those controllers work at 19MHz instead.
318 */
319 if (clock == DEFAULT_SPEED_MAX_DTR)
320 clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25;
321 }
322
323 /* Set the Input and Output Clock Phase Delays */
324 if (clk_data->set_clk_delays)
325 clk_data->set_clk_delays(host);
326
327 sdhci_set_clock(host, clock);
328
329 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
330 /*
331 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
332 * after enabling the clock even though the clock is not
333 * stable. Trying to use a clock without waiting here results
334 * in EILSEQ while detecting some older/slower cards. The
335 * chosen delay is the maximum delay from sdhci_set_clock.
336 */
337 msleep(20);
338
339 if (ctrl_phy) {
340 if (phy_power_on(sdhci_arasan->phy)) {
341 pr_err("%s: Cannot power on phy.\n",
342 mmc_hostname(host->mmc));
343 return;
344 }
345
346 sdhci_arasan->is_phy_on = true;
347 }
348}
349
350static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
351 struct mmc_ios *ios)
352{
353 u32 vendor;
354 struct sdhci_host *host = mmc_priv(mmc);
355
356 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
357 if (ios->enhanced_strobe)
358 vendor |= VENDOR_ENHANCED_STROBE;
359 else
360 vendor &= ~VENDOR_ENHANCED_STROBE;
361
362 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
363}
364
365static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
366{
367 u8 ctrl;
368 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
369 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
370
371 sdhci_and_cqhci_reset(host, mask);
372
373 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
374 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
375 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
376 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
377 }
378}
379
380static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
381 struct mmc_ios *ios)
382{
383 switch (ios->signal_voltage) {
384 case MMC_SIGNAL_VOLTAGE_180:
385 /*
386 * Plese don't switch to 1V8 as arasan,5.1 doesn't
387 * actually refer to this setting to indicate the
388 * signal voltage and the state machine will be broken
389 * actually if we force to enable 1V8. That's something
390 * like broken quirk but we could work around here.
391 */
392 return 0;
393 case MMC_SIGNAL_VOLTAGE_330:
394 case MMC_SIGNAL_VOLTAGE_120:
395 /* We don't support 3V3 and 1V2 */
396 break;
397 }
398
399 return -EINVAL;
400}
401
402static const struct sdhci_ops sdhci_arasan_ops = {
403 .set_clock = sdhci_arasan_set_clock,
404 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
405 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
406 .set_bus_width = sdhci_set_bus_width,
407 .reset = sdhci_arasan_reset,
408 .set_uhs_signaling = sdhci_set_uhs_signaling,
409 .set_power = sdhci_set_power_and_bus_voltage,
410};
411
412static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
413{
414 int cmd_error = 0;
415 int data_error = 0;
416
417 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
418 return intmask;
419
420 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
421
422 return 0;
423}
424
425static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
426{
427 sdhci_dumpregs(mmc_priv(mmc));
428}
429
430static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
431{
432 struct sdhci_host *host = mmc_priv(mmc);
433 u32 reg;
434
435 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
436 while (reg & SDHCI_DATA_AVAILABLE) {
437 sdhci_readl(host, SDHCI_BUFFER);
438 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
439 }
440
441 sdhci_cqe_enable(mmc);
442}
443
444static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
445 .enable = sdhci_arasan_cqe_enable,
446 .disable = sdhci_cqe_disable,
447 .dumpregs = sdhci_arasan_dumpregs,
448};
449
450static const struct sdhci_ops sdhci_arasan_cqe_ops = {
451 .set_clock = sdhci_arasan_set_clock,
452 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
453 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
454 .set_bus_width = sdhci_set_bus_width,
455 .reset = sdhci_arasan_reset,
456 .set_uhs_signaling = sdhci_set_uhs_signaling,
457 .set_power = sdhci_set_power_and_bus_voltage,
458 .irq = sdhci_arasan_cqhci_irq,
459};
460
461static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
462 .ops = &sdhci_arasan_cqe_ops,
463 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
464 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
465 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
466};
467
468static const struct sdhci_pltfm_data sdhci_arasan_thunderbay_pdata = {
469 .ops = &sdhci_arasan_cqe_ops,
470 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
471 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
472 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
473 SDHCI_QUIRK2_STOP_WITH_TC |
474 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
475};
476
477#ifdef CONFIG_PM_SLEEP
478/**
479 * sdhci_arasan_suspend - Suspend method for the driver
480 * @dev: Address of the device structure
481 *
482 * Put the device in a low power state.
483 *
484 * Return: 0 on success and error value on error
485 */
486static int sdhci_arasan_suspend(struct device *dev)
487{
488 struct sdhci_host *host = dev_get_drvdata(dev);
489 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
490 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
491 int ret;
492
493 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
494 mmc_retune_needed(host->mmc);
495
496 if (sdhci_arasan->has_cqe) {
497 ret = cqhci_suspend(host->mmc);
498 if (ret)
499 return ret;
500 }
501
502 ret = sdhci_suspend_host(host);
503 if (ret)
504 return ret;
505
506 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
507 ret = phy_power_off(sdhci_arasan->phy);
508 if (ret) {
509 dev_err(dev, "Cannot power off phy.\n");
510 if (sdhci_resume_host(host))
511 dev_err(dev, "Cannot resume host.\n");
512
513 return ret;
514 }
515 sdhci_arasan->is_phy_on = false;
516 }
517
518 clk_disable(pltfm_host->clk);
519 clk_disable(sdhci_arasan->clk_ahb);
520
521 return 0;
522}
523
524/**
525 * sdhci_arasan_resume - Resume method for the driver
526 * @dev: Address of the device structure
527 *
528 * Resume operation after suspend
529 *
530 * Return: 0 on success and error value on error
531 */
532static int sdhci_arasan_resume(struct device *dev)
533{
534 struct sdhci_host *host = dev_get_drvdata(dev);
535 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
536 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
537 int ret;
538
539 ret = clk_enable(sdhci_arasan->clk_ahb);
540 if (ret) {
541 dev_err(dev, "Cannot enable AHB clock.\n");
542 return ret;
543 }
544
545 ret = clk_enable(pltfm_host->clk);
546 if (ret) {
547 dev_err(dev, "Cannot enable SD clock.\n");
548 return ret;
549 }
550
551 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
552 ret = phy_power_on(sdhci_arasan->phy);
553 if (ret) {
554 dev_err(dev, "Cannot power on phy.\n");
555 return ret;
556 }
557 sdhci_arasan->is_phy_on = true;
558 }
559
560 ret = sdhci_resume_host(host);
561 if (ret) {
562 dev_err(dev, "Cannot resume host.\n");
563 return ret;
564 }
565
566 if (sdhci_arasan->has_cqe)
567 return cqhci_resume(host->mmc);
568
569 return 0;
570}
571#endif /* ! CONFIG_PM_SLEEP */
572
573static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
574 sdhci_arasan_resume);
575
576/**
577 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
578 *
579 * @hw: Pointer to the hardware clock structure.
580 * @parent_rate: The parent rate (should be rate of clk_xin).
581 *
582 * Return the current actual rate of the SD card clock. This can be used
583 * to communicate with out PHY.
584 *
585 * Return: The card clock rate.
586 */
587static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
588 unsigned long parent_rate)
589{
590 struct sdhci_arasan_clk_data *clk_data =
591 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
592 struct sdhci_arasan_data *sdhci_arasan =
593 container_of(clk_data, struct sdhci_arasan_data, clk_data);
594 struct sdhci_host *host = sdhci_arasan->host;
595
596 return host->mmc->actual_clock;
597}
598
599static const struct clk_ops arasan_sdcardclk_ops = {
600 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
601};
602
603/**
604 * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
605 *
606 * @hw: Pointer to the hardware clock structure.
607 * @parent_rate: The parent rate (should be rate of clk_xin).
608 *
609 * Return the current actual rate of the sampling clock. This can be used
610 * to communicate with out PHY.
611 *
612 * Return: The sample clock rate.
613 */
614static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw,
615 unsigned long parent_rate)
616{
617 struct sdhci_arasan_clk_data *clk_data =
618 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
619 struct sdhci_arasan_data *sdhci_arasan =
620 container_of(clk_data, struct sdhci_arasan_data, clk_data);
621 struct sdhci_host *host = sdhci_arasan->host;
622
623 return host->mmc->actual_clock;
624}
625
626static const struct clk_ops arasan_sampleclk_ops = {
627 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
628};
629
630/**
631 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
632 *
633 * @hw: Pointer to the hardware clock structure.
634 * @degrees: The clock phase shift between 0 - 359.
635 *
636 * Set the SD Output Clock Tap Delays for Output path
637 *
638 * Return: 0 on success and error value on error
639 */
640static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
641{
642 struct sdhci_arasan_clk_data *clk_data =
643 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
644 struct sdhci_arasan_data *sdhci_arasan =
645 container_of(clk_data, struct sdhci_arasan_data, clk_data);
646 struct sdhci_host *host = sdhci_arasan->host;
647 const char *clk_name = clk_hw_get_name(hw);
648 u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
649 u8 tap_delay, tap_max = 0;
650 int ret;
651
652 /* This is applicable for SDHCI_SPEC_300 and above */
653 if (host->version < SDHCI_SPEC_300)
654 return 0;
655
656 switch (host->timing) {
657 case MMC_TIMING_MMC_HS:
658 case MMC_TIMING_SD_HS:
659 case MMC_TIMING_UHS_SDR25:
660 case MMC_TIMING_UHS_DDR50:
661 case MMC_TIMING_MMC_DDR52:
662 /* For 50MHz clock, 30 Taps are available */
663 tap_max = 30;
664 break;
665 case MMC_TIMING_UHS_SDR50:
666 /* For 100MHz clock, 15 Taps are available */
667 tap_max = 15;
668 break;
669 case MMC_TIMING_UHS_SDR104:
670 case MMC_TIMING_MMC_HS200:
671 /* For 200MHz clock, 8 Taps are available */
672 tap_max = 8;
673 break;
674 default:
675 break;
676 }
677
678 tap_delay = (degrees * tap_max) / 360;
679
680 /* Set the Clock Phase */
681 ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay);
682 if (ret)
683 pr_err("Error setting Output Tap Delay\n");
684
685 /* Release DLL Reset */
686 zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE);
687
688 return ret;
689}
690
691static const struct clk_ops zynqmp_sdcardclk_ops = {
692 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
693 .set_phase = sdhci_zynqmp_sdcardclk_set_phase,
694};
695
696/**
697 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
698 *
699 * @hw: Pointer to the hardware clock structure.
700 * @degrees: The clock phase shift between 0 - 359.
701 *
702 * Set the SD Input Clock Tap Delays for Input path
703 *
704 * Return: 0 on success and error value on error
705 */
706static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
707{
708 struct sdhci_arasan_clk_data *clk_data =
709 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
710 struct sdhci_arasan_data *sdhci_arasan =
711 container_of(clk_data, struct sdhci_arasan_data, clk_data);
712 struct sdhci_host *host = sdhci_arasan->host;
713 const char *clk_name = clk_hw_get_name(hw);
714 u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1;
715 u8 tap_delay, tap_max = 0;
716 int ret;
717
718 /* This is applicable for SDHCI_SPEC_300 and above */
719 if (host->version < SDHCI_SPEC_300)
720 return 0;
721
722 /* Assert DLL Reset */
723 zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT);
724
725 switch (host->timing) {
726 case MMC_TIMING_MMC_HS:
727 case MMC_TIMING_SD_HS:
728 case MMC_TIMING_UHS_SDR25:
729 case MMC_TIMING_UHS_DDR50:
730 case MMC_TIMING_MMC_DDR52:
731 /* For 50MHz clock, 120 Taps are available */
732 tap_max = 120;
733 break;
734 case MMC_TIMING_UHS_SDR50:
735 /* For 100MHz clock, 60 Taps are available */
736 tap_max = 60;
737 break;
738 case MMC_TIMING_UHS_SDR104:
739 case MMC_TIMING_MMC_HS200:
740 /* For 200MHz clock, 30 Taps are available */
741 tap_max = 30;
742 break;
743 default:
744 break;
745 }
746
747 tap_delay = (degrees * tap_max) / 360;
748
749 /* Set the Clock Phase */
750 ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay);
751 if (ret)
752 pr_err("Error setting Input Tap Delay\n");
753
754 return ret;
755}
756
757static const struct clk_ops zynqmp_sampleclk_ops = {
758 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
759 .set_phase = sdhci_zynqmp_sampleclk_set_phase,
760};
761
762/**
763 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
764 *
765 * @hw: Pointer to the hardware clock structure.
766 * @degrees: The clock phase shift between 0 - 359.
767 *
768 * Set the SD Output Clock Tap Delays for Output path
769 *
770 * Return: 0 on success and error value on error
771 */
772static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
773{
774 struct sdhci_arasan_clk_data *clk_data =
775 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
776 struct sdhci_arasan_data *sdhci_arasan =
777 container_of(clk_data, struct sdhci_arasan_data, clk_data);
778 struct sdhci_host *host = sdhci_arasan->host;
779 u8 tap_delay, tap_max = 0;
780
781 /* This is applicable for SDHCI_SPEC_300 and above */
782 if (host->version < SDHCI_SPEC_300)
783 return 0;
784
785 switch (host->timing) {
786 case MMC_TIMING_MMC_HS:
787 case MMC_TIMING_SD_HS:
788 case MMC_TIMING_UHS_SDR25:
789 case MMC_TIMING_UHS_DDR50:
790 case MMC_TIMING_MMC_DDR52:
791 /* For 50MHz clock, 30 Taps are available */
792 tap_max = 30;
793 break;
794 case MMC_TIMING_UHS_SDR50:
795 /* For 100MHz clock, 15 Taps are available */
796 tap_max = 15;
797 break;
798 case MMC_TIMING_UHS_SDR104:
799 case MMC_TIMING_MMC_HS200:
800 /* For 200MHz clock, 8 Taps are available */
801 tap_max = 8;
802 break;
803 default:
804 break;
805 }
806
807 tap_delay = (degrees * tap_max) / 360;
808
809 /* Set the Clock Phase */
810 if (tap_delay) {
811 u32 regval;
812
813 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
814 regval |= SDHCI_OTAPDLY_ENABLE;
815 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
816 regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
817 regval |= tap_delay;
818 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
819 }
820
821 return 0;
822}
823
824static const struct clk_ops versal_sdcardclk_ops = {
825 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
826 .set_phase = sdhci_versal_sdcardclk_set_phase,
827};
828
829/**
830 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
831 *
832 * @hw: Pointer to the hardware clock structure.
833 * @degrees: The clock phase shift between 0 - 359.
834 *
835 * Set the SD Input Clock Tap Delays for Input path
836 *
837 * Return: 0 on success and error value on error
838 */
839static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
840{
841 struct sdhci_arasan_clk_data *clk_data =
842 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
843 struct sdhci_arasan_data *sdhci_arasan =
844 container_of(clk_data, struct sdhci_arasan_data, clk_data);
845 struct sdhci_host *host = sdhci_arasan->host;
846 u8 tap_delay, tap_max = 0;
847
848 /* This is applicable for SDHCI_SPEC_300 and above */
849 if (host->version < SDHCI_SPEC_300)
850 return 0;
851
852 switch (host->timing) {
853 case MMC_TIMING_MMC_HS:
854 case MMC_TIMING_SD_HS:
855 case MMC_TIMING_UHS_SDR25:
856 case MMC_TIMING_UHS_DDR50:
857 case MMC_TIMING_MMC_DDR52:
858 /* For 50MHz clock, 120 Taps are available */
859 tap_max = 120;
860 break;
861 case MMC_TIMING_UHS_SDR50:
862 /* For 100MHz clock, 60 Taps are available */
863 tap_max = 60;
864 break;
865 case MMC_TIMING_UHS_SDR104:
866 case MMC_TIMING_MMC_HS200:
867 /* For 200MHz clock, 30 Taps are available */
868 tap_max = 30;
869 break;
870 default:
871 break;
872 }
873
874 tap_delay = (degrees * tap_max) / 360;
875
876 /* Set the Clock Phase */
877 if (tap_delay) {
878 u32 regval;
879
880 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
881 regval |= SDHCI_ITAPDLY_CHGWIN;
882 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
883 regval |= SDHCI_ITAPDLY_ENABLE;
884 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
885 regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
886 regval |= tap_delay;
887 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
888 regval &= ~SDHCI_ITAPDLY_CHGWIN;
889 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
890 }
891
892 return 0;
893}
894
895static const struct clk_ops versal_sampleclk_ops = {
896 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
897 .set_phase = sdhci_versal_sampleclk_set_phase,
898};
899
900static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
901{
902 u16 clk;
903
904 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
905 clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
906 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
907
908 /* Issue DLL Reset */
909 zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE);
910
911 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
912
913 sdhci_enable_clk(host, clk);
914}
915
916static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode)
917{
918 struct sdhci_host *host = mmc_priv(mmc);
919 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
920 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
921 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
922 const char *clk_name = clk_hw_get_name(hw);
923 u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 :
924 NODE_SD_1;
925 int err;
926
927 /* ZynqMP SD controller does not perform auto tuning in DDR50 mode */
928 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
929 return 0;
930
931 arasan_zynqmp_dll_reset(host, device_id);
932
933 err = sdhci_execute_tuning(mmc, opcode);
934 if (err)
935 return err;
936
937 arasan_zynqmp_dll_reset(host, device_id);
938
939 return 0;
940}
941
942/**
943 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
944 *
945 * @host: The sdhci_host
946 * @value: The value to write
947 *
948 * The corecfg_clockmultiplier is supposed to contain clock multiplier
949 * value of programmable clock generator.
950 *
951 * NOTES:
952 * - Many existing devices don't seem to do this and work fine. To keep
953 * compatibility for old hardware where the device tree doesn't provide a
954 * register map, this function is a noop if a soc_ctl_map hasn't been provided
955 * for this platform.
956 * - The value of corecfg_clockmultiplier should sync with that of corresponding
957 * value reading from sdhci_capability_register. So this function is called
958 * once at probe time and never called again.
959 */
960static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
961 u32 value)
962{
963 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
964 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
965 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
966 sdhci_arasan->soc_ctl_map;
967
968 /* Having a map is optional */
969 if (!soc_ctl_map)
970 return;
971
972 /* If we have a map, we expect to have a syscon */
973 if (!sdhci_arasan->soc_ctl_base) {
974 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
975 mmc_hostname(host->mmc));
976 return;
977 }
978
979 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
980}
981
982/**
983 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
984 *
985 * @host: The sdhci_host
986 *
987 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
988 * function can be used to make that happen.
989 *
990 * NOTES:
991 * - Many existing devices don't seem to do this and work fine. To keep
992 * compatibility for old hardware where the device tree doesn't provide a
993 * register map, this function is a noop if a soc_ctl_map hasn't been provided
994 * for this platform.
995 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
996 * to achieve lower clock rates. That means that this function is called once
997 * at probe time and never called again.
998 */
999static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
1000{
1001 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1002 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1003 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
1004 sdhci_arasan->soc_ctl_map;
1005 u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);
1006
1007 /* Having a map is optional */
1008 if (!soc_ctl_map)
1009 return;
1010
1011 /* If we have a map, we expect to have a syscon */
1012 if (!sdhci_arasan->soc_ctl_base) {
1013 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1014 mmc_hostname(host->mmc));
1015 return;
1016 }
1017
1018 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
1019}
1020
1021static void sdhci_arasan_set_clk_delays(struct sdhci_host *host)
1022{
1023 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1024 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1025 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1026
1027 clk_set_phase(clk_data->sampleclk,
1028 clk_data->clk_phase_in[host->timing]);
1029 clk_set_phase(clk_data->sdcardclk,
1030 clk_data->clk_phase_out[host->timing]);
1031}
1032
1033static void arasan_dt_read_clk_phase(struct device *dev,
1034 struct sdhci_arasan_clk_data *clk_data,
1035 unsigned int timing, const char *prop)
1036{
1037 struct device_node *np = dev->of_node;
1038
1039 u32 clk_phase[2] = {0};
1040 int ret;
1041
1042 /*
1043 * Read Tap Delay values from DT, if the DT does not contain the
1044 * Tap Values then use the pre-defined values.
1045 */
1046 ret = of_property_read_variable_u32_array(np, prop, &clk_phase[0],
1047 2, 0);
1048 if (ret < 0) {
1049 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
1050 prop, clk_data->clk_phase_in[timing],
1051 clk_data->clk_phase_out[timing]);
1052 return;
1053 }
1054
1055 /* The values read are Input and Output Clock Delays in order */
1056 clk_data->clk_phase_in[timing] = clk_phase[0];
1057 clk_data->clk_phase_out[timing] = clk_phase[1];
1058}
1059
1060/**
1061 * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1062 *
1063 * @dev: Pointer to our struct device.
1064 * @clk_data: Pointer to the Clock Data structure
1065 *
1066 * Called at initialization to parse the values of Clock Delays.
1067 */
1068static void arasan_dt_parse_clk_phases(struct device *dev,
1069 struct sdhci_arasan_clk_data *clk_data)
1070{
1071 u32 mio_bank = 0;
1072 int i;
1073
1074 /*
1075 * This has been kept as a pointer and is assigned a function here.
1076 * So that different controller variants can assign their own handling
1077 * function.
1078 */
1079 clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
1080
1081 if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
1082 u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1083 ZYNQMP_ICLK_PHASE;
1084 u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1085 ZYNQMP_OCLK_PHASE;
1086
1087 of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
1088 if (mio_bank == 2) {
1089 zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
1090 zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90;
1091 }
1092
1093 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1094 clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];
1095 clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];
1096 }
1097 }
1098
1099 if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {
1100 u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1101 VERSAL_ICLK_PHASE;
1102 u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1103 VERSAL_OCLK_PHASE;
1104
1105 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1106 clk_data->clk_phase_in[i] = versal_iclk_phase[i];
1107 clk_data->clk_phase_out[i] = versal_oclk_phase[i];
1108 }
1109 }
1110
1111 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
1112 "clk-phase-legacy");
1113 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
1114 "clk-phase-mmc-hs");
1115 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
1116 "clk-phase-sd-hs");
1117 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
1118 "clk-phase-uhs-sdr12");
1119 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
1120 "clk-phase-uhs-sdr25");
1121 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
1122 "clk-phase-uhs-sdr50");
1123 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
1124 "clk-phase-uhs-sdr104");
1125 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
1126 "clk-phase-uhs-ddr50");
1127 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
1128 "clk-phase-mmc-ddr52");
1129 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
1130 "clk-phase-mmc-hs200");
1131 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
1132 "clk-phase-mmc-hs400");
1133}
1134
1135static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
1136 .ops = &sdhci_arasan_ops,
1137 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1138 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1139 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1140 SDHCI_QUIRK2_STOP_WITH_TC,
1141};
1142
1143static const struct sdhci_arasan_clk_ops arasan_clk_ops = {
1144 .sdcardclk_ops = &arasan_sdcardclk_ops,
1145 .sampleclk_ops = &arasan_sampleclk_ops,
1146};
1147
1148static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
1149 .pdata = &sdhci_arasan_pdata,
1150 .clk_ops = &arasan_clk_ops,
1151};
1152
1153static const struct sdhci_arasan_of_data sdhci_arasan_thunderbay_data = {
1154 .soc_ctl_map = &thunderbay_soc_ctl_map,
1155 .pdata = &sdhci_arasan_thunderbay_pdata,
1156 .clk_ops = &arasan_clk_ops,
1157};
1158
1159static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
1160 .ops = &sdhci_arasan_cqe_ops,
1161 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1162 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1163 SDHCI_QUIRK_NO_LED |
1164 SDHCI_QUIRK_32BIT_DMA_ADDR |
1165 SDHCI_QUIRK_32BIT_DMA_SIZE |
1166 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1167 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1168 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1169 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1170 SDHCI_QUIRK2_STOP_WITH_TC |
1171 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1172};
1173
1174static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
1175 .ops = &sdhci_arasan_ops,
1176 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1177 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1178 SDHCI_QUIRK_NO_LED |
1179 SDHCI_QUIRK_32BIT_DMA_ADDR |
1180 SDHCI_QUIRK_32BIT_DMA_SIZE |
1181 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1182 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1183 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1184 SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1185 SDHCI_QUIRK2_STOP_WITH_TC |
1186 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1187};
1188
1189static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
1190 .ops = &sdhci_arasan_ops,
1191 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1192 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1193 SDHCI_QUIRK_NO_LED |
1194 SDHCI_QUIRK_32BIT_DMA_ADDR |
1195 SDHCI_QUIRK_32BIT_DMA_SIZE |
1196 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1197 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1198 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1199 SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1200 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1201};
1202
1203static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
1204 .soc_ctl_map = &rk3399_soc_ctl_map,
1205 .pdata = &sdhci_arasan_cqe_pdata,
1206 .clk_ops = &arasan_clk_ops,
1207};
1208
1209static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
1210 .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
1211 .pdata = &sdhci_arasan_cqe_pdata,
1212 .clk_ops = &arasan_clk_ops,
1213};
1214
1215static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
1216 .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
1217 .pdata = &sdhci_arasan_cqe_pdata,
1218 .clk_ops = &arasan_clk_ops,
1219};
1220
1221static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
1222 .ops = &sdhci_arasan_ops,
1223 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1224 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1225 SDHCI_QUIRK2_STOP_WITH_TC,
1226};
1227
1228static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = {
1229 .sdcardclk_ops = &zynqmp_sdcardclk_ops,
1230 .sampleclk_ops = &zynqmp_sampleclk_ops,
1231};
1232
1233static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
1234 .pdata = &sdhci_arasan_zynqmp_pdata,
1235 .clk_ops = &zynqmp_clk_ops,
1236};
1237
1238static const struct sdhci_arasan_clk_ops versal_clk_ops = {
1239 .sdcardclk_ops = &versal_sdcardclk_ops,
1240 .sampleclk_ops = &versal_sampleclk_ops,
1241};
1242
1243static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
1244 .pdata = &sdhci_arasan_zynqmp_pdata,
1245 .clk_ops = &versal_clk_ops,
1246};
1247
1248static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
1249 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1250 .pdata = &sdhci_keembay_emmc_pdata,
1251 .clk_ops = &arasan_clk_ops,
1252};
1253
1254static struct sdhci_arasan_of_data intel_keembay_sd_data = {
1255 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1256 .pdata = &sdhci_keembay_sd_pdata,
1257 .clk_ops = &arasan_clk_ops,
1258};
1259
1260static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
1261 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1262 .pdata = &sdhci_keembay_sdio_pdata,
1263 .clk_ops = &arasan_clk_ops,
1264};
1265
1266static const struct of_device_id sdhci_arasan_of_match[] = {
1267 /* SoC-specific compatible strings w/ soc_ctl_map */
1268 {
1269 .compatible = "rockchip,rk3399-sdhci-5.1",
1270 .data = &sdhci_arasan_rk3399_data,
1271 },
1272 {
1273 .compatible = "intel,lgm-sdhci-5.1-emmc",
1274 .data = &intel_lgm_emmc_data,
1275 },
1276 {
1277 .compatible = "intel,lgm-sdhci-5.1-sdxc",
1278 .data = &intel_lgm_sdxc_data,
1279 },
1280 {
1281 .compatible = "intel,keembay-sdhci-5.1-emmc",
1282 .data = &intel_keembay_emmc_data,
1283 },
1284 {
1285 .compatible = "intel,keembay-sdhci-5.1-sd",
1286 .data = &intel_keembay_sd_data,
1287 },
1288 {
1289 .compatible = "intel,keembay-sdhci-5.1-sdio",
1290 .data = &intel_keembay_sdio_data,
1291 },
1292 {
1293 .compatible = "intel,thunderbay-sdhci-5.1",
1294 .data = &sdhci_arasan_thunderbay_data,
1295 },
1296 /* Generic compatible below here */
1297 {
1298 .compatible = "arasan,sdhci-8.9a",
1299 .data = &sdhci_arasan_generic_data,
1300 },
1301 {
1302 .compatible = "arasan,sdhci-5.1",
1303 .data = &sdhci_arasan_generic_data,
1304 },
1305 {
1306 .compatible = "arasan,sdhci-4.9a",
1307 .data = &sdhci_arasan_generic_data,
1308 },
1309 {
1310 .compatible = "xlnx,zynqmp-8.9a",
1311 .data = &sdhci_arasan_zynqmp_data,
1312 },
1313 {
1314 .compatible = "xlnx,versal-8.9a",
1315 .data = &sdhci_arasan_versal_data,
1316 },
1317 { /* sentinel */ }
1318};
1319MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
1320
1321/**
1322 * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1323 *
1324 * @sdhci_arasan: Our private data structure.
1325 * @clk_xin: Pointer to the functional clock
1326 * @dev: Pointer to our struct device.
1327 *
1328 * Some PHY devices need to know what the actual card clock is. In order for
1329 * them to find out, we'll provide a clock through the common clock framework
1330 * for them to query.
1331 *
1332 * Return: 0 on success and error value on error
1333 */
1334static int
1335sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan,
1336 struct clk *clk_xin,
1337 struct device *dev)
1338{
1339 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1340 struct device_node *np = dev->of_node;
1341 struct clk_init_data sdcardclk_init;
1342 const char *parent_clk_name;
1343 int ret;
1344
1345 ret = of_property_read_string_index(np, "clock-output-names", 0,
1346 &sdcardclk_init.name);
1347 if (ret) {
1348 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1349 return ret;
1350 }
1351
1352 parent_clk_name = __clk_get_name(clk_xin);
1353 sdcardclk_init.parent_names = &parent_clk_name;
1354 sdcardclk_init.num_parents = 1;
1355 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
1356 sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops;
1357
1358 clk_data->sdcardclk_hw.init = &sdcardclk_init;
1359 clk_data->sdcardclk =
1360 devm_clk_register(dev, &clk_data->sdcardclk_hw);
1361 if (IS_ERR(clk_data->sdcardclk))
1362 return PTR_ERR(clk_data->sdcardclk);
1363 clk_data->sdcardclk_hw.init = NULL;
1364
1365 ret = of_clk_add_provider(np, of_clk_src_simple_get,
1366 clk_data->sdcardclk);
1367 if (ret)
1368 dev_err(dev, "Failed to add sdcard clock provider\n");
1369
1370 return ret;
1371}
1372
1373/**
1374 * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1375 *
1376 * @sdhci_arasan: Our private data structure.
1377 * @clk_xin: Pointer to the functional clock
1378 * @dev: Pointer to our struct device.
1379 *
1380 * Some PHY devices need to know what the actual card clock is. In order for
1381 * them to find out, we'll provide a clock through the common clock framework
1382 * for them to query.
1383 *
1384 * Return: 0 on success and error value on error
1385 */
1386static int
1387sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan,
1388 struct clk *clk_xin,
1389 struct device *dev)
1390{
1391 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1392 struct device_node *np = dev->of_node;
1393 struct clk_init_data sampleclk_init;
1394 const char *parent_clk_name;
1395 int ret;
1396
1397 ret = of_property_read_string_index(np, "clock-output-names", 1,
1398 &sampleclk_init.name);
1399 if (ret) {
1400 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1401 return ret;
1402 }
1403
1404 parent_clk_name = __clk_get_name(clk_xin);
1405 sampleclk_init.parent_names = &parent_clk_name;
1406 sampleclk_init.num_parents = 1;
1407 sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
1408 sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops;
1409
1410 clk_data->sampleclk_hw.init = &sampleclk_init;
1411 clk_data->sampleclk =
1412 devm_clk_register(dev, &clk_data->sampleclk_hw);
1413 if (IS_ERR(clk_data->sampleclk))
1414 return PTR_ERR(clk_data->sampleclk);
1415 clk_data->sampleclk_hw.init = NULL;
1416
1417 ret = of_clk_add_provider(np, of_clk_src_simple_get,
1418 clk_data->sampleclk);
1419 if (ret)
1420 dev_err(dev, "Failed to add sample clock provider\n");
1421
1422 return ret;
1423}
1424
1425/**
1426 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1427 *
1428 * @dev: Pointer to our struct device.
1429 *
1430 * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
1431 * returned success.
1432 */
1433static void sdhci_arasan_unregister_sdclk(struct device *dev)
1434{
1435 struct device_node *np = dev->of_node;
1436
1437 if (!of_find_property(np, "#clock-cells", NULL))
1438 return;
1439
1440 of_clk_del_provider(dev->of_node);
1441}
1442
1443/**
1444 * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1445 * @host: The sdhci_host
1446 * @value: The value to write
1447 *
1448 * This should be set based on the System Address Bus.
1449 * 0: the Core supports only 32-bit System Address Bus.
1450 * 1: the Core supports 64-bit System Address Bus.
1451 *
1452 * NOTE:
1453 * For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
1454 * Keem Bay does not support 64-bit access.
1455 */
1456static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
1457{
1458 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1459 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1460 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
1461
1462 /* Having a map is optional */
1463 soc_ctl_map = sdhci_arasan->soc_ctl_map;
1464 if (!soc_ctl_map)
1465 return;
1466
1467 /* If we have a map, we expect to have a syscon */
1468 if (!sdhci_arasan->soc_ctl_base) {
1469 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1470 mmc_hostname(host->mmc));
1471 return;
1472 }
1473
1474 sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
1475}
1476
1477/**
1478 * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1479 *
1480 * @sdhci_arasan: Our private data structure.
1481 * @clk_xin: Pointer to the functional clock
1482 * @dev: Pointer to our struct device.
1483 *
1484 * Some PHY devices need to know what the actual card clock is. In order for
1485 * them to find out, we'll provide a clock through the common clock framework
1486 * for them to query.
1487 *
1488 * Note: without seriously re-architecting SDHCI's clock code and testing on
1489 * all platforms, there's no way to create a totally beautiful clock here
1490 * with all clock ops implemented. Instead, we'll just create a clock that can
1491 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
1492 * framework that we're doing things behind its back. This should be sufficient
1493 * to create nice clean device tree bindings and later (if needed) we can try
1494 * re-architecting SDHCI if we see some benefit to it.
1495 *
1496 * Return: 0 on success and error value on error
1497 */
1498static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
1499 struct clk *clk_xin,
1500 struct device *dev)
1501{
1502 struct device_node *np = dev->of_node;
1503 u32 num_clks = 0;
1504 int ret;
1505
1506 /* Providing a clock to the PHY is optional; no error if missing */
1507 if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
1508 return 0;
1509
1510 ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
1511 if (ret)
1512 return ret;
1513
1514 if (num_clks) {
1515 ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
1516 dev);
1517 if (ret) {
1518 sdhci_arasan_unregister_sdclk(dev);
1519 return ret;
1520 }
1521 }
1522
1523 return 0;
1524}
1525
1526static int sdhci_zynqmp_set_dynamic_config(struct device *dev,
1527 struct sdhci_arasan_data *sdhci_arasan)
1528{
1529 struct sdhci_host *host = sdhci_arasan->host;
1530 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
1531 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1532 const char *clk_name = clk_hw_get_name(hw);
1533 u32 mhz, node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
1534 struct reset_control *rstc;
1535 int ret;
1536
1537 /* Obtain SDHC reset control */
1538 rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
1539 if (IS_ERR(rstc)) {
1540 dev_err(dev, "Cannot get SDHC reset.\n");
1541 return PTR_ERR(rstc);
1542 }
1543
1544 ret = reset_control_assert(rstc);
1545 if (ret)
1546 return ret;
1547
1548 ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_FIXED, 0);
1549 if (ret)
1550 return ret;
1551
1552 ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_EMMC_SEL,
1553 !!(host->mmc->caps & MMC_CAP_NONREMOVABLE));
1554 if (ret)
1555 return ret;
1556
1557 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);
1558 if (mhz > 100 && mhz <= 200)
1559 mhz = 200;
1560 else if (mhz > 50 && mhz <= 100)
1561 mhz = 100;
1562 else if (mhz > 25 && mhz <= 50)
1563 mhz = 50;
1564 else
1565 mhz = 25;
1566
1567 ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_BASECLK, mhz);
1568 if (ret)
1569 return ret;
1570
1571 ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_8BIT,
1572 !!(host->mmc->caps & MMC_CAP_8_BIT_DATA));
1573 if (ret)
1574 return ret;
1575
1576 ret = reset_control_deassert(rstc);
1577 if (ret)
1578 return ret;
1579
1580 usleep_range(1000, 1500);
1581
1582 return 0;
1583}
1584
1585static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
1586{
1587 struct sdhci_host *host = sdhci_arasan->host;
1588 struct cqhci_host *cq_host;
1589 bool dma64;
1590 int ret;
1591
1592 if (!sdhci_arasan->has_cqe)
1593 return sdhci_add_host(host);
1594
1595 ret = sdhci_setup_host(host);
1596 if (ret)
1597 return ret;
1598
1599 cq_host = devm_kzalloc(host->mmc->parent,
1600 sizeof(*cq_host), GFP_KERNEL);
1601 if (!cq_host) {
1602 ret = -ENOMEM;
1603 goto cleanup;
1604 }
1605
1606 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
1607 cq_host->ops = &sdhci_arasan_cqhci_ops;
1608
1609 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1610 if (dma64)
1611 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1612
1613 ret = cqhci_init(cq_host, host->mmc, dma64);
1614 if (ret)
1615 goto cleanup;
1616
1617 ret = __sdhci_add_host(host);
1618 if (ret)
1619 goto cleanup;
1620
1621 return 0;
1622
1623cleanup:
1624 sdhci_cleanup_host(host);
1625 return ret;
1626}
1627
1628static int sdhci_arasan_probe(struct platform_device *pdev)
1629{
1630 int ret;
1631 struct device_node *node;
1632 struct clk *clk_xin;
1633 struct sdhci_host *host;
1634 struct sdhci_pltfm_host *pltfm_host;
1635 struct device *dev = &pdev->dev;
1636 struct device_node *np = dev->of_node;
1637 struct sdhci_arasan_data *sdhci_arasan;
1638 const struct sdhci_arasan_of_data *data;
1639
1640 data = of_device_get_match_data(dev);
1641 if (!data)
1642 return -EINVAL;
1643
1644 host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));
1645
1646 if (IS_ERR(host))
1647 return PTR_ERR(host);
1648
1649 pltfm_host = sdhci_priv(host);
1650 sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1651 sdhci_arasan->host = host;
1652
1653 sdhci_arasan->soc_ctl_map = data->soc_ctl_map;
1654 sdhci_arasan->clk_ops = data->clk_ops;
1655
1656 node = of_parse_phandle(np, "arasan,soc-ctl-syscon", 0);
1657 if (node) {
1658 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
1659 of_node_put(node);
1660
1661 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
1662 ret = dev_err_probe(dev,
1663 PTR_ERR(sdhci_arasan->soc_ctl_base),
1664 "Can't get syscon\n");
1665 goto err_pltfm_free;
1666 }
1667 }
1668
1669 sdhci_get_of_property(pdev);
1670
1671 sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb");
1672 if (IS_ERR(sdhci_arasan->clk_ahb)) {
1673 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb),
1674 "clk_ahb clock not found.\n");
1675 goto err_pltfm_free;
1676 }
1677
1678 clk_xin = devm_clk_get(dev, "clk_xin");
1679 if (IS_ERR(clk_xin)) {
1680 ret = dev_err_probe(dev, PTR_ERR(clk_xin), "clk_xin clock not found.\n");
1681 goto err_pltfm_free;
1682 }
1683
1684 ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
1685 if (ret) {
1686 dev_err(dev, "Unable to enable AHB clock.\n");
1687 goto err_pltfm_free;
1688 }
1689
1690 /* If clock-frequency property is set, use the provided value */
1691 if (pltfm_host->clock &&
1692 pltfm_host->clock != clk_get_rate(clk_xin)) {
1693 ret = clk_set_rate(clk_xin, pltfm_host->clock);
1694 if (ret) {
1695 dev_err(&pdev->dev, "Failed to set SD clock rate\n");
1696 goto clk_dis_ahb;
1697 }
1698 }
1699
1700 ret = clk_prepare_enable(clk_xin);
1701 if (ret) {
1702 dev_err(dev, "Unable to enable SD clock.\n");
1703 goto clk_dis_ahb;
1704 }
1705
1706 if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
1707 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
1708
1709 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
1710 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
1711
1712 pltfm_host->clk = clk_xin;
1713
1714 if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1"))
1715 sdhci_arasan_update_clockmultiplier(host, 0x0);
1716
1717 if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
1718 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
1719 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio") ||
1720 of_device_is_compatible(np, "intel,thunderbay-sdhci-5.1")) {
1721 sdhci_arasan_update_clockmultiplier(host, 0x0);
1722 sdhci_arasan_update_support64b(host, 0x0);
1723
1724 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1725 }
1726
1727 sdhci_arasan_update_baseclkfreq(host);
1728
1729 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, dev);
1730 if (ret)
1731 goto clk_disable_all;
1732
1733 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
1734 host->mmc_host_ops.execute_tuning =
1735 arasan_zynqmp_execute_tuning;
1736
1737 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN;
1738 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
1739 }
1740
1741 arasan_dt_parse_clk_phases(dev, &sdhci_arasan->clk_data);
1742
1743 ret = mmc_of_parse(host->mmc);
1744 if (ret) {
1745 ret = dev_err_probe(dev, ret, "parsing dt failed.\n");
1746 goto unreg_clk;
1747 }
1748
1749 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
1750 ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_SD_CONFIG);
1751 if (!ret) {
1752 ret = sdhci_zynqmp_set_dynamic_config(dev, sdhci_arasan);
1753 if (ret)
1754 goto unreg_clk;
1755 }
1756 }
1757
1758 sdhci_arasan->phy = ERR_PTR(-ENODEV);
1759 if (of_device_is_compatible(np, "arasan,sdhci-5.1")) {
1760 sdhci_arasan->phy = devm_phy_get(dev, "phy_arasan");
1761 if (IS_ERR(sdhci_arasan->phy)) {
1762 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->phy),
1763 "No phy for arasan,sdhci-5.1.\n");
1764 goto unreg_clk;
1765 }
1766
1767 ret = phy_init(sdhci_arasan->phy);
1768 if (ret < 0) {
1769 dev_err(dev, "phy_init err.\n");
1770 goto unreg_clk;
1771 }
1772
1773 host->mmc_host_ops.hs400_enhanced_strobe =
1774 sdhci_arasan_hs400_enhanced_strobe;
1775 host->mmc_host_ops.start_signal_voltage_switch =
1776 sdhci_arasan_voltage_switch;
1777 sdhci_arasan->has_cqe = true;
1778 host->mmc->caps2 |= MMC_CAP2_CQE;
1779
1780 if (!of_property_read_bool(np, "disable-cqe-dcmd"))
1781 host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
1782 }
1783
1784 ret = sdhci_arasan_add_host(sdhci_arasan);
1785 if (ret)
1786 goto err_add_host;
1787
1788 return 0;
1789
1790err_add_host:
1791 if (!IS_ERR(sdhci_arasan->phy))
1792 phy_exit(sdhci_arasan->phy);
1793unreg_clk:
1794 sdhci_arasan_unregister_sdclk(dev);
1795clk_disable_all:
1796 clk_disable_unprepare(clk_xin);
1797clk_dis_ahb:
1798 clk_disable_unprepare(sdhci_arasan->clk_ahb);
1799err_pltfm_free:
1800 sdhci_pltfm_free(pdev);
1801 return ret;
1802}
1803
1804static int sdhci_arasan_remove(struct platform_device *pdev)
1805{
1806 struct sdhci_host *host = platform_get_drvdata(pdev);
1807 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1808 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1809 struct clk *clk_ahb = sdhci_arasan->clk_ahb;
1810
1811 if (!IS_ERR(sdhci_arasan->phy)) {
1812 if (sdhci_arasan->is_phy_on)
1813 phy_power_off(sdhci_arasan->phy);
1814 phy_exit(sdhci_arasan->phy);
1815 }
1816
1817 sdhci_arasan_unregister_sdclk(&pdev->dev);
1818
1819 sdhci_pltfm_unregister(pdev);
1820
1821 clk_disable_unprepare(clk_ahb);
1822
1823 return 0;
1824}
1825
1826static struct platform_driver sdhci_arasan_driver = {
1827 .driver = {
1828 .name = "sdhci-arasan",
1829 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1830 .of_match_table = sdhci_arasan_of_match,
1831 .pm = &sdhci_arasan_dev_pm_ops,
1832 },
1833 .probe = sdhci_arasan_probe,
1834 .remove = sdhci_arasan_remove,
1835};
1836
1837module_platform_driver(sdhci_arasan_driver);
1838
1839MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
1840MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
1841MODULE_LICENSE("GPL");
1/*
2 * Arasan Secure Digital Host Controller Interface.
3 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
4 * Copyright (c) 2012 Wind River Systems, Inc.
5 * Copyright (C) 2013 Pengutronix e.K.
6 * Copyright (C) 2013 Xilinx Inc.
7 *
8 * Based on sdhci-of-esdhc.c
9 *
10 * Copyright (c) 2007 Freescale Semiconductor, Inc.
11 * Copyright (c) 2009 MontaVista Software, Inc.
12 *
13 * Authors: Xiaobo Xie <X.Xie@freescale.com>
14 * Anton Vorontsov <avorontsov@ru.mvista.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or (at
19 * your option) any later version.
20 */
21
22#include <linux/clk-provider.h>
23#include <linux/mfd/syscon.h>
24#include <linux/module.h>
25#include <linux/of_device.h>
26#include <linux/phy/phy.h>
27#include <linux/regmap.h>
28#include "sdhci-pltfm.h"
29#include <linux/of.h>
30
31#define SDHCI_ARASAN_VENDOR_REGISTER 0x78
32
33#define VENDOR_ENHANCED_STROBE BIT(0)
34
35#define PHY_CLK_TOO_SLOW_HZ 400000
36
37/*
38 * On some SoCs the syscon area has a feature where the upper 16-bits of
39 * each 32-bit register act as a write mask for the lower 16-bits. This allows
40 * atomic updates of the register without locking. This macro is used on SoCs
41 * that have that feature.
42 */
43#define HIWORD_UPDATE(val, mask, shift) \
44 ((val) << (shift) | (mask) << ((shift) + 16))
45
46/**
47 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
48 *
49 * @reg: Offset within the syscon of the register containing this field
50 * @width: Number of bits for this field
51 * @shift: Bit offset within @reg of this field (or -1 if not avail)
52 */
53struct sdhci_arasan_soc_ctl_field {
54 u32 reg;
55 u16 width;
56 s16 shift;
57};
58
59/**
60 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
61 *
62 * It's up to the licensee of the Arsan IP block to make these available
63 * somewhere if needed. Presumably these will be scattered somewhere that's
64 * accessible via the syscon API.
65 *
66 * @baseclkfreq: Where to find corecfg_baseclkfreq
67 * @clockmultiplier: Where to find corecfg_clockmultiplier
68 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
69 */
70struct sdhci_arasan_soc_ctl_map {
71 struct sdhci_arasan_soc_ctl_field baseclkfreq;
72 struct sdhci_arasan_soc_ctl_field clockmultiplier;
73 bool hiword_update;
74};
75
76/**
77 * struct sdhci_arasan_data
78 * @host: Pointer to the main SDHCI host structure.
79 * @clk_ahb: Pointer to the AHB clock
80 * @phy: Pointer to the generic phy
81 * @is_phy_on: True if the PHY is on; false if not.
82 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
83 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
84 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
85 * @soc_ctl_map: Map to get offsets into soc_ctl registers.
86 */
87struct sdhci_arasan_data {
88 struct sdhci_host *host;
89 struct clk *clk_ahb;
90 struct phy *phy;
91 bool is_phy_on;
92
93 struct clk_hw sdcardclk_hw;
94 struct clk *sdcardclk;
95
96 struct regmap *soc_ctl_base;
97 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
98 unsigned int quirks; /* Arasan deviations from spec */
99
100/* Controller does not have CD wired and will not function normally without */
101#define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
102};
103
104static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
105 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
106 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
107 .hiword_update = true,
108};
109
110/**
111 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
112 *
113 * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
114 * Note that if a field is specified as not available (shift < 0) then
115 * this function will silently return an error code. It will be noisy
116 * and print errors for any other (unexpected) errors.
117 *
118 * @host: The sdhci_host
119 * @fld: The field to write to
120 * @val: The value to write
121 */
122static int sdhci_arasan_syscon_write(struct sdhci_host *host,
123 const struct sdhci_arasan_soc_ctl_field *fld,
124 u32 val)
125{
126 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
127 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
128 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
129 u32 reg = fld->reg;
130 u16 width = fld->width;
131 s16 shift = fld->shift;
132 int ret;
133
134 /*
135 * Silently return errors for shift < 0 so caller doesn't have
136 * to check for fields which are optional. For fields that
137 * are required then caller needs to do something special
138 * anyway.
139 */
140 if (shift < 0)
141 return -EINVAL;
142
143 if (sdhci_arasan->soc_ctl_map->hiword_update)
144 ret = regmap_write(soc_ctl_base, reg,
145 HIWORD_UPDATE(val, GENMASK(width, 0),
146 shift));
147 else
148 ret = regmap_update_bits(soc_ctl_base, reg,
149 GENMASK(shift + width, shift),
150 val << shift);
151
152 /* Yell about (unexpected) regmap errors */
153 if (ret)
154 pr_warn("%s: Regmap write fail: %d\n",
155 mmc_hostname(host->mmc), ret);
156
157 return ret;
158}
159
160static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
161{
162 unsigned long freq;
163 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
164
165 /* SDHCI timeout clock is in kHz */
166 freq = DIV_ROUND_UP(clk_get_rate(pltfm_host->clk), 1000);
167
168 /* or in MHz */
169 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
170 freq = DIV_ROUND_UP(freq, 1000);
171
172 return freq;
173}
174
175static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
176{
177 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
178 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
179 bool ctrl_phy = false;
180
181 if (!IS_ERR(sdhci_arasan->phy)) {
182 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
183 /*
184 * If PHY off, set clock to max speed and power PHY on.
185 *
186 * Although PHY docs apparently suggest power cycling
187 * when changing the clock the PHY doesn't like to be
188 * powered on while at low speeds like those used in ID
189 * mode. Even worse is powering the PHY on while the
190 * clock is off.
191 *
192 * To workaround the PHY limitations, the best we can
193 * do is to power it on at a faster speed and then slam
194 * through low speeds without power cycling.
195 */
196 sdhci_set_clock(host, host->max_clk);
197 spin_unlock_irq(&host->lock);
198 phy_power_on(sdhci_arasan->phy);
199 spin_lock_irq(&host->lock);
200 sdhci_arasan->is_phy_on = true;
201
202 /*
203 * We'll now fall through to the below case with
204 * ctrl_phy = false (so we won't turn off/on). The
205 * sdhci_set_clock() will set the real clock.
206 */
207 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
208 /*
209 * At higher clock speeds the PHY is fine being power
210 * cycled and docs say you _should_ power cycle when
211 * changing clock speeds.
212 */
213 ctrl_phy = true;
214 }
215 }
216
217 if (ctrl_phy && sdhci_arasan->is_phy_on) {
218 spin_unlock_irq(&host->lock);
219 phy_power_off(sdhci_arasan->phy);
220 spin_lock_irq(&host->lock);
221 sdhci_arasan->is_phy_on = false;
222 }
223
224 sdhci_set_clock(host, clock);
225
226 if (ctrl_phy) {
227 spin_unlock_irq(&host->lock);
228 phy_power_on(sdhci_arasan->phy);
229 spin_lock_irq(&host->lock);
230 sdhci_arasan->is_phy_on = true;
231 }
232}
233
234static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
235 struct mmc_ios *ios)
236{
237 u32 vendor;
238 struct sdhci_host *host = mmc_priv(mmc);
239
240 vendor = readl(host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
241 if (ios->enhanced_strobe)
242 vendor |= VENDOR_ENHANCED_STROBE;
243 else
244 vendor &= ~VENDOR_ENHANCED_STROBE;
245
246 writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
247}
248
249static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
250{
251 u8 ctrl;
252 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
253 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
254
255 sdhci_reset(host, mask);
256
257 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
258 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
259 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
260 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
261 }
262}
263
264static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
265 struct mmc_ios *ios)
266{
267 switch (ios->signal_voltage) {
268 case MMC_SIGNAL_VOLTAGE_180:
269 /*
270 * Plese don't switch to 1V8 as arasan,5.1 doesn't
271 * actually refer to this setting to indicate the
272 * signal voltage and the state machine will be broken
273 * actually if we force to enable 1V8. That's something
274 * like broken quirk but we could work around here.
275 */
276 return 0;
277 case MMC_SIGNAL_VOLTAGE_330:
278 case MMC_SIGNAL_VOLTAGE_120:
279 /* We don't support 3V3 and 1V2 */
280 break;
281 }
282
283 return -EINVAL;
284}
285
286static struct sdhci_ops sdhci_arasan_ops = {
287 .set_clock = sdhci_arasan_set_clock,
288 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
289 .get_timeout_clock = sdhci_arasan_get_timeout_clock,
290 .set_bus_width = sdhci_set_bus_width,
291 .reset = sdhci_arasan_reset,
292 .set_uhs_signaling = sdhci_set_uhs_signaling,
293};
294
295static struct sdhci_pltfm_data sdhci_arasan_pdata = {
296 .ops = &sdhci_arasan_ops,
297 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
298 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
299 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
300};
301
302#ifdef CONFIG_PM_SLEEP
303/**
304 * sdhci_arasan_suspend - Suspend method for the driver
305 * @dev: Address of the device structure
306 * Returns 0 on success and error value on error
307 *
308 * Put the device in a low power state.
309 */
310static int sdhci_arasan_suspend(struct device *dev)
311{
312 struct platform_device *pdev = to_platform_device(dev);
313 struct sdhci_host *host = platform_get_drvdata(pdev);
314 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
315 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
316 int ret;
317
318 ret = sdhci_suspend_host(host);
319 if (ret)
320 return ret;
321
322 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
323 ret = phy_power_off(sdhci_arasan->phy);
324 if (ret) {
325 dev_err(dev, "Cannot power off phy.\n");
326 sdhci_resume_host(host);
327 return ret;
328 }
329 sdhci_arasan->is_phy_on = false;
330 }
331
332 clk_disable(pltfm_host->clk);
333 clk_disable(sdhci_arasan->clk_ahb);
334
335 return 0;
336}
337
338/**
339 * sdhci_arasan_resume - Resume method for the driver
340 * @dev: Address of the device structure
341 * Returns 0 on success and error value on error
342 *
343 * Resume operation after suspend
344 */
345static int sdhci_arasan_resume(struct device *dev)
346{
347 struct platform_device *pdev = to_platform_device(dev);
348 struct sdhci_host *host = platform_get_drvdata(pdev);
349 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
350 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
351 int ret;
352
353 ret = clk_enable(sdhci_arasan->clk_ahb);
354 if (ret) {
355 dev_err(dev, "Cannot enable AHB clock.\n");
356 return ret;
357 }
358
359 ret = clk_enable(pltfm_host->clk);
360 if (ret) {
361 dev_err(dev, "Cannot enable SD clock.\n");
362 return ret;
363 }
364
365 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
366 ret = phy_power_on(sdhci_arasan->phy);
367 if (ret) {
368 dev_err(dev, "Cannot power on phy.\n");
369 return ret;
370 }
371 sdhci_arasan->is_phy_on = true;
372 }
373
374 return sdhci_resume_host(host);
375}
376#endif /* ! CONFIG_PM_SLEEP */
377
378static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
379 sdhci_arasan_resume);
380
381static const struct of_device_id sdhci_arasan_of_match[] = {
382 /* SoC-specific compatible strings w/ soc_ctl_map */
383 {
384 .compatible = "rockchip,rk3399-sdhci-5.1",
385 .data = &rk3399_soc_ctl_map,
386 },
387
388 /* Generic compatible below here */
389 { .compatible = "arasan,sdhci-8.9a" },
390 { .compatible = "arasan,sdhci-5.1" },
391 { .compatible = "arasan,sdhci-4.9a" },
392
393 { /* sentinel */ }
394};
395MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
396
397/**
398 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
399 *
400 * Return the current actual rate of the SD card clock. This can be used
401 * to communicate with out PHY.
402 *
403 * @hw: Pointer to the hardware clock structure.
404 * @parent_rate The parent rate (should be rate of clk_xin).
405 * Returns the card clock rate.
406 */
407static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
408 unsigned long parent_rate)
409
410{
411 struct sdhci_arasan_data *sdhci_arasan =
412 container_of(hw, struct sdhci_arasan_data, sdcardclk_hw);
413 struct sdhci_host *host = sdhci_arasan->host;
414
415 return host->mmc->actual_clock;
416}
417
418static const struct clk_ops arasan_sdcardclk_ops = {
419 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
420};
421
422/**
423 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
424 *
425 * The corecfg_clockmultiplier is supposed to contain clock multiplier
426 * value of programmable clock generator.
427 *
428 * NOTES:
429 * - Many existing devices don't seem to do this and work fine. To keep
430 * compatibility for old hardware where the device tree doesn't provide a
431 * register map, this function is a noop if a soc_ctl_map hasn't been provided
432 * for this platform.
433 * - The value of corecfg_clockmultiplier should sync with that of corresponding
434 * value reading from sdhci_capability_register. So this function is called
435 * once at probe time and never called again.
436 *
437 * @host: The sdhci_host
438 */
439static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
440 u32 value)
441{
442 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
443 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
444 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
445 sdhci_arasan->soc_ctl_map;
446
447 /* Having a map is optional */
448 if (!soc_ctl_map)
449 return;
450
451 /* If we have a map, we expect to have a syscon */
452 if (!sdhci_arasan->soc_ctl_base) {
453 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
454 mmc_hostname(host->mmc));
455 return;
456 }
457
458 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
459}
460
461/**
462 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
463 *
464 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
465 * function can be used to make that happen.
466 *
467 * NOTES:
468 * - Many existing devices don't seem to do this and work fine. To keep
469 * compatibility for old hardware where the device tree doesn't provide a
470 * register map, this function is a noop if a soc_ctl_map hasn't been provided
471 * for this platform.
472 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
473 * to achieve lower clock rates. That means that this function is called once
474 * at probe time and never called again.
475 *
476 * @host: The sdhci_host
477 */
478static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
479{
480 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
481 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
482 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
483 sdhci_arasan->soc_ctl_map;
484 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
485
486 /* Having a map is optional */
487 if (!soc_ctl_map)
488 return;
489
490 /* If we have a map, we expect to have a syscon */
491 if (!sdhci_arasan->soc_ctl_base) {
492 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
493 mmc_hostname(host->mmc));
494 return;
495 }
496
497 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
498}
499
500/**
501 * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use
502 *
503 * Some PHY devices need to know what the actual card clock is. In order for
504 * them to find out, we'll provide a clock through the common clock framework
505 * for them to query.
506 *
507 * Note: without seriously re-architecting SDHCI's clock code and testing on
508 * all platforms, there's no way to create a totally beautiful clock here
509 * with all clock ops implemented. Instead, we'll just create a clock that can
510 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
511 * framework that we're doing things behind its back. This should be sufficient
512 * to create nice clean device tree bindings and later (if needed) we can try
513 * re-architecting SDHCI if we see some benefit to it.
514 *
515 * @sdhci_arasan: Our private data structure.
516 * @clk_xin: Pointer to the functional clock
517 * @dev: Pointer to our struct device.
518 * Returns 0 on success and error value on error
519 */
520static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
521 struct clk *clk_xin,
522 struct device *dev)
523{
524 struct device_node *np = dev->of_node;
525 struct clk_init_data sdcardclk_init;
526 const char *parent_clk_name;
527 int ret;
528
529 /* Providing a clock to the PHY is optional; no error if missing */
530 if (!of_find_property(np, "#clock-cells", NULL))
531 return 0;
532
533 ret = of_property_read_string_index(np, "clock-output-names", 0,
534 &sdcardclk_init.name);
535 if (ret) {
536 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
537 return ret;
538 }
539
540 parent_clk_name = __clk_get_name(clk_xin);
541 sdcardclk_init.parent_names = &parent_clk_name;
542 sdcardclk_init.num_parents = 1;
543 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
544 sdcardclk_init.ops = &arasan_sdcardclk_ops;
545
546 sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init;
547 sdhci_arasan->sdcardclk =
548 devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw);
549 sdhci_arasan->sdcardclk_hw.init = NULL;
550
551 ret = of_clk_add_provider(np, of_clk_src_simple_get,
552 sdhci_arasan->sdcardclk);
553 if (ret)
554 dev_err(dev, "Failed to add clock provider\n");
555
556 return ret;
557}
558
559/**
560 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
561 *
562 * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
563 * returned success.
564 *
565 * @dev: Pointer to our struct device.
566 */
567static void sdhci_arasan_unregister_sdclk(struct device *dev)
568{
569 struct device_node *np = dev->of_node;
570
571 if (!of_find_property(np, "#clock-cells", NULL))
572 return;
573
574 of_clk_del_provider(dev->of_node);
575}
576
577static int sdhci_arasan_probe(struct platform_device *pdev)
578{
579 int ret;
580 const struct of_device_id *match;
581 struct device_node *node;
582 struct clk *clk_xin;
583 struct sdhci_host *host;
584 struct sdhci_pltfm_host *pltfm_host;
585 struct sdhci_arasan_data *sdhci_arasan;
586 struct device_node *np = pdev->dev.of_node;
587
588 host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata,
589 sizeof(*sdhci_arasan));
590 if (IS_ERR(host))
591 return PTR_ERR(host);
592
593 pltfm_host = sdhci_priv(host);
594 sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
595 sdhci_arasan->host = host;
596
597 match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
598 sdhci_arasan->soc_ctl_map = match->data;
599
600 node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
601 if (node) {
602 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
603 of_node_put(node);
604
605 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
606 ret = PTR_ERR(sdhci_arasan->soc_ctl_base);
607 if (ret != -EPROBE_DEFER)
608 dev_err(&pdev->dev, "Can't get syscon: %d\n",
609 ret);
610 goto err_pltfm_free;
611 }
612 }
613
614 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
615 if (IS_ERR(sdhci_arasan->clk_ahb)) {
616 dev_err(&pdev->dev, "clk_ahb clock not found.\n");
617 ret = PTR_ERR(sdhci_arasan->clk_ahb);
618 goto err_pltfm_free;
619 }
620
621 clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
622 if (IS_ERR(clk_xin)) {
623 dev_err(&pdev->dev, "clk_xin clock not found.\n");
624 ret = PTR_ERR(clk_xin);
625 goto err_pltfm_free;
626 }
627
628 ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
629 if (ret) {
630 dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
631 goto err_pltfm_free;
632 }
633
634 ret = clk_prepare_enable(clk_xin);
635 if (ret) {
636 dev_err(&pdev->dev, "Unable to enable SD clock.\n");
637 goto clk_dis_ahb;
638 }
639
640 sdhci_get_of_property(pdev);
641
642 if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
643 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
644
645 pltfm_host->clk = clk_xin;
646
647 if (of_device_is_compatible(pdev->dev.of_node,
648 "rockchip,rk3399-sdhci-5.1"))
649 sdhci_arasan_update_clockmultiplier(host, 0x0);
650
651 sdhci_arasan_update_baseclkfreq(host);
652
653 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
654 if (ret)
655 goto clk_disable_all;
656
657 ret = mmc_of_parse(host->mmc);
658 if (ret) {
659 dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret);
660 goto unreg_clk;
661 }
662
663 sdhci_arasan->phy = ERR_PTR(-ENODEV);
664 if (of_device_is_compatible(pdev->dev.of_node,
665 "arasan,sdhci-5.1")) {
666 sdhci_arasan->phy = devm_phy_get(&pdev->dev,
667 "phy_arasan");
668 if (IS_ERR(sdhci_arasan->phy)) {
669 ret = PTR_ERR(sdhci_arasan->phy);
670 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
671 goto unreg_clk;
672 }
673
674 ret = phy_init(sdhci_arasan->phy);
675 if (ret < 0) {
676 dev_err(&pdev->dev, "phy_init err.\n");
677 goto unreg_clk;
678 }
679
680 host->mmc_host_ops.hs400_enhanced_strobe =
681 sdhci_arasan_hs400_enhanced_strobe;
682 host->mmc_host_ops.start_signal_voltage_switch =
683 sdhci_arasan_voltage_switch;
684 }
685
686 ret = sdhci_add_host(host);
687 if (ret)
688 goto err_add_host;
689
690 return 0;
691
692err_add_host:
693 if (!IS_ERR(sdhci_arasan->phy))
694 phy_exit(sdhci_arasan->phy);
695unreg_clk:
696 sdhci_arasan_unregister_sdclk(&pdev->dev);
697clk_disable_all:
698 clk_disable_unprepare(clk_xin);
699clk_dis_ahb:
700 clk_disable_unprepare(sdhci_arasan->clk_ahb);
701err_pltfm_free:
702 sdhci_pltfm_free(pdev);
703 return ret;
704}
705
706static int sdhci_arasan_remove(struct platform_device *pdev)
707{
708 int ret;
709 struct sdhci_host *host = platform_get_drvdata(pdev);
710 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
711 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
712 struct clk *clk_ahb = sdhci_arasan->clk_ahb;
713
714 if (!IS_ERR(sdhci_arasan->phy)) {
715 if (sdhci_arasan->is_phy_on)
716 phy_power_off(sdhci_arasan->phy);
717 phy_exit(sdhci_arasan->phy);
718 }
719
720 sdhci_arasan_unregister_sdclk(&pdev->dev);
721
722 ret = sdhci_pltfm_unregister(pdev);
723
724 clk_disable_unprepare(clk_ahb);
725
726 return ret;
727}
728
729static struct platform_driver sdhci_arasan_driver = {
730 .driver = {
731 .name = "sdhci-arasan",
732 .of_match_table = sdhci_arasan_of_match,
733 .pm = &sdhci_arasan_dev_pm_ops,
734 },
735 .probe = sdhci_arasan_probe,
736 .remove = sdhci_arasan_remove,
737};
738
739module_platform_driver(sdhci_arasan_driver);
740
741MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
742MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
743MODULE_LICENSE("GPL");