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1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
3 *
4 * Author: Stepan Moskovchenko <stepanm@codeaurora.org>
5 */
6
7#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/errno.h>
12#include <linux/io.h>
13#include <linux/io-pgtable.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/spinlock.h>
17#include <linux/slab.h>
18#include <linux/iommu.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21
22#include <asm/cacheflush.h>
23#include <linux/sizes.h>
24
25#include "msm_iommu_hw-8xxx.h"
26#include "msm_iommu.h"
27
28#define MRC(reg, processor, op1, crn, crm, op2) \
29__asm__ __volatile__ ( \
30" mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \
31: "=r" (reg))
32
33/* bitmap of the page sizes currently supported */
34#define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
35
36static DEFINE_SPINLOCK(msm_iommu_lock);
37static LIST_HEAD(qcom_iommu_devices);
38static struct iommu_ops msm_iommu_ops;
39
40struct msm_priv {
41 struct list_head list_attached;
42 struct iommu_domain domain;
43 struct io_pgtable_cfg cfg;
44 struct io_pgtable_ops *iop;
45 struct device *dev;
46 spinlock_t pgtlock; /* pagetable lock */
47};
48
49static struct msm_priv *to_msm_priv(struct iommu_domain *dom)
50{
51 return container_of(dom, struct msm_priv, domain);
52}
53
54static int __enable_clocks(struct msm_iommu_dev *iommu)
55{
56 int ret;
57
58 ret = clk_enable(iommu->pclk);
59 if (ret)
60 goto fail;
61
62 if (iommu->clk) {
63 ret = clk_enable(iommu->clk);
64 if (ret)
65 clk_disable(iommu->pclk);
66 }
67fail:
68 return ret;
69}
70
71static void __disable_clocks(struct msm_iommu_dev *iommu)
72{
73 if (iommu->clk)
74 clk_disable(iommu->clk);
75 clk_disable(iommu->pclk);
76}
77
78static void msm_iommu_reset(void __iomem *base, int ncb)
79{
80 int ctx;
81
82 SET_RPUE(base, 0);
83 SET_RPUEIE(base, 0);
84 SET_ESRRESTORE(base, 0);
85 SET_TBE(base, 0);
86 SET_CR(base, 0);
87 SET_SPDMBE(base, 0);
88 SET_TESTBUSCR(base, 0);
89 SET_TLBRSW(base, 0);
90 SET_GLOBAL_TLBIALL(base, 0);
91 SET_RPU_ACR(base, 0);
92 SET_TLBLKCRWE(base, 1);
93
94 for (ctx = 0; ctx < ncb; ctx++) {
95 SET_BPRCOSH(base, ctx, 0);
96 SET_BPRCISH(base, ctx, 0);
97 SET_BPRCNSH(base, ctx, 0);
98 SET_BPSHCFG(base, ctx, 0);
99 SET_BPMTCFG(base, ctx, 0);
100 SET_ACTLR(base, ctx, 0);
101 SET_SCTLR(base, ctx, 0);
102 SET_FSRRESTORE(base, ctx, 0);
103 SET_TTBR0(base, ctx, 0);
104 SET_TTBR1(base, ctx, 0);
105 SET_TTBCR(base, ctx, 0);
106 SET_BFBCR(base, ctx, 0);
107 SET_PAR(base, ctx, 0);
108 SET_FAR(base, ctx, 0);
109 SET_CTX_TLBIALL(base, ctx, 0);
110 SET_TLBFLPTER(base, ctx, 0);
111 SET_TLBSLPTER(base, ctx, 0);
112 SET_TLBLKCR(base, ctx, 0);
113 SET_CONTEXTIDR(base, ctx, 0);
114 }
115}
116
117static void __flush_iotlb(void *cookie)
118{
119 struct msm_priv *priv = cookie;
120 struct msm_iommu_dev *iommu = NULL;
121 struct msm_iommu_ctx_dev *master;
122 int ret = 0;
123
124 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
125 ret = __enable_clocks(iommu);
126 if (ret)
127 goto fail;
128
129 list_for_each_entry(master, &iommu->ctx_list, list)
130 SET_CTX_TLBIALL(iommu->base, master->num, 0);
131
132 __disable_clocks(iommu);
133 }
134fail:
135 return;
136}
137
138static void __flush_iotlb_range(unsigned long iova, size_t size,
139 size_t granule, bool leaf, void *cookie)
140{
141 struct msm_priv *priv = cookie;
142 struct msm_iommu_dev *iommu = NULL;
143 struct msm_iommu_ctx_dev *master;
144 int ret = 0;
145 int temp_size;
146
147 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
148 ret = __enable_clocks(iommu);
149 if (ret)
150 goto fail;
151
152 list_for_each_entry(master, &iommu->ctx_list, list) {
153 temp_size = size;
154 do {
155 iova &= TLBIVA_VA;
156 iova |= GET_CONTEXTIDR_ASID(iommu->base,
157 master->num);
158 SET_TLBIVA(iommu->base, master->num, iova);
159 iova += granule;
160 } while (temp_size -= granule);
161 }
162
163 __disable_clocks(iommu);
164 }
165
166fail:
167 return;
168}
169
170static void __flush_iotlb_walk(unsigned long iova, size_t size,
171 size_t granule, void *cookie)
172{
173 __flush_iotlb_range(iova, size, granule, false, cookie);
174}
175
176static void __flush_iotlb_page(struct iommu_iotlb_gather *gather,
177 unsigned long iova, size_t granule, void *cookie)
178{
179 __flush_iotlb_range(iova, granule, granule, true, cookie);
180}
181
182static const struct iommu_flush_ops msm_iommu_flush_ops = {
183 .tlb_flush_all = __flush_iotlb,
184 .tlb_flush_walk = __flush_iotlb_walk,
185 .tlb_add_page = __flush_iotlb_page,
186};
187
188static int msm_iommu_alloc_ctx(unsigned long *map, int start, int end)
189{
190 int idx;
191
192 do {
193 idx = find_next_zero_bit(map, end, start);
194 if (idx == end)
195 return -ENOSPC;
196 } while (test_and_set_bit(idx, map));
197
198 return idx;
199}
200
201static void msm_iommu_free_ctx(unsigned long *map, int idx)
202{
203 clear_bit(idx, map);
204}
205
206static void config_mids(struct msm_iommu_dev *iommu,
207 struct msm_iommu_ctx_dev *master)
208{
209 int mid, ctx, i;
210
211 for (i = 0; i < master->num_mids; i++) {
212 mid = master->mids[i];
213 ctx = master->num;
214
215 SET_M2VCBR_N(iommu->base, mid, 0);
216 SET_CBACR_N(iommu->base, ctx, 0);
217
218 /* Set VMID = 0 */
219 SET_VMID(iommu->base, mid, 0);
220
221 /* Set the context number for that MID to this context */
222 SET_CBNDX(iommu->base, mid, ctx);
223
224 /* Set MID associated with this context bank to 0*/
225 SET_CBVMID(iommu->base, ctx, 0);
226
227 /* Set the ASID for TLB tagging for this context */
228 SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);
229
230 /* Set security bit override to be Non-secure */
231 SET_NSCFG(iommu->base, mid, 3);
232 }
233}
234
235static void __reset_context(void __iomem *base, int ctx)
236{
237 SET_BPRCOSH(base, ctx, 0);
238 SET_BPRCISH(base, ctx, 0);
239 SET_BPRCNSH(base, ctx, 0);
240 SET_BPSHCFG(base, ctx, 0);
241 SET_BPMTCFG(base, ctx, 0);
242 SET_ACTLR(base, ctx, 0);
243 SET_SCTLR(base, ctx, 0);
244 SET_FSRRESTORE(base, ctx, 0);
245 SET_TTBR0(base, ctx, 0);
246 SET_TTBR1(base, ctx, 0);
247 SET_TTBCR(base, ctx, 0);
248 SET_BFBCR(base, ctx, 0);
249 SET_PAR(base, ctx, 0);
250 SET_FAR(base, ctx, 0);
251 SET_CTX_TLBIALL(base, ctx, 0);
252 SET_TLBFLPTER(base, ctx, 0);
253 SET_TLBSLPTER(base, ctx, 0);
254 SET_TLBLKCR(base, ctx, 0);
255}
256
257static void __program_context(void __iomem *base, int ctx,
258 struct msm_priv *priv)
259{
260 __reset_context(base, ctx);
261
262 /* Turn on TEX Remap */
263 SET_TRE(base, ctx, 1);
264 SET_AFE(base, ctx, 1);
265
266 /* Set up HTW mode */
267 /* TLB miss configuration: perform HTW on miss */
268 SET_TLBMCFG(base, ctx, 0x3);
269
270 /* V2P configuration: HTW for access */
271 SET_V2PCFG(base, ctx, 0x3);
272
273 SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr);
274 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr);
275 SET_TTBR1(base, ctx, 0);
276
277 /* Set prrr and nmrr */
278 SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr);
279 SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr);
280
281 /* Invalidate the TLB for this context */
282 SET_CTX_TLBIALL(base, ctx, 0);
283
284 /* Set interrupt number to "secure" interrupt */
285 SET_IRPTNDX(base, ctx, 0);
286
287 /* Enable context fault interrupt */
288 SET_CFEIE(base, ctx, 1);
289
290 /* Stall access on a context fault and let the handler deal with it */
291 SET_CFCFG(base, ctx, 1);
292
293 /* Redirect all cacheable requests to L2 slave port. */
294 SET_RCISH(base, ctx, 1);
295 SET_RCOSH(base, ctx, 1);
296 SET_RCNSH(base, ctx, 1);
297
298 /* Turn on BFB prefetch */
299 SET_BFBDFE(base, ctx, 1);
300
301 /* Enable the MMU */
302 SET_M(base, ctx, 1);
303}
304
305static struct iommu_domain *msm_iommu_domain_alloc(unsigned type)
306{
307 struct msm_priv *priv;
308
309 if (type != IOMMU_DOMAIN_UNMANAGED)
310 return NULL;
311
312 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
313 if (!priv)
314 goto fail_nomem;
315
316 INIT_LIST_HEAD(&priv->list_attached);
317
318 priv->domain.geometry.aperture_start = 0;
319 priv->domain.geometry.aperture_end = (1ULL << 32) - 1;
320 priv->domain.geometry.force_aperture = true;
321
322 return &priv->domain;
323
324fail_nomem:
325 kfree(priv);
326 return NULL;
327}
328
329static void msm_iommu_domain_free(struct iommu_domain *domain)
330{
331 struct msm_priv *priv;
332 unsigned long flags;
333
334 spin_lock_irqsave(&msm_iommu_lock, flags);
335 priv = to_msm_priv(domain);
336 kfree(priv);
337 spin_unlock_irqrestore(&msm_iommu_lock, flags);
338}
339
340static int msm_iommu_domain_config(struct msm_priv *priv)
341{
342 spin_lock_init(&priv->pgtlock);
343
344 priv->cfg = (struct io_pgtable_cfg) {
345 .pgsize_bitmap = msm_iommu_ops.pgsize_bitmap,
346 .ias = 32,
347 .oas = 32,
348 .tlb = &msm_iommu_flush_ops,
349 .iommu_dev = priv->dev,
350 };
351
352 priv->iop = alloc_io_pgtable_ops(ARM_V7S, &priv->cfg, priv);
353 if (!priv->iop) {
354 dev_err(priv->dev, "Failed to allocate pgtable\n");
355 return -EINVAL;
356 }
357
358 msm_iommu_ops.pgsize_bitmap = priv->cfg.pgsize_bitmap;
359
360 return 0;
361}
362
363/* Must be called under msm_iommu_lock */
364static struct msm_iommu_dev *find_iommu_for_dev(struct device *dev)
365{
366 struct msm_iommu_dev *iommu, *ret = NULL;
367 struct msm_iommu_ctx_dev *master;
368
369 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
370 master = list_first_entry(&iommu->ctx_list,
371 struct msm_iommu_ctx_dev,
372 list);
373 if (master->of_node == dev->of_node) {
374 ret = iommu;
375 break;
376 }
377 }
378
379 return ret;
380}
381
382static struct iommu_device *msm_iommu_probe_device(struct device *dev)
383{
384 struct msm_iommu_dev *iommu;
385 unsigned long flags;
386
387 spin_lock_irqsave(&msm_iommu_lock, flags);
388 iommu = find_iommu_for_dev(dev);
389 spin_unlock_irqrestore(&msm_iommu_lock, flags);
390
391 if (!iommu)
392 return ERR_PTR(-ENODEV);
393
394 return &iommu->iommu;
395}
396
397static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
398{
399 int ret = 0;
400 unsigned long flags;
401 struct msm_iommu_dev *iommu;
402 struct msm_priv *priv = to_msm_priv(domain);
403 struct msm_iommu_ctx_dev *master;
404
405 priv->dev = dev;
406 msm_iommu_domain_config(priv);
407
408 spin_lock_irqsave(&msm_iommu_lock, flags);
409 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
410 master = list_first_entry(&iommu->ctx_list,
411 struct msm_iommu_ctx_dev,
412 list);
413 if (master->of_node == dev->of_node) {
414 ret = __enable_clocks(iommu);
415 if (ret)
416 goto fail;
417
418 list_for_each_entry(master, &iommu->ctx_list, list) {
419 if (master->num) {
420 dev_err(dev, "domain already attached");
421 ret = -EEXIST;
422 goto fail;
423 }
424 master->num =
425 msm_iommu_alloc_ctx(iommu->context_map,
426 0, iommu->ncb);
427 if (IS_ERR_VALUE(master->num)) {
428 ret = -ENODEV;
429 goto fail;
430 }
431 config_mids(iommu, master);
432 __program_context(iommu->base, master->num,
433 priv);
434 }
435 __disable_clocks(iommu);
436 list_add(&iommu->dom_node, &priv->list_attached);
437 }
438 }
439
440fail:
441 spin_unlock_irqrestore(&msm_iommu_lock, flags);
442
443 return ret;
444}
445
446static void msm_iommu_detach_dev(struct iommu_domain *domain,
447 struct device *dev)
448{
449 struct msm_priv *priv = to_msm_priv(domain);
450 unsigned long flags;
451 struct msm_iommu_dev *iommu;
452 struct msm_iommu_ctx_dev *master;
453 int ret;
454
455 free_io_pgtable_ops(priv->iop);
456
457 spin_lock_irqsave(&msm_iommu_lock, flags);
458 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
459 ret = __enable_clocks(iommu);
460 if (ret)
461 goto fail;
462
463 list_for_each_entry(master, &iommu->ctx_list, list) {
464 msm_iommu_free_ctx(iommu->context_map, master->num);
465 __reset_context(iommu->base, master->num);
466 }
467 __disable_clocks(iommu);
468 }
469fail:
470 spin_unlock_irqrestore(&msm_iommu_lock, flags);
471}
472
473static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova,
474 phys_addr_t pa, size_t pgsize, size_t pgcount,
475 int prot, gfp_t gfp, size_t *mapped)
476{
477 struct msm_priv *priv = to_msm_priv(domain);
478 unsigned long flags;
479 int ret;
480
481 spin_lock_irqsave(&priv->pgtlock, flags);
482 ret = priv->iop->map_pages(priv->iop, iova, pa, pgsize, pgcount, prot,
483 GFP_ATOMIC, mapped);
484 spin_unlock_irqrestore(&priv->pgtlock, flags);
485
486 return ret;
487}
488
489static void msm_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
490 size_t size)
491{
492 struct msm_priv *priv = to_msm_priv(domain);
493
494 __flush_iotlb_range(iova, size, SZ_4K, false, priv);
495}
496
497static size_t msm_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
498 size_t pgsize, size_t pgcount,
499 struct iommu_iotlb_gather *gather)
500{
501 struct msm_priv *priv = to_msm_priv(domain);
502 unsigned long flags;
503 size_t ret;
504
505 spin_lock_irqsave(&priv->pgtlock, flags);
506 ret = priv->iop->unmap_pages(priv->iop, iova, pgsize, pgcount, gather);
507 spin_unlock_irqrestore(&priv->pgtlock, flags);
508
509 return ret;
510}
511
512static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
513 dma_addr_t va)
514{
515 struct msm_priv *priv;
516 struct msm_iommu_dev *iommu;
517 struct msm_iommu_ctx_dev *master;
518 unsigned int par;
519 unsigned long flags;
520 phys_addr_t ret = 0;
521
522 spin_lock_irqsave(&msm_iommu_lock, flags);
523
524 priv = to_msm_priv(domain);
525 iommu = list_first_entry(&priv->list_attached,
526 struct msm_iommu_dev, dom_node);
527
528 if (list_empty(&iommu->ctx_list))
529 goto fail;
530
531 master = list_first_entry(&iommu->ctx_list,
532 struct msm_iommu_ctx_dev, list);
533 if (!master)
534 goto fail;
535
536 ret = __enable_clocks(iommu);
537 if (ret)
538 goto fail;
539
540 /* Invalidate context TLB */
541 SET_CTX_TLBIALL(iommu->base, master->num, 0);
542 SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);
543
544 par = GET_PAR(iommu->base, master->num);
545
546 /* We are dealing with a supersection */
547 if (GET_NOFAULT_SS(iommu->base, master->num))
548 ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
549 else /* Upper 20 bits from PAR, lower 12 from VA */
550 ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
551
552 if (GET_FAULT(iommu->base, master->num))
553 ret = 0;
554
555 __disable_clocks(iommu);
556fail:
557 spin_unlock_irqrestore(&msm_iommu_lock, flags);
558 return ret;
559}
560
561static void print_ctx_regs(void __iomem *base, int ctx)
562{
563 unsigned int fsr = GET_FSR(base, ctx);
564 pr_err("FAR = %08x PAR = %08x\n",
565 GET_FAR(base, ctx), GET_PAR(base, ctx));
566 pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
567 (fsr & 0x02) ? "TF " : "",
568 (fsr & 0x04) ? "AFF " : "",
569 (fsr & 0x08) ? "APF " : "",
570 (fsr & 0x10) ? "TLBMF " : "",
571 (fsr & 0x20) ? "HTWDEEF " : "",
572 (fsr & 0x40) ? "HTWSEEF " : "",
573 (fsr & 0x80) ? "MHF " : "",
574 (fsr & 0x10000) ? "SL " : "",
575 (fsr & 0x40000000) ? "SS " : "",
576 (fsr & 0x80000000) ? "MULTI " : "");
577
578 pr_err("FSYNR0 = %08x FSYNR1 = %08x\n",
579 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
580 pr_err("TTBR0 = %08x TTBR1 = %08x\n",
581 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
582 pr_err("SCTLR = %08x ACTLR = %08x\n",
583 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
584}
585
586static int insert_iommu_master(struct device *dev,
587 struct msm_iommu_dev **iommu,
588 struct of_phandle_args *spec)
589{
590 struct msm_iommu_ctx_dev *master = dev_iommu_priv_get(dev);
591 int sid;
592
593 if (list_empty(&(*iommu)->ctx_list)) {
594 master = kzalloc(sizeof(*master), GFP_ATOMIC);
595 if (!master) {
596 dev_err(dev, "Failed to allocate iommu_master\n");
597 return -ENOMEM;
598 }
599 master->of_node = dev->of_node;
600 list_add(&master->list, &(*iommu)->ctx_list);
601 dev_iommu_priv_set(dev, master);
602 }
603
604 for (sid = 0; sid < master->num_mids; sid++)
605 if (master->mids[sid] == spec->args[0]) {
606 dev_warn(dev, "Stream ID 0x%x repeated; ignoring\n",
607 sid);
608 return 0;
609 }
610
611 master->mids[master->num_mids++] = spec->args[0];
612 return 0;
613}
614
615static int qcom_iommu_of_xlate(struct device *dev,
616 struct of_phandle_args *spec)
617{
618 struct msm_iommu_dev *iommu = NULL, *iter;
619 unsigned long flags;
620 int ret = 0;
621
622 spin_lock_irqsave(&msm_iommu_lock, flags);
623 list_for_each_entry(iter, &qcom_iommu_devices, dev_node) {
624 if (iter->dev->of_node == spec->np) {
625 iommu = iter;
626 break;
627 }
628 }
629
630 if (!iommu) {
631 ret = -ENODEV;
632 goto fail;
633 }
634
635 ret = insert_iommu_master(dev, &iommu, spec);
636fail:
637 spin_unlock_irqrestore(&msm_iommu_lock, flags);
638
639 return ret;
640}
641
642irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
643{
644 struct msm_iommu_dev *iommu = dev_id;
645 unsigned int fsr;
646 int i, ret;
647
648 spin_lock(&msm_iommu_lock);
649
650 if (!iommu) {
651 pr_err("Invalid device ID in context interrupt handler\n");
652 goto fail;
653 }
654
655 pr_err("Unexpected IOMMU page fault!\n");
656 pr_err("base = %08x\n", (unsigned int)iommu->base);
657
658 ret = __enable_clocks(iommu);
659 if (ret)
660 goto fail;
661
662 for (i = 0; i < iommu->ncb; i++) {
663 fsr = GET_FSR(iommu->base, i);
664 if (fsr) {
665 pr_err("Fault occurred in context %d.\n", i);
666 pr_err("Interesting registers:\n");
667 print_ctx_regs(iommu->base, i);
668 SET_FSR(iommu->base, i, 0x4000000F);
669 }
670 }
671 __disable_clocks(iommu);
672fail:
673 spin_unlock(&msm_iommu_lock);
674 return 0;
675}
676
677static struct iommu_ops msm_iommu_ops = {
678 .domain_alloc = msm_iommu_domain_alloc,
679 .probe_device = msm_iommu_probe_device,
680 .device_group = generic_device_group,
681 .pgsize_bitmap = MSM_IOMMU_PGSIZES,
682 .of_xlate = qcom_iommu_of_xlate,
683 .default_domain_ops = &(const struct iommu_domain_ops) {
684 .attach_dev = msm_iommu_attach_dev,
685 .detach_dev = msm_iommu_detach_dev,
686 .map_pages = msm_iommu_map,
687 .unmap_pages = msm_iommu_unmap,
688 /*
689 * Nothing is needed here, the barrier to guarantee
690 * completion of the tlb sync operation is implicitly
691 * taken care when the iommu client does a writel before
692 * kick starting the other master.
693 */
694 .iotlb_sync = NULL,
695 .iotlb_sync_map = msm_iommu_sync_map,
696 .iova_to_phys = msm_iommu_iova_to_phys,
697 .free = msm_iommu_domain_free,
698 }
699};
700
701static int msm_iommu_probe(struct platform_device *pdev)
702{
703 struct resource *r;
704 resource_size_t ioaddr;
705 struct msm_iommu_dev *iommu;
706 int ret, par, val;
707
708 iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);
709 if (!iommu)
710 return -ENODEV;
711
712 iommu->dev = &pdev->dev;
713 INIT_LIST_HEAD(&iommu->ctx_list);
714
715 iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk");
716 if (IS_ERR(iommu->pclk))
717 return dev_err_probe(iommu->dev, PTR_ERR(iommu->pclk),
718 "could not get smmu_pclk\n");
719
720 ret = clk_prepare(iommu->pclk);
721 if (ret)
722 return dev_err_probe(iommu->dev, ret,
723 "could not prepare smmu_pclk\n");
724
725 iommu->clk = devm_clk_get(iommu->dev, "iommu_clk");
726 if (IS_ERR(iommu->clk)) {
727 clk_unprepare(iommu->pclk);
728 return dev_err_probe(iommu->dev, PTR_ERR(iommu->clk),
729 "could not get iommu_clk\n");
730 }
731
732 ret = clk_prepare(iommu->clk);
733 if (ret) {
734 clk_unprepare(iommu->pclk);
735 return dev_err_probe(iommu->dev, ret, "could not prepare iommu_clk\n");
736 }
737
738 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
739 iommu->base = devm_ioremap_resource(iommu->dev, r);
740 if (IS_ERR(iommu->base)) {
741 ret = dev_err_probe(iommu->dev, PTR_ERR(iommu->base), "could not get iommu base\n");
742 goto fail;
743 }
744 ioaddr = r->start;
745
746 iommu->irq = platform_get_irq(pdev, 0);
747 if (iommu->irq < 0) {
748 ret = -ENODEV;
749 goto fail;
750 }
751
752 ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val);
753 if (ret) {
754 dev_err(iommu->dev, "could not get ncb\n");
755 goto fail;
756 }
757 iommu->ncb = val;
758
759 msm_iommu_reset(iommu->base, iommu->ncb);
760 SET_M(iommu->base, 0, 1);
761 SET_PAR(iommu->base, 0, 0);
762 SET_V2PCFG(iommu->base, 0, 1);
763 SET_V2PPR(iommu->base, 0, 0);
764 par = GET_PAR(iommu->base, 0);
765 SET_V2PCFG(iommu->base, 0, 0);
766 SET_M(iommu->base, 0, 0);
767
768 if (!par) {
769 pr_err("Invalid PAR value detected\n");
770 ret = -ENODEV;
771 goto fail;
772 }
773
774 ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL,
775 msm_iommu_fault_handler,
776 IRQF_ONESHOT | IRQF_SHARED,
777 "msm_iommu_secure_irpt_handler",
778 iommu);
779 if (ret) {
780 pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret);
781 goto fail;
782 }
783
784 list_add(&iommu->dev_node, &qcom_iommu_devices);
785
786 ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL,
787 "msm-smmu.%pa", &ioaddr);
788 if (ret) {
789 pr_err("Could not add msm-smmu at %pa to sysfs\n", &ioaddr);
790 goto fail;
791 }
792
793 ret = iommu_device_register(&iommu->iommu, &msm_iommu_ops, &pdev->dev);
794 if (ret) {
795 pr_err("Could not register msm-smmu at %pa\n", &ioaddr);
796 goto fail;
797 }
798
799 pr_info("device mapped at %p, irq %d with %d ctx banks\n",
800 iommu->base, iommu->irq, iommu->ncb);
801
802 return ret;
803fail:
804 clk_unprepare(iommu->clk);
805 clk_unprepare(iommu->pclk);
806 return ret;
807}
808
809static const struct of_device_id msm_iommu_dt_match[] = {
810 { .compatible = "qcom,apq8064-iommu" },
811 {}
812};
813
814static int msm_iommu_remove(struct platform_device *pdev)
815{
816 struct msm_iommu_dev *iommu = platform_get_drvdata(pdev);
817
818 clk_unprepare(iommu->clk);
819 clk_unprepare(iommu->pclk);
820 return 0;
821}
822
823static struct platform_driver msm_iommu_driver = {
824 .driver = {
825 .name = "msm_iommu",
826 .of_match_table = msm_iommu_dt_match,
827 },
828 .probe = msm_iommu_probe,
829 .remove = msm_iommu_remove,
830};
831builtin_platform_driver(msm_iommu_driver);
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/errno.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25#include <linux/list.h>
26#include <linux/spinlock.h>
27#include <linux/slab.h>
28#include <linux/iommu.h>
29#include <linux/clk.h>
30#include <linux/err.h>
31#include <linux/of_iommu.h>
32
33#include <asm/cacheflush.h>
34#include <asm/sizes.h>
35
36#include "msm_iommu_hw-8xxx.h"
37#include "msm_iommu.h"
38#include "io-pgtable.h"
39
40#define MRC(reg, processor, op1, crn, crm, op2) \
41__asm__ __volatile__ ( \
42" mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \
43: "=r" (reg))
44
45/* bitmap of the page sizes currently supported */
46#define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
47
48DEFINE_SPINLOCK(msm_iommu_lock);
49static LIST_HEAD(qcom_iommu_devices);
50static struct iommu_ops msm_iommu_ops;
51
52struct msm_priv {
53 struct list_head list_attached;
54 struct iommu_domain domain;
55 struct io_pgtable_cfg cfg;
56 struct io_pgtable_ops *iop;
57 struct device *dev;
58 spinlock_t pgtlock; /* pagetable lock */
59};
60
61static struct msm_priv *to_msm_priv(struct iommu_domain *dom)
62{
63 return container_of(dom, struct msm_priv, domain);
64}
65
66static int __enable_clocks(struct msm_iommu_dev *iommu)
67{
68 int ret;
69
70 ret = clk_enable(iommu->pclk);
71 if (ret)
72 goto fail;
73
74 if (iommu->clk) {
75 ret = clk_enable(iommu->clk);
76 if (ret)
77 clk_disable(iommu->pclk);
78 }
79fail:
80 return ret;
81}
82
83static void __disable_clocks(struct msm_iommu_dev *iommu)
84{
85 if (iommu->clk)
86 clk_disable(iommu->clk);
87 clk_disable(iommu->pclk);
88}
89
90static void msm_iommu_reset(void __iomem *base, int ncb)
91{
92 int ctx;
93
94 SET_RPUE(base, 0);
95 SET_RPUEIE(base, 0);
96 SET_ESRRESTORE(base, 0);
97 SET_TBE(base, 0);
98 SET_CR(base, 0);
99 SET_SPDMBE(base, 0);
100 SET_TESTBUSCR(base, 0);
101 SET_TLBRSW(base, 0);
102 SET_GLOBAL_TLBIALL(base, 0);
103 SET_RPU_ACR(base, 0);
104 SET_TLBLKCRWE(base, 1);
105
106 for (ctx = 0; ctx < ncb; ctx++) {
107 SET_BPRCOSH(base, ctx, 0);
108 SET_BPRCISH(base, ctx, 0);
109 SET_BPRCNSH(base, ctx, 0);
110 SET_BPSHCFG(base, ctx, 0);
111 SET_BPMTCFG(base, ctx, 0);
112 SET_ACTLR(base, ctx, 0);
113 SET_SCTLR(base, ctx, 0);
114 SET_FSRRESTORE(base, ctx, 0);
115 SET_TTBR0(base, ctx, 0);
116 SET_TTBR1(base, ctx, 0);
117 SET_TTBCR(base, ctx, 0);
118 SET_BFBCR(base, ctx, 0);
119 SET_PAR(base, ctx, 0);
120 SET_FAR(base, ctx, 0);
121 SET_CTX_TLBIALL(base, ctx, 0);
122 SET_TLBFLPTER(base, ctx, 0);
123 SET_TLBSLPTER(base, ctx, 0);
124 SET_TLBLKCR(base, ctx, 0);
125 SET_CONTEXTIDR(base, ctx, 0);
126 }
127}
128
129static void __flush_iotlb(void *cookie)
130{
131 struct msm_priv *priv = cookie;
132 struct msm_iommu_dev *iommu = NULL;
133 struct msm_iommu_ctx_dev *master;
134 int ret = 0;
135
136 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
137 ret = __enable_clocks(iommu);
138 if (ret)
139 goto fail;
140
141 list_for_each_entry(master, &iommu->ctx_list, list)
142 SET_CTX_TLBIALL(iommu->base, master->num, 0);
143
144 __disable_clocks(iommu);
145 }
146fail:
147 return;
148}
149
150static void __flush_iotlb_range(unsigned long iova, size_t size,
151 size_t granule, bool leaf, void *cookie)
152{
153 struct msm_priv *priv = cookie;
154 struct msm_iommu_dev *iommu = NULL;
155 struct msm_iommu_ctx_dev *master;
156 int ret = 0;
157 int temp_size;
158
159 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
160 ret = __enable_clocks(iommu);
161 if (ret)
162 goto fail;
163
164 list_for_each_entry(master, &iommu->ctx_list, list) {
165 temp_size = size;
166 do {
167 iova &= TLBIVA_VA;
168 iova |= GET_CONTEXTIDR_ASID(iommu->base,
169 master->num);
170 SET_TLBIVA(iommu->base, master->num, iova);
171 iova += granule;
172 } while (temp_size -= granule);
173 }
174
175 __disable_clocks(iommu);
176 }
177
178fail:
179 return;
180}
181
182static void __flush_iotlb_sync(void *cookie)
183{
184 /*
185 * Nothing is needed here, the barrier to guarantee
186 * completion of the tlb sync operation is implicitly
187 * taken care when the iommu client does a writel before
188 * kick starting the other master.
189 */
190}
191
192static const struct iommu_gather_ops msm_iommu_gather_ops = {
193 .tlb_flush_all = __flush_iotlb,
194 .tlb_add_flush = __flush_iotlb_range,
195 .tlb_sync = __flush_iotlb_sync,
196};
197
198static int msm_iommu_alloc_ctx(unsigned long *map, int start, int end)
199{
200 int idx;
201
202 do {
203 idx = find_next_zero_bit(map, end, start);
204 if (idx == end)
205 return -ENOSPC;
206 } while (test_and_set_bit(idx, map));
207
208 return idx;
209}
210
211static void msm_iommu_free_ctx(unsigned long *map, int idx)
212{
213 clear_bit(idx, map);
214}
215
216static void config_mids(struct msm_iommu_dev *iommu,
217 struct msm_iommu_ctx_dev *master)
218{
219 int mid, ctx, i;
220
221 for (i = 0; i < master->num_mids; i++) {
222 mid = master->mids[i];
223 ctx = master->num;
224
225 SET_M2VCBR_N(iommu->base, mid, 0);
226 SET_CBACR_N(iommu->base, ctx, 0);
227
228 /* Set VMID = 0 */
229 SET_VMID(iommu->base, mid, 0);
230
231 /* Set the context number for that MID to this context */
232 SET_CBNDX(iommu->base, mid, ctx);
233
234 /* Set MID associated with this context bank to 0*/
235 SET_CBVMID(iommu->base, ctx, 0);
236
237 /* Set the ASID for TLB tagging for this context */
238 SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);
239
240 /* Set security bit override to be Non-secure */
241 SET_NSCFG(iommu->base, mid, 3);
242 }
243}
244
245static void __reset_context(void __iomem *base, int ctx)
246{
247 SET_BPRCOSH(base, ctx, 0);
248 SET_BPRCISH(base, ctx, 0);
249 SET_BPRCNSH(base, ctx, 0);
250 SET_BPSHCFG(base, ctx, 0);
251 SET_BPMTCFG(base, ctx, 0);
252 SET_ACTLR(base, ctx, 0);
253 SET_SCTLR(base, ctx, 0);
254 SET_FSRRESTORE(base, ctx, 0);
255 SET_TTBR0(base, ctx, 0);
256 SET_TTBR1(base, ctx, 0);
257 SET_TTBCR(base, ctx, 0);
258 SET_BFBCR(base, ctx, 0);
259 SET_PAR(base, ctx, 0);
260 SET_FAR(base, ctx, 0);
261 SET_CTX_TLBIALL(base, ctx, 0);
262 SET_TLBFLPTER(base, ctx, 0);
263 SET_TLBSLPTER(base, ctx, 0);
264 SET_TLBLKCR(base, ctx, 0);
265}
266
267static void __program_context(void __iomem *base, int ctx,
268 struct msm_priv *priv)
269{
270 __reset_context(base, ctx);
271
272 /* Turn on TEX Remap */
273 SET_TRE(base, ctx, 1);
274 SET_AFE(base, ctx, 1);
275
276 /* Set up HTW mode */
277 /* TLB miss configuration: perform HTW on miss */
278 SET_TLBMCFG(base, ctx, 0x3);
279
280 /* V2P configuration: HTW for access */
281 SET_V2PCFG(base, ctx, 0x3);
282
283 SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr);
284 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[0]);
285 SET_TTBR1(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[1]);
286
287 /* Set prrr and nmrr */
288 SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr);
289 SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr);
290
291 /* Invalidate the TLB for this context */
292 SET_CTX_TLBIALL(base, ctx, 0);
293
294 /* Set interrupt number to "secure" interrupt */
295 SET_IRPTNDX(base, ctx, 0);
296
297 /* Enable context fault interrupt */
298 SET_CFEIE(base, ctx, 1);
299
300 /* Stall access on a context fault and let the handler deal with it */
301 SET_CFCFG(base, ctx, 1);
302
303 /* Redirect all cacheable requests to L2 slave port. */
304 SET_RCISH(base, ctx, 1);
305 SET_RCOSH(base, ctx, 1);
306 SET_RCNSH(base, ctx, 1);
307
308 /* Turn on BFB prefetch */
309 SET_BFBDFE(base, ctx, 1);
310
311 /* Enable the MMU */
312 SET_M(base, ctx, 1);
313}
314
315static struct iommu_domain *msm_iommu_domain_alloc(unsigned type)
316{
317 struct msm_priv *priv;
318
319 if (type != IOMMU_DOMAIN_UNMANAGED)
320 return NULL;
321
322 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
323 if (!priv)
324 goto fail_nomem;
325
326 INIT_LIST_HEAD(&priv->list_attached);
327
328 priv->domain.geometry.aperture_start = 0;
329 priv->domain.geometry.aperture_end = (1ULL << 32) - 1;
330 priv->domain.geometry.force_aperture = true;
331
332 return &priv->domain;
333
334fail_nomem:
335 kfree(priv);
336 return NULL;
337}
338
339static void msm_iommu_domain_free(struct iommu_domain *domain)
340{
341 struct msm_priv *priv;
342 unsigned long flags;
343
344 spin_lock_irqsave(&msm_iommu_lock, flags);
345 priv = to_msm_priv(domain);
346 kfree(priv);
347 spin_unlock_irqrestore(&msm_iommu_lock, flags);
348}
349
350static int msm_iommu_domain_config(struct msm_priv *priv)
351{
352 spin_lock_init(&priv->pgtlock);
353
354 priv->cfg = (struct io_pgtable_cfg) {
355 .quirks = IO_PGTABLE_QUIRK_TLBI_ON_MAP,
356 .pgsize_bitmap = msm_iommu_ops.pgsize_bitmap,
357 .ias = 32,
358 .oas = 32,
359 .tlb = &msm_iommu_gather_ops,
360 .iommu_dev = priv->dev,
361 };
362
363 priv->iop = alloc_io_pgtable_ops(ARM_V7S, &priv->cfg, priv);
364 if (!priv->iop) {
365 dev_err(priv->dev, "Failed to allocate pgtable\n");
366 return -EINVAL;
367 }
368
369 msm_iommu_ops.pgsize_bitmap = priv->cfg.pgsize_bitmap;
370
371 return 0;
372}
373
374static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
375{
376 int ret = 0;
377 unsigned long flags;
378 struct msm_iommu_dev *iommu;
379 struct msm_priv *priv = to_msm_priv(domain);
380 struct msm_iommu_ctx_dev *master;
381
382 priv->dev = dev;
383 msm_iommu_domain_config(priv);
384
385 spin_lock_irqsave(&msm_iommu_lock, flags);
386 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
387 master = list_first_entry(&iommu->ctx_list,
388 struct msm_iommu_ctx_dev,
389 list);
390 if (master->of_node == dev->of_node) {
391 ret = __enable_clocks(iommu);
392 if (ret)
393 goto fail;
394
395 list_for_each_entry(master, &iommu->ctx_list, list) {
396 if (master->num) {
397 dev_err(dev, "domain already attached");
398 ret = -EEXIST;
399 goto fail;
400 }
401 master->num =
402 msm_iommu_alloc_ctx(iommu->context_map,
403 0, iommu->ncb);
404 if (IS_ERR_VALUE(master->num)) {
405 ret = -ENODEV;
406 goto fail;
407 }
408 config_mids(iommu, master);
409 __program_context(iommu->base, master->num,
410 priv);
411 }
412 __disable_clocks(iommu);
413 list_add(&iommu->dom_node, &priv->list_attached);
414 }
415 }
416
417fail:
418 spin_unlock_irqrestore(&msm_iommu_lock, flags);
419
420 return ret;
421}
422
423static void msm_iommu_detach_dev(struct iommu_domain *domain,
424 struct device *dev)
425{
426 struct msm_priv *priv = to_msm_priv(domain);
427 unsigned long flags;
428 struct msm_iommu_dev *iommu;
429 struct msm_iommu_ctx_dev *master;
430 int ret;
431
432 free_io_pgtable_ops(priv->iop);
433
434 spin_lock_irqsave(&msm_iommu_lock, flags);
435 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
436 ret = __enable_clocks(iommu);
437 if (ret)
438 goto fail;
439
440 list_for_each_entry(master, &iommu->ctx_list, list) {
441 msm_iommu_free_ctx(iommu->context_map, master->num);
442 __reset_context(iommu->base, master->num);
443 }
444 __disable_clocks(iommu);
445 }
446fail:
447 spin_unlock_irqrestore(&msm_iommu_lock, flags);
448}
449
450static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova,
451 phys_addr_t pa, size_t len, int prot)
452{
453 struct msm_priv *priv = to_msm_priv(domain);
454 unsigned long flags;
455 int ret;
456
457 spin_lock_irqsave(&priv->pgtlock, flags);
458 ret = priv->iop->map(priv->iop, iova, pa, len, prot);
459 spin_unlock_irqrestore(&priv->pgtlock, flags);
460
461 return ret;
462}
463
464static size_t msm_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
465 size_t len)
466{
467 struct msm_priv *priv = to_msm_priv(domain);
468 unsigned long flags;
469
470 spin_lock_irqsave(&priv->pgtlock, flags);
471 len = priv->iop->unmap(priv->iop, iova, len);
472 spin_unlock_irqrestore(&priv->pgtlock, flags);
473
474 return len;
475}
476
477static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
478 dma_addr_t va)
479{
480 struct msm_priv *priv;
481 struct msm_iommu_dev *iommu;
482 struct msm_iommu_ctx_dev *master;
483 unsigned int par;
484 unsigned long flags;
485 phys_addr_t ret = 0;
486
487 spin_lock_irqsave(&msm_iommu_lock, flags);
488
489 priv = to_msm_priv(domain);
490 iommu = list_first_entry(&priv->list_attached,
491 struct msm_iommu_dev, dom_node);
492
493 if (list_empty(&iommu->ctx_list))
494 goto fail;
495
496 master = list_first_entry(&iommu->ctx_list,
497 struct msm_iommu_ctx_dev, list);
498 if (!master)
499 goto fail;
500
501 ret = __enable_clocks(iommu);
502 if (ret)
503 goto fail;
504
505 /* Invalidate context TLB */
506 SET_CTX_TLBIALL(iommu->base, master->num, 0);
507 SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);
508
509 par = GET_PAR(iommu->base, master->num);
510
511 /* We are dealing with a supersection */
512 if (GET_NOFAULT_SS(iommu->base, master->num))
513 ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
514 else /* Upper 20 bits from PAR, lower 12 from VA */
515 ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
516
517 if (GET_FAULT(iommu->base, master->num))
518 ret = 0;
519
520 __disable_clocks(iommu);
521fail:
522 spin_unlock_irqrestore(&msm_iommu_lock, flags);
523 return ret;
524}
525
526static bool msm_iommu_capable(enum iommu_cap cap)
527{
528 return false;
529}
530
531static void print_ctx_regs(void __iomem *base, int ctx)
532{
533 unsigned int fsr = GET_FSR(base, ctx);
534 pr_err("FAR = %08x PAR = %08x\n",
535 GET_FAR(base, ctx), GET_PAR(base, ctx));
536 pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
537 (fsr & 0x02) ? "TF " : "",
538 (fsr & 0x04) ? "AFF " : "",
539 (fsr & 0x08) ? "APF " : "",
540 (fsr & 0x10) ? "TLBMF " : "",
541 (fsr & 0x20) ? "HTWDEEF " : "",
542 (fsr & 0x40) ? "HTWSEEF " : "",
543 (fsr & 0x80) ? "MHF " : "",
544 (fsr & 0x10000) ? "SL " : "",
545 (fsr & 0x40000000) ? "SS " : "",
546 (fsr & 0x80000000) ? "MULTI " : "");
547
548 pr_err("FSYNR0 = %08x FSYNR1 = %08x\n",
549 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
550 pr_err("TTBR0 = %08x TTBR1 = %08x\n",
551 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
552 pr_err("SCTLR = %08x ACTLR = %08x\n",
553 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
554}
555
556static void insert_iommu_master(struct device *dev,
557 struct msm_iommu_dev **iommu,
558 struct of_phandle_args *spec)
559{
560 struct msm_iommu_ctx_dev *master = dev->archdata.iommu;
561 int sid;
562
563 if (list_empty(&(*iommu)->ctx_list)) {
564 master = kzalloc(sizeof(*master), GFP_ATOMIC);
565 master->of_node = dev->of_node;
566 list_add(&master->list, &(*iommu)->ctx_list);
567 dev->archdata.iommu = master;
568 }
569
570 for (sid = 0; sid < master->num_mids; sid++)
571 if (master->mids[sid] == spec->args[0]) {
572 dev_warn(dev, "Stream ID 0x%hx repeated; ignoring\n",
573 sid);
574 return;
575 }
576
577 master->mids[master->num_mids++] = spec->args[0];
578}
579
580static int qcom_iommu_of_xlate(struct device *dev,
581 struct of_phandle_args *spec)
582{
583 struct msm_iommu_dev *iommu;
584 unsigned long flags;
585 int ret = 0;
586
587 spin_lock_irqsave(&msm_iommu_lock, flags);
588 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node)
589 if (iommu->dev->of_node == spec->np)
590 break;
591
592 if (!iommu || iommu->dev->of_node != spec->np) {
593 ret = -ENODEV;
594 goto fail;
595 }
596
597 insert_iommu_master(dev, &iommu, spec);
598fail:
599 spin_unlock_irqrestore(&msm_iommu_lock, flags);
600
601 return ret;
602}
603
604irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
605{
606 struct msm_iommu_dev *iommu = dev_id;
607 unsigned int fsr;
608 int i, ret;
609
610 spin_lock(&msm_iommu_lock);
611
612 if (!iommu) {
613 pr_err("Invalid device ID in context interrupt handler\n");
614 goto fail;
615 }
616
617 pr_err("Unexpected IOMMU page fault!\n");
618 pr_err("base = %08x\n", (unsigned int)iommu->base);
619
620 ret = __enable_clocks(iommu);
621 if (ret)
622 goto fail;
623
624 for (i = 0; i < iommu->ncb; i++) {
625 fsr = GET_FSR(iommu->base, i);
626 if (fsr) {
627 pr_err("Fault occurred in context %d.\n", i);
628 pr_err("Interesting registers:\n");
629 print_ctx_regs(iommu->base, i);
630 SET_FSR(iommu->base, i, 0x4000000F);
631 }
632 }
633 __disable_clocks(iommu);
634fail:
635 spin_unlock(&msm_iommu_lock);
636 return 0;
637}
638
639static struct iommu_ops msm_iommu_ops = {
640 .capable = msm_iommu_capable,
641 .domain_alloc = msm_iommu_domain_alloc,
642 .domain_free = msm_iommu_domain_free,
643 .attach_dev = msm_iommu_attach_dev,
644 .detach_dev = msm_iommu_detach_dev,
645 .map = msm_iommu_map,
646 .unmap = msm_iommu_unmap,
647 .map_sg = default_iommu_map_sg,
648 .iova_to_phys = msm_iommu_iova_to_phys,
649 .pgsize_bitmap = MSM_IOMMU_PGSIZES,
650 .of_xlate = qcom_iommu_of_xlate,
651};
652
653static int msm_iommu_probe(struct platform_device *pdev)
654{
655 struct resource *r;
656 struct msm_iommu_dev *iommu;
657 int ret, par, val;
658
659 iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);
660 if (!iommu)
661 return -ENODEV;
662
663 iommu->dev = &pdev->dev;
664 INIT_LIST_HEAD(&iommu->ctx_list);
665
666 iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk");
667 if (IS_ERR(iommu->pclk)) {
668 dev_err(iommu->dev, "could not get smmu_pclk\n");
669 return PTR_ERR(iommu->pclk);
670 }
671
672 ret = clk_prepare(iommu->pclk);
673 if (ret) {
674 dev_err(iommu->dev, "could not prepare smmu_pclk\n");
675 return ret;
676 }
677
678 iommu->clk = devm_clk_get(iommu->dev, "iommu_clk");
679 if (IS_ERR(iommu->clk)) {
680 dev_err(iommu->dev, "could not get iommu_clk\n");
681 clk_unprepare(iommu->pclk);
682 return PTR_ERR(iommu->clk);
683 }
684
685 ret = clk_prepare(iommu->clk);
686 if (ret) {
687 dev_err(iommu->dev, "could not prepare iommu_clk\n");
688 clk_unprepare(iommu->pclk);
689 return ret;
690 }
691
692 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
693 iommu->base = devm_ioremap_resource(iommu->dev, r);
694 if (IS_ERR(iommu->base)) {
695 dev_err(iommu->dev, "could not get iommu base\n");
696 ret = PTR_ERR(iommu->base);
697 goto fail;
698 }
699
700 iommu->irq = platform_get_irq(pdev, 0);
701 if (iommu->irq < 0) {
702 dev_err(iommu->dev, "could not get iommu irq\n");
703 ret = -ENODEV;
704 goto fail;
705 }
706
707 ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val);
708 if (ret) {
709 dev_err(iommu->dev, "could not get ncb\n");
710 goto fail;
711 }
712 iommu->ncb = val;
713
714 msm_iommu_reset(iommu->base, iommu->ncb);
715 SET_M(iommu->base, 0, 1);
716 SET_PAR(iommu->base, 0, 0);
717 SET_V2PCFG(iommu->base, 0, 1);
718 SET_V2PPR(iommu->base, 0, 0);
719 par = GET_PAR(iommu->base, 0);
720 SET_V2PCFG(iommu->base, 0, 0);
721 SET_M(iommu->base, 0, 0);
722
723 if (!par) {
724 pr_err("Invalid PAR value detected\n");
725 ret = -ENODEV;
726 goto fail;
727 }
728
729 ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL,
730 msm_iommu_fault_handler,
731 IRQF_ONESHOT | IRQF_SHARED,
732 "msm_iommu_secure_irpt_handler",
733 iommu);
734 if (ret) {
735 pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret);
736 goto fail;
737 }
738
739 list_add(&iommu->dev_node, &qcom_iommu_devices);
740 of_iommu_set_ops(pdev->dev.of_node, &msm_iommu_ops);
741
742 pr_info("device mapped at %p, irq %d with %d ctx banks\n",
743 iommu->base, iommu->irq, iommu->ncb);
744
745 return ret;
746fail:
747 clk_unprepare(iommu->clk);
748 clk_unprepare(iommu->pclk);
749 return ret;
750}
751
752static const struct of_device_id msm_iommu_dt_match[] = {
753 { .compatible = "qcom,apq8064-iommu" },
754 {}
755};
756
757static int msm_iommu_remove(struct platform_device *pdev)
758{
759 struct msm_iommu_dev *iommu = platform_get_drvdata(pdev);
760
761 clk_unprepare(iommu->clk);
762 clk_unprepare(iommu->pclk);
763 return 0;
764}
765
766static struct platform_driver msm_iommu_driver = {
767 .driver = {
768 .name = "msm_iommu",
769 .of_match_table = msm_iommu_dt_match,
770 },
771 .probe = msm_iommu_probe,
772 .remove = msm_iommu_remove,
773};
774
775static int __init msm_iommu_driver_init(void)
776{
777 int ret;
778
779 ret = platform_driver_register(&msm_iommu_driver);
780 if (ret != 0)
781 pr_err("Failed to register IOMMU driver\n");
782
783 return ret;
784}
785
786static void __exit msm_iommu_driver_exit(void)
787{
788 platform_driver_unregister(&msm_iommu_driver);
789}
790
791subsys_initcall(msm_iommu_driver_init);
792module_exit(msm_iommu_driver_exit);
793
794static int __init msm_iommu_init(void)
795{
796 bus_set_iommu(&platform_bus_type, &msm_iommu_ops);
797 return 0;
798}
799
800static int __init msm_iommu_of_setup(struct device_node *np)
801{
802 msm_iommu_init();
803 return 0;
804}
805
806IOMMU_OF_DECLARE(msm_iommu_of, "qcom,apq8064-iommu", msm_iommu_of_setup);
807
808MODULE_LICENSE("GPL v2");
809MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");