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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 */
5
6#include <linux/clk.h>
7#include <linux/i2c.h>
8#include <linux/interrupt.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12
13#define UNIPHIER_I2C_DTRM 0x00 /* TX register */
14#define UNIPHIER_I2C_DTRM_IRQEN BIT(11) /* enable interrupt */
15#define UNIPHIER_I2C_DTRM_STA BIT(10) /* start condition */
16#define UNIPHIER_I2C_DTRM_STO BIT(9) /* stop condition */
17#define UNIPHIER_I2C_DTRM_NACK BIT(8) /* do not return ACK */
18#define UNIPHIER_I2C_DTRM_RD BIT(0) /* read transaction */
19#define UNIPHIER_I2C_DREC 0x04 /* RX register */
20#define UNIPHIER_I2C_DREC_MST BIT(14) /* 1 = master, 0 = slave */
21#define UNIPHIER_I2C_DREC_TX BIT(13) /* 1 = transmit, 0 = receive */
22#define UNIPHIER_I2C_DREC_STS BIT(12) /* stop condition detected */
23#define UNIPHIER_I2C_DREC_LRB BIT(11) /* no ACK */
24#define UNIPHIER_I2C_DREC_LAB BIT(9) /* arbitration lost */
25#define UNIPHIER_I2C_DREC_BBN BIT(8) /* bus not busy */
26#define UNIPHIER_I2C_MYAD 0x08 /* slave address */
27#define UNIPHIER_I2C_CLK 0x0c /* clock frequency control */
28#define UNIPHIER_I2C_BRST 0x10 /* bus reset */
29#define UNIPHIER_I2C_BRST_FOEN BIT(1) /* normal operation */
30#define UNIPHIER_I2C_BRST_RSCL BIT(0) /* release SCL */
31#define UNIPHIER_I2C_HOLD 0x14 /* hold time control */
32#define UNIPHIER_I2C_BSTS 0x18 /* bus status monitor */
33#define UNIPHIER_I2C_BSTS_SDA BIT(1) /* readback of SDA line */
34#define UNIPHIER_I2C_BSTS_SCL BIT(0) /* readback of SCL line */
35#define UNIPHIER_I2C_NOISE 0x1c /* noise filter control */
36#define UNIPHIER_I2C_SETUP 0x20 /* setup time control */
37
38struct uniphier_i2c_priv {
39 struct completion comp;
40 struct i2c_adapter adap;
41 void __iomem *membase;
42 struct clk *clk;
43 unsigned int busy_cnt;
44 unsigned int clk_cycle;
45};
46
47static irqreturn_t uniphier_i2c_interrupt(int irq, void *dev_id)
48{
49 struct uniphier_i2c_priv *priv = dev_id;
50
51 /*
52 * This hardware uses edge triggered interrupt. Do not touch the
53 * hardware registers in this handler to make sure to catch the next
54 * interrupt edge. Just send a complete signal and return.
55 */
56 complete(&priv->comp);
57
58 return IRQ_HANDLED;
59}
60
61static int uniphier_i2c_xfer_byte(struct i2c_adapter *adap, u32 txdata,
62 u32 *rxdatap)
63{
64 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
65 unsigned long time_left;
66 u32 rxdata;
67
68 reinit_completion(&priv->comp);
69
70 txdata |= UNIPHIER_I2C_DTRM_IRQEN;
71 writel(txdata, priv->membase + UNIPHIER_I2C_DTRM);
72
73 time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
74 if (unlikely(!time_left)) {
75 dev_err(&adap->dev, "transaction timeout\n");
76 return -ETIMEDOUT;
77 }
78
79 rxdata = readl(priv->membase + UNIPHIER_I2C_DREC);
80 if (rxdatap)
81 *rxdatap = rxdata;
82
83 return 0;
84}
85
86static int uniphier_i2c_send_byte(struct i2c_adapter *adap, u32 txdata)
87{
88 u32 rxdata;
89 int ret;
90
91 ret = uniphier_i2c_xfer_byte(adap, txdata, &rxdata);
92 if (ret)
93 return ret;
94
95 if (unlikely(rxdata & UNIPHIER_I2C_DREC_LAB))
96 return -EAGAIN;
97
98 if (unlikely(rxdata & UNIPHIER_I2C_DREC_LRB))
99 return -ENXIO;
100
101 return 0;
102}
103
104static int uniphier_i2c_tx(struct i2c_adapter *adap, u16 addr, u16 len,
105 const u8 *buf)
106{
107 int ret;
108
109 ret = uniphier_i2c_send_byte(adap, addr << 1 |
110 UNIPHIER_I2C_DTRM_STA |
111 UNIPHIER_I2C_DTRM_NACK);
112 if (ret)
113 return ret;
114
115 while (len--) {
116 ret = uniphier_i2c_send_byte(adap,
117 UNIPHIER_I2C_DTRM_NACK | *buf++);
118 if (ret)
119 return ret;
120 }
121
122 return 0;
123}
124
125static int uniphier_i2c_rx(struct i2c_adapter *adap, u16 addr, u16 len,
126 u8 *buf)
127{
128 int ret;
129
130 ret = uniphier_i2c_send_byte(adap, addr << 1 |
131 UNIPHIER_I2C_DTRM_STA |
132 UNIPHIER_I2C_DTRM_NACK |
133 UNIPHIER_I2C_DTRM_RD);
134 if (ret)
135 return ret;
136
137 while (len--) {
138 u32 rxdata;
139
140 ret = uniphier_i2c_xfer_byte(adap,
141 len ? 0 : UNIPHIER_I2C_DTRM_NACK,
142 &rxdata);
143 if (ret)
144 return ret;
145 *buf++ = rxdata;
146 }
147
148 return 0;
149}
150
151static int uniphier_i2c_stop(struct i2c_adapter *adap)
152{
153 return uniphier_i2c_send_byte(adap, UNIPHIER_I2C_DTRM_STO |
154 UNIPHIER_I2C_DTRM_NACK);
155}
156
157static int uniphier_i2c_master_xfer_one(struct i2c_adapter *adap,
158 struct i2c_msg *msg, bool stop)
159{
160 bool is_read = msg->flags & I2C_M_RD;
161 bool recovery = false;
162 int ret;
163
164 if (is_read)
165 ret = uniphier_i2c_rx(adap, msg->addr, msg->len, msg->buf);
166 else
167 ret = uniphier_i2c_tx(adap, msg->addr, msg->len, msg->buf);
168
169 if (ret == -EAGAIN) /* could not acquire bus. bail out without STOP */
170 return ret;
171
172 if (ret == -ETIMEDOUT) {
173 /* This error is fatal. Needs recovery. */
174 stop = false;
175 recovery = true;
176 }
177
178 if (stop) {
179 int ret2 = uniphier_i2c_stop(adap);
180
181 if (ret2) {
182 /* Failed to issue STOP. The bus needs recovery. */
183 recovery = true;
184 ret = ret ?: ret2;
185 }
186 }
187
188 if (recovery)
189 i2c_recover_bus(adap);
190
191 return ret;
192}
193
194static int uniphier_i2c_check_bus_busy(struct i2c_adapter *adap)
195{
196 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
197
198 if (!(readl(priv->membase + UNIPHIER_I2C_DREC) &
199 UNIPHIER_I2C_DREC_BBN)) {
200 if (priv->busy_cnt++ > 3) {
201 /*
202 * If bus busy continues too long, it is probably
203 * in a wrong state. Try bus recovery.
204 */
205 i2c_recover_bus(adap);
206 priv->busy_cnt = 0;
207 }
208
209 return -EAGAIN;
210 }
211
212 priv->busy_cnt = 0;
213 return 0;
214}
215
216static int uniphier_i2c_master_xfer(struct i2c_adapter *adap,
217 struct i2c_msg *msgs, int num)
218{
219 struct i2c_msg *msg, *emsg = msgs + num;
220 int ret;
221
222 ret = uniphier_i2c_check_bus_busy(adap);
223 if (ret)
224 return ret;
225
226 for (msg = msgs; msg < emsg; msg++) {
227 /* Emit STOP if it is the last message or I2C_M_STOP is set. */
228 bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
229
230 ret = uniphier_i2c_master_xfer_one(adap, msg, stop);
231 if (ret)
232 return ret;
233 }
234
235 return num;
236}
237
238static u32 uniphier_i2c_functionality(struct i2c_adapter *adap)
239{
240 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
241}
242
243static const struct i2c_algorithm uniphier_i2c_algo = {
244 .master_xfer = uniphier_i2c_master_xfer,
245 .functionality = uniphier_i2c_functionality,
246};
247
248static void uniphier_i2c_reset(struct uniphier_i2c_priv *priv, bool reset_on)
249{
250 u32 val = UNIPHIER_I2C_BRST_RSCL;
251
252 val |= reset_on ? 0 : UNIPHIER_I2C_BRST_FOEN;
253 writel(val, priv->membase + UNIPHIER_I2C_BRST);
254}
255
256static int uniphier_i2c_get_scl(struct i2c_adapter *adap)
257{
258 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
259
260 return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
261 UNIPHIER_I2C_BSTS_SCL);
262}
263
264static void uniphier_i2c_set_scl(struct i2c_adapter *adap, int val)
265{
266 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
267
268 writel(val ? UNIPHIER_I2C_BRST_RSCL : 0,
269 priv->membase + UNIPHIER_I2C_BRST);
270}
271
272static int uniphier_i2c_get_sda(struct i2c_adapter *adap)
273{
274 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
275
276 return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
277 UNIPHIER_I2C_BSTS_SDA);
278}
279
280static void uniphier_i2c_unprepare_recovery(struct i2c_adapter *adap)
281{
282 uniphier_i2c_reset(i2c_get_adapdata(adap), false);
283}
284
285static struct i2c_bus_recovery_info uniphier_i2c_bus_recovery_info = {
286 .recover_bus = i2c_generic_scl_recovery,
287 .get_scl = uniphier_i2c_get_scl,
288 .set_scl = uniphier_i2c_set_scl,
289 .get_sda = uniphier_i2c_get_sda,
290 .unprepare_recovery = uniphier_i2c_unprepare_recovery,
291};
292
293static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv)
294{
295 unsigned int cyc = priv->clk_cycle;
296
297 uniphier_i2c_reset(priv, true);
298
299 /*
300 * Bit30-16: clock cycles of tLOW.
301 * Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us
302 * Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us
303 * "tLow/tHIGH = 5/4" meets both.
304 */
305 writel((cyc * 5 / 9 << 16) | cyc, priv->membase + UNIPHIER_I2C_CLK);
306
307 uniphier_i2c_reset(priv, false);
308}
309
310static int uniphier_i2c_probe(struct platform_device *pdev)
311{
312 struct device *dev = &pdev->dev;
313 struct uniphier_i2c_priv *priv;
314 u32 bus_speed;
315 unsigned long clk_rate;
316 int irq, ret;
317
318 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
319 if (!priv)
320 return -ENOMEM;
321
322 priv->membase = devm_platform_ioremap_resource(pdev, 0);
323 if (IS_ERR(priv->membase))
324 return PTR_ERR(priv->membase);
325
326 irq = platform_get_irq(pdev, 0);
327 if (irq < 0)
328 return irq;
329
330 if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
331 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
332
333 if (!bus_speed || bus_speed > I2C_MAX_FAST_MODE_FREQ) {
334 dev_err(dev, "invalid clock-frequency %d\n", bus_speed);
335 return -EINVAL;
336 }
337
338 priv->clk = devm_clk_get(dev, NULL);
339 if (IS_ERR(priv->clk)) {
340 dev_err(dev, "failed to get clock\n");
341 return PTR_ERR(priv->clk);
342 }
343
344 ret = clk_prepare_enable(priv->clk);
345 if (ret)
346 return ret;
347
348 clk_rate = clk_get_rate(priv->clk);
349 if (!clk_rate) {
350 dev_err(dev, "input clock rate should not be zero\n");
351 ret = -EINVAL;
352 goto disable_clk;
353 }
354
355 priv->clk_cycle = clk_rate / bus_speed;
356 init_completion(&priv->comp);
357 priv->adap.owner = THIS_MODULE;
358 priv->adap.algo = &uniphier_i2c_algo;
359 priv->adap.dev.parent = dev;
360 priv->adap.dev.of_node = dev->of_node;
361 strscpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
362 priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info;
363 i2c_set_adapdata(&priv->adap, priv);
364 platform_set_drvdata(pdev, priv);
365
366 uniphier_i2c_hw_init(priv);
367
368 ret = devm_request_irq(dev, irq, uniphier_i2c_interrupt, 0, pdev->name,
369 priv);
370 if (ret) {
371 dev_err(dev, "failed to request irq %d\n", irq);
372 goto disable_clk;
373 }
374
375 ret = i2c_add_adapter(&priv->adap);
376disable_clk:
377 if (ret)
378 clk_disable_unprepare(priv->clk);
379
380 return ret;
381}
382
383static int uniphier_i2c_remove(struct platform_device *pdev)
384{
385 struct uniphier_i2c_priv *priv = platform_get_drvdata(pdev);
386
387 i2c_del_adapter(&priv->adap);
388 clk_disable_unprepare(priv->clk);
389
390 return 0;
391}
392
393static int __maybe_unused uniphier_i2c_suspend(struct device *dev)
394{
395 struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
396
397 clk_disable_unprepare(priv->clk);
398
399 return 0;
400}
401
402static int __maybe_unused uniphier_i2c_resume(struct device *dev)
403{
404 struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
405 int ret;
406
407 ret = clk_prepare_enable(priv->clk);
408 if (ret)
409 return ret;
410
411 uniphier_i2c_hw_init(priv);
412
413 return 0;
414}
415
416static const struct dev_pm_ops uniphier_i2c_pm_ops = {
417 SET_SYSTEM_SLEEP_PM_OPS(uniphier_i2c_suspend, uniphier_i2c_resume)
418};
419
420static const struct of_device_id uniphier_i2c_match[] = {
421 { .compatible = "socionext,uniphier-i2c" },
422 { /* sentinel */ }
423};
424MODULE_DEVICE_TABLE(of, uniphier_i2c_match);
425
426static struct platform_driver uniphier_i2c_drv = {
427 .probe = uniphier_i2c_probe,
428 .remove = uniphier_i2c_remove,
429 .driver = {
430 .name = "uniphier-i2c",
431 .of_match_table = uniphier_i2c_match,
432 .pm = &uniphier_i2c_pm_ops,
433 },
434};
435module_platform_driver(uniphier_i2c_drv);
436
437MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
438MODULE_DESCRIPTION("UniPhier I2C bus driver");
439MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21
22#define UNIPHIER_I2C_DTRM 0x00 /* TX register */
23#define UNIPHIER_I2C_DTRM_IRQEN BIT(11) /* enable interrupt */
24#define UNIPHIER_I2C_DTRM_STA BIT(10) /* start condition */
25#define UNIPHIER_I2C_DTRM_STO BIT(9) /* stop condition */
26#define UNIPHIER_I2C_DTRM_NACK BIT(8) /* do not return ACK */
27#define UNIPHIER_I2C_DTRM_RD BIT(0) /* read transaction */
28#define UNIPHIER_I2C_DREC 0x04 /* RX register */
29#define UNIPHIER_I2C_DREC_MST BIT(14) /* 1 = master, 0 = slave */
30#define UNIPHIER_I2C_DREC_TX BIT(13) /* 1 = transmit, 0 = receive */
31#define UNIPHIER_I2C_DREC_STS BIT(12) /* stop condition detected */
32#define UNIPHIER_I2C_DREC_LRB BIT(11) /* no ACK */
33#define UNIPHIER_I2C_DREC_LAB BIT(9) /* arbitration lost */
34#define UNIPHIER_I2C_DREC_BBN BIT(8) /* bus not busy */
35#define UNIPHIER_I2C_MYAD 0x08 /* slave address */
36#define UNIPHIER_I2C_CLK 0x0c /* clock frequency control */
37#define UNIPHIER_I2C_BRST 0x10 /* bus reset */
38#define UNIPHIER_I2C_BRST_FOEN BIT(1) /* normal operation */
39#define UNIPHIER_I2C_BRST_RSCL BIT(0) /* release SCL */
40#define UNIPHIER_I2C_HOLD 0x14 /* hold time control */
41#define UNIPHIER_I2C_BSTS 0x18 /* bus status monitor */
42#define UNIPHIER_I2C_BSTS_SDA BIT(1) /* readback of SDA line */
43#define UNIPHIER_I2C_BSTS_SCL BIT(0) /* readback of SCL line */
44#define UNIPHIER_I2C_NOISE 0x1c /* noise filter control */
45#define UNIPHIER_I2C_SETUP 0x20 /* setup time control */
46
47#define UNIPHIER_I2C_DEFAULT_SPEED 100000
48#define UNIPHIER_I2C_MAX_SPEED 400000
49
50struct uniphier_i2c_priv {
51 struct completion comp;
52 struct i2c_adapter adap;
53 void __iomem *membase;
54 struct clk *clk;
55 unsigned int busy_cnt;
56};
57
58static irqreturn_t uniphier_i2c_interrupt(int irq, void *dev_id)
59{
60 struct uniphier_i2c_priv *priv = dev_id;
61
62 /*
63 * This hardware uses edge triggered interrupt. Do not touch the
64 * hardware registers in this handler to make sure to catch the next
65 * interrupt edge. Just send a complete signal and return.
66 */
67 complete(&priv->comp);
68
69 return IRQ_HANDLED;
70}
71
72static int uniphier_i2c_xfer_byte(struct i2c_adapter *adap, u32 txdata,
73 u32 *rxdatap)
74{
75 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
76 unsigned long time_left;
77 u32 rxdata;
78
79 reinit_completion(&priv->comp);
80
81 txdata |= UNIPHIER_I2C_DTRM_IRQEN;
82 dev_dbg(&adap->dev, "write data: 0x%04x\n", txdata);
83 writel(txdata, priv->membase + UNIPHIER_I2C_DTRM);
84
85 time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
86 if (unlikely(!time_left)) {
87 dev_err(&adap->dev, "transaction timeout\n");
88 return -ETIMEDOUT;
89 }
90
91 rxdata = readl(priv->membase + UNIPHIER_I2C_DREC);
92 dev_dbg(&adap->dev, "read data: 0x%04x\n", rxdata);
93
94 if (rxdatap)
95 *rxdatap = rxdata;
96
97 return 0;
98}
99
100static int uniphier_i2c_send_byte(struct i2c_adapter *adap, u32 txdata)
101{
102 u32 rxdata;
103 int ret;
104
105 ret = uniphier_i2c_xfer_byte(adap, txdata, &rxdata);
106 if (ret)
107 return ret;
108
109 if (unlikely(rxdata & UNIPHIER_I2C_DREC_LAB)) {
110 dev_dbg(&adap->dev, "arbitration lost\n");
111 return -EAGAIN;
112 }
113 if (unlikely(rxdata & UNIPHIER_I2C_DREC_LRB)) {
114 dev_dbg(&adap->dev, "could not get ACK\n");
115 return -ENXIO;
116 }
117
118 return 0;
119}
120
121static int uniphier_i2c_tx(struct i2c_adapter *adap, u16 addr, u16 len,
122 const u8 *buf)
123{
124 int ret;
125
126 dev_dbg(&adap->dev, "start condition\n");
127 ret = uniphier_i2c_send_byte(adap, addr << 1 |
128 UNIPHIER_I2C_DTRM_STA |
129 UNIPHIER_I2C_DTRM_NACK);
130 if (ret)
131 return ret;
132
133 while (len--) {
134 ret = uniphier_i2c_send_byte(adap,
135 UNIPHIER_I2C_DTRM_NACK | *buf++);
136 if (ret)
137 return ret;
138 }
139
140 return 0;
141}
142
143static int uniphier_i2c_rx(struct i2c_adapter *adap, u16 addr, u16 len,
144 u8 *buf)
145{
146 int ret;
147
148 dev_dbg(&adap->dev, "start condition\n");
149 ret = uniphier_i2c_send_byte(adap, addr << 1 |
150 UNIPHIER_I2C_DTRM_STA |
151 UNIPHIER_I2C_DTRM_NACK |
152 UNIPHIER_I2C_DTRM_RD);
153 if (ret)
154 return ret;
155
156 while (len--) {
157 u32 rxdata;
158
159 ret = uniphier_i2c_xfer_byte(adap,
160 len ? 0 : UNIPHIER_I2C_DTRM_NACK,
161 &rxdata);
162 if (ret)
163 return ret;
164 *buf++ = rxdata;
165 }
166
167 return 0;
168}
169
170static int uniphier_i2c_stop(struct i2c_adapter *adap)
171{
172 dev_dbg(&adap->dev, "stop condition\n");
173 return uniphier_i2c_send_byte(adap, UNIPHIER_I2C_DTRM_STO |
174 UNIPHIER_I2C_DTRM_NACK);
175}
176
177static int uniphier_i2c_master_xfer_one(struct i2c_adapter *adap,
178 struct i2c_msg *msg, bool stop)
179{
180 bool is_read = msg->flags & I2C_M_RD;
181 bool recovery = false;
182 int ret;
183
184 dev_dbg(&adap->dev, "%s: addr=0x%02x, len=%d, stop=%d\n",
185 is_read ? "receive" : "transmit", msg->addr, msg->len, stop);
186
187 if (is_read)
188 ret = uniphier_i2c_rx(adap, msg->addr, msg->len, msg->buf);
189 else
190 ret = uniphier_i2c_tx(adap, msg->addr, msg->len, msg->buf);
191
192 if (ret == -EAGAIN) /* could not acquire bus. bail out without STOP */
193 return ret;
194
195 if (ret == -ETIMEDOUT) {
196 /* This error is fatal. Needs recovery. */
197 stop = false;
198 recovery = true;
199 }
200
201 if (stop) {
202 int ret2 = uniphier_i2c_stop(adap);
203
204 if (ret2) {
205 /* Failed to issue STOP. The bus needs recovery. */
206 recovery = true;
207 ret = ret ?: ret2;
208 }
209 }
210
211 if (recovery)
212 i2c_recover_bus(adap);
213
214 return ret;
215}
216
217static int uniphier_i2c_check_bus_busy(struct i2c_adapter *adap)
218{
219 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
220
221 if (!(readl(priv->membase + UNIPHIER_I2C_DREC) &
222 UNIPHIER_I2C_DREC_BBN)) {
223 if (priv->busy_cnt++ > 3) {
224 /*
225 * If bus busy continues too long, it is probably
226 * in a wrong state. Try bus recovery.
227 */
228 i2c_recover_bus(adap);
229 priv->busy_cnt = 0;
230 }
231
232 return -EAGAIN;
233 }
234
235 priv->busy_cnt = 0;
236 return 0;
237}
238
239static int uniphier_i2c_master_xfer(struct i2c_adapter *adap,
240 struct i2c_msg *msgs, int num)
241{
242 struct i2c_msg *msg, *emsg = msgs + num;
243 int ret;
244
245 ret = uniphier_i2c_check_bus_busy(adap);
246 if (ret)
247 return ret;
248
249 for (msg = msgs; msg < emsg; msg++) {
250 /* If next message is read, skip the stop condition */
251 bool stop = !(msg + 1 < emsg && msg[1].flags & I2C_M_RD);
252 /* but, force it if I2C_M_STOP is set */
253 if (msg->flags & I2C_M_STOP)
254 stop = true;
255
256 ret = uniphier_i2c_master_xfer_one(adap, msg, stop);
257 if (ret)
258 return ret;
259 }
260
261 return num;
262}
263
264static u32 uniphier_i2c_functionality(struct i2c_adapter *adap)
265{
266 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
267}
268
269static const struct i2c_algorithm uniphier_i2c_algo = {
270 .master_xfer = uniphier_i2c_master_xfer,
271 .functionality = uniphier_i2c_functionality,
272};
273
274static void uniphier_i2c_reset(struct uniphier_i2c_priv *priv, bool reset_on)
275{
276 u32 val = UNIPHIER_I2C_BRST_RSCL;
277
278 val |= reset_on ? 0 : UNIPHIER_I2C_BRST_FOEN;
279 writel(val, priv->membase + UNIPHIER_I2C_BRST);
280}
281
282static int uniphier_i2c_get_scl(struct i2c_adapter *adap)
283{
284 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
285
286 return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
287 UNIPHIER_I2C_BSTS_SCL);
288}
289
290static void uniphier_i2c_set_scl(struct i2c_adapter *adap, int val)
291{
292 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
293
294 writel(val ? UNIPHIER_I2C_BRST_RSCL : 0,
295 priv->membase + UNIPHIER_I2C_BRST);
296}
297
298static int uniphier_i2c_get_sda(struct i2c_adapter *adap)
299{
300 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
301
302 return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
303 UNIPHIER_I2C_BSTS_SDA);
304}
305
306static void uniphier_i2c_unprepare_recovery(struct i2c_adapter *adap)
307{
308 uniphier_i2c_reset(i2c_get_adapdata(adap), false);
309}
310
311static struct i2c_bus_recovery_info uniphier_i2c_bus_recovery_info = {
312 .recover_bus = i2c_generic_scl_recovery,
313 .get_scl = uniphier_i2c_get_scl,
314 .set_scl = uniphier_i2c_set_scl,
315 .get_sda = uniphier_i2c_get_sda,
316 .unprepare_recovery = uniphier_i2c_unprepare_recovery,
317};
318
319static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv,
320 u32 bus_speed, unsigned long clk_rate)
321{
322 uniphier_i2c_reset(priv, true);
323
324 writel((clk_rate / bus_speed / 2 << 16) | (clk_rate / bus_speed),
325 priv->membase + UNIPHIER_I2C_CLK);
326
327 uniphier_i2c_reset(priv, false);
328}
329
330static int uniphier_i2c_probe(struct platform_device *pdev)
331{
332 struct device *dev = &pdev->dev;
333 struct uniphier_i2c_priv *priv;
334 struct resource *regs;
335 u32 bus_speed;
336 unsigned long clk_rate;
337 int irq, ret;
338
339 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
340 if (!priv)
341 return -ENOMEM;
342
343 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
344 priv->membase = devm_ioremap_resource(dev, regs);
345 if (IS_ERR(priv->membase))
346 return PTR_ERR(priv->membase);
347
348 irq = platform_get_irq(pdev, 0);
349 if (irq < 0) {
350 dev_err(dev, "failed to get IRQ number\n");
351 return irq;
352 }
353
354 if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
355 bus_speed = UNIPHIER_I2C_DEFAULT_SPEED;
356
357 if (!bus_speed || bus_speed > UNIPHIER_I2C_MAX_SPEED) {
358 dev_err(dev, "invalid clock-frequency %d\n", bus_speed);
359 return -EINVAL;
360 }
361
362 priv->clk = devm_clk_get(dev, NULL);
363 if (IS_ERR(priv->clk)) {
364 dev_err(dev, "failed to get clock\n");
365 return PTR_ERR(priv->clk);
366 }
367
368 ret = clk_prepare_enable(priv->clk);
369 if (ret)
370 return ret;
371
372 clk_rate = clk_get_rate(priv->clk);
373 if (!clk_rate) {
374 dev_err(dev, "input clock rate should not be zero\n");
375 ret = -EINVAL;
376 goto disable_clk;
377 }
378
379 init_completion(&priv->comp);
380 priv->adap.owner = THIS_MODULE;
381 priv->adap.algo = &uniphier_i2c_algo;
382 priv->adap.dev.parent = dev;
383 priv->adap.dev.of_node = dev->of_node;
384 strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
385 priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info;
386 i2c_set_adapdata(&priv->adap, priv);
387 platform_set_drvdata(pdev, priv);
388
389 uniphier_i2c_hw_init(priv, bus_speed, clk_rate);
390
391 ret = devm_request_irq(dev, irq, uniphier_i2c_interrupt, 0, pdev->name,
392 priv);
393 if (ret) {
394 dev_err(dev, "failed to request irq %d\n", irq);
395 goto disable_clk;
396 }
397
398 ret = i2c_add_adapter(&priv->adap);
399disable_clk:
400 if (ret)
401 clk_disable_unprepare(priv->clk);
402
403 return ret;
404}
405
406static int uniphier_i2c_remove(struct platform_device *pdev)
407{
408 struct uniphier_i2c_priv *priv = platform_get_drvdata(pdev);
409
410 i2c_del_adapter(&priv->adap);
411 clk_disable_unprepare(priv->clk);
412
413 return 0;
414}
415
416static const struct of_device_id uniphier_i2c_match[] = {
417 { .compatible = "socionext,uniphier-i2c" },
418 { /* sentinel */ }
419};
420MODULE_DEVICE_TABLE(of, uniphier_i2c_match);
421
422static struct platform_driver uniphier_i2c_drv = {
423 .probe = uniphier_i2c_probe,
424 .remove = uniphier_i2c_remove,
425 .driver = {
426 .name = "uniphier-i2c",
427 .of_match_table = uniphier_i2c_match,
428 },
429};
430module_platform_driver(uniphier_i2c_drv);
431
432MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
433MODULE_DESCRIPTION("UniPhier I2C bus driver");
434MODULE_LICENSE("GPL");