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1/*
2 * I2C bus driver for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/interrupt.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/slab.h>
13#include <linux/platform_device.h>
14#include <linux/i2c.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18
19#define SIRFSOC_I2C_CLK_CTRL 0x00
20#define SIRFSOC_I2C_STATUS 0x0C
21#define SIRFSOC_I2C_CTRL 0x10
22#define SIRFSOC_I2C_IO_CTRL 0x14
23#define SIRFSOC_I2C_SDA_DELAY 0x18
24#define SIRFSOC_I2C_CMD_START 0x1C
25#define SIRFSOC_I2C_CMD_BUF 0x30
26#define SIRFSOC_I2C_DATA_BUF 0x80
27
28#define SIRFSOC_I2C_CMD_BUF_MAX 16
29#define SIRFSOC_I2C_DATA_BUF_MAX 16
30
31#define SIRFSOC_I2C_CMD(x) (SIRFSOC_I2C_CMD_BUF + (x)*0x04)
32#define SIRFSOC_I2C_DATA_MASK(x) (0xFF<<(((x)&3)*8))
33#define SIRFSOC_I2C_DATA_SHIFT(x) (((x)&3)*8)
34
35#define SIRFSOC_I2C_DIV_MASK (0xFFFF)
36
37/* I2C status flags */
38#define SIRFSOC_I2C_STAT_BUSY BIT(0)
39#define SIRFSOC_I2C_STAT_TIP BIT(1)
40#define SIRFSOC_I2C_STAT_NACK BIT(2)
41#define SIRFSOC_I2C_STAT_TR_INT BIT(4)
42#define SIRFSOC_I2C_STAT_STOP BIT(6)
43#define SIRFSOC_I2C_STAT_CMD_DONE BIT(8)
44#define SIRFSOC_I2C_STAT_ERR BIT(9)
45#define SIRFSOC_I2C_CMD_INDEX (0x1F<<16)
46
47/* I2C control flags */
48#define SIRFSOC_I2C_RESET BIT(0)
49#define SIRFSOC_I2C_CORE_EN BIT(1)
50#define SIRFSOC_I2C_MASTER_MODE BIT(2)
51#define SIRFSOC_I2C_CMD_DONE_EN BIT(11)
52#define SIRFSOC_I2C_ERR_INT_EN BIT(12)
53
54#define SIRFSOC_I2C_SDA_DELAY_MASK (0xFF)
55#define SIRFSOC_I2C_SCLF_FILTER (3<<8)
56
57#define SIRFSOC_I2C_START_CMD BIT(0)
58
59#define SIRFSOC_I2C_CMD_RP(x) ((x)&0x7)
60#define SIRFSOC_I2C_NACK BIT(3)
61#define SIRFSOC_I2C_WRITE BIT(4)
62#define SIRFSOC_I2C_READ BIT(5)
63#define SIRFSOC_I2C_STOP BIT(6)
64#define SIRFSOC_I2C_START BIT(7)
65
66#define SIRFSOC_I2C_DEFAULT_SPEED 100000
67#define SIRFSOC_I2C_ERR_NOACK 1
68#define SIRFSOC_I2C_ERR_TIMEOUT 2
69
70struct sirfsoc_i2c {
71 void __iomem *base;
72 struct clk *clk;
73 u32 cmd_ptr; /* Current position in CMD buffer */
74 u8 *buf; /* Buffer passed by user */
75 u32 msg_len; /* Message length */
76 u32 finished_len; /* number of bytes read/written */
77 u32 read_cmd_len; /* number of read cmd sent */
78 int msg_read; /* 1 indicates a read message */
79 int err_status; /* 1 indicates an error on bus */
80
81 u32 sda_delay; /* For suspend/resume */
82 u32 clk_div;
83 int last; /* Last message in transfer, STOP cmd can be sent */
84
85 struct completion done; /* indicates completion of message transfer */
86 struct i2c_adapter adapter;
87};
88
89static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic)
90{
91 u32 data = 0;
92 int i;
93
94 for (i = 0; i < siic->read_cmd_len; i++) {
95 if (!(i & 0x3))
96 data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i);
97 siic->buf[siic->finished_len++] =
98 (u8)((data & SIRFSOC_I2C_DATA_MASK(i)) >>
99 SIRFSOC_I2C_DATA_SHIFT(i));
100 }
101}
102
103static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic)
104{
105 u32 regval;
106 int i = 0;
107
108 if (siic->msg_read) {
109 while (((siic->finished_len + i) < siic->msg_len)
110 && (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) {
111 regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0);
112 if (((siic->finished_len + i) ==
113 (siic->msg_len - 1)) && siic->last)
114 regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK;
115 writel(regval,
116 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
117 i++;
118 }
119
120 siic->read_cmd_len = i;
121 } else {
122 while ((siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX - 1)
123 && (siic->finished_len < siic->msg_len)) {
124 regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0);
125 if ((siic->finished_len == (siic->msg_len - 1))
126 && siic->last)
127 regval |= SIRFSOC_I2C_STOP;
128 writel(regval,
129 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
130 writel(siic->buf[siic->finished_len++],
131 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
132 }
133 }
134 siic->cmd_ptr = 0;
135
136 /* Trigger the transfer */
137 writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START);
138}
139
140static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id)
141{
142 struct sirfsoc_i2c *siic = (struct sirfsoc_i2c *)dev_id;
143 u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS);
144
145 if (i2c_stat & SIRFSOC_I2C_STAT_ERR) {
146 /* Error conditions */
147 siic->err_status = SIRFSOC_I2C_ERR_NOACK;
148 writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS);
149
150 if (i2c_stat & SIRFSOC_I2C_STAT_NACK)
151 dev_dbg(&siic->adapter.dev, "ACK not received\n");
152 else
153 dev_err(&siic->adapter.dev, "I2C error\n");
154
155 /*
156 * Due to hardware ANOMALY, we need to reset I2C earlier after
157 * we get NOACK while accessing non-existing clients, otherwise
158 * we will get errors even we access existing clients later
159 */
160 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
161 siic->base + SIRFSOC_I2C_CTRL);
162 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
163 cpu_relax();
164
165 complete(&siic->done);
166 } else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) {
167 /* CMD buffer execution complete */
168 if (siic->msg_read)
169 i2c_sirfsoc_read_data(siic);
170 if (siic->finished_len == siic->msg_len)
171 complete(&siic->done);
172 else /* Fill a new CMD buffer for left data */
173 i2c_sirfsoc_queue_cmd(siic);
174
175 writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS);
176 }
177
178 return IRQ_HANDLED;
179}
180
181static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic,
182 struct i2c_msg *msg)
183{
184 unsigned char addr;
185 u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE;
186
187 /* no data and last message -> add STOP */
188 if (siic->last && (msg->len == 0))
189 regval |= SIRFSOC_I2C_STOP;
190
191 writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
192
193 addr = i2c_8bit_addr_from_msg(msg);
194
195 /* Reverse direction bit */
196 if (msg->flags & I2C_M_REV_DIR_ADDR)
197 addr ^= 1;
198
199 writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
200}
201
202static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg)
203{
204 u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL);
205 /* timeout waiting for the xfer to finish or fail */
206 int timeout = msecs_to_jiffies((msg->len + 1) * 50);
207
208 i2c_sirfsoc_set_address(siic, msg);
209
210 writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN,
211 siic->base + SIRFSOC_I2C_CTRL);
212 i2c_sirfsoc_queue_cmd(siic);
213
214 if (wait_for_completion_timeout(&siic->done, timeout) == 0) {
215 siic->err_status = SIRFSOC_I2C_ERR_TIMEOUT;
216 dev_err(&siic->adapter.dev, "Transfer timeout\n");
217 }
218
219 writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN),
220 siic->base + SIRFSOC_I2C_CTRL);
221 writel(0, siic->base + SIRFSOC_I2C_CMD_START);
222
223 /* i2c control doesn't response, reset it */
224 if (siic->err_status == SIRFSOC_I2C_ERR_TIMEOUT) {
225 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
226 siic->base + SIRFSOC_I2C_CTRL);
227 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
228 cpu_relax();
229 }
230 return siic->err_status ? -EAGAIN : 0;
231}
232
233static u32 i2c_sirfsoc_func(struct i2c_adapter *adap)
234{
235 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
236}
237
238static int i2c_sirfsoc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
239 int num)
240{
241 struct sirfsoc_i2c *siic = adap->algo_data;
242 int i, ret;
243
244 clk_enable(siic->clk);
245
246 for (i = 0; i < num; i++) {
247 siic->buf = msgs[i].buf;
248 siic->msg_len = msgs[i].len;
249 siic->msg_read = !!(msgs[i].flags & I2C_M_RD);
250 siic->err_status = 0;
251 siic->cmd_ptr = 0;
252 siic->finished_len = 0;
253 siic->last = (i == (num - 1));
254
255 ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]);
256 if (ret) {
257 clk_disable(siic->clk);
258 return ret;
259 }
260 }
261
262 clk_disable(siic->clk);
263 return num;
264}
265
266/* I2C algorithms associated with this master controller driver */
267static const struct i2c_algorithm i2c_sirfsoc_algo = {
268 .master_xfer = i2c_sirfsoc_xfer,
269 .functionality = i2c_sirfsoc_func,
270};
271
272static int i2c_sirfsoc_probe(struct platform_device *pdev)
273{
274 struct sirfsoc_i2c *siic;
275 struct i2c_adapter *adap;
276 struct resource *mem_res;
277 struct clk *clk;
278 int bitrate;
279 int ctrl_speed;
280 int irq;
281
282 int err;
283 u32 regval;
284
285 clk = clk_get(&pdev->dev, NULL);
286 if (IS_ERR(clk)) {
287 err = PTR_ERR(clk);
288 dev_err(&pdev->dev, "Clock get failed\n");
289 goto err_get_clk;
290 }
291
292 err = clk_prepare(clk);
293 if (err) {
294 dev_err(&pdev->dev, "Clock prepare failed\n");
295 goto err_clk_prep;
296 }
297
298 err = clk_enable(clk);
299 if (err) {
300 dev_err(&pdev->dev, "Clock enable failed\n");
301 goto err_clk_en;
302 }
303
304 ctrl_speed = clk_get_rate(clk);
305
306 siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL);
307 if (!siic) {
308 err = -ENOMEM;
309 goto out;
310 }
311 adap = &siic->adapter;
312 adap->class = I2C_CLASS_DEPRECATED;
313
314 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
315 siic->base = devm_ioremap_resource(&pdev->dev, mem_res);
316 if (IS_ERR(siic->base)) {
317 err = PTR_ERR(siic->base);
318 goto out;
319 }
320
321 irq = platform_get_irq(pdev, 0);
322 if (irq < 0) {
323 err = irq;
324 goto out;
325 }
326 err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0,
327 dev_name(&pdev->dev), siic);
328 if (err)
329 goto out;
330
331 adap->algo = &i2c_sirfsoc_algo;
332 adap->algo_data = siic;
333 adap->retries = 3;
334
335 adap->dev.of_node = pdev->dev.of_node;
336 adap->dev.parent = &pdev->dev;
337 adap->nr = pdev->id;
338
339 strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name));
340
341 platform_set_drvdata(pdev, adap);
342 init_completion(&siic->done);
343
344 /* Controller Initalisation */
345
346 writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
347 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
348 cpu_relax();
349 writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
350 siic->base + SIRFSOC_I2C_CTRL);
351
352 siic->clk = clk;
353
354 err = of_property_read_u32(pdev->dev.of_node,
355 "clock-frequency", &bitrate);
356 if (err < 0)
357 bitrate = SIRFSOC_I2C_DEFAULT_SPEED;
358
359 /*
360 * Due to some hardware design issues, we need to tune the formula.
361 * Since i2c is open drain interface that allows the slave to
362 * stall the transaction by holding the SCL line at '0', the RTL
363 * implementation is waiting for SCL feedback from the pin after
364 * setting it to High-Z ('1'). This wait adds to the high-time
365 * interval counter few cycles of the input synchronization
366 * (depending on the SCL_FILTER_REG field), and also the time it
367 * takes for the board pull-up resistor to rise the SCL line.
368 * For slow SCL settings these additions are negligible,
369 * but they start to affect the speed when clock is set to faster
370 * frequencies.
371 * Through the actual tests, use the different user_div value(which
372 * in the divider formular 'Fio / (Fi2c * user_div)') to adapt
373 * the different ranges of i2c bus clock frequency, to make the SCL
374 * more accurate.
375 */
376 if (bitrate <= 30000)
377 regval = ctrl_speed / (bitrate * 5);
378 else if (bitrate > 30000 && bitrate <= 280000)
379 regval = (2 * ctrl_speed) / (bitrate * 11);
380 else
381 regval = ctrl_speed / (bitrate * 6);
382
383 writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL);
384 if (regval > 0xFF)
385 writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY);
386 else
387 writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY);
388
389 err = i2c_add_numbered_adapter(adap);
390 if (err < 0)
391 goto out;
392
393 clk_disable(clk);
394
395 dev_info(&pdev->dev, " I2C adapter ready to operate\n");
396
397 return 0;
398
399out:
400 clk_disable(clk);
401err_clk_en:
402 clk_unprepare(clk);
403err_clk_prep:
404 clk_put(clk);
405err_get_clk:
406 return err;
407}
408
409static int i2c_sirfsoc_remove(struct platform_device *pdev)
410{
411 struct i2c_adapter *adapter = platform_get_drvdata(pdev);
412 struct sirfsoc_i2c *siic = adapter->algo_data;
413
414 writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
415 i2c_del_adapter(adapter);
416 clk_unprepare(siic->clk);
417 clk_put(siic->clk);
418 return 0;
419}
420
421#ifdef CONFIG_PM
422static int i2c_sirfsoc_suspend(struct device *dev)
423{
424 struct platform_device *pdev = to_platform_device(dev);
425 struct i2c_adapter *adapter = platform_get_drvdata(pdev);
426 struct sirfsoc_i2c *siic = adapter->algo_data;
427
428 clk_enable(siic->clk);
429 siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY);
430 siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL);
431 clk_disable(siic->clk);
432 return 0;
433}
434
435static int i2c_sirfsoc_resume(struct device *dev)
436{
437 struct platform_device *pdev = to_platform_device(dev);
438 struct i2c_adapter *adapter = platform_get_drvdata(pdev);
439 struct sirfsoc_i2c *siic = adapter->algo_data;
440
441 clk_enable(siic->clk);
442 writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
443 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
444 cpu_relax();
445 writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
446 siic->base + SIRFSOC_I2C_CTRL);
447 writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL);
448 writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY);
449 clk_disable(siic->clk);
450 return 0;
451}
452
453static const struct dev_pm_ops i2c_sirfsoc_pm_ops = {
454 .suspend = i2c_sirfsoc_suspend,
455 .resume = i2c_sirfsoc_resume,
456};
457#endif
458
459static const struct of_device_id sirfsoc_i2c_of_match[] = {
460 { .compatible = "sirf,prima2-i2c", },
461 {},
462};
463MODULE_DEVICE_TABLE(of, sirfsoc_i2c_of_match);
464
465static struct platform_driver i2c_sirfsoc_driver = {
466 .driver = {
467 .name = "sirfsoc_i2c",
468#ifdef CONFIG_PM
469 .pm = &i2c_sirfsoc_pm_ops,
470#endif
471 .of_match_table = sirfsoc_i2c_of_match,
472 },
473 .probe = i2c_sirfsoc_probe,
474 .remove = i2c_sirfsoc_remove,
475};
476module_platform_driver(i2c_sirfsoc_driver);
477
478MODULE_DESCRIPTION("SiRF SoC I2C master controller driver");
479MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
480 "Xiangzhen Ye <Xiangzhen.Ye@csr.com>");
481MODULE_LICENSE("GPL v2");