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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Mellanox BlueField I2C bus driver
4 *
5 * Copyright (C) 2020 Mellanox Technologies, Ltd.
6 */
7
8#include <linux/acpi.h>
9#include <linux/bitfield.h>
10#include <linux/delay.h>
11#include <linux/err.h>
12#include <linux/interrupt.h>
13#include <linux/i2c.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/mutex.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/string.h>
21
22/* Defines what functionality is present. */
23#define MLXBF_I2C_FUNC_SMBUS_BLOCK \
24 (I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL)
25
26#define MLXBF_I2C_FUNC_SMBUS_DEFAULT \
27 (I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | \
28 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_I2C_BLOCK | \
29 I2C_FUNC_SMBUS_PROC_CALL)
30
31#define MLXBF_I2C_FUNC_ALL \
32 (MLXBF_I2C_FUNC_SMBUS_DEFAULT | MLXBF_I2C_FUNC_SMBUS_BLOCK | \
33 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SLAVE)
34
35/* Shared resources info in BlueField platforms. */
36
37#define MLXBF_I2C_COALESCE_TYU_ADDR 0x02801300
38#define MLXBF_I2C_COALESCE_TYU_SIZE 0x010
39
40#define MLXBF_I2C_GPIO_TYU_ADDR 0x02802000
41#define MLXBF_I2C_GPIO_TYU_SIZE 0x100
42
43#define MLXBF_I2C_COREPLL_TYU_ADDR 0x02800358
44#define MLXBF_I2C_COREPLL_TYU_SIZE 0x008
45
46#define MLXBF_I2C_COREPLL_YU_ADDR 0x02800c30
47#define MLXBF_I2C_COREPLL_YU_SIZE 0x00c
48
49#define MLXBF_I2C_COREPLL_RSH_YU_ADDR 0x13409824
50#define MLXBF_I2C_COREPLL_RSH_YU_SIZE 0x00c
51
52#define MLXBF_I2C_SHARED_RES_MAX 3
53
54/*
55 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses
56 * refer to their respective offsets relative to the corresponding
57 * memory-mapped region whose addresses are specified in either the DT or
58 * the ACPI tables or above.
59 */
60
61/*
62 * SMBus Master core clock frequency. Timing configurations are
63 * strongly dependent on the core clock frequency of the SMBus
64 * Master. Default value is set to 400MHz.
65 */
66#define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000)
67/* Reference clock for Bluefield - 156 MHz. */
68#define MLXBF_I2C_PLL_IN_FREQ 156250000ULL
69
70/* Constant used to determine the PLL frequency. */
71#define MLNXBF_I2C_COREPLL_CONST 16384ULL
72
73#define MLXBF_I2C_FREQUENCY_1GHZ 1000000000ULL
74
75/* PLL registers. */
76#define MLXBF_I2C_CORE_PLL_REG1 0x4
77#define MLXBF_I2C_CORE_PLL_REG2 0x8
78
79/* OR cause register. */
80#define MLXBF_I2C_CAUSE_OR_EVTEN0 0x14
81#define MLXBF_I2C_CAUSE_OR_CLEAR 0x18
82
83/* Arbiter Cause Register. */
84#define MLXBF_I2C_CAUSE_ARBITER 0x1c
85
86/*
87 * Cause Status flags. Note that those bits might be considered
88 * as interrupt enabled bits.
89 */
90
91/* Transaction ended with STOP. */
92#define MLXBF_I2C_CAUSE_TRANSACTION_ENDED BIT(0)
93/* Master arbitration lost. */
94#define MLXBF_I2C_CAUSE_M_ARBITRATION_LOST BIT(1)
95/* Unexpected start detected. */
96#define MLXBF_I2C_CAUSE_UNEXPECTED_START BIT(2)
97/* Unexpected stop detected. */
98#define MLXBF_I2C_CAUSE_UNEXPECTED_STOP BIT(3)
99/* Wait for transfer continuation. */
100#define MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA BIT(4)
101/* Failed to generate STOP. */
102#define MLXBF_I2C_CAUSE_PUT_STOP_FAILED BIT(5)
103/* Failed to generate START. */
104#define MLXBF_I2C_CAUSE_PUT_START_FAILED BIT(6)
105/* Clock toggle completed. */
106#define MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE BIT(7)
107/* Transfer timeout occurred. */
108#define MLXBF_I2C_CAUSE_M_FW_TIMEOUT BIT(8)
109/* Master busy bit reset. */
110#define MLXBF_I2C_CAUSE_M_GW_BUSY_FALL BIT(9)
111
112#define MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK GENMASK(9, 0)
113
114#define MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR \
115 (MLXBF_I2C_CAUSE_M_ARBITRATION_LOST | \
116 MLXBF_I2C_CAUSE_UNEXPECTED_START | \
117 MLXBF_I2C_CAUSE_UNEXPECTED_STOP | \
118 MLXBF_I2C_CAUSE_PUT_STOP_FAILED | \
119 MLXBF_I2C_CAUSE_PUT_START_FAILED | \
120 MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE | \
121 MLXBF_I2C_CAUSE_M_FW_TIMEOUT)
122
123/*
124 * Slave cause status flags. Note that those bits might be considered
125 * as interrupt enabled bits.
126 */
127
128/* Write transaction received successfully. */
129#define MLXBF_I2C_CAUSE_WRITE_SUCCESS BIT(0)
130/* Read transaction received, waiting for response. */
131#define MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE BIT(13)
132/* Slave busy bit reset. */
133#define MLXBF_I2C_CAUSE_S_GW_BUSY_FALL BIT(18)
134
135/* Cause coalesce registers. */
136#define MLXBF_I2C_CAUSE_COALESCE_0 0x00
137
138#define MLXBF_I2C_CAUSE_TYU_SLAVE_BIT 3
139#define MLXBF_I2C_CAUSE_YU_SLAVE_BIT 1
140
141/* Functional enable register. */
142#define MLXBF_I2C_GPIO_0_FUNC_EN_0 0x28
143/* Force OE enable register. */
144#define MLXBF_I2C_GPIO_0_FORCE_OE_EN 0x30
145/*
146 * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control
147 * SDA/SCL lines:
148 *
149 * SMBUS GW0 -> bits[26:25]
150 * SMBUS GW1 -> bits[28:27]
151 * SMBUS GW2 -> bits[30:29]
152 */
153#define MLXBF_I2C_GPIO_SMBUS_GW_PINS(num) (25 + ((num) << 1))
154
155/* Note that gw_id can be 0,1 or 2. */
156#define MLXBF_I2C_GPIO_SMBUS_GW_MASK(num) \
157 (0xffffffff & (~(0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num))))
158
159#define MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(num, val) \
160 ((val) & MLXBF_I2C_GPIO_SMBUS_GW_MASK(num))
161
162#define MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(num, val) \
163 ((val) | (0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num)))
164
165/*
166 * Defines SMBus operating frequency and core clock frequency.
167 * According to ADB files, default values are compliant to 100KHz SMBus
168 * @ 400MHz core clock. The driver should be able to calculate core
169 * frequency based on PLL parameters.
170 */
171#define MLXBF_I2C_COREPLL_FREQ MLXBF_I2C_TYU_PLL_OUT_FREQ
172
173/* Core PLL TYU configuration. */
174#define MLXBF_I2C_COREPLL_CORE_F_TYU_MASK GENMASK(15, 3)
175#define MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK GENMASK(19, 16)
176#define MLXBF_I2C_COREPLL_CORE_R_TYU_MASK GENMASK(25, 20)
177
178/* Core PLL YU configuration. */
179#define MLXBF_I2C_COREPLL_CORE_F_YU_MASK GENMASK(25, 0)
180#define MLXBF_I2C_COREPLL_CORE_OD_YU_MASK GENMASK(3, 0)
181#define MLXBF_I2C_COREPLL_CORE_R_YU_MASK GENMASK(31, 26)
182
183/* SMBus timing parameters. */
184#define MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH 0x00
185#define MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE 0x04
186#define MLXBF_I2C_SMBUS_TIMER_THOLD 0x08
187#define MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP 0x0c
188#define MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA 0x10
189#define MLXBF_I2C_SMBUS_THIGH_MAX_TBUF 0x14
190#define MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT 0x18
191
192#define MLXBF_I2C_SHIFT_0 0
193#define MLXBF_I2C_SHIFT_8 8
194#define MLXBF_I2C_SHIFT_16 16
195#define MLXBF_I2C_SHIFT_24 24
196
197#define MLXBF_I2C_MASK_8 GENMASK(7, 0)
198#define MLXBF_I2C_MASK_16 GENMASK(15, 0)
199
200#define MLXBF_I2C_MST_ADDR_OFFSET 0x200
201
202/* SMBus Master GW. */
203#define MLXBF_I2C_SMBUS_MASTER_GW 0x0
204/* Number of bytes received and sent. */
205#define MLXBF_I2C_YU_SMBUS_RS_BYTES 0x100
206#define MLXBF_I2C_RSH_YU_SMBUS_RS_BYTES 0x10c
207/* Packet error check (PEC) value. */
208#define MLXBF_I2C_SMBUS_MASTER_PEC 0x104
209/* Status bits (ACK/NACK/FW Timeout). */
210#define MLXBF_I2C_SMBUS_MASTER_STATUS 0x108
211/* SMbus Master Finite State Machine. */
212#define MLXBF_I2C_YU_SMBUS_MASTER_FSM 0x110
213#define MLXBF_I2C_RSH_YU_SMBUS_MASTER_FSM 0x100
214
215/* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */
216#define MLXBF_I2C_MASTER_LOCK_BIT BIT(31) /* Lock bit. */
217#define MLXBF_I2C_MASTER_BUSY_BIT BIT(30) /* Busy bit. */
218#define MLXBF_I2C_MASTER_START_BIT BIT(29) /* Control start. */
219#define MLXBF_I2C_MASTER_CTL_WRITE_BIT BIT(28) /* Control write phase. */
220#define MLXBF_I2C_MASTER_CTL_READ_BIT BIT(19) /* Control read phase. */
221#define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */
222
223#define MLXBF_I2C_MASTER_ENABLE \
224 (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \
225 MLXBF_I2C_MASTER_START_BIT | MLXBF_I2C_MASTER_STOP_BIT)
226
227#define MLXBF_I2C_MASTER_ENABLE_WRITE \
228 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT)
229
230#define MLXBF_I2C_MASTER_ENABLE_READ \
231 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_READ_BIT)
232
233#define MLXBF_I2C_MASTER_WRITE_SHIFT 21 /* Control write bytes */
234#define MLXBF_I2C_MASTER_SEND_PEC_SHIFT 20 /* Send PEC byte when set to 1 */
235#define MLXBF_I2C_MASTER_PARSE_EXP_SHIFT 11 /* Control parse expected bytes */
236#define MLXBF_I2C_MASTER_SLV_ADDR_SHIFT 12 /* Slave address */
237#define MLXBF_I2C_MASTER_READ_SHIFT 4 /* Control read bytes */
238
239/* SMBus master GW Data descriptor. */
240#define MLXBF_I2C_MASTER_DATA_DESC_ADDR 0x80
241#define MLXBF_I2C_MASTER_DATA_DESC_SIZE 0x80 /* Size in bytes. */
242
243/* Maximum bytes to read/write per SMBus transaction. */
244#define MLXBF_I2C_MASTER_DATA_R_LENGTH MLXBF_I2C_MASTER_DATA_DESC_SIZE
245#define MLXBF_I2C_MASTER_DATA_W_LENGTH (MLXBF_I2C_MASTER_DATA_DESC_SIZE - 1)
246
247/* All bytes were transmitted. */
248#define MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE BIT(0)
249/* NACK received. */
250#define MLXBF_I2C_SMBUS_STATUS_NACK_RCV BIT(1)
251/* Slave's byte count >128 bytes. */
252#define MLXBF_I2C_SMBUS_STATUS_READ_ERR BIT(2)
253/* Timeout occurred. */
254#define MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT BIT(3)
255
256#define MLXBF_I2C_SMBUS_MASTER_STATUS_MASK GENMASK(3, 0)
257
258#define MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR \
259 (MLXBF_I2C_SMBUS_STATUS_NACK_RCV | \
260 MLXBF_I2C_SMBUS_STATUS_READ_ERR | \
261 MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT)
262
263#define MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK BIT(31)
264#define MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK BIT(15)
265
266#define MLXBF_I2C_SLV_ADDR_OFFSET 0x400
267
268/* SMBus slave GW. */
269#define MLXBF_I2C_SMBUS_SLAVE_GW 0x0
270/* Number of bytes received and sent from/to master. */
271#define MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES 0x100
272/* Packet error check (PEC) value. */
273#define MLXBF_I2C_SMBUS_SLAVE_PEC 0x104
274/* SMBus slave Finite State Machine (FSM). */
275#define MLXBF_I2C_SMBUS_SLAVE_FSM 0x110
276/*
277 * Should be set when all raised causes handled, and cleared by HW on
278 * every new cause.
279 */
280#define MLXBF_I2C_SMBUS_SLAVE_READY 0x12c
281
282/* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */
283#define MLXBF_I2C_SLAVE_BUSY_BIT BIT(30) /* Busy bit. */
284#define MLXBF_I2C_SLAVE_WRITE_BIT BIT(29) /* Control write enable. */
285
286#define MLXBF_I2C_SLAVE_ENABLE \
287 (MLXBF_I2C_SLAVE_BUSY_BIT | MLXBF_I2C_SLAVE_WRITE_BIT)
288
289#define MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT 22 /* Number of bytes to write. */
290#define MLXBF_I2C_SLAVE_SEND_PEC_SHIFT 21 /* Send PEC byte shift. */
291
292/* SMBus slave GW Data descriptor. */
293#define MLXBF_I2C_SLAVE_DATA_DESC_ADDR 0x80
294#define MLXBF_I2C_SLAVE_DATA_DESC_SIZE 0x80 /* Size in bytes. */
295
296/* SMbus slave configuration registers. */
297#define MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG 0x114
298#define MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT 16
299#define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT BIT(7)
300#define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0)
301
302/*
303 * Timeout is given in microsends. Note also that timeout handling is not
304 * exact.
305 */
306#define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */
307#define MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT (300 * 1000) /* 300ms */
308
309/* Polling frequency in microseconds. */
310#define MLXBF_I2C_POLL_FREQ_IN_USEC 200
311
312#define MLXBF_I2C_SMBUS_OP_CNT_1 1
313#define MLXBF_I2C_SMBUS_OP_CNT_2 2
314#define MLXBF_I2C_SMBUS_OP_CNT_3 3
315#define MLXBF_I2C_SMBUS_MAX_OP_CNT MLXBF_I2C_SMBUS_OP_CNT_3
316
317/* Helper macro to define an I2C resource parameters. */
318#define MLXBF_I2C_RES_PARAMS(addr, size, str) \
319 { \
320 .start = (addr), \
321 .end = (addr) + (size) - 1, \
322 .name = (str) \
323 }
324
325enum {
326 MLXBF_I2C_TIMING_100KHZ = 100000,
327 MLXBF_I2C_TIMING_400KHZ = 400000,
328 MLXBF_I2C_TIMING_1000KHZ = 1000000,
329};
330
331enum {
332 MLXBF_I2C_F_READ = BIT(0),
333 MLXBF_I2C_F_WRITE = BIT(1),
334 MLXBF_I2C_F_NORESTART = BIT(3),
335 MLXBF_I2C_F_SMBUS_OPERATION = BIT(4),
336 MLXBF_I2C_F_SMBUS_BLOCK = BIT(5),
337 MLXBF_I2C_F_SMBUS_PEC = BIT(6),
338 MLXBF_I2C_F_SMBUS_PROCESS_CALL = BIT(7),
339};
340
341/* Mellanox BlueField chip type. */
342enum mlxbf_i2c_chip_type {
343 MLXBF_I2C_CHIP_TYPE_1, /* Mellanox BlueField-1 chip. */
344 MLXBF_I2C_CHIP_TYPE_2, /* Mellanox BlueField-2 chip. */
345 MLXBF_I2C_CHIP_TYPE_3 /* Mellanox BlueField-3 chip. */
346};
347
348/* List of chip resources that are being accessed by the driver. */
349enum {
350 MLXBF_I2C_SMBUS_RES,
351 MLXBF_I2C_MST_CAUSE_RES,
352 MLXBF_I2C_SLV_CAUSE_RES,
353 MLXBF_I2C_COALESCE_RES,
354 MLXBF_I2C_SMBUS_TIMER_RES,
355 MLXBF_I2C_SMBUS_MST_RES,
356 MLXBF_I2C_SMBUS_SLV_RES,
357 MLXBF_I2C_COREPLL_RES,
358 MLXBF_I2C_GPIO_RES,
359 MLXBF_I2C_END_RES
360};
361
362/* Encapsulates timing parameters. */
363struct mlxbf_i2c_timings {
364 u16 scl_high; /* Clock high period. */
365 u16 scl_low; /* Clock low period. */
366 u8 sda_rise; /* Data rise time. */
367 u8 sda_fall; /* Data fall time. */
368 u8 scl_rise; /* Clock rise time. */
369 u8 scl_fall; /* Clock fall time. */
370 u16 hold_start; /* Hold time after (REPEATED) START. */
371 u16 hold_data; /* Data hold time. */
372 u16 setup_start; /* REPEATED START condition setup time. */
373 u16 setup_stop; /* STOP condition setup time. */
374 u16 setup_data; /* Data setup time. */
375 u16 pad; /* Padding. */
376 u16 buf; /* Bus free time between STOP and START. */
377 u16 thigh_max; /* Thigh max. */
378 u32 timeout; /* Detect clock low timeout. */
379};
380
381struct mlxbf_i2c_smbus_operation {
382 u32 flags;
383 u32 length; /* Buffer length in bytes. */
384 u8 *buffer;
385};
386
387struct mlxbf_i2c_smbus_request {
388 u8 slave;
389 u8 operation_cnt;
390 struct mlxbf_i2c_smbus_operation operation[MLXBF_I2C_SMBUS_MAX_OP_CNT];
391};
392
393struct mlxbf_i2c_resource {
394 void __iomem *io;
395 struct resource *params;
396 struct mutex *lock; /* Mutex to protect mlxbf_i2c_resource. */
397 u8 type;
398};
399
400struct mlxbf_i2c_chip_info {
401 enum mlxbf_i2c_chip_type type;
402 /* Chip shared resources that are being used by the I2C controller. */
403 struct mlxbf_i2c_resource *shared_res[MLXBF_I2C_SHARED_RES_MAX];
404
405 /* Callback to calculate the core PLL frequency. */
406 u64 (*calculate_freq)(struct mlxbf_i2c_resource *corepll_res);
407
408 /* Registers' address offset */
409 u32 smbus_master_rs_bytes_off;
410 u32 smbus_master_fsm_off;
411};
412
413struct mlxbf_i2c_priv {
414 const struct mlxbf_i2c_chip_info *chip;
415 struct i2c_adapter adap;
416 struct mlxbf_i2c_resource *smbus;
417 struct mlxbf_i2c_resource *timer;
418 struct mlxbf_i2c_resource *mst;
419 struct mlxbf_i2c_resource *slv;
420 struct mlxbf_i2c_resource *mst_cause;
421 struct mlxbf_i2c_resource *slv_cause;
422 struct mlxbf_i2c_resource *coalesce;
423 u64 frequency; /* Core frequency in Hz. */
424 int bus; /* Physical bus identifier. */
425 int irq;
426 struct i2c_client *slave[MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT];
427 u32 resource_version;
428};
429
430/* Core PLL frequency. */
431static u64 mlxbf_i2c_corepll_frequency;
432
433static struct resource mlxbf_i2c_coalesce_tyu_params =
434 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COALESCE_TYU_ADDR,
435 MLXBF_I2C_COALESCE_TYU_SIZE,
436 "COALESCE_MEM");
437static struct resource mlxbf_i2c_corepll_tyu_params =
438 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_TYU_ADDR,
439 MLXBF_I2C_COREPLL_TYU_SIZE,
440 "COREPLL_MEM");
441static struct resource mlxbf_i2c_corepll_yu_params =
442 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_YU_ADDR,
443 MLXBF_I2C_COREPLL_YU_SIZE,
444 "COREPLL_MEM");
445static struct resource mlxbf_i2c_corepll_rsh_yu_params =
446 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_RSH_YU_ADDR,
447 MLXBF_I2C_COREPLL_RSH_YU_SIZE,
448 "COREPLL_MEM");
449static struct resource mlxbf_i2c_gpio_tyu_params =
450 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_GPIO_TYU_ADDR,
451 MLXBF_I2C_GPIO_TYU_SIZE,
452 "GPIO_MEM");
453
454static struct mutex mlxbf_i2c_coalesce_lock;
455static struct mutex mlxbf_i2c_corepll_lock;
456static struct mutex mlxbf_i2c_gpio_lock;
457
458static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = {
459 [MLXBF_I2C_CHIP_TYPE_1] = {
460 .params = &mlxbf_i2c_coalesce_tyu_params,
461 .lock = &mlxbf_i2c_coalesce_lock,
462 .type = MLXBF_I2C_COALESCE_RES
463 },
464 {}
465};
466
467static struct mlxbf_i2c_resource mlxbf_i2c_corepll_res[] = {
468 [MLXBF_I2C_CHIP_TYPE_1] = {
469 .params = &mlxbf_i2c_corepll_tyu_params,
470 .lock = &mlxbf_i2c_corepll_lock,
471 .type = MLXBF_I2C_COREPLL_RES
472 },
473 [MLXBF_I2C_CHIP_TYPE_2] = {
474 .params = &mlxbf_i2c_corepll_yu_params,
475 .lock = &mlxbf_i2c_corepll_lock,
476 .type = MLXBF_I2C_COREPLL_RES,
477 },
478 [MLXBF_I2C_CHIP_TYPE_3] = {
479 .params = &mlxbf_i2c_corepll_rsh_yu_params,
480 .lock = &mlxbf_i2c_corepll_lock,
481 .type = MLXBF_I2C_COREPLL_RES,
482 }
483};
484
485static struct mlxbf_i2c_resource mlxbf_i2c_gpio_res[] = {
486 [MLXBF_I2C_CHIP_TYPE_1] = {
487 .params = &mlxbf_i2c_gpio_tyu_params,
488 .lock = &mlxbf_i2c_gpio_lock,
489 .type = MLXBF_I2C_GPIO_RES
490 },
491 {}
492};
493
494static u8 mlxbf_i2c_bus_count;
495
496static struct mutex mlxbf_i2c_bus_lock;
497
498/*
499 * Function to poll a set of bits at a specific address; it checks whether
500 * the bits are equal to zero when eq_zero is set to 'true', and not equal
501 * to zero when eq_zero is set to 'false'.
502 * Note that the timeout is given in microseconds.
503 */
504static u32 mlxbf_i2c_poll(void __iomem *io, u32 addr, u32 mask,
505 bool eq_zero, u32 timeout)
506{
507 u32 bits;
508
509 timeout = (timeout / MLXBF_I2C_POLL_FREQ_IN_USEC) + 1;
510
511 do {
512 bits = readl(io + addr) & mask;
513 if (eq_zero ? bits == 0 : bits != 0)
514 return eq_zero ? 1 : bits;
515 udelay(MLXBF_I2C_POLL_FREQ_IN_USEC);
516 } while (timeout-- != 0);
517
518 return 0;
519}
520
521/*
522 * SW must make sure that the SMBus Master GW is idle before starting
523 * a transaction. Accordingly, this function polls the Master FSM stop
524 * bit; it returns false when the bit is asserted, true if not.
525 */
526static bool mlxbf_i2c_smbus_master_wait_for_idle(struct mlxbf_i2c_priv *priv)
527{
528 u32 mask = MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK;
529 u32 addr = priv->chip->smbus_master_fsm_off;
530 u32 timeout = MLXBF_I2C_SMBUS_TIMEOUT;
531
532 if (mlxbf_i2c_poll(priv->mst->io, addr, mask, true, timeout))
533 return true;
534
535 return false;
536}
537
538/*
539 * wait for the lock to be released before acquiring it.
540 */
541static bool mlxbf_i2c_smbus_master_lock(struct mlxbf_i2c_priv *priv)
542{
543 if (mlxbf_i2c_poll(priv->mst->io, MLXBF_I2C_SMBUS_MASTER_GW,
544 MLXBF_I2C_MASTER_LOCK_BIT, true,
545 MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT))
546 return true;
547
548 return false;
549}
550
551static void mlxbf_i2c_smbus_master_unlock(struct mlxbf_i2c_priv *priv)
552{
553 /* Clear the gw to clear the lock */
554 writel(0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW);
555}
556
557static bool mlxbf_i2c_smbus_transaction_success(u32 master_status,
558 u32 cause_status)
559{
560 /*
561 * When transaction ended with STOP, all bytes were transmitted,
562 * and no NACK received, then the transaction ended successfully.
563 * On the other hand, when the GW is configured with the stop bit
564 * de-asserted then the SMBus expects the following GW configuration
565 * for transfer continuation.
566 */
567 if ((cause_status & MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA) ||
568 ((cause_status & MLXBF_I2C_CAUSE_TRANSACTION_ENDED) &&
569 (master_status & MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE) &&
570 !(master_status & MLXBF_I2C_SMBUS_STATUS_NACK_RCV)))
571 return true;
572
573 return false;
574}
575
576/*
577 * Poll SMBus master status and return transaction status,
578 * i.e. whether succeeded or failed. I2C and SMBus fault codes
579 * are returned as negative numbers from most calls, with zero
580 * or some positive number indicating a non-fault return.
581 */
582static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv)
583{
584 u32 master_status_bits;
585 u32 cause_status_bits;
586
587 /*
588 * GW busy bit is raised by the driver and cleared by the HW
589 * when the transaction is completed. The busy bit is a good
590 * indicator of transaction status. So poll the busy bit, and
591 * then read the cause and master status bits to determine if
592 * errors occurred during the transaction.
593 */
594 mlxbf_i2c_poll(priv->mst->io, MLXBF_I2C_SMBUS_MASTER_GW,
595 MLXBF_I2C_MASTER_BUSY_BIT, true,
596 MLXBF_I2C_SMBUS_TIMEOUT);
597
598 /* Read cause status bits. */
599 cause_status_bits = readl(priv->mst_cause->io +
600 MLXBF_I2C_CAUSE_ARBITER);
601 cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK;
602
603 /*
604 * Parse both Cause and Master GW bits, then return transaction status.
605 */
606
607 master_status_bits = readl(priv->mst->io +
608 MLXBF_I2C_SMBUS_MASTER_STATUS);
609 master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK;
610
611 if (mlxbf_i2c_smbus_transaction_success(master_status_bits,
612 cause_status_bits))
613 return 0;
614
615 /*
616 * In case of timeout on GW busy, the ISR will clear busy bit but
617 * transaction ended bits cause will not be set so the transaction
618 * fails. Then, we must check Master GW status bits.
619 */
620 if ((master_status_bits & MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR) &&
621 (cause_status_bits & (MLXBF_I2C_CAUSE_TRANSACTION_ENDED |
622 MLXBF_I2C_CAUSE_M_GW_BUSY_FALL)))
623 return -EIO;
624
625 if (cause_status_bits & MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR)
626 return -EAGAIN;
627
628 return -ETIMEDOUT;
629}
630
631static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv,
632 const u8 *data, u8 length, u32 addr,
633 bool is_master)
634{
635 u8 offset, aligned_length;
636 u32 data32;
637
638 aligned_length = round_up(length, 4);
639
640 /*
641 * Copy data bytes from 4-byte aligned source buffer.
642 * Data copied to the Master GW Data Descriptor MUST be shifted
643 * left so the data starts at the MSB of the descriptor registers
644 * as required by the underlying hardware. Enable byte swapping
645 * when writing data bytes to the 32 * 32-bit HW Data registers
646 * a.k.a Master GW Data Descriptor.
647 */
648 for (offset = 0; offset < aligned_length; offset += sizeof(u32)) {
649 data32 = *((u32 *)(data + offset));
650 if (is_master)
651 iowrite32be(data32, priv->mst->io + addr + offset);
652 else
653 iowrite32be(data32, priv->slv->io + addr + offset);
654 }
655}
656
657static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv,
658 u8 *data, u8 length, u32 addr,
659 bool is_master)
660{
661 u32 data32, mask;
662 u8 byte, offset;
663
664 mask = sizeof(u32) - 1;
665
666 /*
667 * Data bytes in the Master GW Data Descriptor are shifted left
668 * so the data starts at the MSB of the descriptor registers as
669 * set by the underlying hardware. Enable byte swapping while
670 * reading data bytes from the 32 * 32-bit HW Data registers
671 * a.k.a Master GW Data Descriptor.
672 */
673
674 for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) {
675 if (is_master)
676 data32 = ioread32be(priv->mst->io + addr + offset);
677 else
678 data32 = ioread32be(priv->slv->io + addr + offset);
679 *((u32 *)(data + offset)) = data32;
680 }
681
682 if (!(length & mask))
683 return;
684
685 if (is_master)
686 data32 = ioread32be(priv->mst->io + addr + offset);
687 else
688 data32 = ioread32be(priv->slv->io + addr + offset);
689
690 for (byte = 0; byte < (length & mask); byte++) {
691 data[offset + byte] = data32 & GENMASK(7, 0);
692 data32 = ror32(data32, MLXBF_I2C_SHIFT_8);
693 }
694}
695
696static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave,
697 u8 len, u8 block_en, u8 pec_en, bool read)
698{
699 u32 command;
700
701 /* Set Master GW control word. */
702 if (read) {
703 command = MLXBF_I2C_MASTER_ENABLE_READ;
704 command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT);
705 } else {
706 command = MLXBF_I2C_MASTER_ENABLE_WRITE;
707 command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT);
708 }
709 command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT);
710 command |= rol32(block_en, MLXBF_I2C_MASTER_PARSE_EXP_SHIFT);
711 command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT);
712
713 /* Clear status bits. */
714 writel(0x0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_STATUS);
715 /* Set the cause data. */
716 writel(~0x0, priv->mst_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
717 /* Zero PEC byte. */
718 writel(0x0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_PEC);
719 /* Zero byte count. */
720 writel(0x0, priv->mst->io + priv->chip->smbus_master_rs_bytes_off);
721
722 /* GW activation. */
723 writel(command, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW);
724
725 /*
726 * Poll master status and check status bits. An ACK is sent when
727 * completing writing data to the bus (Master 'byte_count_done' bit
728 * is set to 1).
729 */
730 return mlxbf_i2c_smbus_check_status(priv);
731}
732
733static int
734mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv,
735 struct mlxbf_i2c_smbus_request *request)
736{
737 u8 data_desc[MLXBF_I2C_MASTER_DATA_DESC_SIZE] = { 0 };
738 u8 op_idx, data_idx, data_len, write_len, read_len;
739 struct mlxbf_i2c_smbus_operation *operation;
740 u8 read_en, write_en, block_en, pec_en;
741 u8 slave, flags, addr;
742 u8 *read_buf;
743 int ret = 0;
744
745 if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT)
746 return -EINVAL;
747
748 read_buf = NULL;
749 data_idx = 0;
750 read_en = 0;
751 write_en = 0;
752 write_len = 0;
753 read_len = 0;
754 block_en = 0;
755 pec_en = 0;
756 slave = request->slave & GENMASK(6, 0);
757 addr = slave << 1;
758
759 /*
760 * Try to acquire the smbus gw lock before any reads of the GW register since
761 * a read sets the lock.
762 */
763 if (WARN_ON(!mlxbf_i2c_smbus_master_lock(priv)))
764 return -EBUSY;
765
766 /* Check whether the HW is idle */
767 if (WARN_ON(!mlxbf_i2c_smbus_master_wait_for_idle(priv))) {
768 ret = -EBUSY;
769 goto out_unlock;
770 }
771
772 /* Set first byte. */
773 data_desc[data_idx++] = addr;
774
775 for (op_idx = 0; op_idx < request->operation_cnt; op_idx++) {
776 operation = &request->operation[op_idx];
777 flags = operation->flags;
778
779 /*
780 * Note that read and write operations might be handled by a
781 * single command. If the MLXBF_I2C_F_SMBUS_OPERATION is set
782 * then write command byte and set the optional SMBus specific
783 * bits such as block_en and pec_en. These bits MUST be
784 * submitted by the first operation only.
785 */
786 if (op_idx == 0 && flags & MLXBF_I2C_F_SMBUS_OPERATION) {
787 block_en = flags & MLXBF_I2C_F_SMBUS_BLOCK;
788 pec_en = flags & MLXBF_I2C_F_SMBUS_PEC;
789 }
790
791 if (flags & MLXBF_I2C_F_WRITE) {
792 write_en = 1;
793 write_len += operation->length;
794 if (data_idx + operation->length >
795 MLXBF_I2C_MASTER_DATA_DESC_SIZE) {
796 ret = -ENOBUFS;
797 goto out_unlock;
798 }
799 memcpy(data_desc + data_idx,
800 operation->buffer, operation->length);
801 data_idx += operation->length;
802 }
803 /*
804 * We assume that read operations are performed only once per
805 * SMBus transaction. *TBD* protect this statement so it won't
806 * be executed twice? or return an error if we try to read more
807 * than once?
808 */
809 if (flags & MLXBF_I2C_F_READ) {
810 read_en = 1;
811 /* Subtract 1 as required by HW. */
812 read_len = operation->length - 1;
813 read_buf = operation->buffer;
814 }
815 }
816
817 /* Set Master GW data descriptor. */
818 data_len = write_len + 1; /* Add one byte of the slave address. */
819 /*
820 * Note that data_len cannot be 0. Indeed, the slave address byte
821 * must be written to the data registers.
822 */
823 mlxbf_i2c_smbus_write_data(priv, (const u8 *)data_desc, data_len,
824 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true);
825
826 if (write_en) {
827 ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en,
828 pec_en, 0);
829 if (ret)
830 goto out_unlock;
831 }
832
833 if (read_en) {
834 /* Write slave address to Master GW data descriptor. */
835 mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1,
836 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true);
837 ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en,
838 pec_en, 1);
839 if (!ret) {
840 /* Get Master GW data descriptor. */
841 mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1,
842 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true);
843
844 /* Get data from Master GW data descriptor. */
845 memcpy(read_buf, data_desc, read_len + 1);
846 }
847
848 /*
849 * After a read operation the SMBus FSM ps (present state)
850 * needs to be 'manually' reset. This should be removed in
851 * next tag integration.
852 */
853 writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK,
854 priv->mst->io + priv->chip->smbus_master_fsm_off);
855 }
856
857out_unlock:
858 mlxbf_i2c_smbus_master_unlock(priv);
859
860 return ret;
861}
862
863/* I2C SMBus protocols. */
864
865static void
866mlxbf_i2c_smbus_quick_command(struct mlxbf_i2c_smbus_request *request,
867 u8 read)
868{
869 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1;
870
871 request->operation[0].length = 0;
872 request->operation[0].flags = MLXBF_I2C_F_WRITE;
873 request->operation[0].flags |= read ? MLXBF_I2C_F_READ : 0;
874}
875
876static void mlxbf_i2c_smbus_byte_func(struct mlxbf_i2c_smbus_request *request,
877 u8 *data, bool read, bool pec_check)
878{
879 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1;
880
881 request->operation[0].length = 1;
882 request->operation[0].length += pec_check;
883
884 request->operation[0].flags = MLXBF_I2C_F_SMBUS_OPERATION;
885 request->operation[0].flags |= read ?
886 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
887 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
888
889 request->operation[0].buffer = data;
890}
891
892static void
893mlxbf_i2c_smbus_data_byte_func(struct mlxbf_i2c_smbus_request *request,
894 u8 *command, u8 *data, bool read, bool pec_check)
895{
896 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
897
898 request->operation[0].length = 1;
899 request->operation[0].flags =
900 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
901 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
902 request->operation[0].buffer = command;
903
904 request->operation[1].length = 1;
905 request->operation[1].length += pec_check;
906 request->operation[1].flags = read ?
907 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
908 request->operation[1].buffer = data;
909}
910
911static void
912mlxbf_i2c_smbus_data_word_func(struct mlxbf_i2c_smbus_request *request,
913 u8 *command, u8 *data, bool read, bool pec_check)
914{
915 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
916
917 request->operation[0].length = 1;
918 request->operation[0].flags =
919 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
920 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
921 request->operation[0].buffer = command;
922
923 request->operation[1].length = 2;
924 request->operation[1].length += pec_check;
925 request->operation[1].flags = read ?
926 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
927 request->operation[1].buffer = data;
928}
929
930static void
931mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request *request,
932 u8 *command, u8 *data, u8 *data_len, bool read,
933 bool pec_check)
934{
935 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
936
937 request->operation[0].length = 1;
938 request->operation[0].flags =
939 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
940 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
941 request->operation[0].buffer = command;
942
943 /*
944 * As specified in the standard, the max number of bytes to read/write
945 * per block operation is 32 bytes. In Golan code, the controller can
946 * read up to 128 bytes and write up to 127 bytes.
947 */
948 request->operation[1].length =
949 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?
950 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;
951 request->operation[1].flags = read ?
952 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
953 /*
954 * Skip the first data byte, which corresponds to the number of bytes
955 * to read/write.
956 */
957 request->operation[1].buffer = data + 1;
958
959 *data_len = request->operation[1].length;
960
961 /* Set the number of byte to read. This will be used by userspace. */
962 if (read)
963 data[0] = *data_len;
964}
965
966static void mlxbf_i2c_smbus_block_func(struct mlxbf_i2c_smbus_request *request,
967 u8 *command, u8 *data, u8 *data_len,
968 bool read, bool pec_check)
969{
970 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
971
972 request->operation[0].length = 1;
973 request->operation[0].flags =
974 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
975 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;
976 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
977 request->operation[0].buffer = command;
978
979 request->operation[1].length =
980 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?
981 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;
982 request->operation[1].flags = read ?
983 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
984 request->operation[1].buffer = data + 1;
985
986 *data_len = request->operation[1].length;
987
988 /* Set the number of bytes to read. This will be used by userspace. */
989 if (read)
990 data[0] = *data_len;
991}
992
993static void
994mlxbf_i2c_smbus_process_call_func(struct mlxbf_i2c_smbus_request *request,
995 u8 *command, u8 *data, bool pec_check)
996{
997 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3;
998
999 request->operation[0].length = 1;
1000 request->operation[0].flags =
1001 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
1002 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;
1003 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
1004 request->operation[0].buffer = command;
1005
1006 request->operation[1].length = 2;
1007 request->operation[1].flags = MLXBF_I2C_F_WRITE;
1008 request->operation[1].buffer = data;
1009
1010 request->operation[2].length = 3;
1011 request->operation[2].flags = MLXBF_I2C_F_READ;
1012 request->operation[2].buffer = data;
1013}
1014
1015static void
1016mlxbf_i2c_smbus_blk_process_call_func(struct mlxbf_i2c_smbus_request *request,
1017 u8 *command, u8 *data, u8 *data_len,
1018 bool pec_check)
1019{
1020 u32 length;
1021
1022 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3;
1023
1024 request->operation[0].length = 1;
1025 request->operation[0].flags =
1026 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
1027 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;
1028 request->operation[0].flags |= (pec_check) ? MLXBF_I2C_F_SMBUS_PEC : 0;
1029 request->operation[0].buffer = command;
1030
1031 length = (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?
1032 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;
1033
1034 request->operation[1].length = length - pec_check;
1035 request->operation[1].flags = MLXBF_I2C_F_WRITE;
1036 request->operation[1].buffer = data;
1037
1038 request->operation[2].length = length;
1039 request->operation[2].flags = MLXBF_I2C_F_READ;
1040 request->operation[2].buffer = data;
1041
1042 *data_len = length; /* including PEC byte. */
1043}
1044
1045/* Initialization functions. */
1046
1047static bool mlxbf_i2c_has_chip_type(struct mlxbf_i2c_priv *priv, u8 type)
1048{
1049 return priv->chip->type == type;
1050}
1051
1052static struct mlxbf_i2c_resource *
1053mlxbf_i2c_get_shared_resource(struct mlxbf_i2c_priv *priv, u8 type)
1054{
1055 const struct mlxbf_i2c_chip_info *chip = priv->chip;
1056 struct mlxbf_i2c_resource *res;
1057 u8 res_idx = 0;
1058
1059 for (res_idx = 0; res_idx < MLXBF_I2C_SHARED_RES_MAX; res_idx++) {
1060 res = chip->shared_res[res_idx];
1061 if (res && res->type == type)
1062 return res;
1063 }
1064
1065 return NULL;
1066}
1067
1068static int mlxbf_i2c_init_resource(struct platform_device *pdev,
1069 struct mlxbf_i2c_resource **res,
1070 u8 type)
1071{
1072 struct mlxbf_i2c_resource *tmp_res;
1073 struct device *dev = &pdev->dev;
1074
1075 if (!res || *res || type >= MLXBF_I2C_END_RES)
1076 return -EINVAL;
1077
1078 tmp_res = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource),
1079 GFP_KERNEL);
1080 if (!tmp_res)
1081 return -ENOMEM;
1082
1083 tmp_res->params = platform_get_resource(pdev, IORESOURCE_MEM, type);
1084 if (!tmp_res->params) {
1085 devm_kfree(dev, tmp_res);
1086 return -EIO;
1087 }
1088
1089 tmp_res->io = devm_ioremap_resource(dev, tmp_res->params);
1090 if (IS_ERR(tmp_res->io)) {
1091 devm_kfree(dev, tmp_res);
1092 return PTR_ERR(tmp_res->io);
1093 }
1094
1095 tmp_res->type = type;
1096
1097 *res = tmp_res;
1098
1099 return 0;
1100}
1101
1102static u32 mlxbf_i2c_get_ticks(struct mlxbf_i2c_priv *priv, u64 nanoseconds,
1103 bool minimum)
1104{
1105 u64 frequency;
1106 u32 ticks;
1107
1108 /*
1109 * Compute ticks as follow:
1110 *
1111 * Ticks
1112 * Time = --------- x 10^9 => Ticks = Time x Frequency x 10^-9
1113 * Frequency
1114 */
1115 frequency = priv->frequency;
1116 ticks = (nanoseconds * frequency) / MLXBF_I2C_FREQUENCY_1GHZ;
1117 /*
1118 * The number of ticks is rounded down and if minimum is equal to 1
1119 * then add one tick.
1120 */
1121 if (minimum)
1122 ticks++;
1123
1124 return ticks;
1125}
1126
1127static u32 mlxbf_i2c_set_timer(struct mlxbf_i2c_priv *priv, u64 nsec, bool opt,
1128 u32 mask, u8 shift)
1129{
1130 u32 val = (mlxbf_i2c_get_ticks(priv, nsec, opt) & mask) << shift;
1131
1132 return val;
1133}
1134
1135static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv,
1136 const struct mlxbf_i2c_timings *timings)
1137{
1138 u32 timer;
1139
1140 timer = mlxbf_i2c_set_timer(priv, timings->scl_high,
1141 false, MLXBF_I2C_MASK_16,
1142 MLXBF_I2C_SHIFT_0);
1143 timer |= mlxbf_i2c_set_timer(priv, timings->scl_low,
1144 false, MLXBF_I2C_MASK_16,
1145 MLXBF_I2C_SHIFT_16);
1146 writel(timer, priv->timer->io +
1147 MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH);
1148
1149 timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false,
1150 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0);
1151 timer |= mlxbf_i2c_set_timer(priv, timings->sda_fall, false,
1152 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_8);
1153 timer |= mlxbf_i2c_set_timer(priv, timings->scl_rise, false,
1154 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16);
1155 timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false,
1156 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24);
1157 writel(timer, priv->timer->io +
1158 MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE);
1159
1160 timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true,
1161 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
1162 timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true,
1163 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
1164 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_TIMER_THOLD);
1165
1166 timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true,
1167 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
1168 timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true,
1169 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
1170 writel(timer, priv->timer->io +
1171 MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP);
1172
1173 timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true,
1174 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
1175 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA);
1176
1177 timer = mlxbf_i2c_set_timer(priv, timings->buf, false,
1178 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
1179 timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false,
1180 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
1181 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF);
1182
1183 timer = timings->timeout;
1184 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT);
1185}
1186
1187enum mlxbf_i2c_timings_config {
1188 MLXBF_I2C_TIMING_CONFIG_100KHZ,
1189 MLXBF_I2C_TIMING_CONFIG_400KHZ,
1190 MLXBF_I2C_TIMING_CONFIG_1000KHZ,
1191};
1192
1193/*
1194 * Note that the mlxbf_i2c_timings->timeout value is not related to the
1195 * bus frequency, it is impacted by the time it takes the driver to
1196 * complete data transmission before transaction abort.
1197 */
1198static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = {
1199 [MLXBF_I2C_TIMING_CONFIG_100KHZ] = {
1200 .scl_high = 4810,
1201 .scl_low = 5000,
1202 .hold_start = 4000,
1203 .setup_start = 4800,
1204 .setup_stop = 4000,
1205 .setup_data = 250,
1206 .sda_rise = 50,
1207 .sda_fall = 50,
1208 .scl_rise = 50,
1209 .scl_fall = 50,
1210 .hold_data = 300,
1211 .buf = 20000,
1212 .thigh_max = 5000,
1213 .timeout = 106500
1214 },
1215 [MLXBF_I2C_TIMING_CONFIG_400KHZ] = {
1216 .scl_high = 1011,
1217 .scl_low = 1300,
1218 .hold_start = 600,
1219 .setup_start = 700,
1220 .setup_stop = 600,
1221 .setup_data = 100,
1222 .sda_rise = 50,
1223 .sda_fall = 50,
1224 .scl_rise = 50,
1225 .scl_fall = 50,
1226 .hold_data = 300,
1227 .buf = 20000,
1228 .thigh_max = 5000,
1229 .timeout = 106500
1230 },
1231 [MLXBF_I2C_TIMING_CONFIG_1000KHZ] = {
1232 .scl_high = 600,
1233 .scl_low = 1300,
1234 .hold_start = 600,
1235 .setup_start = 600,
1236 .setup_stop = 600,
1237 .setup_data = 100,
1238 .sda_rise = 50,
1239 .sda_fall = 50,
1240 .scl_rise = 50,
1241 .scl_fall = 50,
1242 .hold_data = 300,
1243 .buf = 20000,
1244 .thigh_max = 5000,
1245 .timeout = 106500
1246 }
1247};
1248
1249static int mlxbf_i2c_init_timings(struct platform_device *pdev,
1250 struct mlxbf_i2c_priv *priv)
1251{
1252 enum mlxbf_i2c_timings_config config_idx;
1253 struct device *dev = &pdev->dev;
1254 u32 config_khz;
1255
1256 int ret;
1257
1258 ret = device_property_read_u32(dev, "clock-frequency", &config_khz);
1259 if (ret < 0)
1260 config_khz = I2C_MAX_STANDARD_MODE_FREQ;
1261
1262 switch (config_khz) {
1263 default:
1264 /* Default settings is 100 KHz. */
1265 pr_warn("Illegal value %d: defaulting to 100 KHz\n",
1266 config_khz);
1267 fallthrough;
1268 case I2C_MAX_STANDARD_MODE_FREQ:
1269 config_idx = MLXBF_I2C_TIMING_CONFIG_100KHZ;
1270 break;
1271
1272 case I2C_MAX_FAST_MODE_FREQ:
1273 config_idx = MLXBF_I2C_TIMING_CONFIG_400KHZ;
1274 break;
1275
1276 case I2C_MAX_FAST_MODE_PLUS_FREQ:
1277 config_idx = MLXBF_I2C_TIMING_CONFIG_1000KHZ;
1278 break;
1279 }
1280
1281 mlxbf_i2c_set_timings(priv, &mlxbf_i2c_timings[config_idx]);
1282
1283 return 0;
1284}
1285
1286static int mlxbf_i2c_get_gpio(struct platform_device *pdev,
1287 struct mlxbf_i2c_priv *priv)
1288{
1289 struct mlxbf_i2c_resource *gpio_res;
1290 struct device *dev = &pdev->dev;
1291 struct resource *params;
1292 resource_size_t size;
1293
1294 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);
1295 if (!gpio_res)
1296 return -EPERM;
1297
1298 /*
1299 * The GPIO region in TYU space is shared among I2C busses.
1300 * This function MUST be serialized to avoid racing when
1301 * claiming the memory region and/or setting up the GPIO.
1302 */
1303 lockdep_assert_held(gpio_res->lock);
1304
1305 /* Check whether the memory map exist. */
1306 if (gpio_res->io)
1307 return 0;
1308
1309 params = gpio_res->params;
1310 size = resource_size(params);
1311
1312 if (!devm_request_mem_region(dev, params->start, size, params->name))
1313 return -EFAULT;
1314
1315 gpio_res->io = devm_ioremap(dev, params->start, size);
1316 if (!gpio_res->io) {
1317 devm_release_mem_region(dev, params->start, size);
1318 return -ENOMEM;
1319 }
1320
1321 return 0;
1322}
1323
1324static int mlxbf_i2c_release_gpio(struct platform_device *pdev,
1325 struct mlxbf_i2c_priv *priv)
1326{
1327 struct mlxbf_i2c_resource *gpio_res;
1328 struct device *dev = &pdev->dev;
1329 struct resource *params;
1330
1331 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);
1332 if (!gpio_res)
1333 return 0;
1334
1335 mutex_lock(gpio_res->lock);
1336
1337 if (gpio_res->io) {
1338 /* Release the GPIO resource. */
1339 params = gpio_res->params;
1340 devm_iounmap(dev, gpio_res->io);
1341 devm_release_mem_region(dev, params->start,
1342 resource_size(params));
1343 }
1344
1345 mutex_unlock(gpio_res->lock);
1346
1347 return 0;
1348}
1349
1350static int mlxbf_i2c_get_corepll(struct platform_device *pdev,
1351 struct mlxbf_i2c_priv *priv)
1352{
1353 struct mlxbf_i2c_resource *corepll_res;
1354 struct device *dev = &pdev->dev;
1355 struct resource *params;
1356 resource_size_t size;
1357
1358 corepll_res = mlxbf_i2c_get_shared_resource(priv,
1359 MLXBF_I2C_COREPLL_RES);
1360 if (!corepll_res)
1361 return -EPERM;
1362
1363 /*
1364 * The COREPLL region in TYU space is shared among I2C busses.
1365 * This function MUST be serialized to avoid racing when
1366 * claiming the memory region.
1367 */
1368 lockdep_assert_held(corepll_res->lock);
1369
1370 /* Check whether the memory map exist. */
1371 if (corepll_res->io)
1372 return 0;
1373
1374 params = corepll_res->params;
1375 size = resource_size(params);
1376
1377 if (!devm_request_mem_region(dev, params->start, size, params->name))
1378 return -EFAULT;
1379
1380 corepll_res->io = devm_ioremap(dev, params->start, size);
1381 if (!corepll_res->io) {
1382 devm_release_mem_region(dev, params->start, size);
1383 return -ENOMEM;
1384 }
1385
1386 return 0;
1387}
1388
1389static int mlxbf_i2c_release_corepll(struct platform_device *pdev,
1390 struct mlxbf_i2c_priv *priv)
1391{
1392 struct mlxbf_i2c_resource *corepll_res;
1393 struct device *dev = &pdev->dev;
1394 struct resource *params;
1395
1396 corepll_res = mlxbf_i2c_get_shared_resource(priv,
1397 MLXBF_I2C_COREPLL_RES);
1398
1399 mutex_lock(corepll_res->lock);
1400
1401 if (corepll_res->io) {
1402 /* Release the CorePLL resource. */
1403 params = corepll_res->params;
1404 devm_iounmap(dev, corepll_res->io);
1405 devm_release_mem_region(dev, params->start,
1406 resource_size(params));
1407 }
1408
1409 mutex_unlock(corepll_res->lock);
1410
1411 return 0;
1412}
1413
1414static int mlxbf_i2c_init_master(struct platform_device *pdev,
1415 struct mlxbf_i2c_priv *priv)
1416{
1417 struct mlxbf_i2c_resource *gpio_res;
1418 struct device *dev = &pdev->dev;
1419 u32 config_reg;
1420 int ret;
1421
1422 /* This configuration is only needed for BlueField 1. */
1423 if (!mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1))
1424 return 0;
1425
1426 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);
1427 if (!gpio_res)
1428 return -EPERM;
1429
1430 /*
1431 * The GPIO region in TYU space is shared among I2C busses.
1432 * This function MUST be serialized to avoid racing when
1433 * claiming the memory region and/or setting up the GPIO.
1434 */
1435
1436 mutex_lock(gpio_res->lock);
1437
1438 ret = mlxbf_i2c_get_gpio(pdev, priv);
1439 if (ret < 0) {
1440 dev_err(dev, "Failed to get gpio resource");
1441 mutex_unlock(gpio_res->lock);
1442 return ret;
1443 }
1444
1445 /*
1446 * TYU - Configuration for GPIO pins. Those pins must be asserted in
1447 * MLXBF_I2C_GPIO_0_FUNC_EN_0, i.e. GPIO 0 is controlled by HW, and must
1448 * be reset in MLXBF_I2C_GPIO_0_FORCE_OE_EN, i.e. GPIO_OE will be driven
1449 * instead of HW_OE.
1450 * For now, we do not reset the GPIO state when the driver is removed.
1451 * First, it is not necessary to disable the bus since we are using
1452 * the same busses. Then, some busses might be shared among Linux and
1453 * platform firmware; disabling the bus might compromise the system
1454 * functionality.
1455 */
1456 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
1457 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus,
1458 config_reg);
1459 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
1460
1461 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
1462 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus,
1463 config_reg);
1464 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
1465
1466 mutex_unlock(gpio_res->lock);
1467
1468 return 0;
1469}
1470
1471static u64 mlxbf_i2c_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res)
1472{
1473 u64 core_frequency;
1474 u8 core_od, core_r;
1475 u32 corepll_val;
1476 u16 core_f;
1477
1478 corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
1479
1480 /* Get Core PLL configuration bits. */
1481 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_TYU_MASK, corepll_val);
1482 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK, corepll_val);
1483 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_TYU_MASK, corepll_val);
1484
1485 /*
1486 * Compute PLL output frequency as follow:
1487 *
1488 * CORE_F + 1
1489 * PLL_OUT_FREQ = PLL_IN_FREQ * ----------------------------
1490 * (CORE_R + 1) * (CORE_OD + 1)
1491 *
1492 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency
1493 * and PadFrequency, respectively.
1494 */
1495 core_frequency = MLXBF_I2C_PLL_IN_FREQ * (++core_f);
1496 core_frequency /= (++core_r) * (++core_od);
1497
1498 return core_frequency;
1499}
1500
1501static u64 mlxbf_i2c_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res)
1502{
1503 u32 corepll_reg1_val, corepll_reg2_val;
1504 u64 corepll_frequency;
1505 u8 core_od, core_r;
1506 u32 core_f;
1507
1508 corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
1509 corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2);
1510
1511 /* Get Core PLL configuration bits */
1512 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_YU_MASK, corepll_reg1_val);
1513 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_YU_MASK, corepll_reg1_val);
1514 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_YU_MASK, corepll_reg2_val);
1515
1516 /*
1517 * Compute PLL output frequency as follow:
1518 *
1519 * CORE_F / 16384
1520 * PLL_OUT_FREQ = PLL_IN_FREQ * ----------------------------
1521 * (CORE_R + 1) * (CORE_OD + 1)
1522 *
1523 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency
1524 * and PadFrequency, respectively.
1525 */
1526 corepll_frequency = (MLXBF_I2C_PLL_IN_FREQ * core_f) / MLNXBF_I2C_COREPLL_CONST;
1527 corepll_frequency /= (++core_r) * (++core_od);
1528
1529 return corepll_frequency;
1530}
1531
1532static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev,
1533 struct mlxbf_i2c_priv *priv)
1534{
1535 const struct mlxbf_i2c_chip_info *chip = priv->chip;
1536 struct mlxbf_i2c_resource *corepll_res;
1537 struct device *dev = &pdev->dev;
1538 u64 *freq = &priv->frequency;
1539 int ret;
1540
1541 corepll_res = mlxbf_i2c_get_shared_resource(priv,
1542 MLXBF_I2C_COREPLL_RES);
1543 if (!corepll_res)
1544 return -EPERM;
1545
1546 /*
1547 * First, check whether the TYU core Clock frequency is set.
1548 * The TYU core frequency is the same for all I2C busses; when
1549 * the first device gets probed the frequency is determined and
1550 * stored into a globally visible variable. So, first of all,
1551 * check whether the frequency is already set. Here, we assume
1552 * that the frequency is expected to be greater than 0.
1553 */
1554 mutex_lock(corepll_res->lock);
1555 if (!mlxbf_i2c_corepll_frequency) {
1556 if (!chip->calculate_freq) {
1557 mutex_unlock(corepll_res->lock);
1558 return -EPERM;
1559 }
1560
1561 ret = mlxbf_i2c_get_corepll(pdev, priv);
1562 if (ret < 0) {
1563 dev_err(dev, "Failed to get corePLL resource");
1564 mutex_unlock(corepll_res->lock);
1565 return ret;
1566 }
1567
1568 mlxbf_i2c_corepll_frequency = chip->calculate_freq(corepll_res);
1569 }
1570 mutex_unlock(corepll_res->lock);
1571
1572 *freq = mlxbf_i2c_corepll_frequency;
1573
1574 return 0;
1575}
1576
1577static int mlxbf_i2c_slave_enable(struct mlxbf_i2c_priv *priv,
1578 struct i2c_client *slave)
1579{
1580 u8 reg, reg_cnt, byte, addr_tmp;
1581 u32 slave_reg, slave_reg_tmp;
1582
1583 if (!priv)
1584 return -EPERM;
1585
1586 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2;
1587
1588 /*
1589 * Read the slave registers. There are 4 * 32-bit slave registers.
1590 * Each slave register can hold up to 4 * 8-bit slave configuration:
1591 * 1) A 7-bit address
1592 * 2) And a status bit (1 if enabled, 0 if not).
1593 * Look for the next available slave register slot.
1594 */
1595 for (reg = 0; reg < reg_cnt; reg++) {
1596 slave_reg = readl(priv->slv->io +
1597 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
1598 /*
1599 * Each register holds 4 slave addresses. So, we have to keep
1600 * the byte order consistent with the value read in order to
1601 * update the register correctly, if needed.
1602 */
1603 slave_reg_tmp = slave_reg;
1604 for (byte = 0; byte < 4; byte++) {
1605 addr_tmp = slave_reg_tmp & GENMASK(7, 0);
1606
1607 /*
1608 * If an enable bit is not set in the
1609 * MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG register, then the
1610 * slave address slot associated with that bit is
1611 * free. So set the enable bit and write the
1612 * slave address bits.
1613 */
1614 if (!(addr_tmp & MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT)) {
1615 slave_reg &= ~(MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK << (byte * 8));
1616 slave_reg |= (slave->addr << (byte * 8));
1617 slave_reg |= MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT << (byte * 8);
1618 writel(slave_reg, priv->slv->io +
1619 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
1620 (reg * 0x4));
1621
1622 /*
1623 * Set the slave at the corresponding index.
1624 */
1625 priv->slave[(reg * 4) + byte] = slave;
1626
1627 return 0;
1628 }
1629
1630 /* Parse next byte. */
1631 slave_reg_tmp >>= 8;
1632 }
1633 }
1634
1635 return -EBUSY;
1636}
1637
1638static int mlxbf_i2c_slave_disable(struct mlxbf_i2c_priv *priv, u8 addr)
1639{
1640 u8 addr_tmp, reg, reg_cnt, byte;
1641 u32 slave_reg, slave_reg_tmp;
1642
1643 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2;
1644
1645 /*
1646 * Read the slave registers. There are 4 * 32-bit slave registers.
1647 * Each slave register can hold up to 4 * 8-bit slave configuration:
1648 * 1) A 7-bit address
1649 * 2) And a status bit (1 if enabled, 0 if not).
1650 * Check if addr is present in the registers.
1651 */
1652 for (reg = 0; reg < reg_cnt; reg++) {
1653 slave_reg = readl(priv->slv->io +
1654 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
1655
1656 /* Check whether the address slots are empty. */
1657 if (!slave_reg)
1658 continue;
1659
1660 /*
1661 * Check if addr matches any of the 4 slave addresses
1662 * in the register.
1663 */
1664 slave_reg_tmp = slave_reg;
1665 for (byte = 0; byte < 4; byte++) {
1666 addr_tmp = slave_reg_tmp & MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK;
1667 /*
1668 * Parse slave address bytes and check whether the
1669 * slave address already exists.
1670 */
1671 if (addr_tmp == addr) {
1672 /* Clear the slave address slot. */
1673 slave_reg &= ~(GENMASK(7, 0) << (byte * 8));
1674 writel(slave_reg, priv->slv->io +
1675 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
1676 (reg * 0x4));
1677 /* Free slave at the corresponding index */
1678 priv->slave[(reg * 4) + byte] = NULL;
1679
1680 return 0;
1681 }
1682
1683 /* Parse next byte. */
1684 slave_reg_tmp >>= 8;
1685 }
1686 }
1687
1688 return -ENXIO;
1689}
1690
1691static int mlxbf_i2c_init_coalesce(struct platform_device *pdev,
1692 struct mlxbf_i2c_priv *priv)
1693{
1694 struct mlxbf_i2c_resource *coalesce_res;
1695 struct resource *params;
1696 resource_size_t size;
1697 int ret = 0;
1698
1699 /*
1700 * Unlike BlueField-1 platform, the coalesce registers is a dedicated
1701 * resource in the next generations of BlueField.
1702 */
1703 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) {
1704 coalesce_res = mlxbf_i2c_get_shared_resource(priv,
1705 MLXBF_I2C_COALESCE_RES);
1706 if (!coalesce_res)
1707 return -EPERM;
1708
1709 /*
1710 * The Cause Coalesce group in TYU space is shared among
1711 * I2C busses. This function MUST be serialized to avoid
1712 * racing when claiming the memory region.
1713 */
1714 lockdep_assert_held(mlxbf_i2c_gpio_res->lock);
1715
1716 /* Check whether the memory map exist. */
1717 if (coalesce_res->io) {
1718 priv->coalesce = coalesce_res;
1719 return 0;
1720 }
1721
1722 params = coalesce_res->params;
1723 size = resource_size(params);
1724
1725 if (!request_mem_region(params->start, size, params->name))
1726 return -EFAULT;
1727
1728 coalesce_res->io = ioremap(params->start, size);
1729 if (!coalesce_res->io) {
1730 release_mem_region(params->start, size);
1731 return -ENOMEM;
1732 }
1733
1734 priv->coalesce = coalesce_res;
1735
1736 } else {
1737 ret = mlxbf_i2c_init_resource(pdev, &priv->coalesce,
1738 MLXBF_I2C_COALESCE_RES);
1739 }
1740
1741 return ret;
1742}
1743
1744static int mlxbf_i2c_release_coalesce(struct platform_device *pdev,
1745 struct mlxbf_i2c_priv *priv)
1746{
1747 struct mlxbf_i2c_resource *coalesce_res;
1748 struct device *dev = &pdev->dev;
1749 struct resource *params;
1750 resource_size_t size;
1751
1752 coalesce_res = priv->coalesce;
1753
1754 if (coalesce_res->io) {
1755 params = coalesce_res->params;
1756 size = resource_size(params);
1757 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) {
1758 mutex_lock(coalesce_res->lock);
1759 iounmap(coalesce_res->io);
1760 release_mem_region(params->start, size);
1761 mutex_unlock(coalesce_res->lock);
1762 } else {
1763 devm_release_mem_region(dev, params->start, size);
1764 }
1765 }
1766
1767 return 0;
1768}
1769
1770static int mlxbf_i2c_init_slave(struct platform_device *pdev,
1771 struct mlxbf_i2c_priv *priv)
1772{
1773 struct device *dev = &pdev->dev;
1774 u32 int_reg;
1775 int ret;
1776
1777 /* Reset FSM. */
1778 writel(0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_FSM);
1779
1780 /*
1781 * Enable slave cause interrupt bits. Drive
1782 * MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE and
1783 * MLXBF_I2C_CAUSE_WRITE_SUCCESS, these are enabled when an external
1784 * masters issue a Read and Write, respectively. But, clear all
1785 * interrupts first.
1786 */
1787 writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
1788 int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE;
1789 int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS;
1790 writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0);
1791
1792 /* Finally, set the 'ready' bit to start handling transactions. */
1793 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY);
1794
1795 /* Initialize the cause coalesce resource. */
1796 ret = mlxbf_i2c_init_coalesce(pdev, priv);
1797 if (ret < 0) {
1798 dev_err(dev, "failed to initialize cause coalesce\n");
1799 return ret;
1800 }
1801
1802 return 0;
1803}
1804
1805static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read,
1806 bool *write)
1807{
1808 const struct mlxbf_i2c_chip_info *chip = priv->chip;
1809 u32 coalesce0_reg, cause_reg;
1810 u8 slave_shift, is_set;
1811
1812 *write = false;
1813 *read = false;
1814
1815 slave_shift = chip->type != MLXBF_I2C_CHIP_TYPE_1 ?
1816 MLXBF_I2C_CAUSE_YU_SLAVE_BIT :
1817 priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT;
1818
1819 coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0);
1820 is_set = coalesce0_reg & (1 << slave_shift);
1821
1822 if (!is_set)
1823 return false;
1824
1825 /* Check the source of the interrupt, i.e. whether a Read or Write. */
1826 cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER);
1827 if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE)
1828 *read = true;
1829 else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS)
1830 *write = true;
1831
1832 /* Clear cause bits. */
1833 writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
1834
1835 return true;
1836}
1837
1838static bool mlxbf_i2c_slave_wait_for_idle(struct mlxbf_i2c_priv *priv,
1839 u32 timeout)
1840{
1841 u32 mask = MLXBF_I2C_CAUSE_S_GW_BUSY_FALL;
1842 u32 addr = MLXBF_I2C_CAUSE_ARBITER;
1843
1844 if (mlxbf_i2c_poll(priv->slv_cause->io, addr, mask, false, timeout))
1845 return true;
1846
1847 return false;
1848}
1849
1850static struct i2c_client *mlxbf_i2c_get_slave_from_addr(
1851 struct mlxbf_i2c_priv *priv, u8 addr)
1852{
1853 int i;
1854
1855 for (i = 0; i < MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT; i++) {
1856 if (!priv->slave[i])
1857 continue;
1858
1859 if (priv->slave[i]->addr == addr)
1860 return priv->slave[i];
1861 }
1862
1863 return NULL;
1864}
1865
1866/*
1867 * Send byte to 'external' smbus master. This function is executed when
1868 * an external smbus master wants to read data from the BlueField.
1869 */
1870static int mlxbf_i2c_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
1871{
1872 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 };
1873 u8 write_size, pec_en, addr, value, byte_cnt;
1874 struct i2c_client *slave;
1875 u32 control32, data32;
1876 int ret = 0;
1877
1878 /*
1879 * Read the first byte received from the external master to
1880 * determine the slave address. This byte is located in the
1881 * first data descriptor register of the slave GW.
1882 */
1883 data32 = ioread32be(priv->slv->io +
1884 MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
1885 addr = (data32 & GENMASK(7, 0)) >> 1;
1886
1887 /*
1888 * Check if the slave address received in the data descriptor register
1889 * matches any of the slave addresses registered. If there is a match,
1890 * set the slave.
1891 */
1892 slave = mlxbf_i2c_get_slave_from_addr(priv, addr);
1893 if (!slave) {
1894 ret = -ENXIO;
1895 goto clear_csr;
1896 }
1897
1898 /*
1899 * An I2C read can consist of a WRITE bit transaction followed by
1900 * a READ bit transaction. Indeed, slave devices often expect
1901 * the slave address to be followed by the internal address.
1902 * So, write the internal address byte first, and then, send the
1903 * requested data to the master.
1904 */
1905 if (recv_bytes > 1) {
1906 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1907 value = (data32 >> 8) & GENMASK(7, 0);
1908 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED,
1909 &value);
1910 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
1911
1912 if (ret < 0)
1913 goto clear_csr;
1914 }
1915
1916 /*
1917 * Send data to the master. Currently, the driver supports
1918 * READ_BYTE, READ_WORD and BLOCK READ protocols. The
1919 * hardware can send up to 128 bytes per transfer which is
1920 * the total size of the data registers.
1921 */
1922 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1923
1924 for (byte_cnt = 0; byte_cnt < MLXBF_I2C_SLAVE_DATA_DESC_SIZE; byte_cnt++) {
1925 data_desc[byte_cnt] = value;
1926 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
1927 }
1928
1929 /* Send a stop condition to the backend. */
1930 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
1931
1932 /* Set the number of bytes to write to master. */
1933 write_size = (byte_cnt - 1) & 0x7f;
1934
1935 /* Write data to Slave GW data descriptor. */
1936 mlxbf_i2c_smbus_write_data(priv, data_desc, byte_cnt,
1937 MLXBF_I2C_SLAVE_DATA_DESC_ADDR, false);
1938
1939 pec_en = 0; /* Disable PEC since it is not supported. */
1940
1941 /* Prepare control word. */
1942 control32 = MLXBF_I2C_SLAVE_ENABLE;
1943 control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT);
1944 control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT);
1945
1946 writel(control32, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_GW);
1947
1948 /*
1949 * Wait until the transfer is completed; the driver will wait
1950 * until the GW is idle, a cause will rise on fall of GW busy.
1951 */
1952 mlxbf_i2c_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT);
1953
1954clear_csr:
1955 /* Release the Slave GW. */
1956 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
1957 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
1958 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY);
1959
1960 return ret;
1961}
1962
1963/*
1964 * Receive bytes from 'external' smbus master. This function is executed when
1965 * an external smbus master wants to write data to the BlueField.
1966 */
1967static int mlxbf_i2c_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
1968{
1969 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 };
1970 struct i2c_client *slave;
1971 u8 value, byte, addr;
1972 int ret = 0;
1973
1974 /* Read data from Slave GW data descriptor. */
1975 mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes,
1976 MLXBF_I2C_SLAVE_DATA_DESC_ADDR, false);
1977 addr = data_desc[0] >> 1;
1978
1979 /*
1980 * Check if the slave address received in the data descriptor register
1981 * matches any of the slave addresses registered.
1982 */
1983 slave = mlxbf_i2c_get_slave_from_addr(priv, addr);
1984 if (!slave) {
1985 ret = -EINVAL;
1986 goto clear_csr;
1987 }
1988
1989 /*
1990 * Notify the slave backend that an smbus master wants to write data
1991 * to the BlueField.
1992 */
1993 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1994
1995 /* Send the received data to the slave backend. */
1996 for (byte = 1; byte < recv_bytes; byte++) {
1997 value = data_desc[byte];
1998 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED,
1999 &value);
2000 if (ret < 0)
2001 break;
2002 }
2003
2004 /*
2005 * Send a stop event to the slave backend, to signal
2006 * the end of the write transactions.
2007 */
2008 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
2009
2010clear_csr:
2011 /* Release the Slave GW. */
2012 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
2013 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
2014 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY);
2015
2016 return ret;
2017}
2018
2019static irqreturn_t mlxbf_i2c_irq(int irq, void *ptr)
2020{
2021 struct mlxbf_i2c_priv *priv = ptr;
2022 bool read, write, irq_is_set;
2023 u32 rw_bytes_reg;
2024 u8 recv_bytes;
2025
2026 /*
2027 * Read TYU interrupt register and determine the source of the
2028 * interrupt. Based on the source of the interrupt one of the
2029 * following actions are performed:
2030 * - Receive data and send response to master.
2031 * - Send data and release slave GW.
2032 *
2033 * Handle read/write transaction only. CRmaster and Iarp requests
2034 * are ignored for now.
2035 */
2036 irq_is_set = mlxbf_i2c_has_coalesce(priv, &read, &write);
2037 if (!irq_is_set || (!read && !write)) {
2038 /* Nothing to do here, interrupt was not from this device. */
2039 return IRQ_NONE;
2040 }
2041
2042 /*
2043 * The MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES includes the number of
2044 * bytes from/to master. These are defined by 8-bits each. If the lower
2045 * 8 bits are set, then the master expect to read N bytes from the
2046 * slave, if the higher 8 bits are sent then the slave expect N bytes
2047 * from the master.
2048 */
2049 rw_bytes_reg = readl(priv->slv->io +
2050 MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
2051 recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0);
2052
2053 /*
2054 * For now, the slave supports 128 bytes transfer. Discard remaining
2055 * data bytes if the master wrote more than
2056 * MLXBF_I2C_SLAVE_DATA_DESC_SIZE, i.e, the actual size of the slave
2057 * data descriptor.
2058 *
2059 * Note that we will never expect to transfer more than 128 bytes; as
2060 * specified in the SMBus standard, block transactions cannot exceed
2061 * 32 bytes.
2062 */
2063 recv_bytes = recv_bytes > MLXBF_I2C_SLAVE_DATA_DESC_SIZE ?
2064 MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes;
2065
2066 if (read)
2067 mlxbf_i2c_irq_send(priv, recv_bytes);
2068 else
2069 mlxbf_i2c_irq_recv(priv, recv_bytes);
2070
2071 return IRQ_HANDLED;
2072}
2073
2074/* Return negative errno on error. */
2075static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr,
2076 unsigned short flags, char read_write,
2077 u8 command, int size,
2078 union i2c_smbus_data *data)
2079{
2080 struct mlxbf_i2c_smbus_request request = { 0 };
2081 struct mlxbf_i2c_priv *priv;
2082 bool read, pec;
2083 u8 byte_cnt;
2084
2085 request.slave = addr;
2086
2087 read = (read_write == I2C_SMBUS_READ);
2088 pec = flags & I2C_FUNC_SMBUS_PEC;
2089
2090 switch (size) {
2091 case I2C_SMBUS_QUICK:
2092 mlxbf_i2c_smbus_quick_command(&request, read);
2093 dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr);
2094 break;
2095
2096 case I2C_SMBUS_BYTE:
2097 mlxbf_i2c_smbus_byte_func(&request,
2098 read ? &data->byte : &command, read,
2099 pec);
2100 dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n",
2101 read ? "read" : "write", addr);
2102 break;
2103
2104 case I2C_SMBUS_BYTE_DATA:
2105 mlxbf_i2c_smbus_data_byte_func(&request, &command, &data->byte,
2106 read, pec);
2107 dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n",
2108 read ? "read" : "write", command, addr);
2109 break;
2110
2111 case I2C_SMBUS_WORD_DATA:
2112 mlxbf_i2c_smbus_data_word_func(&request, &command,
2113 (u8 *)&data->word, read, pec);
2114 dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n",
2115 read ? "read" : "write", command, addr);
2116 break;
2117
2118 case I2C_SMBUS_I2C_BLOCK_DATA:
2119 byte_cnt = data->block[0];
2120 mlxbf_i2c_smbus_i2c_block_func(&request, &command, data->block,
2121 &byte_cnt, read, pec);
2122 dev_dbg(&adap->dev, "i2c %s block data, %d bytes at 0x%02x, slave 0x%02x.\n",
2123 read ? "read" : "write", byte_cnt, command, addr);
2124 break;
2125
2126 case I2C_SMBUS_BLOCK_DATA:
2127 byte_cnt = read ? I2C_SMBUS_BLOCK_MAX : data->block[0];
2128 mlxbf_i2c_smbus_block_func(&request, &command, data->block,
2129 &byte_cnt, read, pec);
2130 dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n",
2131 read ? "read" : "write", byte_cnt, command, addr);
2132 break;
2133
2134 case I2C_FUNC_SMBUS_PROC_CALL:
2135 mlxbf_i2c_smbus_process_call_func(&request, &command,
2136 (u8 *)&data->word, pec);
2137 dev_dbg(&adap->dev, "process call, wr/rd at 0x%02x, slave 0x%02x.\n",
2138 command, addr);
2139 break;
2140
2141 case I2C_FUNC_SMBUS_BLOCK_PROC_CALL:
2142 byte_cnt = data->block[0];
2143 mlxbf_i2c_smbus_blk_process_call_func(&request, &command,
2144 data->block, &byte_cnt,
2145 pec);
2146 dev_dbg(&adap->dev, "block process call, wr/rd %d bytes, slave 0x%02x.\n",
2147 byte_cnt, addr);
2148 break;
2149
2150 default:
2151 dev_dbg(&adap->dev, "Unsupported I2C/SMBus command %d\n",
2152 size);
2153 return -EOPNOTSUPP;
2154 }
2155
2156 priv = i2c_get_adapdata(adap);
2157
2158 return mlxbf_i2c_smbus_start_transaction(priv, &request);
2159}
2160
2161static int mlxbf_i2c_reg_slave(struct i2c_client *slave)
2162{
2163 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
2164 struct device *dev = &slave->dev;
2165 int ret;
2166
2167 /*
2168 * Do not support ten bit chip address and do not use Packet Error
2169 * Checking (PEC).
2170 */
2171 if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC)) {
2172 dev_err(dev, "SMBus PEC and 10 bit address not supported\n");
2173 return -EAFNOSUPPORT;
2174 }
2175
2176 ret = mlxbf_i2c_slave_enable(priv, slave);
2177 if (ret)
2178 dev_err(dev, "Surpassed max number of registered slaves allowed\n");
2179
2180 return 0;
2181}
2182
2183static int mlxbf_i2c_unreg_slave(struct i2c_client *slave)
2184{
2185 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
2186 struct device *dev = &slave->dev;
2187 int ret;
2188
2189 /*
2190 * Unregister slave by:
2191 * 1) Disabling the slave address in hardware
2192 * 2) Freeing priv->slave at the corresponding index
2193 */
2194 ret = mlxbf_i2c_slave_disable(priv, slave->addr);
2195 if (ret)
2196 dev_err(dev, "Unable to find slave 0x%x\n", slave->addr);
2197
2198 return ret;
2199}
2200
2201static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap)
2202{
2203 return MLXBF_I2C_FUNC_ALL;
2204}
2205
2206static struct mlxbf_i2c_chip_info mlxbf_i2c_chip[] = {
2207 [MLXBF_I2C_CHIP_TYPE_1] = {
2208 .type = MLXBF_I2C_CHIP_TYPE_1,
2209 .shared_res = {
2210 [0] = &mlxbf_i2c_coalesce_res[MLXBF_I2C_CHIP_TYPE_1],
2211 [1] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_1],
2212 [2] = &mlxbf_i2c_gpio_res[MLXBF_I2C_CHIP_TYPE_1]
2213 },
2214 .calculate_freq = mlxbf_i2c_calculate_freq_from_tyu,
2215 .smbus_master_rs_bytes_off = MLXBF_I2C_YU_SMBUS_RS_BYTES,
2216 .smbus_master_fsm_off = MLXBF_I2C_YU_SMBUS_MASTER_FSM
2217 },
2218 [MLXBF_I2C_CHIP_TYPE_2] = {
2219 .type = MLXBF_I2C_CHIP_TYPE_2,
2220 .shared_res = {
2221 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_2]
2222 },
2223 .calculate_freq = mlxbf_i2c_calculate_freq_from_yu,
2224 .smbus_master_rs_bytes_off = MLXBF_I2C_YU_SMBUS_RS_BYTES,
2225 .smbus_master_fsm_off = MLXBF_I2C_YU_SMBUS_MASTER_FSM
2226 },
2227 [MLXBF_I2C_CHIP_TYPE_3] = {
2228 .type = MLXBF_I2C_CHIP_TYPE_3,
2229 .shared_res = {
2230 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_3]
2231 },
2232 .calculate_freq = mlxbf_i2c_calculate_freq_from_yu,
2233 .smbus_master_rs_bytes_off = MLXBF_I2C_RSH_YU_SMBUS_RS_BYTES,
2234 .smbus_master_fsm_off = MLXBF_I2C_RSH_YU_SMBUS_MASTER_FSM
2235 }
2236};
2237
2238static const struct i2c_algorithm mlxbf_i2c_algo = {
2239 .smbus_xfer = mlxbf_i2c_smbus_xfer,
2240 .functionality = mlxbf_i2c_functionality,
2241 .reg_slave = mlxbf_i2c_reg_slave,
2242 .unreg_slave = mlxbf_i2c_unreg_slave,
2243};
2244
2245static struct i2c_adapter_quirks mlxbf_i2c_quirks = {
2246 .max_read_len = MLXBF_I2C_MASTER_DATA_R_LENGTH,
2247 .max_write_len = MLXBF_I2C_MASTER_DATA_W_LENGTH,
2248};
2249
2250static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = {
2251 { "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] },
2252 { "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] },
2253 { "MLNXBF31", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_3] },
2254 {},
2255};
2256
2257MODULE_DEVICE_TABLE(acpi, mlxbf_i2c_acpi_ids);
2258
2259static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
2260{
2261 const struct acpi_device_id *aid;
2262 u64 bus_id;
2263 int ret;
2264
2265 if (acpi_disabled)
2266 return -ENOENT;
2267
2268 aid = acpi_match_device(mlxbf_i2c_acpi_ids, dev);
2269 if (!aid)
2270 return -ENODEV;
2271
2272 priv->chip = (struct mlxbf_i2c_chip_info *)aid->driver_data;
2273
2274 ret = acpi_dev_uid_to_integer(ACPI_COMPANION(dev), &bus_id);
2275 if (ret) {
2276 dev_err(dev, "Cannot retrieve UID\n");
2277 return ret;
2278 }
2279
2280 priv->bus = bus_id;
2281
2282 return 0;
2283}
2284
2285static int mlxbf_i2c_probe(struct platform_device *pdev)
2286{
2287 struct device *dev = &pdev->dev;
2288 struct mlxbf_i2c_priv *priv;
2289 struct i2c_adapter *adap;
2290 u32 resource_version;
2291 int irq, ret;
2292
2293 priv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_priv), GFP_KERNEL);
2294 if (!priv)
2295 return -ENOMEM;
2296
2297 ret = mlxbf_i2c_acpi_probe(dev, priv);
2298 if (ret < 0)
2299 return ret;
2300
2301 /* This property allows the driver to stay backward compatible with older
2302 * ACPI tables.
2303 * Starting BlueField-3 SoC, the "smbus" resource was broken down into 3
2304 * separate resources "timer", "master" and "slave".
2305 */
2306 if (device_property_read_u32(dev, "resource_version", &resource_version))
2307 resource_version = 0;
2308
2309 priv->resource_version = resource_version;
2310
2311 if (priv->chip->type < MLXBF_I2C_CHIP_TYPE_3 && resource_version == 0) {
2312 priv->timer = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL);
2313 if (!priv->timer)
2314 return -ENOMEM;
2315
2316 priv->mst = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL);
2317 if (!priv->mst)
2318 return -ENOMEM;
2319
2320 priv->slv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL);
2321 if (!priv->slv)
2322 return -ENOMEM;
2323
2324 ret = mlxbf_i2c_init_resource(pdev, &priv->smbus,
2325 MLXBF_I2C_SMBUS_RES);
2326 if (ret < 0) {
2327 dev_err(dev, "Cannot fetch smbus resource info");
2328 return ret;
2329 }
2330
2331 priv->timer->io = priv->smbus->io;
2332 priv->mst->io = priv->smbus->io + MLXBF_I2C_MST_ADDR_OFFSET;
2333 priv->slv->io = priv->smbus->io + MLXBF_I2C_SLV_ADDR_OFFSET;
2334 } else {
2335 ret = mlxbf_i2c_init_resource(pdev, &priv->timer,
2336 MLXBF_I2C_SMBUS_TIMER_RES);
2337 if (ret < 0) {
2338 dev_err(dev, "Cannot fetch timer resource info");
2339 return ret;
2340 }
2341
2342 ret = mlxbf_i2c_init_resource(pdev, &priv->mst,
2343 MLXBF_I2C_SMBUS_MST_RES);
2344 if (ret < 0) {
2345 dev_err(dev, "Cannot fetch master resource info");
2346 return ret;
2347 }
2348
2349 ret = mlxbf_i2c_init_resource(pdev, &priv->slv,
2350 MLXBF_I2C_SMBUS_SLV_RES);
2351 if (ret < 0) {
2352 dev_err(dev, "Cannot fetch slave resource info");
2353 return ret;
2354 }
2355 }
2356
2357 ret = mlxbf_i2c_init_resource(pdev, &priv->mst_cause,
2358 MLXBF_I2C_MST_CAUSE_RES);
2359 if (ret < 0) {
2360 dev_err(dev, "Cannot fetch cause master resource info");
2361 return ret;
2362 }
2363
2364 ret = mlxbf_i2c_init_resource(pdev, &priv->slv_cause,
2365 MLXBF_I2C_SLV_CAUSE_RES);
2366 if (ret < 0) {
2367 dev_err(dev, "Cannot fetch cause slave resource info");
2368 return ret;
2369 }
2370
2371 adap = &priv->adap;
2372 adap->owner = THIS_MODULE;
2373 adap->class = I2C_CLASS_HWMON;
2374 adap->algo = &mlxbf_i2c_algo;
2375 adap->quirks = &mlxbf_i2c_quirks;
2376 adap->dev.parent = dev;
2377 adap->dev.of_node = dev->of_node;
2378 adap->nr = priv->bus;
2379
2380 snprintf(adap->name, sizeof(adap->name), "i2c%d", adap->nr);
2381 i2c_set_adapdata(adap, priv);
2382
2383 /* Read Core PLL frequency. */
2384 ret = mlxbf_i2c_calculate_corepll_freq(pdev, priv);
2385 if (ret < 0) {
2386 dev_err(dev, "cannot get core clock frequency\n");
2387 /* Set to default value. */
2388 priv->frequency = MLXBF_I2C_COREPLL_FREQ;
2389 }
2390
2391 /*
2392 * Initialize master.
2393 * Note that a physical bus might be shared among Linux and firmware
2394 * (e.g., ATF). Thus, the bus should be initialized and ready and
2395 * bus initialization would be unnecessary. This requires additional
2396 * knowledge about physical busses. But, since an extra initialization
2397 * does not really hurt, then keep the code as is.
2398 */
2399 ret = mlxbf_i2c_init_master(pdev, priv);
2400 if (ret < 0) {
2401 dev_err(dev, "failed to initialize smbus master %d",
2402 priv->bus);
2403 return ret;
2404 }
2405
2406 mlxbf_i2c_init_timings(pdev, priv);
2407
2408 mlxbf_i2c_init_slave(pdev, priv);
2409
2410 irq = platform_get_irq(pdev, 0);
2411 if (irq < 0)
2412 return irq;
2413 ret = devm_request_irq(dev, irq, mlxbf_i2c_irq,
2414 IRQF_SHARED | IRQF_PROBE_SHARED,
2415 dev_name(dev), priv);
2416 if (ret < 0) {
2417 dev_err(dev, "Cannot get irq %d\n", irq);
2418 return ret;
2419 }
2420
2421 priv->irq = irq;
2422
2423 platform_set_drvdata(pdev, priv);
2424
2425 ret = i2c_add_numbered_adapter(adap);
2426 if (ret < 0)
2427 return ret;
2428
2429 mutex_lock(&mlxbf_i2c_bus_lock);
2430 mlxbf_i2c_bus_count++;
2431 mutex_unlock(&mlxbf_i2c_bus_lock);
2432
2433 return 0;
2434}
2435
2436static int mlxbf_i2c_remove(struct platform_device *pdev)
2437{
2438 struct mlxbf_i2c_priv *priv = platform_get_drvdata(pdev);
2439 struct device *dev = &pdev->dev;
2440 struct resource *params;
2441
2442 if (priv->chip->type < MLXBF_I2C_CHIP_TYPE_3 && priv->resource_version == 0) {
2443 params = priv->smbus->params;
2444 devm_release_mem_region(dev, params->start, resource_size(params));
2445 } else {
2446 params = priv->timer->params;
2447 devm_release_mem_region(dev, params->start, resource_size(params));
2448
2449 params = priv->mst->params;
2450 devm_release_mem_region(dev, params->start, resource_size(params));
2451
2452 params = priv->slv->params;
2453 devm_release_mem_region(dev, params->start, resource_size(params));
2454 }
2455
2456 params = priv->mst_cause->params;
2457 devm_release_mem_region(dev, params->start, resource_size(params));
2458
2459 params = priv->slv_cause->params;
2460 devm_release_mem_region(dev, params->start, resource_size(params));
2461
2462 /*
2463 * Release shared resources. This should be done when releasing
2464 * the I2C controller.
2465 */
2466 mutex_lock(&mlxbf_i2c_bus_lock);
2467 if (--mlxbf_i2c_bus_count == 0) {
2468 mlxbf_i2c_release_coalesce(pdev, priv);
2469 mlxbf_i2c_release_corepll(pdev, priv);
2470 mlxbf_i2c_release_gpio(pdev, priv);
2471 }
2472 mutex_unlock(&mlxbf_i2c_bus_lock);
2473
2474 devm_free_irq(dev, priv->irq, priv);
2475
2476 i2c_del_adapter(&priv->adap);
2477
2478 return 0;
2479}
2480
2481static struct platform_driver mlxbf_i2c_driver = {
2482 .probe = mlxbf_i2c_probe,
2483 .remove = mlxbf_i2c_remove,
2484 .driver = {
2485 .name = "i2c-mlxbf",
2486 .acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids),
2487 },
2488};
2489
2490static int __init mlxbf_i2c_init(void)
2491{
2492 mutex_init(&mlxbf_i2c_coalesce_lock);
2493 mutex_init(&mlxbf_i2c_corepll_lock);
2494 mutex_init(&mlxbf_i2c_gpio_lock);
2495
2496 mutex_init(&mlxbf_i2c_bus_lock);
2497
2498 return platform_driver_register(&mlxbf_i2c_driver);
2499}
2500module_init(mlxbf_i2c_init);
2501
2502static void __exit mlxbf_i2c_exit(void)
2503{
2504 platform_driver_unregister(&mlxbf_i2c_driver);
2505
2506 mutex_destroy(&mlxbf_i2c_bus_lock);
2507
2508 mutex_destroy(&mlxbf_i2c_gpio_lock);
2509 mutex_destroy(&mlxbf_i2c_corepll_lock);
2510 mutex_destroy(&mlxbf_i2c_coalesce_lock);
2511}
2512module_exit(mlxbf_i2c_exit);
2513
2514MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver");
2515MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>");
2516MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
2517MODULE_LICENSE("GPL v2");