Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 *
5 * Description: CoreSight Trace Port Interface Unit driver
6 */
7
8#include <linux/atomic.h>
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/device.h>
12#include <linux/io.h>
13#include <linux/err.h>
14#include <linux/slab.h>
15#include <linux/pm_runtime.h>
16#include <linux/coresight.h>
17#include <linux/amba/bus.h>
18#include <linux/clk.h>
19
20#include "coresight-priv.h"
21
22#define TPIU_SUPP_PORTSZ 0x000
23#define TPIU_CURR_PORTSZ 0x004
24#define TPIU_SUPP_TRIGMODES 0x100
25#define TPIU_TRIG_CNTRVAL 0x104
26#define TPIU_TRIG_MULT 0x108
27#define TPIU_SUPP_TESTPATM 0x200
28#define TPIU_CURR_TESTPATM 0x204
29#define TPIU_TEST_PATREPCNTR 0x208
30#define TPIU_FFSR 0x300
31#define TPIU_FFCR 0x304
32#define TPIU_FSYNC_CNTR 0x308
33#define TPIU_EXTCTL_INPORT 0x400
34#define TPIU_EXTCTL_OUTPORT 0x404
35#define TPIU_ITTRFLINACK 0xee4
36#define TPIU_ITTRFLIN 0xee8
37#define TPIU_ITATBDATA0 0xeec
38#define TPIU_ITATBCTR2 0xef0
39#define TPIU_ITATBCTR1 0xef4
40#define TPIU_ITATBCTR0 0xef8
41
42/** register definition **/
43/* FFSR - 0x300 */
44#define FFSR_FT_STOPPED_BIT 1
45/* FFCR - 0x304 */
46#define FFCR_FON_MAN_BIT 6
47#define FFCR_FON_MAN BIT(6)
48#define FFCR_STOP_FI BIT(12)
49
50DEFINE_CORESIGHT_DEVLIST(tpiu_devs, "tpiu");
51
52/*
53 * @base: memory mapped base address for this component.
54 * @atclk: optional clock for the core parts of the TPIU.
55 * @csdev: component vitals needed by the framework.
56 */
57struct tpiu_drvdata {
58 void __iomem *base;
59 struct clk *atclk;
60 struct coresight_device *csdev;
61};
62
63static void tpiu_enable_hw(struct csdev_access *csa)
64{
65 CS_UNLOCK(csa->base);
66
67 /* TODO: fill this up */
68
69 CS_LOCK(csa->base);
70}
71
72static int tpiu_enable(struct coresight_device *csdev, u32 mode, void *__unused)
73{
74 tpiu_enable_hw(&csdev->access);
75 atomic_inc(csdev->refcnt);
76 dev_dbg(&csdev->dev, "TPIU enabled\n");
77 return 0;
78}
79
80static void tpiu_disable_hw(struct csdev_access *csa)
81{
82 CS_UNLOCK(csa->base);
83
84 /* Clear formatter and stop on flush */
85 csdev_access_relaxed_write32(csa, FFCR_STOP_FI, TPIU_FFCR);
86 /* Generate manual flush */
87 csdev_access_relaxed_write32(csa, FFCR_STOP_FI | FFCR_FON_MAN, TPIU_FFCR);
88 /* Wait for flush to complete */
89 coresight_timeout(csa, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
90 /* Wait for formatter to stop */
91 coresight_timeout(csa, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
92
93 CS_LOCK(csa->base);
94}
95
96static int tpiu_disable(struct coresight_device *csdev)
97{
98 if (atomic_dec_return(csdev->refcnt))
99 return -EBUSY;
100
101 tpiu_disable_hw(&csdev->access);
102
103 dev_dbg(&csdev->dev, "TPIU disabled\n");
104 return 0;
105}
106
107static const struct coresight_ops_sink tpiu_sink_ops = {
108 .enable = tpiu_enable,
109 .disable = tpiu_disable,
110};
111
112static const struct coresight_ops tpiu_cs_ops = {
113 .sink_ops = &tpiu_sink_ops,
114};
115
116static int tpiu_probe(struct amba_device *adev, const struct amba_id *id)
117{
118 int ret;
119 void __iomem *base;
120 struct device *dev = &adev->dev;
121 struct coresight_platform_data *pdata = NULL;
122 struct tpiu_drvdata *drvdata;
123 struct resource *res = &adev->res;
124 struct coresight_desc desc = { 0 };
125
126 desc.name = coresight_alloc_device_name(&tpiu_devs, dev);
127 if (!desc.name)
128 return -ENOMEM;
129
130 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
131 if (!drvdata)
132 return -ENOMEM;
133
134 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
135 if (!IS_ERR(drvdata->atclk)) {
136 ret = clk_prepare_enable(drvdata->atclk);
137 if (ret)
138 return ret;
139 }
140 dev_set_drvdata(dev, drvdata);
141
142 /* Validity for the resource is already checked by the AMBA core */
143 base = devm_ioremap_resource(dev, res);
144 if (IS_ERR(base))
145 return PTR_ERR(base);
146
147 drvdata->base = base;
148 desc.access = CSDEV_ACCESS_IOMEM(base);
149
150 /* Disable tpiu to support older devices */
151 tpiu_disable_hw(&desc.access);
152
153 pdata = coresight_get_platform_data(dev);
154 if (IS_ERR(pdata))
155 return PTR_ERR(pdata);
156 dev->platform_data = pdata;
157
158 desc.type = CORESIGHT_DEV_TYPE_SINK;
159 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PORT;
160 desc.ops = &tpiu_cs_ops;
161 desc.pdata = pdata;
162 desc.dev = dev;
163 drvdata->csdev = coresight_register(&desc);
164
165 if (!IS_ERR(drvdata->csdev)) {
166 pm_runtime_put(&adev->dev);
167 return 0;
168 }
169
170 return PTR_ERR(drvdata->csdev);
171}
172
173static void tpiu_remove(struct amba_device *adev)
174{
175 struct tpiu_drvdata *drvdata = dev_get_drvdata(&adev->dev);
176
177 coresight_unregister(drvdata->csdev);
178}
179
180#ifdef CONFIG_PM
181static int tpiu_runtime_suspend(struct device *dev)
182{
183 struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
184
185 if (drvdata && !IS_ERR(drvdata->atclk))
186 clk_disable_unprepare(drvdata->atclk);
187
188 return 0;
189}
190
191static int tpiu_runtime_resume(struct device *dev)
192{
193 struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
194
195 if (drvdata && !IS_ERR(drvdata->atclk))
196 clk_prepare_enable(drvdata->atclk);
197
198 return 0;
199}
200#endif
201
202static const struct dev_pm_ops tpiu_dev_pm_ops = {
203 SET_RUNTIME_PM_OPS(tpiu_runtime_suspend, tpiu_runtime_resume, NULL)
204};
205
206static const struct amba_id tpiu_ids[] = {
207 {
208 .id = 0x000bb912,
209 .mask = 0x000fffff,
210 },
211 {
212 .id = 0x0004b912,
213 .mask = 0x0007ffff,
214 },
215 {
216 /* Coresight SoC-600 */
217 .id = 0x000bb9e7,
218 .mask = 0x000fffff,
219 },
220 { 0, 0},
221};
222
223MODULE_DEVICE_TABLE(amba, tpiu_ids);
224
225static struct amba_driver tpiu_driver = {
226 .drv = {
227 .name = "coresight-tpiu",
228 .owner = THIS_MODULE,
229 .pm = &tpiu_dev_pm_ops,
230 .suppress_bind_attrs = true,
231 },
232 .probe = tpiu_probe,
233 .remove = tpiu_remove,
234 .id_table = tpiu_ids,
235};
236
237module_amba_driver(tpiu_driver);
238
239MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
240MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
241MODULE_DESCRIPTION("Arm CoreSight TPIU (Trace Port Interface Unit) driver");
242MODULE_LICENSE("GPL v2");
1/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
2 *
3 * Description: CoreSight Trace Port Interface Unit driver
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/device.h>
18#include <linux/io.h>
19#include <linux/err.h>
20#include <linux/slab.h>
21#include <linux/pm_runtime.h>
22#include <linux/coresight.h>
23#include <linux/amba/bus.h>
24#include <linux/clk.h>
25
26#include "coresight-priv.h"
27
28#define TPIU_SUPP_PORTSZ 0x000
29#define TPIU_CURR_PORTSZ 0x004
30#define TPIU_SUPP_TRIGMODES 0x100
31#define TPIU_TRIG_CNTRVAL 0x104
32#define TPIU_TRIG_MULT 0x108
33#define TPIU_SUPP_TESTPATM 0x200
34#define TPIU_CURR_TESTPATM 0x204
35#define TPIU_TEST_PATREPCNTR 0x208
36#define TPIU_FFSR 0x300
37#define TPIU_FFCR 0x304
38#define TPIU_FSYNC_CNTR 0x308
39#define TPIU_EXTCTL_INPORT 0x400
40#define TPIU_EXTCTL_OUTPORT 0x404
41#define TPIU_ITTRFLINACK 0xee4
42#define TPIU_ITTRFLIN 0xee8
43#define TPIU_ITATBDATA0 0xeec
44#define TPIU_ITATBCTR2 0xef0
45#define TPIU_ITATBCTR1 0xef4
46#define TPIU_ITATBCTR0 0xef8
47
48/** register definition **/
49/* FFCR - 0x304 */
50#define FFCR_FON_MAN BIT(6)
51
52/**
53 * @base: memory mapped base address for this component.
54 * @dev: the device entity associated to this component.
55 * @atclk: optional clock for the core parts of the TPIU.
56 * @csdev: component vitals needed by the framework.
57 */
58struct tpiu_drvdata {
59 void __iomem *base;
60 struct device *dev;
61 struct clk *atclk;
62 struct coresight_device *csdev;
63};
64
65static void tpiu_enable_hw(struct tpiu_drvdata *drvdata)
66{
67 CS_UNLOCK(drvdata->base);
68
69 /* TODO: fill this up */
70
71 CS_LOCK(drvdata->base);
72}
73
74static int tpiu_enable(struct coresight_device *csdev, u32 mode)
75{
76 struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
77
78 tpiu_enable_hw(drvdata);
79
80 dev_info(drvdata->dev, "TPIU enabled\n");
81 return 0;
82}
83
84static void tpiu_disable_hw(struct tpiu_drvdata *drvdata)
85{
86 CS_UNLOCK(drvdata->base);
87
88 /* Clear formatter controle reg. */
89 writel_relaxed(0x0, drvdata->base + TPIU_FFCR);
90 /* Generate manual flush */
91 writel_relaxed(FFCR_FON_MAN, drvdata->base + TPIU_FFCR);
92
93 CS_LOCK(drvdata->base);
94}
95
96static void tpiu_disable(struct coresight_device *csdev)
97{
98 struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
99
100 tpiu_disable_hw(drvdata);
101
102 dev_info(drvdata->dev, "TPIU disabled\n");
103}
104
105static const struct coresight_ops_sink tpiu_sink_ops = {
106 .enable = tpiu_enable,
107 .disable = tpiu_disable,
108};
109
110static const struct coresight_ops tpiu_cs_ops = {
111 .sink_ops = &tpiu_sink_ops,
112};
113
114static int tpiu_probe(struct amba_device *adev, const struct amba_id *id)
115{
116 int ret;
117 void __iomem *base;
118 struct device *dev = &adev->dev;
119 struct coresight_platform_data *pdata = NULL;
120 struct tpiu_drvdata *drvdata;
121 struct resource *res = &adev->res;
122 struct coresight_desc desc = { 0 };
123 struct device_node *np = adev->dev.of_node;
124
125 if (np) {
126 pdata = of_get_coresight_platform_data(dev, np);
127 if (IS_ERR(pdata))
128 return PTR_ERR(pdata);
129 adev->dev.platform_data = pdata;
130 }
131
132 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
133 if (!drvdata)
134 return -ENOMEM;
135
136 drvdata->dev = &adev->dev;
137 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
138 if (!IS_ERR(drvdata->atclk)) {
139 ret = clk_prepare_enable(drvdata->atclk);
140 if (ret)
141 return ret;
142 }
143 dev_set_drvdata(dev, drvdata);
144
145 /* Validity for the resource is already checked by the AMBA core */
146 base = devm_ioremap_resource(dev, res);
147 if (IS_ERR(base))
148 return PTR_ERR(base);
149
150 drvdata->base = base;
151
152 /* Disable tpiu to support older devices */
153 tpiu_disable_hw(drvdata);
154
155 pm_runtime_put(&adev->dev);
156
157 desc.type = CORESIGHT_DEV_TYPE_SINK;
158 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PORT;
159 desc.ops = &tpiu_cs_ops;
160 desc.pdata = pdata;
161 desc.dev = dev;
162 drvdata->csdev = coresight_register(&desc);
163 if (IS_ERR(drvdata->csdev))
164 return PTR_ERR(drvdata->csdev);
165
166 return 0;
167}
168
169#ifdef CONFIG_PM
170static int tpiu_runtime_suspend(struct device *dev)
171{
172 struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
173
174 if (drvdata && !IS_ERR(drvdata->atclk))
175 clk_disable_unprepare(drvdata->atclk);
176
177 return 0;
178}
179
180static int tpiu_runtime_resume(struct device *dev)
181{
182 struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
183
184 if (drvdata && !IS_ERR(drvdata->atclk))
185 clk_prepare_enable(drvdata->atclk);
186
187 return 0;
188}
189#endif
190
191static const struct dev_pm_ops tpiu_dev_pm_ops = {
192 SET_RUNTIME_PM_OPS(tpiu_runtime_suspend, tpiu_runtime_resume, NULL)
193};
194
195static struct amba_id tpiu_ids[] = {
196 {
197 .id = 0x0003b912,
198 .mask = 0x0003ffff,
199 },
200 {
201 .id = 0x0004b912,
202 .mask = 0x0007ffff,
203 },
204 { 0, 0},
205};
206
207static struct amba_driver tpiu_driver = {
208 .drv = {
209 .name = "coresight-tpiu",
210 .owner = THIS_MODULE,
211 .pm = &tpiu_dev_pm_ops,
212 .suppress_bind_attrs = true,
213 },
214 .probe = tpiu_probe,
215 .id_table = tpiu_ids,
216};
217builtin_amba_driver(tpiu_driver);