Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
4 *
5 * Description: CoreSight System Trace Macrocell driver
6 *
7 * Initial implementation by Pratik Patel
8 * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
9 *
10 * Serious refactoring, code cleanup and upgrading to the Coresight upstream
11 * framework by Mathieu Poirier
12 * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
13 *
14 * Guaranteed timing and support for various packet type coming from the
15 * generic STM API by Chunyan Zhang
16 * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
17 */
18#include <asm/local.h>
19#include <linux/acpi.h>
20#include <linux/amba/bus.h>
21#include <linux/bitmap.h>
22#include <linux/clk.h>
23#include <linux/coresight.h>
24#include <linux/coresight-stm.h>
25#include <linux/err.h>
26#include <linux/kernel.h>
27#include <linux/moduleparam.h>
28#include <linux/of_address.h>
29#include <linux/perf_event.h>
30#include <linux/pm_runtime.h>
31#include <linux/stm.h>
32
33#include "coresight-priv.h"
34
35#define STMDMASTARTR 0xc04
36#define STMDMASTOPR 0xc08
37#define STMDMASTATR 0xc0c
38#define STMDMACTLR 0xc10
39#define STMDMAIDR 0xcfc
40#define STMHEER 0xd00
41#define STMHETER 0xd20
42#define STMHEBSR 0xd60
43#define STMHEMCR 0xd64
44#define STMHEMASTR 0xdf4
45#define STMHEFEAT1R 0xdf8
46#define STMHEIDR 0xdfc
47#define STMSPER 0xe00
48#define STMSPTER 0xe20
49#define STMPRIVMASKR 0xe40
50#define STMSPSCR 0xe60
51#define STMSPMSCR 0xe64
52#define STMSPOVERRIDER 0xe68
53#define STMSPMOVERRIDER 0xe6c
54#define STMSPTRIGCSR 0xe70
55#define STMTCSR 0xe80
56#define STMTSSTIMR 0xe84
57#define STMTSFREQR 0xe8c
58#define STMSYNCR 0xe90
59#define STMAUXCR 0xe94
60#define STMSPFEAT1R 0xea0
61#define STMSPFEAT2R 0xea4
62#define STMSPFEAT3R 0xea8
63#define STMITTRIGGER 0xee8
64#define STMITATBDATA0 0xeec
65#define STMITATBCTR2 0xef0
66#define STMITATBID 0xef4
67#define STMITATBCTR0 0xef8
68
69#define STM_32_CHANNEL 32
70#define BYTES_PER_CHANNEL 256
71#define STM_TRACE_BUF_SIZE 4096
72#define STM_SW_MASTER_END 127
73
74/* Register bit definition */
75#define STMTCSR_BUSY_BIT 23
76/* Reserve the first 10 channels for kernel usage */
77#define STM_CHANNEL_OFFSET 0
78
79enum stm_pkt_type {
80 STM_PKT_TYPE_DATA = 0x98,
81 STM_PKT_TYPE_FLAG = 0xE8,
82 STM_PKT_TYPE_TRIG = 0xF8,
83};
84
85#define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \
86 (ch * BYTES_PER_CHANNEL))
87#define stm_channel_off(type, opts) (type & ~opts)
88
89static int boot_nr_channel;
90
91/*
92 * Not really modular but using module_param is the easiest way to
93 * remain consistent with existing use cases for now.
94 */
95module_param_named(
96 boot_nr_channel, boot_nr_channel, int, S_IRUGO
97);
98
99/*
100 * struct channel_space - central management entity for extended ports
101 * @base: memory mapped base address where channels start.
102 * @phys: physical base address of channel region.
103 * @guaraneed: is the channel delivery guaranteed.
104 */
105struct channel_space {
106 void __iomem *base;
107 phys_addr_t phys;
108 unsigned long *guaranteed;
109};
110
111DEFINE_CORESIGHT_DEVLIST(stm_devs, "stm");
112
113/**
114 * struct stm_drvdata - specifics associated to an STM component
115 * @base: memory mapped base address for this component.
116 * @atclk: optional clock for the core parts of the STM.
117 * @csdev: component vitals needed by the framework.
118 * @spinlock: only one at a time pls.
119 * @chs: the channels accociated to this STM.
120 * @stm: structure associated to the generic STM interface.
121 * @mode: this tracer's mode, i.e sysFS, or disabled.
122 * @traceid: value of the current ID for this component.
123 * @write_bytes: Maximus bytes this STM can write at a time.
124 * @stmsper: settings for register STMSPER.
125 * @stmspscr: settings for register STMSPSCR.
126 * @numsp: the total number of stimulus port support by this STM.
127 * @stmheer: settings for register STMHEER.
128 * @stmheter: settings for register STMHETER.
129 * @stmhebsr: settings for register STMHEBSR.
130 */
131struct stm_drvdata {
132 void __iomem *base;
133 struct clk *atclk;
134 struct coresight_device *csdev;
135 spinlock_t spinlock;
136 struct channel_space chs;
137 struct stm_data stm;
138 local_t mode;
139 u8 traceid;
140 u32 write_bytes;
141 u32 stmsper;
142 u32 stmspscr;
143 u32 numsp;
144 u32 stmheer;
145 u32 stmheter;
146 u32 stmhebsr;
147};
148
149static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
150{
151 CS_UNLOCK(drvdata->base);
152
153 writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
154 writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
155 writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
156 writel_relaxed(0x01 | /* Enable HW event tracing */
157 0x04, /* Error detection on event tracing */
158 drvdata->base + STMHEMCR);
159
160 CS_LOCK(drvdata->base);
161}
162
163static void stm_port_enable_hw(struct stm_drvdata *drvdata)
164{
165 CS_UNLOCK(drvdata->base);
166 /* ATB trigger enable on direct writes to TRIG locations */
167 writel_relaxed(0x10,
168 drvdata->base + STMSPTRIGCSR);
169 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
170 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
171
172 CS_LOCK(drvdata->base);
173}
174
175static void stm_enable_hw(struct stm_drvdata *drvdata)
176{
177 if (drvdata->stmheer)
178 stm_hwevent_enable_hw(drvdata);
179
180 stm_port_enable_hw(drvdata);
181
182 CS_UNLOCK(drvdata->base);
183
184 /* 4096 byte between synchronisation packets */
185 writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
186 writel_relaxed((drvdata->traceid << 16 | /* trace id */
187 0x02 | /* timestamp enable */
188 0x01), /* global STM enable */
189 drvdata->base + STMTCSR);
190
191 CS_LOCK(drvdata->base);
192}
193
194static int stm_enable(struct coresight_device *csdev,
195 struct perf_event *event, u32 mode)
196{
197 u32 val;
198 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
199
200 if (mode != CS_MODE_SYSFS)
201 return -EINVAL;
202
203 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
204
205 /* Someone is already using the tracer */
206 if (val)
207 return -EBUSY;
208
209 pm_runtime_get_sync(csdev->dev.parent);
210
211 spin_lock(&drvdata->spinlock);
212 stm_enable_hw(drvdata);
213 spin_unlock(&drvdata->spinlock);
214
215 dev_dbg(&csdev->dev, "STM tracing enabled\n");
216 return 0;
217}
218
219static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata)
220{
221 CS_UNLOCK(drvdata->base);
222
223 writel_relaxed(0x0, drvdata->base + STMHEMCR);
224 writel_relaxed(0x0, drvdata->base + STMHEER);
225 writel_relaxed(0x0, drvdata->base + STMHETER);
226
227 CS_LOCK(drvdata->base);
228}
229
230static void stm_port_disable_hw(struct stm_drvdata *drvdata)
231{
232 CS_UNLOCK(drvdata->base);
233
234 writel_relaxed(0x0, drvdata->base + STMSPER);
235 writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
236
237 CS_LOCK(drvdata->base);
238}
239
240static void stm_disable_hw(struct stm_drvdata *drvdata)
241{
242 u32 val;
243
244 CS_UNLOCK(drvdata->base);
245
246 val = readl_relaxed(drvdata->base + STMTCSR);
247 val &= ~0x1; /* clear global STM enable [0] */
248 writel_relaxed(val, drvdata->base + STMTCSR);
249
250 CS_LOCK(drvdata->base);
251
252 stm_port_disable_hw(drvdata);
253 if (drvdata->stmheer)
254 stm_hwevent_disable_hw(drvdata);
255}
256
257static void stm_disable(struct coresight_device *csdev,
258 struct perf_event *event)
259{
260 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
261 struct csdev_access *csa = &csdev->access;
262
263 /*
264 * For as long as the tracer isn't disabled another entity can't
265 * change its status. As such we can read the status here without
266 * fearing it will change under us.
267 */
268 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
269 spin_lock(&drvdata->spinlock);
270 stm_disable_hw(drvdata);
271 spin_unlock(&drvdata->spinlock);
272
273 /* Wait until the engine has completely stopped */
274 coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0);
275
276 pm_runtime_put(csdev->dev.parent);
277
278 local_set(&drvdata->mode, CS_MODE_DISABLED);
279 dev_dbg(&csdev->dev, "STM tracing disabled\n");
280 }
281}
282
283static int stm_trace_id(struct coresight_device *csdev)
284{
285 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
286
287 return drvdata->traceid;
288}
289
290static const struct coresight_ops_source stm_source_ops = {
291 .trace_id = stm_trace_id,
292 .enable = stm_enable,
293 .disable = stm_disable,
294};
295
296static const struct coresight_ops stm_cs_ops = {
297 .source_ops = &stm_source_ops,
298};
299
300static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes)
301{
302 return ((unsigned long)addr & (write_bytes - 1));
303}
304
305static void stm_send(void __iomem *addr, const void *data,
306 u32 size, u8 write_bytes)
307{
308 u8 paload[8];
309
310 if (stm_addr_unaligned(data, write_bytes)) {
311 memcpy(paload, data, size);
312 data = paload;
313 }
314
315 /* now we are 64bit/32bit aligned */
316 switch (size) {
317#ifdef CONFIG_64BIT
318 case 8:
319 writeq_relaxed(*(u64 *)data, addr);
320 break;
321#endif
322 case 4:
323 writel_relaxed(*(u32 *)data, addr);
324 break;
325 case 2:
326 writew_relaxed(*(u16 *)data, addr);
327 break;
328 case 1:
329 writeb_relaxed(*(u8 *)data, addr);
330 break;
331 default:
332 break;
333 }
334}
335
336static int stm_generic_link(struct stm_data *stm_data,
337 unsigned int master, unsigned int channel)
338{
339 struct stm_drvdata *drvdata = container_of(stm_data,
340 struct stm_drvdata, stm);
341 if (!drvdata || !drvdata->csdev)
342 return -EINVAL;
343
344 return coresight_enable(drvdata->csdev);
345}
346
347static void stm_generic_unlink(struct stm_data *stm_data,
348 unsigned int master, unsigned int channel)
349{
350 struct stm_drvdata *drvdata = container_of(stm_data,
351 struct stm_drvdata, stm);
352 if (!drvdata || !drvdata->csdev)
353 return;
354
355 coresight_disable(drvdata->csdev);
356}
357
358static phys_addr_t
359stm_mmio_addr(struct stm_data *stm_data, unsigned int master,
360 unsigned int channel, unsigned int nr_chans)
361{
362 struct stm_drvdata *drvdata = container_of(stm_data,
363 struct stm_drvdata, stm);
364 phys_addr_t addr;
365
366 addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL;
367
368 if (offset_in_page(addr) ||
369 offset_in_page(nr_chans * BYTES_PER_CHANNEL))
370 return 0;
371
372 return addr;
373}
374
375static long stm_generic_set_options(struct stm_data *stm_data,
376 unsigned int master,
377 unsigned int channel,
378 unsigned int nr_chans,
379 unsigned long options)
380{
381 struct stm_drvdata *drvdata = container_of(stm_data,
382 struct stm_drvdata, stm);
383 if (!(drvdata && local_read(&drvdata->mode)))
384 return -EINVAL;
385
386 if (channel >= drvdata->numsp)
387 return -EINVAL;
388
389 switch (options) {
390 case STM_OPTION_GUARANTEED:
391 set_bit(channel, drvdata->chs.guaranteed);
392 break;
393
394 case STM_OPTION_INVARIANT:
395 clear_bit(channel, drvdata->chs.guaranteed);
396 break;
397
398 default:
399 return -EINVAL;
400 }
401
402 return 0;
403}
404
405static ssize_t notrace stm_generic_packet(struct stm_data *stm_data,
406 unsigned int master,
407 unsigned int channel,
408 unsigned int packet,
409 unsigned int flags,
410 unsigned int size,
411 const unsigned char *payload)
412{
413 void __iomem *ch_addr;
414 struct stm_drvdata *drvdata = container_of(stm_data,
415 struct stm_drvdata, stm);
416 unsigned int stm_flags;
417
418 if (!(drvdata && local_read(&drvdata->mode)))
419 return -EACCES;
420
421 if (channel >= drvdata->numsp)
422 return -EINVAL;
423
424 ch_addr = stm_channel_addr(drvdata, channel);
425
426 stm_flags = (flags & STP_PACKET_TIMESTAMPED) ?
427 STM_FLAG_TIMESTAMPED : 0;
428 stm_flags |= test_bit(channel, drvdata->chs.guaranteed) ?
429 STM_FLAG_GUARANTEED : 0;
430
431 if (size > drvdata->write_bytes)
432 size = drvdata->write_bytes;
433 else
434 size = rounddown_pow_of_two(size);
435
436 switch (packet) {
437 case STP_PACKET_FLAG:
438 ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, stm_flags);
439
440 /*
441 * The generic STM core sets a size of '0' on flag packets.
442 * As such send a flag packet of size '1' and tell the
443 * core we did so.
444 */
445 stm_send(ch_addr, payload, 1, drvdata->write_bytes);
446 size = 1;
447 break;
448
449 case STP_PACKET_DATA:
450 stm_flags |= (flags & STP_PACKET_MARKED) ? STM_FLAG_MARKED : 0;
451 ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, stm_flags);
452 stm_send(ch_addr, payload, size,
453 drvdata->write_bytes);
454 break;
455
456 default:
457 return -ENOTSUPP;
458 }
459
460 return size;
461}
462
463static ssize_t hwevent_enable_show(struct device *dev,
464 struct device_attribute *attr, char *buf)
465{
466 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
467 unsigned long val = drvdata->stmheer;
468
469 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
470}
471
472static ssize_t hwevent_enable_store(struct device *dev,
473 struct device_attribute *attr,
474 const char *buf, size_t size)
475{
476 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
477 unsigned long val;
478 int ret = 0;
479
480 ret = kstrtoul(buf, 16, &val);
481 if (ret)
482 return -EINVAL;
483
484 drvdata->stmheer = val;
485 /* HW event enable and trigger go hand in hand */
486 drvdata->stmheter = val;
487
488 return size;
489}
490static DEVICE_ATTR_RW(hwevent_enable);
491
492static ssize_t hwevent_select_show(struct device *dev,
493 struct device_attribute *attr, char *buf)
494{
495 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
496 unsigned long val = drvdata->stmhebsr;
497
498 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
499}
500
501static ssize_t hwevent_select_store(struct device *dev,
502 struct device_attribute *attr,
503 const char *buf, size_t size)
504{
505 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
506 unsigned long val;
507 int ret = 0;
508
509 ret = kstrtoul(buf, 16, &val);
510 if (ret)
511 return -EINVAL;
512
513 drvdata->stmhebsr = val;
514
515 return size;
516}
517static DEVICE_ATTR_RW(hwevent_select);
518
519static ssize_t port_select_show(struct device *dev,
520 struct device_attribute *attr, char *buf)
521{
522 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
523 unsigned long val;
524
525 if (!local_read(&drvdata->mode)) {
526 val = drvdata->stmspscr;
527 } else {
528 spin_lock(&drvdata->spinlock);
529 val = readl_relaxed(drvdata->base + STMSPSCR);
530 spin_unlock(&drvdata->spinlock);
531 }
532
533 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
534}
535
536static ssize_t port_select_store(struct device *dev,
537 struct device_attribute *attr,
538 const char *buf, size_t size)
539{
540 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
541 unsigned long val, stmsper;
542 int ret = 0;
543
544 ret = kstrtoul(buf, 16, &val);
545 if (ret)
546 return ret;
547
548 spin_lock(&drvdata->spinlock);
549 drvdata->stmspscr = val;
550
551 if (local_read(&drvdata->mode)) {
552 CS_UNLOCK(drvdata->base);
553 /* Process as per ARM's TRM recommendation */
554 stmsper = readl_relaxed(drvdata->base + STMSPER);
555 writel_relaxed(0x0, drvdata->base + STMSPER);
556 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
557 writel_relaxed(stmsper, drvdata->base + STMSPER);
558 CS_LOCK(drvdata->base);
559 }
560 spin_unlock(&drvdata->spinlock);
561
562 return size;
563}
564static DEVICE_ATTR_RW(port_select);
565
566static ssize_t port_enable_show(struct device *dev,
567 struct device_attribute *attr, char *buf)
568{
569 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
570 unsigned long val;
571
572 if (!local_read(&drvdata->mode)) {
573 val = drvdata->stmsper;
574 } else {
575 spin_lock(&drvdata->spinlock);
576 val = readl_relaxed(drvdata->base + STMSPER);
577 spin_unlock(&drvdata->spinlock);
578 }
579
580 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
581}
582
583static ssize_t port_enable_store(struct device *dev,
584 struct device_attribute *attr,
585 const char *buf, size_t size)
586{
587 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
588 unsigned long val;
589 int ret = 0;
590
591 ret = kstrtoul(buf, 16, &val);
592 if (ret)
593 return ret;
594
595 spin_lock(&drvdata->spinlock);
596 drvdata->stmsper = val;
597
598 if (local_read(&drvdata->mode)) {
599 CS_UNLOCK(drvdata->base);
600 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
601 CS_LOCK(drvdata->base);
602 }
603 spin_unlock(&drvdata->spinlock);
604
605 return size;
606}
607static DEVICE_ATTR_RW(port_enable);
608
609static ssize_t traceid_show(struct device *dev,
610 struct device_attribute *attr, char *buf)
611{
612 unsigned long val;
613 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
614
615 val = drvdata->traceid;
616 return sprintf(buf, "%#lx\n", val);
617}
618
619static ssize_t traceid_store(struct device *dev,
620 struct device_attribute *attr,
621 const char *buf, size_t size)
622{
623 int ret;
624 unsigned long val;
625 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
626
627 ret = kstrtoul(buf, 16, &val);
628 if (ret)
629 return ret;
630
631 /* traceid field is 7bit wide on STM32 */
632 drvdata->traceid = val & 0x7f;
633 return size;
634}
635static DEVICE_ATTR_RW(traceid);
636
637static struct attribute *coresight_stm_attrs[] = {
638 &dev_attr_hwevent_enable.attr,
639 &dev_attr_hwevent_select.attr,
640 &dev_attr_port_enable.attr,
641 &dev_attr_port_select.attr,
642 &dev_attr_traceid.attr,
643 NULL,
644};
645
646static struct attribute *coresight_stm_mgmt_attrs[] = {
647 coresight_simple_reg32(tcsr, STMTCSR),
648 coresight_simple_reg32(tsfreqr, STMTSFREQR),
649 coresight_simple_reg32(syncr, STMSYNCR),
650 coresight_simple_reg32(sper, STMSPER),
651 coresight_simple_reg32(spter, STMSPTER),
652 coresight_simple_reg32(privmaskr, STMPRIVMASKR),
653 coresight_simple_reg32(spscr, STMSPSCR),
654 coresight_simple_reg32(spmscr, STMSPMSCR),
655 coresight_simple_reg32(spfeat1r, STMSPFEAT1R),
656 coresight_simple_reg32(spfeat2r, STMSPFEAT2R),
657 coresight_simple_reg32(spfeat3r, STMSPFEAT3R),
658 coresight_simple_reg32(devid, CORESIGHT_DEVID),
659 NULL,
660};
661
662static const struct attribute_group coresight_stm_group = {
663 .attrs = coresight_stm_attrs,
664};
665
666static const struct attribute_group coresight_stm_mgmt_group = {
667 .attrs = coresight_stm_mgmt_attrs,
668 .name = "mgmt",
669};
670
671static const struct attribute_group *coresight_stm_groups[] = {
672 &coresight_stm_group,
673 &coresight_stm_mgmt_group,
674 NULL,
675};
676
677#ifdef CONFIG_OF
678static int of_stm_get_stimulus_area(struct device *dev, struct resource *res)
679{
680 const char *name = NULL;
681 int index = 0, found = 0;
682 struct device_node *np = dev->of_node;
683
684 while (!of_property_read_string_index(np, "reg-names", index, &name)) {
685 if (strcmp("stm-stimulus-base", name)) {
686 index++;
687 continue;
688 }
689
690 /* We have a match and @index is where it's at */
691 found = 1;
692 break;
693 }
694
695 if (!found)
696 return -EINVAL;
697
698 return of_address_to_resource(np, index, res);
699}
700#else
701static inline int of_stm_get_stimulus_area(struct device *dev,
702 struct resource *res)
703{
704 return -ENOENT;
705}
706#endif
707
708#ifdef CONFIG_ACPI
709static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res)
710{
711 int rc;
712 bool found_base = false;
713 struct resource_entry *rent;
714 LIST_HEAD(res_list);
715
716 struct acpi_device *adev = ACPI_COMPANION(dev);
717
718 rc = acpi_dev_get_resources(adev, &res_list, NULL, NULL);
719 if (rc < 0)
720 return rc;
721
722 /*
723 * The stimulus base for STM device must be listed as the second memory
724 * resource, followed by the programming base address as described in
725 * "Section 2.3 Resources" in ACPI for CoreSightTM 1.0 Platform Design
726 * document (DEN0067).
727 */
728 rc = -ENOENT;
729 list_for_each_entry(rent, &res_list, node) {
730 if (resource_type(rent->res) != IORESOURCE_MEM)
731 continue;
732 if (found_base) {
733 *res = *rent->res;
734 rc = 0;
735 break;
736 }
737
738 found_base = true;
739 }
740
741 acpi_dev_free_resource_list(&res_list);
742 return rc;
743}
744#else
745static inline int acpi_stm_get_stimulus_area(struct device *dev,
746 struct resource *res)
747{
748 return -ENOENT;
749}
750#endif
751
752static int stm_get_stimulus_area(struct device *dev, struct resource *res)
753{
754 struct fwnode_handle *fwnode = dev_fwnode(dev);
755
756 if (is_of_node(fwnode))
757 return of_stm_get_stimulus_area(dev, res);
758 else if (is_acpi_node(fwnode))
759 return acpi_stm_get_stimulus_area(dev, res);
760 return -ENOENT;
761}
762
763static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata)
764{
765 u32 stmspfeat2r;
766
767 if (!IS_ENABLED(CONFIG_64BIT))
768 return 4;
769
770 stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R);
771
772 /*
773 * bit[15:12] represents the fundamental data size
774 * 0 - 32-bit data
775 * 1 - 64-bit data
776 */
777 return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4;
778}
779
780static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata)
781{
782 u32 numsp;
783
784 numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
785 /*
786 * NUMPS in STMDEVID is 17 bit long and if equal to 0x0,
787 * 32 stimulus ports are supported.
788 */
789 numsp &= 0x1ffff;
790 if (!numsp)
791 numsp = STM_32_CHANNEL;
792 return numsp;
793}
794
795static void stm_init_default_data(struct stm_drvdata *drvdata)
796{
797 /* Don't use port selection */
798 drvdata->stmspscr = 0x0;
799 /*
800 * Enable all channel regardless of their number. When port
801 * selection isn't used (see above) STMSPER applies to all
802 * 32 channel group available, hence setting all 32 bits to 1
803 */
804 drvdata->stmsper = ~0x0;
805
806 /*
807 * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and
808 * anything equal to or higher than 0x70 is reserved. Since 0x00 is
809 * also reserved the STM trace ID needs to be higher than 0x00 and
810 * lowner than 0x10.
811 */
812 drvdata->traceid = 0x1;
813
814 /* Set invariant transaction timing on all channels */
815 bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);
816}
817
818static void stm_init_generic_data(struct stm_drvdata *drvdata,
819 const char *name)
820{
821 drvdata->stm.name = name;
822
823 /*
824 * MasterIDs are assigned at HW design phase. As such the core is
825 * using a single master for interaction with this device.
826 */
827 drvdata->stm.sw_start = 1;
828 drvdata->stm.sw_end = 1;
829 drvdata->stm.hw_override = true;
830 drvdata->stm.sw_nchannels = drvdata->numsp;
831 drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL;
832 drvdata->stm.packet = stm_generic_packet;
833 drvdata->stm.mmio_addr = stm_mmio_addr;
834 drvdata->stm.link = stm_generic_link;
835 drvdata->stm.unlink = stm_generic_unlink;
836 drvdata->stm.set_options = stm_generic_set_options;
837}
838
839static int stm_probe(struct amba_device *adev, const struct amba_id *id)
840{
841 int ret;
842 void __iomem *base;
843 struct device *dev = &adev->dev;
844 struct coresight_platform_data *pdata = NULL;
845 struct stm_drvdata *drvdata;
846 struct resource *res = &adev->res;
847 struct resource ch_res;
848 struct coresight_desc desc = { 0 };
849
850 desc.name = coresight_alloc_device_name(&stm_devs, dev);
851 if (!desc.name)
852 return -ENOMEM;
853
854 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
855 if (!drvdata)
856 return -ENOMEM;
857
858 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
859 if (!IS_ERR(drvdata->atclk)) {
860 ret = clk_prepare_enable(drvdata->atclk);
861 if (ret)
862 return ret;
863 }
864 dev_set_drvdata(dev, drvdata);
865
866 base = devm_ioremap_resource(dev, res);
867 if (IS_ERR(base))
868 return PTR_ERR(base);
869 drvdata->base = base;
870 desc.access = CSDEV_ACCESS_IOMEM(base);
871
872 ret = stm_get_stimulus_area(dev, &ch_res);
873 if (ret)
874 return ret;
875 drvdata->chs.phys = ch_res.start;
876
877 base = devm_ioremap_resource(dev, &ch_res);
878 if (IS_ERR(base))
879 return PTR_ERR(base);
880 drvdata->chs.base = base;
881
882 drvdata->write_bytes = stm_fundamental_data_size(drvdata);
883
884 if (boot_nr_channel)
885 drvdata->numsp = boot_nr_channel;
886 else
887 drvdata->numsp = stm_num_stimulus_port(drvdata);
888
889 drvdata->chs.guaranteed = devm_bitmap_zalloc(dev, drvdata->numsp,
890 GFP_KERNEL);
891 if (!drvdata->chs.guaranteed)
892 return -ENOMEM;
893
894 spin_lock_init(&drvdata->spinlock);
895
896 stm_init_default_data(drvdata);
897 stm_init_generic_data(drvdata, desc.name);
898
899 if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) {
900 dev_info(dev,
901 "%s : stm_register_device failed, probing deferred\n",
902 desc.name);
903 return -EPROBE_DEFER;
904 }
905
906 pdata = coresight_get_platform_data(dev);
907 if (IS_ERR(pdata)) {
908 ret = PTR_ERR(pdata);
909 goto stm_unregister;
910 }
911 adev->dev.platform_data = pdata;
912
913 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
914 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE;
915 desc.ops = &stm_cs_ops;
916 desc.pdata = pdata;
917 desc.dev = dev;
918 desc.groups = coresight_stm_groups;
919 drvdata->csdev = coresight_register(&desc);
920 if (IS_ERR(drvdata->csdev)) {
921 ret = PTR_ERR(drvdata->csdev);
922 goto stm_unregister;
923 }
924
925 pm_runtime_put(&adev->dev);
926
927 dev_info(&drvdata->csdev->dev, "%s initialized\n",
928 (char *)coresight_get_uci_data(id));
929 return 0;
930
931stm_unregister:
932 stm_unregister_device(&drvdata->stm);
933 return ret;
934}
935
936static void stm_remove(struct amba_device *adev)
937{
938 struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
939
940 coresight_unregister(drvdata->csdev);
941
942 stm_unregister_device(&drvdata->stm);
943}
944
945#ifdef CONFIG_PM
946static int stm_runtime_suspend(struct device *dev)
947{
948 struct stm_drvdata *drvdata = dev_get_drvdata(dev);
949
950 if (drvdata && !IS_ERR(drvdata->atclk))
951 clk_disable_unprepare(drvdata->atclk);
952
953 return 0;
954}
955
956static int stm_runtime_resume(struct device *dev)
957{
958 struct stm_drvdata *drvdata = dev_get_drvdata(dev);
959
960 if (drvdata && !IS_ERR(drvdata->atclk))
961 clk_prepare_enable(drvdata->atclk);
962
963 return 0;
964}
965#endif
966
967static const struct dev_pm_ops stm_dev_pm_ops = {
968 SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL)
969};
970
971static const struct amba_id stm_ids[] = {
972 CS_AMBA_ID_DATA(0x000bb962, "STM32"),
973 CS_AMBA_ID_DATA(0x000bb963, "STM500"),
974 { 0, 0},
975};
976
977MODULE_DEVICE_TABLE(amba, stm_ids);
978
979static struct amba_driver stm_driver = {
980 .drv = {
981 .name = "coresight-stm",
982 .owner = THIS_MODULE,
983 .pm = &stm_dev_pm_ops,
984 .suppress_bind_attrs = true,
985 },
986 .probe = stm_probe,
987 .remove = stm_remove,
988 .id_table = stm_ids,
989};
990
991module_amba_driver(stm_driver);
992
993MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
994MODULE_DESCRIPTION("Arm CoreSight System Trace Macrocell driver");
995MODULE_LICENSE("GPL v2");
1/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
2 *
3 * Description: CoreSight System Trace Macrocell driver
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * Initial implementation by Pratik Patel
15 * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
16 *
17 * Serious refactoring, code cleanup and upgrading to the Coresight upstream
18 * framework by Mathieu Poirier
19 * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
20 *
21 * Guaranteed timing and support for various packet type coming from the
22 * generic STM API by Chunyan Zhang
23 * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
24 */
25#include <asm/local.h>
26#include <linux/amba/bus.h>
27#include <linux/bitmap.h>
28#include <linux/clk.h>
29#include <linux/coresight.h>
30#include <linux/coresight-stm.h>
31#include <linux/err.h>
32#include <linux/kernel.h>
33#include <linux/moduleparam.h>
34#include <linux/of_address.h>
35#include <linux/perf_event.h>
36#include <linux/pm_runtime.h>
37#include <linux/stm.h>
38
39#include "coresight-priv.h"
40
41#define STMDMASTARTR 0xc04
42#define STMDMASTOPR 0xc08
43#define STMDMASTATR 0xc0c
44#define STMDMACTLR 0xc10
45#define STMDMAIDR 0xcfc
46#define STMHEER 0xd00
47#define STMHETER 0xd20
48#define STMHEBSR 0xd60
49#define STMHEMCR 0xd64
50#define STMHEMASTR 0xdf4
51#define STMHEFEAT1R 0xdf8
52#define STMHEIDR 0xdfc
53#define STMSPER 0xe00
54#define STMSPTER 0xe20
55#define STMPRIVMASKR 0xe40
56#define STMSPSCR 0xe60
57#define STMSPMSCR 0xe64
58#define STMSPOVERRIDER 0xe68
59#define STMSPMOVERRIDER 0xe6c
60#define STMSPTRIGCSR 0xe70
61#define STMTCSR 0xe80
62#define STMTSSTIMR 0xe84
63#define STMTSFREQR 0xe8c
64#define STMSYNCR 0xe90
65#define STMAUXCR 0xe94
66#define STMSPFEAT1R 0xea0
67#define STMSPFEAT2R 0xea4
68#define STMSPFEAT3R 0xea8
69#define STMITTRIGGER 0xee8
70#define STMITATBDATA0 0xeec
71#define STMITATBCTR2 0xef0
72#define STMITATBID 0xef4
73#define STMITATBCTR0 0xef8
74
75#define STM_32_CHANNEL 32
76#define BYTES_PER_CHANNEL 256
77#define STM_TRACE_BUF_SIZE 4096
78#define STM_SW_MASTER_END 127
79
80/* Register bit definition */
81#define STMTCSR_BUSY_BIT 23
82/* Reserve the first 10 channels for kernel usage */
83#define STM_CHANNEL_OFFSET 0
84
85enum stm_pkt_type {
86 STM_PKT_TYPE_DATA = 0x98,
87 STM_PKT_TYPE_FLAG = 0xE8,
88 STM_PKT_TYPE_TRIG = 0xF8,
89};
90
91#define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \
92 (ch * BYTES_PER_CHANNEL))
93#define stm_channel_off(type, opts) (type & ~opts)
94
95static int boot_nr_channel;
96
97/*
98 * Not really modular but using module_param is the easiest way to
99 * remain consistent with existing use cases for now.
100 */
101module_param_named(
102 boot_nr_channel, boot_nr_channel, int, S_IRUGO
103);
104
105/**
106 * struct channel_space - central management entity for extended ports
107 * @base: memory mapped base address where channels start.
108 * @phys: physical base address of channel region.
109 * @guaraneed: is the channel delivery guaranteed.
110 */
111struct channel_space {
112 void __iomem *base;
113 phys_addr_t phys;
114 unsigned long *guaranteed;
115};
116
117/**
118 * struct stm_drvdata - specifics associated to an STM component
119 * @base: memory mapped base address for this component.
120 * @dev: the device entity associated to this component.
121 * @atclk: optional clock for the core parts of the STM.
122 * @csdev: component vitals needed by the framework.
123 * @spinlock: only one at a time pls.
124 * @chs: the channels accociated to this STM.
125 * @stm: structure associated to the generic STM interface.
126 * @mode: this tracer's mode, i.e sysFS, or disabled.
127 * @traceid: value of the current ID for this component.
128 * @write_bytes: Maximus bytes this STM can write at a time.
129 * @stmsper: settings for register STMSPER.
130 * @stmspscr: settings for register STMSPSCR.
131 * @numsp: the total number of stimulus port support by this STM.
132 * @stmheer: settings for register STMHEER.
133 * @stmheter: settings for register STMHETER.
134 * @stmhebsr: settings for register STMHEBSR.
135 */
136struct stm_drvdata {
137 void __iomem *base;
138 struct device *dev;
139 struct clk *atclk;
140 struct coresight_device *csdev;
141 spinlock_t spinlock;
142 struct channel_space chs;
143 struct stm_data stm;
144 local_t mode;
145 u8 traceid;
146 u32 write_bytes;
147 u32 stmsper;
148 u32 stmspscr;
149 u32 numsp;
150 u32 stmheer;
151 u32 stmheter;
152 u32 stmhebsr;
153};
154
155static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
156{
157 CS_UNLOCK(drvdata->base);
158
159 writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
160 writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
161 writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
162 writel_relaxed(0x01 | /* Enable HW event tracing */
163 0x04, /* Error detection on event tracing */
164 drvdata->base + STMHEMCR);
165
166 CS_LOCK(drvdata->base);
167}
168
169static void stm_port_enable_hw(struct stm_drvdata *drvdata)
170{
171 CS_UNLOCK(drvdata->base);
172 /* ATB trigger enable on direct writes to TRIG locations */
173 writel_relaxed(0x10,
174 drvdata->base + STMSPTRIGCSR);
175 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
176 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
177
178 CS_LOCK(drvdata->base);
179}
180
181static void stm_enable_hw(struct stm_drvdata *drvdata)
182{
183 if (drvdata->stmheer)
184 stm_hwevent_enable_hw(drvdata);
185
186 stm_port_enable_hw(drvdata);
187
188 CS_UNLOCK(drvdata->base);
189
190 /* 4096 byte between synchronisation packets */
191 writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
192 writel_relaxed((drvdata->traceid << 16 | /* trace id */
193 0x02 | /* timestamp enable */
194 0x01), /* global STM enable */
195 drvdata->base + STMTCSR);
196
197 CS_LOCK(drvdata->base);
198}
199
200static int stm_enable(struct coresight_device *csdev,
201 struct perf_event *event, u32 mode)
202{
203 u32 val;
204 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
205
206 if (mode != CS_MODE_SYSFS)
207 return -EINVAL;
208
209 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
210
211 /* Someone is already using the tracer */
212 if (val)
213 return -EBUSY;
214
215 pm_runtime_get_sync(drvdata->dev);
216
217 spin_lock(&drvdata->spinlock);
218 stm_enable_hw(drvdata);
219 spin_unlock(&drvdata->spinlock);
220
221 dev_info(drvdata->dev, "STM tracing enabled\n");
222 return 0;
223}
224
225static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata)
226{
227 CS_UNLOCK(drvdata->base);
228
229 writel_relaxed(0x0, drvdata->base + STMHEMCR);
230 writel_relaxed(0x0, drvdata->base + STMHEER);
231 writel_relaxed(0x0, drvdata->base + STMHETER);
232
233 CS_LOCK(drvdata->base);
234}
235
236static void stm_port_disable_hw(struct stm_drvdata *drvdata)
237{
238 CS_UNLOCK(drvdata->base);
239
240 writel_relaxed(0x0, drvdata->base + STMSPER);
241 writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
242
243 CS_LOCK(drvdata->base);
244}
245
246static void stm_disable_hw(struct stm_drvdata *drvdata)
247{
248 u32 val;
249
250 CS_UNLOCK(drvdata->base);
251
252 val = readl_relaxed(drvdata->base + STMTCSR);
253 val &= ~0x1; /* clear global STM enable [0] */
254 writel_relaxed(val, drvdata->base + STMTCSR);
255
256 CS_LOCK(drvdata->base);
257
258 stm_port_disable_hw(drvdata);
259 if (drvdata->stmheer)
260 stm_hwevent_disable_hw(drvdata);
261}
262
263static void stm_disable(struct coresight_device *csdev,
264 struct perf_event *event)
265{
266 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
267
268 /*
269 * For as long as the tracer isn't disabled another entity can't
270 * change its status. As such we can read the status here without
271 * fearing it will change under us.
272 */
273 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
274 spin_lock(&drvdata->spinlock);
275 stm_disable_hw(drvdata);
276 spin_unlock(&drvdata->spinlock);
277
278 /* Wait until the engine has completely stopped */
279 coresight_timeout(drvdata, STMTCSR, STMTCSR_BUSY_BIT, 0);
280
281 pm_runtime_put(drvdata->dev);
282
283 local_set(&drvdata->mode, CS_MODE_DISABLED);
284 dev_info(drvdata->dev, "STM tracing disabled\n");
285 }
286}
287
288static int stm_trace_id(struct coresight_device *csdev)
289{
290 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
291
292 return drvdata->traceid;
293}
294
295static const struct coresight_ops_source stm_source_ops = {
296 .trace_id = stm_trace_id,
297 .enable = stm_enable,
298 .disable = stm_disable,
299};
300
301static const struct coresight_ops stm_cs_ops = {
302 .source_ops = &stm_source_ops,
303};
304
305static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes)
306{
307 return ((unsigned long)addr & (write_bytes - 1));
308}
309
310static void stm_send(void *addr, const void *data, u32 size, u8 write_bytes)
311{
312 u8 paload[8];
313
314 if (stm_addr_unaligned(data, write_bytes)) {
315 memcpy(paload, data, size);
316 data = paload;
317 }
318
319 /* now we are 64bit/32bit aligned */
320 switch (size) {
321#ifdef CONFIG_64BIT
322 case 8:
323 writeq_relaxed(*(u64 *)data, addr);
324 break;
325#endif
326 case 4:
327 writel_relaxed(*(u32 *)data, addr);
328 break;
329 case 2:
330 writew_relaxed(*(u16 *)data, addr);
331 break;
332 case 1:
333 writeb_relaxed(*(u8 *)data, addr);
334 break;
335 default:
336 break;
337 }
338}
339
340static int stm_generic_link(struct stm_data *stm_data,
341 unsigned int master, unsigned int channel)
342{
343 struct stm_drvdata *drvdata = container_of(stm_data,
344 struct stm_drvdata, stm);
345 if (!drvdata || !drvdata->csdev)
346 return -EINVAL;
347
348 return coresight_enable(drvdata->csdev);
349}
350
351static void stm_generic_unlink(struct stm_data *stm_data,
352 unsigned int master, unsigned int channel)
353{
354 struct stm_drvdata *drvdata = container_of(stm_data,
355 struct stm_drvdata, stm);
356 if (!drvdata || !drvdata->csdev)
357 return;
358
359 coresight_disable(drvdata->csdev);
360}
361
362static phys_addr_t
363stm_mmio_addr(struct stm_data *stm_data, unsigned int master,
364 unsigned int channel, unsigned int nr_chans)
365{
366 struct stm_drvdata *drvdata = container_of(stm_data,
367 struct stm_drvdata, stm);
368 phys_addr_t addr;
369
370 addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL;
371
372 if (offset_in_page(addr) ||
373 offset_in_page(nr_chans * BYTES_PER_CHANNEL))
374 return 0;
375
376 return addr;
377}
378
379static long stm_generic_set_options(struct stm_data *stm_data,
380 unsigned int master,
381 unsigned int channel,
382 unsigned int nr_chans,
383 unsigned long options)
384{
385 struct stm_drvdata *drvdata = container_of(stm_data,
386 struct stm_drvdata, stm);
387 if (!(drvdata && local_read(&drvdata->mode)))
388 return -EINVAL;
389
390 if (channel >= drvdata->numsp)
391 return -EINVAL;
392
393 switch (options) {
394 case STM_OPTION_GUARANTEED:
395 set_bit(channel, drvdata->chs.guaranteed);
396 break;
397
398 case STM_OPTION_INVARIANT:
399 clear_bit(channel, drvdata->chs.guaranteed);
400 break;
401
402 default:
403 return -EINVAL;
404 }
405
406 return 0;
407}
408
409static ssize_t notrace stm_generic_packet(struct stm_data *stm_data,
410 unsigned int master,
411 unsigned int channel,
412 unsigned int packet,
413 unsigned int flags,
414 unsigned int size,
415 const unsigned char *payload)
416{
417 unsigned long ch_addr;
418 struct stm_drvdata *drvdata = container_of(stm_data,
419 struct stm_drvdata, stm);
420
421 if (!(drvdata && local_read(&drvdata->mode)))
422 return -EACCES;
423
424 if (channel >= drvdata->numsp)
425 return -EINVAL;
426
427 ch_addr = (unsigned long)stm_channel_addr(drvdata, channel);
428
429 flags = (flags == STP_PACKET_TIMESTAMPED) ? STM_FLAG_TIMESTAMPED : 0;
430 flags |= test_bit(channel, drvdata->chs.guaranteed) ?
431 STM_FLAG_GUARANTEED : 0;
432
433 if (size > drvdata->write_bytes)
434 size = drvdata->write_bytes;
435 else
436 size = rounddown_pow_of_two(size);
437
438 switch (packet) {
439 case STP_PACKET_FLAG:
440 ch_addr |= stm_channel_off(STM_PKT_TYPE_FLAG, flags);
441
442 /*
443 * The generic STM core sets a size of '0' on flag packets.
444 * As such send a flag packet of size '1' and tell the
445 * core we did so.
446 */
447 stm_send((void *)ch_addr, payload, 1, drvdata->write_bytes);
448 size = 1;
449 break;
450
451 case STP_PACKET_DATA:
452 ch_addr |= stm_channel_off(STM_PKT_TYPE_DATA, flags);
453 stm_send((void *)ch_addr, payload, size,
454 drvdata->write_bytes);
455 break;
456
457 default:
458 return -ENOTSUPP;
459 }
460
461 return size;
462}
463
464static ssize_t hwevent_enable_show(struct device *dev,
465 struct device_attribute *attr, char *buf)
466{
467 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
468 unsigned long val = drvdata->stmheer;
469
470 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
471}
472
473static ssize_t hwevent_enable_store(struct device *dev,
474 struct device_attribute *attr,
475 const char *buf, size_t size)
476{
477 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
478 unsigned long val;
479 int ret = 0;
480
481 ret = kstrtoul(buf, 16, &val);
482 if (ret)
483 return -EINVAL;
484
485 drvdata->stmheer = val;
486 /* HW event enable and trigger go hand in hand */
487 drvdata->stmheter = val;
488
489 return size;
490}
491static DEVICE_ATTR_RW(hwevent_enable);
492
493static ssize_t hwevent_select_show(struct device *dev,
494 struct device_attribute *attr, char *buf)
495{
496 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
497 unsigned long val = drvdata->stmhebsr;
498
499 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
500}
501
502static ssize_t hwevent_select_store(struct device *dev,
503 struct device_attribute *attr,
504 const char *buf, size_t size)
505{
506 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
507 unsigned long val;
508 int ret = 0;
509
510 ret = kstrtoul(buf, 16, &val);
511 if (ret)
512 return -EINVAL;
513
514 drvdata->stmhebsr = val;
515
516 return size;
517}
518static DEVICE_ATTR_RW(hwevent_select);
519
520static ssize_t port_select_show(struct device *dev,
521 struct device_attribute *attr, char *buf)
522{
523 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
524 unsigned long val;
525
526 if (!local_read(&drvdata->mode)) {
527 val = drvdata->stmspscr;
528 } else {
529 spin_lock(&drvdata->spinlock);
530 val = readl_relaxed(drvdata->base + STMSPSCR);
531 spin_unlock(&drvdata->spinlock);
532 }
533
534 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
535}
536
537static ssize_t port_select_store(struct device *dev,
538 struct device_attribute *attr,
539 const char *buf, size_t size)
540{
541 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
542 unsigned long val, stmsper;
543 int ret = 0;
544
545 ret = kstrtoul(buf, 16, &val);
546 if (ret)
547 return ret;
548
549 spin_lock(&drvdata->spinlock);
550 drvdata->stmspscr = val;
551
552 if (local_read(&drvdata->mode)) {
553 CS_UNLOCK(drvdata->base);
554 /* Process as per ARM's TRM recommendation */
555 stmsper = readl_relaxed(drvdata->base + STMSPER);
556 writel_relaxed(0x0, drvdata->base + STMSPER);
557 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
558 writel_relaxed(stmsper, drvdata->base + STMSPER);
559 CS_LOCK(drvdata->base);
560 }
561 spin_unlock(&drvdata->spinlock);
562
563 return size;
564}
565static DEVICE_ATTR_RW(port_select);
566
567static ssize_t port_enable_show(struct device *dev,
568 struct device_attribute *attr, char *buf)
569{
570 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
571 unsigned long val;
572
573 if (!local_read(&drvdata->mode)) {
574 val = drvdata->stmsper;
575 } else {
576 spin_lock(&drvdata->spinlock);
577 val = readl_relaxed(drvdata->base + STMSPER);
578 spin_unlock(&drvdata->spinlock);
579 }
580
581 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
582}
583
584static ssize_t port_enable_store(struct device *dev,
585 struct device_attribute *attr,
586 const char *buf, size_t size)
587{
588 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
589 unsigned long val;
590 int ret = 0;
591
592 ret = kstrtoul(buf, 16, &val);
593 if (ret)
594 return ret;
595
596 spin_lock(&drvdata->spinlock);
597 drvdata->stmsper = val;
598
599 if (local_read(&drvdata->mode)) {
600 CS_UNLOCK(drvdata->base);
601 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
602 CS_LOCK(drvdata->base);
603 }
604 spin_unlock(&drvdata->spinlock);
605
606 return size;
607}
608static DEVICE_ATTR_RW(port_enable);
609
610static ssize_t traceid_show(struct device *dev,
611 struct device_attribute *attr, char *buf)
612{
613 unsigned long val;
614 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
615
616 val = drvdata->traceid;
617 return sprintf(buf, "%#lx\n", val);
618}
619
620static ssize_t traceid_store(struct device *dev,
621 struct device_attribute *attr,
622 const char *buf, size_t size)
623{
624 int ret;
625 unsigned long val;
626 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
627
628 ret = kstrtoul(buf, 16, &val);
629 if (ret)
630 return ret;
631
632 /* traceid field is 7bit wide on STM32 */
633 drvdata->traceid = val & 0x7f;
634 return size;
635}
636static DEVICE_ATTR_RW(traceid);
637
638#define coresight_stm_simple_func(name, offset) \
639 coresight_simple_func(struct stm_drvdata, NULL, name, offset)
640
641coresight_stm_simple_func(tcsr, STMTCSR);
642coresight_stm_simple_func(tsfreqr, STMTSFREQR);
643coresight_stm_simple_func(syncr, STMSYNCR);
644coresight_stm_simple_func(sper, STMSPER);
645coresight_stm_simple_func(spter, STMSPTER);
646coresight_stm_simple_func(privmaskr, STMPRIVMASKR);
647coresight_stm_simple_func(spscr, STMSPSCR);
648coresight_stm_simple_func(spmscr, STMSPMSCR);
649coresight_stm_simple_func(spfeat1r, STMSPFEAT1R);
650coresight_stm_simple_func(spfeat2r, STMSPFEAT2R);
651coresight_stm_simple_func(spfeat3r, STMSPFEAT3R);
652coresight_stm_simple_func(devid, CORESIGHT_DEVID);
653
654static struct attribute *coresight_stm_attrs[] = {
655 &dev_attr_hwevent_enable.attr,
656 &dev_attr_hwevent_select.attr,
657 &dev_attr_port_enable.attr,
658 &dev_attr_port_select.attr,
659 &dev_attr_traceid.attr,
660 NULL,
661};
662
663static struct attribute *coresight_stm_mgmt_attrs[] = {
664 &dev_attr_tcsr.attr,
665 &dev_attr_tsfreqr.attr,
666 &dev_attr_syncr.attr,
667 &dev_attr_sper.attr,
668 &dev_attr_spter.attr,
669 &dev_attr_privmaskr.attr,
670 &dev_attr_spscr.attr,
671 &dev_attr_spmscr.attr,
672 &dev_attr_spfeat1r.attr,
673 &dev_attr_spfeat2r.attr,
674 &dev_attr_spfeat3r.attr,
675 &dev_attr_devid.attr,
676 NULL,
677};
678
679static const struct attribute_group coresight_stm_group = {
680 .attrs = coresight_stm_attrs,
681};
682
683static const struct attribute_group coresight_stm_mgmt_group = {
684 .attrs = coresight_stm_mgmt_attrs,
685 .name = "mgmt",
686};
687
688static const struct attribute_group *coresight_stm_groups[] = {
689 &coresight_stm_group,
690 &coresight_stm_mgmt_group,
691 NULL,
692};
693
694static int stm_get_resource_byname(struct device_node *np,
695 char *ch_base, struct resource *res)
696{
697 const char *name = NULL;
698 int index = 0, found = 0;
699
700 while (!of_property_read_string_index(np, "reg-names", index, &name)) {
701 if (strcmp(ch_base, name)) {
702 index++;
703 continue;
704 }
705
706 /* We have a match and @index is where it's at */
707 found = 1;
708 break;
709 }
710
711 if (!found)
712 return -EINVAL;
713
714 return of_address_to_resource(np, index, res);
715}
716
717static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata)
718{
719 u32 stmspfeat2r;
720
721 if (!IS_ENABLED(CONFIG_64BIT))
722 return 4;
723
724 stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R);
725
726 /*
727 * bit[15:12] represents the fundamental data size
728 * 0 - 32-bit data
729 * 1 - 64-bit data
730 */
731 return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4;
732}
733
734static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata)
735{
736 u32 numsp;
737
738 numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
739 /*
740 * NUMPS in STMDEVID is 17 bit long and if equal to 0x0,
741 * 32 stimulus ports are supported.
742 */
743 numsp &= 0x1ffff;
744 if (!numsp)
745 numsp = STM_32_CHANNEL;
746 return numsp;
747}
748
749static void stm_init_default_data(struct stm_drvdata *drvdata)
750{
751 /* Don't use port selection */
752 drvdata->stmspscr = 0x0;
753 /*
754 * Enable all channel regardless of their number. When port
755 * selection isn't used (see above) STMSPER applies to all
756 * 32 channel group available, hence setting all 32 bits to 1
757 */
758 drvdata->stmsper = ~0x0;
759
760 /*
761 * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and
762 * anything equal to or higher than 0x70 is reserved. Since 0x00 is
763 * also reserved the STM trace ID needs to be higher than 0x00 and
764 * lowner than 0x10.
765 */
766 drvdata->traceid = 0x1;
767
768 /* Set invariant transaction timing on all channels */
769 bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);
770}
771
772static void stm_init_generic_data(struct stm_drvdata *drvdata)
773{
774 drvdata->stm.name = dev_name(drvdata->dev);
775
776 /*
777 * MasterIDs are assigned at HW design phase. As such the core is
778 * using a single master for interaction with this device.
779 */
780 drvdata->stm.sw_start = 1;
781 drvdata->stm.sw_end = 1;
782 drvdata->stm.hw_override = true;
783 drvdata->stm.sw_nchannels = drvdata->numsp;
784 drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL;
785 drvdata->stm.packet = stm_generic_packet;
786 drvdata->stm.mmio_addr = stm_mmio_addr;
787 drvdata->stm.link = stm_generic_link;
788 drvdata->stm.unlink = stm_generic_unlink;
789 drvdata->stm.set_options = stm_generic_set_options;
790}
791
792static int stm_probe(struct amba_device *adev, const struct amba_id *id)
793{
794 int ret;
795 void __iomem *base;
796 unsigned long *guaranteed;
797 struct device *dev = &adev->dev;
798 struct coresight_platform_data *pdata = NULL;
799 struct stm_drvdata *drvdata;
800 struct resource *res = &adev->res;
801 struct resource ch_res;
802 size_t res_size, bitmap_size;
803 struct coresight_desc desc = { 0 };
804 struct device_node *np = adev->dev.of_node;
805
806 if (np) {
807 pdata = of_get_coresight_platform_data(dev, np);
808 if (IS_ERR(pdata))
809 return PTR_ERR(pdata);
810 adev->dev.platform_data = pdata;
811 }
812 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
813 if (!drvdata)
814 return -ENOMEM;
815
816 drvdata->dev = &adev->dev;
817 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
818 if (!IS_ERR(drvdata->atclk)) {
819 ret = clk_prepare_enable(drvdata->atclk);
820 if (ret)
821 return ret;
822 }
823 dev_set_drvdata(dev, drvdata);
824
825 base = devm_ioremap_resource(dev, res);
826 if (IS_ERR(base))
827 return PTR_ERR(base);
828 drvdata->base = base;
829
830 ret = stm_get_resource_byname(np, "stm-stimulus-base", &ch_res);
831 if (ret)
832 return ret;
833 drvdata->chs.phys = ch_res.start;
834
835 base = devm_ioremap_resource(dev, &ch_res);
836 if (IS_ERR(base))
837 return PTR_ERR(base);
838 drvdata->chs.base = base;
839
840 drvdata->write_bytes = stm_fundamental_data_size(drvdata);
841
842 if (boot_nr_channel) {
843 drvdata->numsp = boot_nr_channel;
844 res_size = min((resource_size_t)(boot_nr_channel *
845 BYTES_PER_CHANNEL), resource_size(res));
846 } else {
847 drvdata->numsp = stm_num_stimulus_port(drvdata);
848 res_size = min((resource_size_t)(drvdata->numsp *
849 BYTES_PER_CHANNEL), resource_size(res));
850 }
851 bitmap_size = BITS_TO_LONGS(drvdata->numsp) * sizeof(long);
852
853 guaranteed = devm_kzalloc(dev, bitmap_size, GFP_KERNEL);
854 if (!guaranteed)
855 return -ENOMEM;
856 drvdata->chs.guaranteed = guaranteed;
857
858 spin_lock_init(&drvdata->spinlock);
859
860 stm_init_default_data(drvdata);
861 stm_init_generic_data(drvdata);
862
863 if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) {
864 dev_info(dev,
865 "stm_register_device failed, probing deffered\n");
866 return -EPROBE_DEFER;
867 }
868
869 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
870 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE;
871 desc.ops = &stm_cs_ops;
872 desc.pdata = pdata;
873 desc.dev = dev;
874 desc.groups = coresight_stm_groups;
875 drvdata->csdev = coresight_register(&desc);
876 if (IS_ERR(drvdata->csdev)) {
877 ret = PTR_ERR(drvdata->csdev);
878 goto stm_unregister;
879 }
880
881 pm_runtime_put(&adev->dev);
882
883 dev_info(dev, "%s initialized\n", (char *)id->data);
884 return 0;
885
886stm_unregister:
887 stm_unregister_device(&drvdata->stm);
888 return ret;
889}
890
891#ifdef CONFIG_PM
892static int stm_runtime_suspend(struct device *dev)
893{
894 struct stm_drvdata *drvdata = dev_get_drvdata(dev);
895
896 if (drvdata && !IS_ERR(drvdata->atclk))
897 clk_disable_unprepare(drvdata->atclk);
898
899 return 0;
900}
901
902static int stm_runtime_resume(struct device *dev)
903{
904 struct stm_drvdata *drvdata = dev_get_drvdata(dev);
905
906 if (drvdata && !IS_ERR(drvdata->atclk))
907 clk_prepare_enable(drvdata->atclk);
908
909 return 0;
910}
911#endif
912
913static const struct dev_pm_ops stm_dev_pm_ops = {
914 SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL)
915};
916
917static struct amba_id stm_ids[] = {
918 {
919 .id = 0x0003b962,
920 .mask = 0x0003ffff,
921 .data = "STM32",
922 },
923 {
924 .id = 0x0003b963,
925 .mask = 0x0003ffff,
926 .data = "STM500",
927 },
928 { 0, 0},
929};
930
931static struct amba_driver stm_driver = {
932 .drv = {
933 .name = "coresight-stm",
934 .owner = THIS_MODULE,
935 .pm = &stm_dev_pm_ops,
936 .suppress_bind_attrs = true,
937 },
938 .probe = stm_probe,
939 .id_table = stm_ids,
940};
941
942builtin_amba_driver(stm_driver);