1/*
   2 * Copyright 2009 Jerome Glisse.
   3 * All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the
   7 * "Software"), to deal in the Software without restriction, including
   8 * without limitation the rights to use, copy, modify, merge, publish,
   9 * distribute, sub license, and/or sell copies of the Software, and to
  10 * permit persons to whom the Software is furnished to do so, subject to
  11 * the following conditions:
  12 *
  13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20 *
  21 * The above copyright notice and this permission notice (including the
  22 * next paragraph) shall be included in all copies or substantial portions
  23 * of the Software.
  24 *
  25 */
  26/*
  27 * Authors:
  28 *    Jerome Glisse <glisse@freedesktop.org>
  29 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30 *    Dave Airlie
  31 */
  32
  33#include <linux/dma-mapping.h>
  34#include <linux/iommu.h>
  35#include <linux/pagemap.h>
  36#include <linux/sched/task.h>
  37#include <linux/sched/mm.h>
 
  38#include <linux/seq_file.h>
  39#include <linux/slab.h>
  40#include <linux/swap.h>
  41#include <linux/swiotlb.h>
  42#include <linux/dma-buf.h>
  43#include <linux/sizes.h>
  44#include <linux/module.h>
  45
  46#include <drm/drm_drv.h>
  47#include <drm/ttm/ttm_bo_api.h>
  48#include <drm/ttm/ttm_bo_driver.h>
  49#include <drm/ttm/ttm_placement.h>
  50#include <drm/ttm/ttm_range_manager.h>
  51
  52#include <drm/amdgpu_drm.h>
  53#include <drm/drm_drv.h>
  54
  55#include "amdgpu.h"
  56#include "amdgpu_object.h"
  57#include "amdgpu_trace.h"
  58#include "amdgpu_amdkfd.h"
  59#include "amdgpu_sdma.h"
  60#include "amdgpu_ras.h"
  61#include "amdgpu_hmm.h"
  62#include "amdgpu_atomfirmware.h"
  63#include "amdgpu_res_cursor.h"
  64#include "bif/bif_4_1_d.h"
  65
  66MODULE_IMPORT_NS(DMA_BUF);
  67
  68#define AMDGPU_TTM_VRAM_MAX_DW_READ	(size_t)128
 
  69
  70static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
  71				   struct ttm_tt *ttm,
  72				   struct ttm_resource *bo_mem);
  73static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
  74				      struct ttm_tt *ttm);
  75
  76static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  77				    unsigned int type,
  78				    uint64_t size_in_page)
  79{
  80	return ttm_range_man_init(&adev->mman.bdev, type,
  81				  false, size_in_page);
  82}
  83
  84/**
  85 * amdgpu_evict_flags - Compute placement flags
  86 *
  87 * @bo: The buffer object to evict
  88 * @placement: Possible destination(s) for evicted BO
  89 *
  90 * Fill in placement data when ttm_bo_evict() is called
  91 */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  92static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  93				struct ttm_placement *placement)
  94{
  95	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  96	struct amdgpu_bo *abo;
  97	static const struct ttm_place placements = {
  98		.fpfn = 0,
  99		.lpfn = 0,
 100		.mem_type = TTM_PL_SYSTEM,
 101		.flags = 0
 102	};
 
 103
 104	/* Don't handle scatter gather BOs */
 105	if (bo->type == ttm_bo_type_sg) {
 106		placement->num_placement = 0;
 107		placement->num_busy_placement = 0;
 108		return;
 109	}
 110
 111	/* Object isn't an AMDGPU object so ignore */
 112	if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 113		placement->placement = &placements;
 114		placement->busy_placement = &placements;
 115		placement->num_placement = 1;
 116		placement->num_busy_placement = 1;
 117		return;
 118	}
 119
 120	abo = ttm_to_amdgpu_bo(bo);
 121	if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) {
 122		placement->num_placement = 0;
 123		placement->num_busy_placement = 0;
 124		return;
 125	}
 126
 127	switch (bo->resource->mem_type) {
 128	case AMDGPU_PL_GDS:
 129	case AMDGPU_PL_GWS:
 130	case AMDGPU_PL_OA:
 131		placement->num_placement = 0;
 132		placement->num_busy_placement = 0;
 133		return;
 134
 135	case TTM_PL_VRAM:
 136		if (!adev->mman.buffer_funcs_enabled) {
 137			/* Move to system memory */
 138			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 139		} else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 140			   !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 141			   amdgpu_bo_in_cpu_visible_vram(abo)) {
 142
 143			/* Try evicting to the CPU inaccessible part of VRAM
 144			 * first, but only set GTT as busy placement, so this
 145			 * BO will be evicted to GTT rather than causing other
 146			 * BOs to be evicted from VRAM
 147			 */
 148			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 149							AMDGPU_GEM_DOMAIN_GTT |
 150							AMDGPU_GEM_DOMAIN_CPU);
 151			abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 152			abo->placements[0].lpfn = 0;
 153			abo->placement.busy_placement = &abo->placements[1];
 154			abo->placement.num_busy_placement = 1;
 155		} else {
 156			/* Move to GTT memory */
 157			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT |
 158							AMDGPU_GEM_DOMAIN_CPU);
 
 
 
 
 
 
 
 
 
 
 
 
 159		}
 160		break;
 161	case TTM_PL_TT:
 162	case AMDGPU_PL_PREEMPT:
 163	default:
 164		amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 165		break;
 166	}
 167	*placement = abo->placement;
 168}
 169
 170/**
 171 * amdgpu_ttm_map_buffer - Map memory into the GART windows
 172 * @bo: buffer object to map
 173 * @mem: memory object to map
 174 * @mm_cur: range to map
 175 * @window: which GART window to use
 176 * @ring: DMA ring to use for the copy
 177 * @tmz: if we should setup a TMZ enabled mapping
 178 * @size: in number of bytes to map, out number of bytes mapped
 179 * @addr: resulting address inside the MC address space
 180 *
 181 * Setup one of the GART windows to access a specific piece of memory or return
 182 * the physical address for local memory.
 183 */
 184static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 185				 struct ttm_resource *mem,
 186				 struct amdgpu_res_cursor *mm_cur,
 187				 unsigned window, struct amdgpu_ring *ring,
 188				 bool tmz, uint64_t *size, uint64_t *addr)
 189{
 190	struct amdgpu_device *adev = ring->adev;
 191	unsigned offset, num_pages, num_dw, num_bytes;
 192	uint64_t src_addr, dst_addr;
 193	struct amdgpu_job *job;
 194	void *cpu_addr;
 195	uint64_t flags;
 196	unsigned int i;
 197	int r;
 198
 199	BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 200	       AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 201
 202	if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT))
 203		return -EINVAL;
 204
 205	/* Map only what can't be accessed directly */
 206	if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 207		*addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
 208			mm_cur->start;
 209		return 0;
 210	}
 211
 212
 213	/*
 214	 * If start begins at an offset inside the page, then adjust the size
 215	 * and addr accordingly
 216	 */
 217	offset = mm_cur->start & ~PAGE_MASK;
 218
 219	num_pages = PFN_UP(*size + offset);
 220	num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE);
 221
 222	*size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset);
 223
 224	*addr = adev->gmc.gart_start;
 225	*addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 226		AMDGPU_GPU_PAGE_SIZE;
 227	*addr += offset;
 228
 229	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 230	num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
 231
 232	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,
 233				     AMDGPU_FENCE_OWNER_UNDEFINED,
 234				     num_dw * 4 + num_bytes,
 235				     AMDGPU_IB_POOL_DELAYED, &job);
 236	if (r)
 237		return r;
 238
 239	src_addr = num_dw * 4;
 240	src_addr += job->ibs[0].gpu_addr;
 241
 242	dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 243	dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 244	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 245				dst_addr, num_bytes, false);
 246
 247	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 248	WARN_ON(job->ibs[0].length_dw > num_dw);
 249
 250	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 251	if (tmz)
 252		flags |= AMDGPU_PTE_TMZ;
 253
 254	cpu_addr = &job->ibs[0].ptr[num_dw];
 
 
 
 255
 256	if (mem->mem_type == TTM_PL_TT) {
 257		dma_addr_t *dma_addr;
 
 
 258
 259		dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
 260		amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr);
 261	} else {
 262		dma_addr_t dma_address;
 
 
 263
 264		dma_address = mm_cur->start;
 265		dma_address += adev->vm_manager.vram_base_offset;
 
 
 
 266
 267		for (i = 0; i < num_pages; ++i) {
 268			amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address,
 269					flags, cpu_addr);
 270			dma_address += PAGE_SIZE;
 271		}
 
 
 272	}
 273
 274	dma_fence_put(amdgpu_job_submit(job));
 275	return 0;
 276}
 277
 278/**
 279 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
 280 * @adev: amdgpu device
 281 * @src: buffer/address where to read from
 282 * @dst: buffer/address where to write to
 283 * @size: number of bytes to copy
 284 * @tmz: if a secure copy should be used
 285 * @resv: resv object to sync to
 286 * @f: Returns the last fence if multiple jobs are submitted.
 287 *
 288 * The function copies @size bytes from {src->mem + src->offset} to
 289 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 290 * move and different for a BO to BO copy.
 291 *
 292 */
 293int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 294			       const struct amdgpu_copy_mem *src,
 295			       const struct amdgpu_copy_mem *dst,
 296			       uint64_t size, bool tmz,
 297			       struct dma_resv *resv,
 298			       struct dma_fence **f)
 299{
 
 300	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 301	struct amdgpu_res_cursor src_mm, dst_mm;
 
 
 
 302	struct dma_fence *fence = NULL;
 303	int r = 0;
 
 
 304
 305	if (!adev->mman.buffer_funcs_enabled) {
 306		DRM_ERROR("Trying to move memory with ring turned off.\n");
 307		return -EINVAL;
 308	}
 309
 310	amdgpu_res_first(src->mem, src->offset, size, &src_mm);
 311	amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
 312
 313	mutex_lock(&adev->mman.gtt_window_lock);
 314	while (src_mm.remaining) {
 315		uint64_t from, to, cur_size;
 316		struct dma_fence *next;
 317
 318		/* Never copy more than 256MiB at once to avoid a timeout */
 319		cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20);
 320
 321		/* Map src to window 0 and dst to window 1. */
 322		r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
 323					  0, ring, tmz, &cur_size, &from);
 324		if (r)
 325			goto error;
 326
 327		r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
 328					  1, ring, tmz, &cur_size, &to);
 329		if (r)
 330			goto error;
 331
 332		r = amdgpu_copy_buffer(ring, from, to, cur_size,
 333				       resv, &next, false, true, tmz);
 
 334		if (r)
 335			goto error;
 336
 337		dma_fence_put(fence);
 338		fence = next;
 339
 340		amdgpu_res_next(&src_mm, cur_size);
 341		amdgpu_res_next(&dst_mm, cur_size);
 342	}
 343error:
 344	mutex_unlock(&adev->mman.gtt_window_lock);
 345	if (f)
 346		*f = dma_fence_get(fence);
 347	dma_fence_put(fence);
 348	return r;
 349}
 350
 351/*
 352 * amdgpu_move_blit - Copy an entire buffer to another buffer
 353 *
 354 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 355 * help move buffers to and from VRAM.
 356 */
 357static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 358			    bool evict,
 359			    struct ttm_resource *new_mem,
 360			    struct ttm_resource *old_mem)
 361{
 362	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 363	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 364	struct amdgpu_copy_mem src, dst;
 365	struct dma_fence *fence = NULL;
 366	int r;
 367
 368	src.bo = bo;
 369	dst.bo = bo;
 370	src.mem = old_mem;
 371	dst.mem = new_mem;
 372	src.offset = 0;
 373	dst.offset = 0;
 374
 375	r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 376				       new_mem->size,
 377				       amdgpu_bo_encrypted(abo),
 378				       bo->base.resv, &fence);
 379	if (r)
 380		goto error;
 381
 382	/* clear the space being freed */
 383	if (old_mem->mem_type == TTM_PL_VRAM &&
 384	    (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 385		struct dma_fence *wipe_fence = NULL;
 
 
 386
 387		r = amdgpu_fill_buffer(abo, AMDGPU_POISON, NULL, &wipe_fence);
 388		if (r) {
 389			goto error;
 390		} else if (wipe_fence) {
 391			dma_fence_put(fence);
 392			fence = wipe_fence;
 393		}
 394	}
 395
 396	/* Always block for VM page tables before committing the new location */
 397	if (bo->type == ttm_bo_type_kernel)
 398		r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 399	else
 400		r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 401	dma_fence_put(fence);
 402	return r;
 403
 404error:
 405	if (fence)
 406		dma_fence_wait(fence, false);
 407	dma_fence_put(fence);
 408	return r;
 409}
 410
 411/*
 412 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 413 *
 414 * Called by amdgpu_bo_move()
 415 */
 416static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 417			       struct ttm_resource *mem)
 418{
 419	u64 mem_size = (u64)mem->size;
 420	struct amdgpu_res_cursor cursor;
 421	u64 end;
 422
 423	if (mem->mem_type == TTM_PL_SYSTEM ||
 424	    mem->mem_type == TTM_PL_TT)
 425		return true;
 426	if (mem->mem_type != TTM_PL_VRAM)
 427		return false;
 428
 429	amdgpu_res_first(mem, 0, mem_size, &cursor);
 430	end = cursor.start + cursor.size;
 431	while (cursor.remaining) {
 432		amdgpu_res_next(&cursor, cursor.size);
 
 
 
 
 
 
 
 
 
 
 
 433
 434		if (!cursor.remaining)
 435			break;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 436
 437		/* ttm_resource_ioremap only supports contiguous memory */
 438		if (end != cursor.start)
 439			return false;
 
 
 
 
 
 
 
 
 440
 441		end = cursor.start + cursor.size;
 
 
 
 
 
 
 
 
 
 
 
 
 
 442	}
 443
 444	return end <= adev->gmc.visible_vram_size;
 
 
 
 
 
 
 
 
 
 445}
 446
 447/*
 448 * amdgpu_bo_move - Move a buffer object to a new memory location
 449 *
 450 * Called by ttm_bo_handle_move_mem()
 451 */
 452static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 453			  struct ttm_operation_ctx *ctx,
 454			  struct ttm_resource *new_mem,
 455			  struct ttm_place *hop)
 456{
 457	struct amdgpu_device *adev;
 458	struct amdgpu_bo *abo;
 459	struct ttm_resource *old_mem = bo->resource;
 460	int r;
 461
 462	if (new_mem->mem_type == TTM_PL_TT ||
 463	    new_mem->mem_type == AMDGPU_PL_PREEMPT) {
 464		r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 465		if (r)
 466			return r;
 467	}
 468
 469	/* Can't move a pinned BO */
 470	abo = ttm_to_amdgpu_bo(bo);
 471	if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 472		return -EINVAL;
 473
 474	adev = amdgpu_ttm_adev(bo->bdev);
 475
 476	if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
 477			 bo->ttm == NULL)) {
 478		ttm_bo_move_null(bo, new_mem);
 479		goto out;
 480	}
 481	if (old_mem->mem_type == TTM_PL_SYSTEM &&
 482	    (new_mem->mem_type == TTM_PL_TT ||
 483	     new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
 484		ttm_bo_move_null(bo, new_mem);
 485		goto out;
 486	}
 487	if ((old_mem->mem_type == TTM_PL_TT ||
 488	     old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
 489	    new_mem->mem_type == TTM_PL_SYSTEM) {
 490		r = ttm_bo_wait_ctx(bo, ctx);
 491		if (r)
 492			return r;
 493
 494		amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 495		ttm_resource_free(bo, &bo->resource);
 496		ttm_bo_assign_mem(bo, new_mem);
 497		goto out;
 498	}
 499
 500	if (old_mem->mem_type == AMDGPU_PL_GDS ||
 501	    old_mem->mem_type == AMDGPU_PL_GWS ||
 502	    old_mem->mem_type == AMDGPU_PL_OA ||
 503	    new_mem->mem_type == AMDGPU_PL_GDS ||
 504	    new_mem->mem_type == AMDGPU_PL_GWS ||
 505	    new_mem->mem_type == AMDGPU_PL_OA) {
 506		/* Nothing to save here */
 507		ttm_bo_move_null(bo, new_mem);
 508		goto out;
 509	}
 510
 511	if (bo->type == ttm_bo_type_device &&
 512	    new_mem->mem_type == TTM_PL_VRAM &&
 513	    old_mem->mem_type != TTM_PL_VRAM) {
 514		/* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 515		 * accesses the BO after it's moved.
 516		 */
 517		abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 518	}
 519
 520	if (adev->mman.buffer_funcs_enabled) {
 521		if (((old_mem->mem_type == TTM_PL_SYSTEM &&
 522		      new_mem->mem_type == TTM_PL_VRAM) ||
 523		     (old_mem->mem_type == TTM_PL_VRAM &&
 524		      new_mem->mem_type == TTM_PL_SYSTEM))) {
 525			hop->fpfn = 0;
 526			hop->lpfn = 0;
 527			hop->mem_type = TTM_PL_TT;
 528			hop->flags = TTM_PL_FLAG_TEMPORARY;
 529			return -EMULTIHOP;
 530		}
 531
 532		r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 533	} else {
 534		r = -ENODEV;
 535	}
 536
 537	if (r) {
 538		/* Check that all memory is CPU accessible */
 539		if (!amdgpu_mem_visible(adev, old_mem) ||
 540		    !amdgpu_mem_visible(adev, new_mem)) {
 541			pr_err("Move buffer fallback to memcpy unavailable\n");
 542			return r;
 543		}
 544
 545		r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 546		if (r)
 547			return r;
 548	}
 549
 550out:
 551	/* update statistics */
 552	atomic64_add(bo->base.size, &adev->num_bytes_moved);
 553	amdgpu_bo_move_notify(bo, evict, new_mem);
 554	return 0;
 555}
 556
 557/*
 558 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 559 *
 560 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 561 */
 562static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
 563				     struct ttm_resource *mem)
 564{
 
 565	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 566	size_t bus_size = (size_t)mem->size;
 567
 
 
 
 
 
 
 
 568	switch (mem->mem_type) {
 569	case TTM_PL_SYSTEM:
 570		/* system memory */
 571		return 0;
 572	case TTM_PL_TT:
 573	case AMDGPU_PL_PREEMPT:
 574		break;
 575	case TTM_PL_VRAM:
 576		mem->bus.offset = mem->start << PAGE_SHIFT;
 577		/* check if it's visible */
 578		if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 579			return -EINVAL;
 580
 581		if (adev->mman.aper_base_kaddr &&
 582		    mem->placement & TTM_PL_FLAG_CONTIGUOUS)
 583			mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 584					mem->bus.offset;
 585
 586		mem->bus.offset += adev->gmc.aper_base;
 587		mem->bus.is_iomem = true;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 588		break;
 589	default:
 590		return -EINVAL;
 591	}
 592	return 0;
 593}
 594
 595static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 596					   unsigned long page_offset)
 597{
 598	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 599	struct amdgpu_res_cursor cursor;
 600
 601	amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
 602			 &cursor);
 603	return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
 604}
 605
 606/**
 607 * amdgpu_ttm_domain_start - Returns GPU start address
 608 * @adev: amdgpu device object
 609 * @type: type of the memory
 610 *
 611 * Returns:
 612 * GPU start address of a memory domain
 613 */
 614
 615uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 616{
 617	switch (type) {
 618	case TTM_PL_TT:
 619		return adev->gmc.gart_start;
 620	case TTM_PL_VRAM:
 621		return adev->gmc.vram_start;
 622	}
 623
 624	return 0;
 625}
 626
 627/*
 628 * TTM backend functions.
 629 */
 
 
 
 
 
 630struct amdgpu_ttm_tt {
 631	struct ttm_tt	ttm;
 632	struct drm_gem_object	*gobj;
 633	u64			offset;
 634	uint64_t		userptr;
 635	struct task_struct	*usertask;
 636	uint32_t		userflags;
 637	bool			bound;
 
 
 
 638};
 639
 640#define ttm_to_amdgpu_ttm_tt(ptr)	container_of(ptr, struct amdgpu_ttm_tt, ttm)
 641
 642#ifdef CONFIG_DRM_AMDGPU_USERPTR
 643/*
 644 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 645 * memory and start HMM tracking CPU page table update
 646 *
 647 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 648 * once afterwards to stop HMM tracking
 649 */
 650int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,
 651				 struct hmm_range **range)
 652{
 653	struct ttm_tt *ttm = bo->tbo.ttm;
 654	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 655	unsigned long start = gtt->userptr;
 656	struct vm_area_struct *vma;
 657	struct mm_struct *mm;
 658	bool readonly;
 659	int r = 0;
 660
 661	/* Make sure get_user_pages_done() can cleanup gracefully */
 662	*range = NULL;
 663
 664	mm = bo->notifier.mm;
 665	if (unlikely(!mm)) {
 666		DRM_DEBUG_DRIVER("BO is not registered?\n");
 667		return -EFAULT;
 668	}
 669
 670	if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 671		return -ESRCH;
 672
 673	mmap_read_lock(mm);
 674	vma = vma_lookup(mm, start);
 675	if (unlikely(!vma)) {
 676		r = -EFAULT;
 677		goto out_unlock;
 678	}
 679	if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 680		vma->vm_file)) {
 681		r = -EPERM;
 682		goto out_unlock;
 683	}
 684
 685	readonly = amdgpu_ttm_tt_is_readonly(ttm);
 686	r = amdgpu_hmm_range_get_pages(&bo->notifier, start, ttm->num_pages,
 687				       readonly, NULL, pages, range);
 688out_unlock:
 689	mmap_read_unlock(mm);
 690	if (r)
 691		pr_debug("failed %d to get user pages 0x%lx\n", r, start);
 692
 693	mmput(mm);
 
 694
 695	return r;
 696}
 
 
 
 697
 698/* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations
 699 */
 700void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
 701				      struct hmm_range *range)
 702{
 703	struct amdgpu_ttm_tt *gtt = (void *)ttm;
 704
 705	if (gtt && gtt->userptr && range)
 706		amdgpu_hmm_range_get_pages_done(range);
 707}
 
 
 708
 709/*
 710 * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change
 711 * Check if the pages backing this ttm range have been invalidated
 712 *
 713 * Returns: true if pages are still valid
 714 */
 715bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
 716				       struct hmm_range *range)
 717{
 718	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 719
 720	if (!gtt || !gtt->userptr || !range)
 721		return false;
 722
 723	DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 724		gtt->userptr, ttm->num_pages);
 
 725
 726	WARN_ONCE(!range->hmm_pfns, "No user pages to check\n");
 
 727
 728	return !amdgpu_hmm_range_get_pages_done(range);
 729}
 730#endif
 731
 732/*
 733 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 734 *
 735 * Called by amdgpu_cs_list_validate(). This creates the page list
 736 * that backs user memory and will ultimately be mapped into the device
 737 * address space.
 738 */
 739void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 740{
 741	unsigned long i;
 742
 743	for (i = 0; i < ttm->num_pages; ++i)
 744		ttm->pages[i] = pages ? pages[i] : NULL;
 
 745}
 746
 747/*
 748 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 749 *
 750 * Called by amdgpu_ttm_backend_bind()
 751 **/
 752static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
 753				     struct ttm_tt *ttm)
 754{
 755	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 756	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 
 
 
 757	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 758	enum dma_data_direction direction = write ?
 759		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 760	int r;
 761
 762	/* Allocate an SG array and squash pages into it */
 763	r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 764				      (u64)ttm->num_pages << PAGE_SHIFT,
 765				      GFP_KERNEL);
 766	if (r)
 767		goto release_sg;
 768
 769	/* Map SG to device */
 770	r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 771	if (r)
 772		goto release_sg;
 773
 774	/* convert SG to linear array of pages and dma addresses */
 775	drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 776				       ttm->num_pages);
 777
 778	return 0;
 779
 780release_sg:
 781	kfree(ttm->sg);
 782	ttm->sg = NULL;
 783	return r;
 784}
 785
 786/*
 787 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 788 */
 789static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
 790					struct ttm_tt *ttm)
 791{
 792	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 793	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 
 
 794	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 795	enum dma_data_direction direction = write ?
 796		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 797
 798	/* double check that we don't free the table twice */
 799	if (!ttm->sg || !ttm->sg->sgl)
 800		return;
 801
 802	/* unmap the pages mapped to the device */
 803	dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 804	sg_free_table(ttm->sg);
 805}
 806
 807static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 808				 struct ttm_buffer_object *tbo,
 809				 uint64_t flags)
 810{
 811	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 812	struct ttm_tt *ttm = tbo->ttm;
 813	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 814
 815	if (amdgpu_bo_encrypted(abo))
 816		flags |= AMDGPU_PTE_TMZ;
 817
 818	if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 819		uint64_t page_idx = 1;
 820
 821		amdgpu_gart_bind(adev, gtt->offset, page_idx,
 822				 gtt->ttm.dma_address, flags);
 823
 824		/* The memory type of the first page defaults to UC. Now
 825		 * modify the memory type to NC from the second page of
 826		 * the BO onward.
 827		 */
 828		flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 829		flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 830
 831		amdgpu_gart_bind(adev, gtt->offset + (page_idx << PAGE_SHIFT),
 832				 ttm->num_pages - page_idx,
 833				 &(gtt->ttm.dma_address[page_idx]), flags);
 834	} else {
 835		amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 836				 gtt->ttm.dma_address, flags);
 837	}
 
 
 838}
 839
 840/*
 841 * amdgpu_ttm_backend_bind - Bind GTT memory
 842 *
 843 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 844 * This handles binding GTT memory to the device address space.
 845 */
 846static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 847				   struct ttm_tt *ttm,
 848				   struct ttm_resource *bo_mem)
 849{
 850	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 851	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 852	uint64_t flags;
 853	int r;
 854
 855	if (!bo_mem)
 856		return -EINVAL;
 857
 858	if (gtt->bound)
 859		return 0;
 860
 861	if (gtt->userptr) {
 862		r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
 863		if (r) {
 864			DRM_ERROR("failed to pin userptr\n");
 865			return r;
 866		}
 867	} else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) {
 868		if (!ttm->sg) {
 869			struct dma_buf_attachment *attach;
 870			struct sg_table *sgt;
 871
 872			attach = gtt->gobj->import_attach;
 873			sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
 874			if (IS_ERR(sgt))
 875				return PTR_ERR(sgt);
 876
 877			ttm->sg = sgt;
 878		}
 879
 880		drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 881					       ttm->num_pages);
 882	}
 883
 884	if (!ttm->num_pages) {
 885		WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 886		     ttm->num_pages, bo_mem, ttm);
 887	}
 888
 889	if (bo_mem->mem_type != TTM_PL_TT ||
 890	    !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 891		gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 892		return 0;
 893	}
 894
 895	/* compute PTE flags relevant to this BO memory */
 896	flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 897
 898	/* bind pages into GART page tables */
 899	gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 900	amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 901			 gtt->ttm.dma_address, flags);
 902	gtt->bound = true;
 903	return 0;
 904}
 905
 906/*
 907 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
 908 * through AGP or GART aperture.
 909 *
 910 * If bo is accessible through AGP aperture, then use AGP aperture
 911 * to access bo; otherwise allocate logical space in GART aperture
 912 * and map bo to GART aperture.
 913 */
 914int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 915{
 916	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 917	struct ttm_operation_ctx ctx = { false, false };
 918	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
 919	struct ttm_placement placement;
 920	struct ttm_place placements;
 921	struct ttm_resource *tmp;
 922	uint64_t addr, flags;
 
 
 
 923	int r;
 924
 925	if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
 926		return 0;
 927
 928	addr = amdgpu_gmc_agp_addr(bo);
 929	if (addr != AMDGPU_BO_INVALID_OFFSET) {
 930		bo->resource->start = addr >> PAGE_SHIFT;
 931		return 0;
 
 932	}
 933
 934	/* allocate GART space */
 935	placement.num_placement = 1;
 936	placement.placement = &placements;
 937	placement.num_busy_placement = 1;
 938	placement.busy_placement = &placements;
 939	placements.fpfn = 0;
 940	placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 941	placements.mem_type = TTM_PL_TT;
 942	placements.flags = bo->resource->placement;
 943
 944	r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 945	if (unlikely(r))
 
 946		return r;
 947
 948	/* compute PTE flags for this buffer object */
 949	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
 950
 951	/* Bind pages */
 952	gtt->offset = (u64)tmp->start << PAGE_SHIFT;
 953	amdgpu_ttm_gart_bind(adev, bo, flags);
 954	amdgpu_gart_invalidate_tlb(adev);
 955	ttm_resource_free(bo, &bo->resource);
 956	ttm_bo_assign_mem(bo, tmp);
 957
 958	return 0;
 959}
 960
 961/*
 962 * amdgpu_ttm_recover_gart - Rebind GTT pages
 963 *
 964 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
 965 * rebind GTT pages during a GPU reset.
 966 */
 967void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
 968{
 969	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
 970	uint64_t flags;
 971
 972	if (!tbo->ttm)
 973		return;
 974
 975	flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
 976	amdgpu_ttm_gart_bind(adev, tbo, flags);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 977}
 978
 979/*
 980 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
 981 *
 982 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
 983 * ttm_tt_destroy().
 984 */
 985static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
 986				      struct ttm_tt *ttm)
 987{
 988	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 989	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 990
 991	/* if the pages have userptr pinning then clear that first */
 992	if (gtt->userptr) {
 993		amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
 994	} else if (ttm->sg && gtt->gobj->import_attach) {
 995		struct dma_buf_attachment *attach;
 996
 997		attach = gtt->gobj->import_attach;
 998		dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
 999		ttm->sg = NULL;
1000	}
1001
1002	if (!gtt->bound)
1003		return;
 
1004
1005	if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1006		return;
 
1007
1008	/* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1009	amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1010	gtt->bound = false;
1011}
1012
1013static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1014				       struct ttm_tt *ttm)
1015{
1016	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1017
1018	if (gtt->usertask)
1019		put_task_struct(gtt->usertask);
1020
1021	ttm_tt_fini(&gtt->ttm);
1022	kfree(gtt);
1023}
1024
1025/**
1026 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1027 *
1028 * @bo: The buffer object to create a GTT ttm_tt object around
1029 * @page_flags: Page flags to be added to the ttm_tt object
1030 *
1031 * Called by ttm_tt_create().
1032 */
1033static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1034					   uint32_t page_flags)
1035{
1036	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1037	struct amdgpu_ttm_tt *gtt;
1038	enum ttm_caching caching;
 
1039
1040	gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1041	if (gtt == NULL) {
1042		return NULL;
1043	}
1044	gtt->gobj = &bo->base;
1045
1046	if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1047		caching = ttm_write_combined;
1048	else
1049		caching = ttm_cached;
1050
1051	/* allocate space for the uninitialized page entries */
1052	if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1053		kfree(gtt);
1054		return NULL;
1055	}
1056	return &gtt->ttm;
 
1057}
1058
1059/*
1060 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1061 *
1062 * Map the pages of a ttm_tt object to an address space visible
1063 * to the underlying device.
1064 */
1065static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1066				  struct ttm_tt *ttm,
1067				  struct ttm_operation_ctx *ctx)
1068{
1069	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1070	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1071	pgoff_t i;
1072	int ret;
 
1073
1074	/* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1075	if (gtt->userptr) {
 
 
1076		ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1077		if (!ttm->sg)
1078			return -ENOMEM;
 
 
 
1079		return 0;
1080	}
1081
1082	if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
 
 
 
1083		return 0;
 
 
 
1084
1085	ret = ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1086	if (ret)
1087		return ret;
 
 
1088
1089	for (i = 0; i < ttm->num_pages; ++i)
1090		ttm->pages[i]->mapping = bdev->dev_mapping;
 
 
1091
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1092	return 0;
1093}
1094
1095/*
1096 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1097 *
1098 * Unmaps pages of a ttm_tt object from the device address space and
1099 * unpopulates the page array backing it.
1100 */
1101static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1102				     struct ttm_tt *ttm)
1103{
1104	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1105	struct amdgpu_device *adev;
1106	pgoff_t i;
1107
1108	amdgpu_ttm_backend_unbind(bdev, ttm);
1109
1110	if (gtt->userptr) {
1111		amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1112		kfree(ttm->sg);
1113		ttm->sg = NULL;
1114		return;
1115	}
1116
1117	if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1118		return;
1119
1120	for (i = 0; i < ttm->num_pages; ++i)
1121		ttm->pages[i]->mapping = NULL;
1122
1123	adev = amdgpu_ttm_adev(bdev);
1124	return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1125}
1126
1127/**
1128 * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current
1129 * task
1130 *
1131 * @tbo: The ttm_buffer_object that contains the userptr
1132 * @user_addr:  The returned value
1133 */
1134int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
1135			      uint64_t *user_addr)
1136{
1137	struct amdgpu_ttm_tt *gtt;
1138
1139	if (!tbo->ttm)
1140		return -EINVAL;
 
 
 
 
1141
1142	gtt = (void *)tbo->ttm;
1143	*user_addr = gtt->userptr;
1144	return 0;
1145}
1146
1147/**
1148 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1149 * task
1150 *
1151 * @bo: The ttm_buffer_object to bind this userptr to
1152 * @addr:  The address in the current tasks VM space to use
1153 * @flags: Requirements of userptr object.
1154 *
1155 * Called by amdgpu_gem_userptr_ioctl() and kfd_ioctl_alloc_memory_of_gpu() to
1156 * bind userptr pages to current task and by kfd_ioctl_acquire_vm() to
1157 * initialize GPU VM for a KFD process.
1158 */
1159int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1160			      uint64_t addr, uint32_t flags)
1161{
1162	struct amdgpu_ttm_tt *gtt;
1163
1164	if (!bo->ttm) {
1165		/* TODO: We want a separate TTM object type for userptrs */
1166		bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1167		if (bo->ttm == NULL)
1168			return -ENOMEM;
1169	}
1170
1171	/* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */
1172	bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL;
1173
1174	gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
1175	gtt->userptr = addr;
 
1176	gtt->userflags = flags;
1177
1178	if (gtt->usertask)
1179		put_task_struct(gtt->usertask);
1180	gtt->usertask = current->group_leader;
1181	get_task_struct(gtt->usertask);
1182
1183	return 0;
1184}
1185
1186/*
1187 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1188 */
1189struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1190{
1191	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1192
1193	if (gtt == NULL)
1194		return NULL;
1195
1196	if (gtt->usertask == NULL)
1197		return NULL;
1198
1199	return gtt->usertask->mm;
1200}
1201
1202/*
1203 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1204 * address range for the current task.
1205 *
1206 */
1207bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1208				  unsigned long end, unsigned long *userptr)
1209{
1210	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 
1211	unsigned long size;
1212
1213	if (gtt == NULL || !gtt->userptr)
1214		return false;
1215
1216	/* Return false if no part of the ttm_tt object lies within
1217	 * the range
1218	 */
1219	size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1220	if (gtt->userptr > end || gtt->userptr + size <= start)
1221		return false;
1222
1223	if (userptr)
1224		*userptr = gtt->userptr;
 
 
 
 
 
 
 
 
 
1225	return true;
1226}
1227
1228/*
1229 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1230 */
1231bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1232{
1233	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1234
1235	if (gtt == NULL || !gtt->userptr)
1236		return false;
1237
1238	return true;
 
1239}
1240
1241/*
1242 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1243 */
1244bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1245{
1246	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1247
1248	if (gtt == NULL)
1249		return false;
1250
1251	return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1252}
1253
1254/**
1255 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1256 *
1257 * @ttm: The ttm_tt object to compute the flags for
1258 * @mem: The memory registry backing this ttm_tt object
1259 *
1260 * Figure out the flags to use for a VM PDE (Page Directory Entry).
1261 */
1262uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1263{
1264	uint64_t flags = 0;
1265
1266	if (mem && mem->mem_type != TTM_PL_SYSTEM)
1267		flags |= AMDGPU_PTE_VALID;
1268
1269	if (mem && (mem->mem_type == TTM_PL_TT ||
1270		    mem->mem_type == AMDGPU_PL_PREEMPT)) {
1271		flags |= AMDGPU_PTE_SYSTEM;
1272
1273		if (ttm->caching == ttm_cached)
1274			flags |= AMDGPU_PTE_SNOOPED;
1275	}
1276
1277	if (mem && mem->mem_type == TTM_PL_VRAM &&
1278			mem->bus.caching == ttm_cached)
1279		flags |= AMDGPU_PTE_SNOOPED;
1280
1281	return flags;
1282}
1283
1284/**
1285 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1286 *
1287 * @adev: amdgpu_device pointer
1288 * @ttm: The ttm_tt object to compute the flags for
1289 * @mem: The memory registry backing this ttm_tt object
1290 *
1291 * Figure out the flags to use for a VM PTE (Page Table Entry).
1292 */
1293uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1294				 struct ttm_resource *mem)
1295{
1296	uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1297
1298	flags |= adev->gart.gart_pte_flags;
1299	flags |= AMDGPU_PTE_READABLE;
1300
1301	if (!amdgpu_ttm_tt_is_readonly(ttm))
1302		flags |= AMDGPU_PTE_WRITEABLE;
1303
1304	return flags;
1305}
1306
1307/*
1308 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1309 * object.
1310 *
1311 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1312 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1313 * it can find space for a new object and by ttm_bo_force_list_clean() which is
1314 * used to clean out a memory space.
1315 */
1316static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1317					    const struct ttm_place *place)
1318{
1319	struct dma_resv_iter resv_cursor;
1320	struct dma_fence *f;
1321
1322	if (!amdgpu_bo_is_amdgpu_bo(bo))
1323		return ttm_bo_eviction_valuable(bo, place);
1324
1325	/* Swapout? */
1326	if (bo->resource->mem_type == TTM_PL_SYSTEM)
1327		return true;
1328
1329	if (bo->type == ttm_bo_type_kernel &&
1330	    !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1331		return false;
1332
1333	/* If bo is a KFD BO, check if the bo belongs to the current process.
1334	 * If true, then return false as any KFD process needs all its BOs to
1335	 * be resident to run successfully
1336	 */
1337	dma_resv_for_each_fence(&resv_cursor, bo->base.resv,
1338				DMA_RESV_USAGE_BOOKKEEP, f) {
1339		if (amdkfd_fence_check_mm(f, current->mm))
1340			return false;
1341	}
1342
1343	/* Preemptible BOs don't own system resources managed by the
1344	 * driver (pages, VRAM, GART space). They point to resources
1345	 * owned by someone else (e.g. pageable memory in user mode
1346	 * or a DMABuf). They are used in a preemptible context so we
1347	 * can guarantee no deadlocks and good QoS in case of MMU
1348	 * notifiers or DMABuf move notifiers from the resource owner.
1349	 */
1350	if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
1351		return false;
1352
1353	if (bo->resource->mem_type == TTM_PL_TT &&
1354	    amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1355		return false;
1356
1357	return ttm_bo_eviction_valuable(bo, place);
1358}
1359
1360static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
1361				      void *buf, size_t size, bool write)
1362{
1363	while (size) {
1364		uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
1365		uint64_t bytes = 4 - (pos & 0x3);
1366		uint32_t shift = (pos & 0x3) * 8;
1367		uint32_t mask = 0xffffffff << shift;
1368		uint32_t value = 0;
1369
1370		if (size < bytes) {
1371			mask &= 0xffffffff >> (bytes - size) * 8;
1372			bytes = size;
1373		}
1374
1375		if (mask != 0xffffffff) {
1376			amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false);
1377			if (write) {
1378				value &= ~mask;
1379				value |= (*(uint32_t *)buf << shift) & mask;
1380				amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true);
1381			} else {
1382				value = (value & mask) >> shift;
1383				memcpy(buf, &value, bytes);
1384			}
1385		} else {
1386			amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write);
1387		}
1388
1389		pos += bytes;
1390		buf += bytes;
1391		size -= bytes;
1392	}
1393}
1394
1395static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
1396					unsigned long offset, void *buf,
1397					int len, int write)
1398{
1399	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1400	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1401	struct amdgpu_res_cursor src_mm;
1402	struct amdgpu_job *job;
1403	struct dma_fence *fence;
1404	uint64_t src_addr, dst_addr;
1405	unsigned int num_dw;
1406	int r, idx;
1407
1408	if (len != PAGE_SIZE)
1409		return -EINVAL;
1410
1411	if (!adev->mman.sdma_access_ptr)
1412		return -EACCES;
1413
1414	if (!drm_dev_enter(adev_to_drm(adev), &idx))
1415		return -ENODEV;
1416
1417	if (write)
1418		memcpy(adev->mman.sdma_access_ptr, buf, len);
1419
1420	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
1421	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,
1422				     AMDGPU_FENCE_OWNER_UNDEFINED,
1423				     num_dw * 4, AMDGPU_IB_POOL_DELAYED,
1424				     &job);
1425	if (r)
1426		goto out;
1427
1428	amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm);
1429	src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) +
1430		src_mm.start;
1431	dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo);
1432	if (write)
1433		swap(src_addr, dst_addr);
1434
1435	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr,
1436				PAGE_SIZE, false);
1437
1438	amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]);
1439	WARN_ON(job->ibs[0].length_dw > num_dw);
1440
1441	fence = amdgpu_job_submit(job);
 
 
 
1442
1443	if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout))
1444		r = -ETIMEDOUT;
1445	dma_fence_put(fence);
1446
1447	if (!(r || write))
1448		memcpy(buf, adev->mman.sdma_access_ptr, len);
1449out:
1450	drm_dev_exit(idx);
1451	return r;
1452}
1453
1454/**
1455 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1456 *
1457 * @bo:  The buffer object to read/write
1458 * @offset:  Offset into buffer object
1459 * @buf:  Secondary buffer to write/read from
1460 * @len: Length in bytes of access
1461 * @write:  true if writing
1462 *
1463 * This is used to access VRAM that backs a buffer object via MMIO
1464 * access for debugging purposes.
1465 */
1466static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1467				    unsigned long offset, void *buf, int len,
1468				    int write)
1469{
1470	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1471	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1472	struct amdgpu_res_cursor cursor;
1473	int ret = 0;
1474
1475	if (bo->resource->mem_type != TTM_PL_VRAM)
1476		return -EIO;
1477
1478	if (amdgpu_device_has_timeouts_enabled(adev) &&
1479			!amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write))
1480		return len;
1481
1482	amdgpu_res_first(bo->resource, offset, len, &cursor);
1483	while (cursor.remaining) {
1484		size_t count, size = cursor.size;
1485		loff_t pos = cursor.start;
1486
1487		count = amdgpu_device_aper_access(adev, pos, buf, size, write);
1488		size -= count;
1489		if (size) {
1490			/* using MM to access rest vram and handle un-aligned address */
1491			pos += count;
1492			buf += count;
1493			amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
1494		}
1495
1496		ret += cursor.size;
1497		buf += cursor.size;
1498		amdgpu_res_next(&cursor, cursor.size);
1499	}
1500
1501	return ret;
1502}
1503
1504static void
1505amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1506{
1507	amdgpu_bo_move_notify(bo, false, NULL);
1508}
1509
1510static struct ttm_device_funcs amdgpu_bo_driver = {
1511	.ttm_tt_create = &amdgpu_ttm_tt_create,
1512	.ttm_tt_populate = &amdgpu_ttm_tt_populate,
1513	.ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1514	.ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
 
1515	.eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1516	.evict_flags = &amdgpu_evict_flags,
1517	.move = &amdgpu_bo_move,
1518	.delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1519	.release_notify = &amdgpu_bo_release_notify,
 
1520	.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1521	.io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1522	.access_memory = &amdgpu_ttm_access_memory,
 
 
1523};
1524
1525/*
1526 * Firmware Reservation functions
1527 */
1528/**
1529 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1530 *
1531 * @adev: amdgpu_device pointer
1532 *
1533 * free fw reserved vram if it has been reserved.
1534 */
1535static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1536{
1537	amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1538		NULL, &adev->mman.fw_vram_usage_va);
1539}
1540
1541/*
1542 * Driver Reservation functions
1543 */
1544/**
1545 * amdgpu_ttm_drv_reserve_vram_fini - free drv reserved vram
1546 *
1547 * @adev: amdgpu_device pointer
1548 *
1549 * free drv reserved vram if it has been reserved.
1550 */
1551static void amdgpu_ttm_drv_reserve_vram_fini(struct amdgpu_device *adev)
1552{
1553	amdgpu_bo_free_kernel(&adev->mman.drv_vram_usage_reserved_bo,
1554						  NULL,
1555						  &adev->mman.drv_vram_usage_va);
1556}
1557
1558/**
1559 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1560 *
1561 * @adev: amdgpu_device pointer
1562 *
1563 * create bo vram reservation from fw.
1564 */
1565static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1566{
1567	uint64_t vram_size = adev->gmc.visible_vram_size;
1568
1569	adev->mman.fw_vram_usage_va = NULL;
1570	adev->mman.fw_vram_usage_reserved_bo = NULL;
1571
1572	if (adev->mman.fw_vram_usage_size == 0 ||
1573	    adev->mman.fw_vram_usage_size > vram_size)
1574		return 0;
1575
1576	return amdgpu_bo_create_kernel_at(adev,
1577					  adev->mman.fw_vram_usage_start_offset,
1578					  adev->mman.fw_vram_usage_size,
1579					  &adev->mman.fw_vram_usage_reserved_bo,
1580					  &adev->mman.fw_vram_usage_va);
1581}
1582
1583/**
1584 * amdgpu_ttm_drv_reserve_vram_init - create bo vram reservation from driver
1585 *
1586 * @adev: amdgpu_device pointer
1587 *
1588 * create bo vram reservation from drv.
1589 */
1590static int amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device *adev)
1591{
1592	u64 vram_size = adev->gmc.visible_vram_size;
1593
1594	adev->mman.drv_vram_usage_va = NULL;
1595	adev->mman.drv_vram_usage_reserved_bo = NULL;
1596
1597	if (adev->mman.drv_vram_usage_size == 0 ||
1598	    adev->mman.drv_vram_usage_size > vram_size)
1599		return 0;
1600
1601	return amdgpu_bo_create_kernel_at(adev,
1602					  adev->mman.drv_vram_usage_start_offset,
1603					  adev->mman.drv_vram_usage_size,
1604					  &adev->mman.drv_vram_usage_reserved_bo,
1605					  &adev->mman.drv_vram_usage_va);
1606}
1607
1608/*
1609 * Memoy training reservation functions
1610 */
1611
1612/**
1613 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1614 *
1615 * @adev: amdgpu_device pointer
1616 *
1617 * free memory training reserved vram if it has been reserved.
1618 */
1619static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1620{
1621	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1622
1623	ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1624	amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1625	ctx->c2p_bo = NULL;
1626
1627	return 0;
1628}
1629
1630static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1631{
1632	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1633
1634	memset(ctx, 0, sizeof(*ctx));
1635
1636	ctx->c2p_train_data_offset =
1637		ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1638	ctx->p2c_train_data_offset =
1639		(adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1640	ctx->train_data_size =
1641		GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1642
1643	DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1644			ctx->train_data_size,
1645			ctx->p2c_train_data_offset,
1646			ctx->c2p_train_data_offset);
1647}
1648
1649/*
1650 * reserve TMR memory at the top of VRAM which holds
1651 * IP Discovery data and is protected by PSP.
1652 */
1653static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1654{
1655	int ret;
1656	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1657	bool mem_train_support = false;
1658
1659	if (!amdgpu_sriov_vf(adev)) {
1660		if (amdgpu_atomfirmware_mem_training_supported(adev))
1661			mem_train_support = true;
1662		else
1663			DRM_DEBUG("memory training does not support!\n");
1664	}
1665
1666	/*
1667	 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1668	 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1669	 *
1670	 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1671	 * discovery data and G6 memory training data respectively
1672	 */
1673	adev->mman.discovery_tmr_size =
1674		amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1675	if (!adev->mman.discovery_tmr_size)
1676		adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1677
1678	if (mem_train_support) {
1679		/* reserve vram for mem train according to TMR location */
1680		amdgpu_ttm_training_data_block_init(adev);
1681		ret = amdgpu_bo_create_kernel_at(adev,
1682					 ctx->c2p_train_data_offset,
1683					 ctx->train_data_size,
1684					 &ctx->c2p_bo,
1685					 NULL);
1686		if (ret) {
1687			DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1688			amdgpu_ttm_training_reserve_vram_fini(adev);
1689			return ret;
1690		}
1691		ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1692	}
1693
1694	ret = amdgpu_bo_create_kernel_at(adev,
1695				adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1696				adev->mman.discovery_tmr_size,
1697				&adev->mman.discovery_memory,
1698				NULL);
1699	if (ret) {
1700		DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1701		amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1702		return ret;
1703	}
1704
1705	return 0;
1706}
1707
1708/*
1709 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1710 * gtt/vram related fields.
1711 *
1712 * This initializes all of the memory space pools that the TTM layer
1713 * will need such as the GTT space (system memory mapped to the device),
1714 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1715 * can be mapped per VMID.
1716 */
1717int amdgpu_ttm_init(struct amdgpu_device *adev)
1718{
1719	uint64_t gtt_size;
1720	int r;
1721	u64 vis_vram_limit;
1722
1723	mutex_init(&adev->mman.gtt_window_lock);
1724
1725	/* No others user of address space so set it to 0 */
1726	r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1727			       adev_to_drm(adev)->anon_inode->i_mapping,
1728			       adev_to_drm(adev)->vma_offset_manager,
1729			       adev->need_swiotlb,
1730			       dma_addressing_limited(adev->dev));
1731	if (r) {
1732		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1733		return r;
1734	}
1735	adev->mman.initialized = true;
1736
1737	/* Initialize VRAM pool with all of VRAM divided into pages */
1738	r = amdgpu_vram_mgr_init(adev);
 
 
 
1739	if (r) {
1740		DRM_ERROR("Failed initializing VRAM heap.\n");
1741		return r;
1742	}
1743
1744	/* Reduce size of CPU-visible VRAM if requested */
1745	vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1746	if (amdgpu_vis_vram_limit > 0 &&
1747	    vis_vram_limit <= adev->gmc.visible_vram_size)
1748		adev->gmc.visible_vram_size = vis_vram_limit;
1749
1750	/* Change the size here instead of the init above so only lpfn is affected */
1751	amdgpu_ttm_set_buffer_funcs_status(adev, false);
1752#ifdef CONFIG_64BIT
1753#ifdef CONFIG_X86
1754	if (adev->gmc.xgmi.connected_to_cpu)
1755		adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1756				adev->gmc.visible_vram_size);
1757
1758	else
1759#endif
1760		adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1761				adev->gmc.visible_vram_size);
1762#endif
1763
1764	/*
1765	 *The reserved vram for firmware must be pinned to the specified
1766	 *place on the VRAM, so reserve it early.
1767	 */
1768	r = amdgpu_ttm_fw_reserve_vram_init(adev);
1769	if (r) {
 
1770		return r;
1771	}
 
 
1772
1773	/*
1774	 *The reserved vram for driver must be pinned to the specified
1775	 *place on the VRAM, so reserve it early.
1776	 */
1777	r = amdgpu_ttm_drv_reserve_vram_init(adev);
1778	if (r)
1779		return r;
1780
1781	/*
1782	 * only NAVI10 and onwards ASIC support for IP discovery.
1783	 * If IP discovery enabled, a block of memory should be
1784	 * reserved for IP discovey.
1785	 */
1786	if (adev->mman.discovery_bin) {
1787		r = amdgpu_ttm_reserve_tmr(adev);
1788		if (r)
1789			return r;
1790	}
1791
1792	/* allocate memory as required for VGA
1793	 * This is used for VGA emulation and pre-OS scanout buffers to
1794	 * avoid display artifacts while transitioning between pre-OS
1795	 * and driver.  */
1796	r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1797				       &adev->mman.stolen_vga_memory,
1798				       NULL);
1799	if (r)
1800		return r;
1801	r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1802				       adev->mman.stolen_extended_size,
1803				       &adev->mman.stolen_extended_memory,
1804				       NULL);
1805	if (r)
1806		return r;
1807	r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset,
1808				       adev->mman.stolen_reserved_size,
1809				       &adev->mman.stolen_reserved_memory,
1810				       NULL);
1811	if (r)
1812		return r;
1813
1814	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1815		 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1816
1817	/* Compute GTT size, either based on 1/2 the size of RAM size
1818	 * or whatever the user passed on module init */
1819	if (amdgpu_gtt_size == -1) {
1820		struct sysinfo si;
1821
1822		si_meminfo(&si);
1823		/* Certain GL unit tests for large textures can cause problems
1824		 * with the OOM killer since there is no way to link this memory
1825		 * to a process.  This was originally mitigated (but not necessarily
1826		 * eliminated) by limiting the GTT size.  The problem is this limit
1827		 * is often too low for many modern games so just make the limit 1/2
1828		 * of system memory which aligns with TTM. The OOM accounting needs
1829		 * to be addressed, but we shouldn't prevent common 3D applications
1830		 * from being usable just to potentially mitigate that corner case.
1831		 */
1832		gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1833			       (u64)si.totalram * si.mem_unit / 2);
1834	} else {
1835		gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1836	}
1837
1838	/* Initialize GTT memory pool */
1839	r = amdgpu_gtt_mgr_init(adev, gtt_size);
 
1840	if (r) {
1841		DRM_ERROR("Failed initializing GTT heap.\n");
1842		return r;
1843	}
1844	DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1845		 (unsigned)(gtt_size / (1024 * 1024)));
1846
1847	/* Initialize preemptible memory pool */
1848	r = amdgpu_preempt_mgr_init(adev);
1849	if (r) {
1850		DRM_ERROR("Failed initializing PREEMPT heap.\n");
1851		return r;
1852	}
1853
1854	/* Initialize various on-chip memory pools */
1855	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
 
 
 
1856	if (r) {
1857		DRM_ERROR("Failed initializing GDS heap.\n");
1858		return r;
1859	}
1860
1861	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
 
 
1862	if (r) {
1863		DRM_ERROR("Failed initializing gws heap.\n");
1864		return r;
1865	}
1866
1867	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
 
 
1868	if (r) {
1869		DRM_ERROR("Failed initializing oa heap.\n");
1870		return r;
1871	}
1872
1873	if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
1874				AMDGPU_GEM_DOMAIN_GTT,
1875				&adev->mman.sdma_access_bo, NULL,
1876				&adev->mman.sdma_access_ptr))
1877		DRM_WARN("Debug VRAM access will use slowpath MM access\n");
1878
1879	return 0;
1880}
1881
1882/*
1883 * amdgpu_ttm_fini - De-initialize the TTM memory pools
1884 */
1885void amdgpu_ttm_fini(struct amdgpu_device *adev)
1886{
1887	int idx;
 
1888	if (!adev->mman.initialized)
1889		return;
1890
1891	amdgpu_ttm_training_reserve_vram_fini(adev);
1892	/* return the stolen vga memory back to VRAM */
1893	amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1894	amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1895	/* return the IP Discovery TMR memory back to VRAM */
1896	amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1897	if (adev->mman.stolen_reserved_size)
1898		amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
1899				      NULL, NULL);
1900	amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL,
1901					&adev->mman.sdma_access_ptr);
1902	amdgpu_ttm_fw_reserve_vram_fini(adev);
1903	amdgpu_ttm_drv_reserve_vram_fini(adev);
1904
1905	if (drm_dev_enter(adev_to_drm(adev), &idx)) {
1906
1907		if (adev->mman.aper_base_kaddr)
1908			iounmap(adev->mman.aper_base_kaddr);
1909		adev->mman.aper_base_kaddr = NULL;
1910
1911		drm_dev_exit(idx);
1912	}
1913
1914	amdgpu_vram_mgr_fini(adev);
1915	amdgpu_gtt_mgr_fini(adev);
1916	amdgpu_preempt_mgr_fini(adev);
1917	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1918	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1919	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1920	ttm_device_fini(&adev->mman.bdev);
1921	adev->mman.initialized = false;
1922	DRM_INFO("amdgpu: ttm finalized\n");
1923}
1924
1925/**
1926 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1927 *
1928 * @adev: amdgpu_device pointer
1929 * @enable: true when we can use buffer functions.
1930 *
1931 * Enable/disable use of buffer functions during suspend/resume. This should
1932 * only be called at bootup or when userspace isn't running.
1933 */
1934void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1935{
1936	struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1937	uint64_t size;
1938	int r;
1939
1940	if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1941	    adev->mman.buffer_funcs_enabled == enable)
1942		return;
1943
1944	if (enable) {
1945		struct amdgpu_ring *ring;
1946		struct drm_gpu_scheduler *sched;
1947
1948		ring = adev->mman.buffer_funcs_ring;
1949		sched = &ring->sched;
1950		r = drm_sched_entity_init(&adev->mman.entity,
1951					  DRM_SCHED_PRIORITY_KERNEL, &sched,
1952					  1, NULL);
1953		if (r) {
1954			DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1955				  r);
1956			return;
1957		}
1958	} else {
1959		drm_sched_entity_destroy(&adev->mman.entity);
1960		dma_fence_put(man->move);
1961		man->move = NULL;
1962	}
1963
1964	/* this just adjusts TTM size idea, which sets lpfn to the correct value */
1965	if (enable)
1966		size = adev->gmc.real_vram_size;
1967	else
1968		size = adev->gmc.visible_vram_size;
1969	man->size = size;
1970	adev->mman.buffer_funcs_enabled = enable;
1971}
1972
1973static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
1974				  bool direct_submit,
1975				  unsigned int num_dw,
1976				  struct dma_resv *resv,
1977				  bool vm_needs_flush,
1978				  struct amdgpu_job **job)
1979{
1980	enum amdgpu_ib_pool_type pool = direct_submit ?
1981		AMDGPU_IB_POOL_DIRECT :
1982		AMDGPU_IB_POOL_DELAYED;
1983	int r;
1984
1985	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,
1986				     AMDGPU_FENCE_OWNER_UNDEFINED,
1987				     num_dw * 4, pool, job);
1988	if (r)
1989		return r;
1990
1991	if (vm_needs_flush) {
1992		(*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1993							adev->gmc.pdb0_bo :
1994							adev->gart.bo);
1995		(*job)->vm_needs_flush = true;
1996	}
1997	if (!resv)
1998		return 0;
1999
2000	return drm_sched_job_add_resv_dependencies(&(*job)->base, resv,
2001						   DMA_RESV_USAGE_BOOKKEEP);
2002}
2003
2004int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2005		       uint64_t dst_offset, uint32_t byte_count,
2006		       struct dma_resv *resv,
2007		       struct dma_fence **fence, bool direct_submit,
2008		       bool vm_needs_flush, bool tmz)
 
2009{
2010	struct amdgpu_device *adev = ring->adev;
2011	unsigned num_loops, num_dw;
2012	struct amdgpu_job *job;
 
2013	uint32_t max_bytes;
 
2014	unsigned i;
2015	int r;
2016
2017	if (!direct_submit && !ring->sched.ready) {
2018		DRM_ERROR("Trying to move memory with ring turned off.\n");
2019		return -EINVAL;
2020	}
2021
2022	max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2023	num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2024	num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2025	r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,
2026				   resv, vm_needs_flush, &job);
 
 
 
 
2027	if (r)
2028		return r;
2029
 
 
 
 
 
 
 
 
 
2030	for (i = 0; i < num_loops; i++) {
2031		uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2032
2033		amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2034					dst_offset, cur_size_in_bytes, tmz);
2035
2036		src_offset += cur_size_in_bytes;
2037		dst_offset += cur_size_in_bytes;
2038		byte_count -= cur_size_in_bytes;
2039	}
2040
2041	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2042	WARN_ON(job->ibs[0].length_dw > num_dw);
2043	if (direct_submit)
2044		r = amdgpu_job_submit_direct(job, ring, fence);
2045	else
2046		*fence = amdgpu_job_submit(job);
2047	if (r)
2048		goto error_free;
 
 
 
 
 
 
 
2049
2050	return r;
2051
2052error_free:
2053	amdgpu_job_free(job);
2054	DRM_ERROR("Error scheduling IBs (%d)\n", r);
2055	return r;
2056}
2057
2058static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
2059			       uint64_t dst_addr, uint32_t byte_count,
2060			       struct dma_resv *resv,
2061			       struct dma_fence **fence,
2062			       bool vm_needs_flush)
2063{
2064	struct amdgpu_device *adev = ring->adev;
 
 
 
 
 
2065	unsigned int num_loops, num_dw;
 
2066	struct amdgpu_job *job;
2067	uint32_t max_bytes;
2068	unsigned int i;
2069	int r;
2070
2071	max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2072	num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
2073	num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
2074	r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
2075				   &job);
2076	if (r)
2077		return r;
2078
2079	for (i = 0; i < num_loops; i++) {
2080		uint32_t cur_size = min(byte_count, max_bytes);
2081
2082		amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2083					cur_size);
2084
2085		dst_addr += cur_size;
2086		byte_count -= cur_size;
 
 
 
 
 
 
 
2087	}
 
2088
2089	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2090	WARN_ON(job->ibs[0].length_dw > num_dw);
2091	*fence = amdgpu_job_submit(job);
2092	return 0;
2093}
2094
2095int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2096			uint32_t src_data,
2097			struct dma_resv *resv,
2098			struct dma_fence **f)
2099{
2100	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2101	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2102	struct dma_fence *fence = NULL;
2103	struct amdgpu_res_cursor dst;
2104	int r;
2105
2106	if (!adev->mman.buffer_funcs_enabled) {
2107		DRM_ERROR("Trying to clear memory with ring turned off.\n");
2108		return -EINVAL;
 
 
 
 
2109	}
2110
2111	amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
 
2112
2113	mutex_lock(&adev->mman.gtt_window_lock);
2114	while (dst.remaining) {
2115		struct dma_fence *next;
2116		uint64_t cur_size, to;
2117
2118		/* Never fill more than 256MiB at once to avoid timeouts */
2119		cur_size = min(dst.size, 256ULL << 20);
2120
2121		r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst,
2122					  1, ring, false, &cur_size, &to);
2123		if (r)
2124			goto error;
2125
2126		r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv,
2127					&next, true);
2128		if (r)
2129			goto error;
2130
2131		dma_fence_put(fence);
2132		fence = next;
 
 
 
 
2133
2134		amdgpu_res_next(&dst, cur_size);
 
2135	}
2136error:
2137	mutex_unlock(&adev->mman.gtt_window_lock);
2138	if (f)
2139		*f = dma_fence_get(fence);
2140	dma_fence_put(fence);
2141	return r;
2142}
2143
2144/**
2145 * amdgpu_ttm_evict_resources - evict memory buffers
2146 * @adev: amdgpu device object
2147 * @mem_type: evicted BO's memory type
2148 *
2149 * Evicts all @mem_type buffers on the lru list of the memory type.
2150 *
2151 * Returns:
2152 * 0 for success or a negative error code on failure.
2153 */
2154int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type)
2155{
2156	struct ttm_resource_manager *man;
2157
2158	switch (mem_type) {
2159	case TTM_PL_VRAM:
2160	case TTM_PL_TT:
2161	case AMDGPU_PL_GWS:
2162	case AMDGPU_PL_GDS:
2163	case AMDGPU_PL_OA:
2164		man = ttm_manager_type(&adev->mman.bdev, mem_type);
2165		break;
2166	default:
2167		DRM_ERROR("Trying to evict invalid memory type\n");
2168		return -EINVAL;
2169	}
2170
2171	return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
 
 
2172}
2173
2174#if defined(CONFIG_DEBUG_FS)
2175
2176static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2177{
2178	struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
 
 
 
 
 
 
2179
2180	return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
 
 
 
 
 
 
 
 
2181}
2182
2183DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2184
2185/*
2186 * amdgpu_ttm_vram_read - Linear read access to VRAM
2187 *
2188 * Accesses VRAM via MMIO for debugging purposes.
2189 */
2190static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2191				    size_t size, loff_t *pos)
2192{
2193	struct amdgpu_device *adev = file_inode(f)->i_private;
2194	ssize_t result = 0;
2195
2196	if (size & 0x3 || *pos & 0x3)
2197		return -EINVAL;
2198
2199	if (*pos >= adev->gmc.mc_vram_size)
2200		return -ENXIO;
2201
2202	size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2203	while (size) {
2204		size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2205		uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2206
2207		amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2208		if (copy_to_user(buf, value, bytes))
2209			return -EFAULT;
2210
2211		result += bytes;
2212		buf += bytes;
2213		*pos += bytes;
2214		size -= bytes;
2215	}
2216
2217	return result;
2218}
2219
2220/*
2221 * amdgpu_ttm_vram_write - Linear write access to VRAM
2222 *
2223 * Accesses VRAM via MMIO for debugging purposes.
2224 */
2225static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2226				    size_t size, loff_t *pos)
2227{
2228	struct amdgpu_device *adev = file_inode(f)->i_private;
2229	ssize_t result = 0;
2230	int r;
2231
2232	if (size & 0x3 || *pos & 0x3)
2233		return -EINVAL;
2234
2235	if (*pos >= adev->gmc.mc_vram_size)
2236		return -ENXIO;
2237
2238	while (size) {
 
2239		uint32_t value;
2240
2241		if (*pos >= adev->gmc.mc_vram_size)
2242			return result;
2243
2244		r = get_user(value, (uint32_t *)buf);
 
 
 
 
 
 
2245		if (r)
2246			return r;
2247
2248		amdgpu_device_mm_access(adev, *pos, &value, 4, true);
2249
2250		result += 4;
2251		buf += 4;
2252		*pos += 4;
2253		size -= 4;
2254	}
2255
2256	return result;
2257}
2258
2259static const struct file_operations amdgpu_ttm_vram_fops = {
2260	.owner = THIS_MODULE,
2261	.read = amdgpu_ttm_vram_read,
2262	.write = amdgpu_ttm_vram_write,
2263	.llseek = default_llseek,
2264};
2265
2266/*
2267 * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2268 *
2269 * This function is used to read memory that has been mapped to the
2270 * GPU and the known addresses are not physical addresses but instead
2271 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2272 */
2273static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2274				 size_t size, loff_t *pos)
2275{
2276	struct amdgpu_device *adev = file_inode(f)->i_private;
2277	struct iommu_domain *dom;
2278	ssize_t result = 0;
2279	int r;
2280
2281	/* retrieve the IOMMU domain if any for this device */
2282	dom = iommu_get_domain_for_dev(adev->dev);
2283
2284	while (size) {
2285		phys_addr_t addr = *pos & PAGE_MASK;
2286		loff_t off = *pos & ~PAGE_MASK;
2287		size_t bytes = PAGE_SIZE - off;
2288		unsigned long pfn;
2289		struct page *p;
2290		void *ptr;
2291
2292		bytes = bytes < size ? bytes : size;
2293
2294		/* Translate the bus address to a physical address.  If
2295		 * the domain is NULL it means there is no IOMMU active
2296		 * and the address translation is the identity
2297		 */
2298		addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2299
2300		pfn = addr >> PAGE_SHIFT;
2301		if (!pfn_valid(pfn))
2302			return -EPERM;
2303
2304		p = pfn_to_page(pfn);
2305		if (p->mapping != adev->mman.bdev.dev_mapping)
2306			return -EPERM;
 
 
 
 
 
 
2307
2308		ptr = kmap_local_page(p);
2309		r = copy_to_user(buf, ptr + off, bytes);
2310		kunmap_local(ptr);
2311		if (r)
2312			return -EFAULT;
2313
2314		size -= bytes;
2315		*pos += bytes;
2316		result += bytes;
 
2317	}
2318
2319	return result;
2320}
2321
2322/*
2323 * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2324 *
2325 * This function is used to write memory that has been mapped to the
2326 * GPU and the known addresses are not physical addresses but instead
2327 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2328 */
2329static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2330				 size_t size, loff_t *pos)
2331{
2332	struct amdgpu_device *adev = file_inode(f)->i_private;
2333	struct iommu_domain *dom;
2334	ssize_t result = 0;
2335	int r;
2336
2337	dom = iommu_get_domain_for_dev(adev->dev);
2338
2339	while (size) {
2340		phys_addr_t addr = *pos & PAGE_MASK;
2341		loff_t off = *pos & ~PAGE_MASK;
2342		size_t bytes = PAGE_SIZE - off;
2343		unsigned long pfn;
2344		struct page *p;
2345		void *ptr;
2346
2347		bytes = bytes < size ? bytes : size;
2348
2349		addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2350
2351		pfn = addr >> PAGE_SHIFT;
2352		if (!pfn_valid(pfn))
2353			return -EPERM;
 
2354
2355		p = pfn_to_page(pfn);
2356		if (p->mapping != adev->mman.bdev.dev_mapping)
2357			return -EPERM;
2358
2359		ptr = kmap_local_page(p);
2360		r = copy_from_user(ptr + off, buf, bytes);
2361		kunmap_local(ptr);
2362		if (r)
2363			return -EFAULT;
 
 
 
 
 
 
 
 
 
2364
2365		size -= bytes;
2366		*pos += bytes;
2367		result += bytes;
2368	}
2369
2370	return result;
2371}
 
 
2372
2373static const struct file_operations amdgpu_ttm_iomem_fops = {
2374	.owner = THIS_MODULE,
2375	.read = amdgpu_iomem_read,
2376	.write = amdgpu_iomem_write,
2377	.llseek = default_llseek
2378};
2379
 
2380#endif
 
2381
2382void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2383{
2384#if defined(CONFIG_DEBUG_FS)
2385	struct drm_minor *minor = adev_to_drm(adev)->primary;
2386	struct dentry *root = minor->debugfs_root;
2387
2388	debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2389				 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2390	debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2391			    &amdgpu_ttm_iomem_fops);
2392	debugfs_create_file("ttm_page_pool", 0444, root, adev,
2393			    &amdgpu_ttm_page_pool_fops);
2394	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2395							     TTM_PL_VRAM),
2396					    root, "amdgpu_vram_mm");
2397	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2398							     TTM_PL_TT),
2399					    root, "amdgpu_gtt_mm");
2400	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2401							     AMDGPU_PL_GDS),
2402					    root, "amdgpu_gds_mm");
2403	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2404							     AMDGPU_PL_GWS),
2405					    root, "amdgpu_gws_mm");
2406	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2407							     AMDGPU_PL_OA),
2408					    root, "amdgpu_oa_mm");
2409
2410#endif
2411}