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1/*
2 * Toumaz Xenif TZ1090 GPIO handling.
3 *
4 * Copyright (C) 2008-2013 Imagination Technologies Ltd.
5 *
6 * Based on ARM PXA code and others.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/bitops.h>
14#include <linux/export.h>
15#include <linux/gpio.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/kernel.h>
21#include <linux/of_irq.h>
22#include <linux/pinctrl/consumer.h>
23#include <linux/platform_device.h>
24#include <linux/slab.h>
25#include <linux/syscore_ops.h>
26#include <asm/global_lock.h>
27
28/* Register offsets from bank base address */
29#define REG_GPIO_DIR 0x00
30#define REG_GPIO_IRQ_PLRT 0x20
31#define REG_GPIO_IRQ_TYPE 0x30
32#define REG_GPIO_IRQ_EN 0x40
33#define REG_GPIO_IRQ_STS 0x50
34#define REG_GPIO_BIT_EN 0x60
35#define REG_GPIO_DIN 0x70
36#define REG_GPIO_DOUT 0x80
37
38/* REG_GPIO_IRQ_PLRT */
39#define REG_GPIO_IRQ_PLRT_LOW 0
40#define REG_GPIO_IRQ_PLRT_HIGH 1
41
42/* REG_GPIO_IRQ_TYPE */
43#define REG_GPIO_IRQ_TYPE_LEVEL 0
44#define REG_GPIO_IRQ_TYPE_EDGE 1
45
46/**
47 * struct tz1090_gpio_bank - GPIO bank private data
48 * @chip: Generic GPIO chip for GPIO bank
49 * @domain: IRQ domain for GPIO bank (may be NULL)
50 * @reg: Base of registers, offset for this GPIO bank
51 * @irq: IRQ number for GPIO bank
52 * @label: Debug GPIO bank label, used for storage of chip->label
53 *
54 * This is the main private data for a GPIO bank. It encapsulates a gpio_chip,
55 * and the callbacks for the gpio_chip can access the private data with the
56 * to_bank() macro below.
57 */
58struct tz1090_gpio_bank {
59 struct gpio_chip chip;
60 struct irq_domain *domain;
61 void __iomem *reg;
62 int irq;
63 char label[16];
64};
65
66/**
67 * struct tz1090_gpio - Overall GPIO device private data
68 * @dev: Device (from platform device)
69 * @reg: Base of GPIO registers
70 *
71 * Represents the overall GPIO device. This structure is actually only
72 * temporary, and used during init.
73 */
74struct tz1090_gpio {
75 struct device *dev;
76 void __iomem *reg;
77};
78
79/**
80 * struct tz1090_gpio_bank_info - Temporary registration info for GPIO bank
81 * @priv: Overall GPIO device private data
82 * @node: Device tree node specific to this GPIO bank
83 * @index: Index of bank in range 0-2
84 */
85struct tz1090_gpio_bank_info {
86 struct tz1090_gpio *priv;
87 struct device_node *node;
88 unsigned int index;
89};
90
91/* Convenience register accessors */
92static inline void tz1090_gpio_write(struct tz1090_gpio_bank *bank,
93 unsigned int reg_offs, u32 data)
94{
95 iowrite32(data, bank->reg + reg_offs);
96}
97
98static inline u32 tz1090_gpio_read(struct tz1090_gpio_bank *bank,
99 unsigned int reg_offs)
100{
101 return ioread32(bank->reg + reg_offs);
102}
103
104/* caller must hold LOCK2 */
105static inline void _tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank,
106 unsigned int reg_offs,
107 unsigned int offset)
108{
109 u32 value;
110
111 value = tz1090_gpio_read(bank, reg_offs);
112 value &= ~BIT(offset);
113 tz1090_gpio_write(bank, reg_offs, value);
114}
115
116static void tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank,
117 unsigned int reg_offs,
118 unsigned int offset)
119{
120 int lstat;
121
122 __global_lock2(lstat);
123 _tz1090_gpio_clear_bit(bank, reg_offs, offset);
124 __global_unlock2(lstat);
125}
126
127/* caller must hold LOCK2 */
128static inline void _tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank,
129 unsigned int reg_offs,
130 unsigned int offset)
131{
132 u32 value;
133
134 value = tz1090_gpio_read(bank, reg_offs);
135 value |= BIT(offset);
136 tz1090_gpio_write(bank, reg_offs, value);
137}
138
139static void tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank,
140 unsigned int reg_offs,
141 unsigned int offset)
142{
143 int lstat;
144
145 __global_lock2(lstat);
146 _tz1090_gpio_set_bit(bank, reg_offs, offset);
147 __global_unlock2(lstat);
148}
149
150/* caller must hold LOCK2 */
151static inline void _tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank,
152 unsigned int reg_offs,
153 unsigned int offset,
154 bool val)
155{
156 u32 value;
157
158 value = tz1090_gpio_read(bank, reg_offs);
159 value &= ~BIT(offset);
160 if (val)
161 value |= BIT(offset);
162 tz1090_gpio_write(bank, reg_offs, value);
163}
164
165static void tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank,
166 unsigned int reg_offs,
167 unsigned int offset,
168 bool val)
169{
170 int lstat;
171
172 __global_lock2(lstat);
173 _tz1090_gpio_mod_bit(bank, reg_offs, offset, val);
174 __global_unlock2(lstat);
175}
176
177static inline int tz1090_gpio_read_bit(struct tz1090_gpio_bank *bank,
178 unsigned int reg_offs,
179 unsigned int offset)
180{
181 return tz1090_gpio_read(bank, reg_offs) & BIT(offset);
182}
183
184/* GPIO chip callbacks */
185
186static int tz1090_gpio_direction_input(struct gpio_chip *chip,
187 unsigned int offset)
188{
189 struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
190 tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset);
191
192 return 0;
193}
194
195static int tz1090_gpio_direction_output(struct gpio_chip *chip,
196 unsigned int offset, int output_value)
197{
198 struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
199 int lstat;
200
201 __global_lock2(lstat);
202 _tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value);
203 _tz1090_gpio_clear_bit(bank, REG_GPIO_DIR, offset);
204 __global_unlock2(lstat);
205
206 return 0;
207}
208
209/*
210 * Return GPIO level
211 */
212static int tz1090_gpio_get(struct gpio_chip *chip, unsigned int offset)
213{
214 struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
215
216 return !!tz1090_gpio_read_bit(bank, REG_GPIO_DIN, offset);
217}
218
219/*
220 * Set output GPIO level
221 */
222static void tz1090_gpio_set(struct gpio_chip *chip, unsigned int offset,
223 int output_value)
224{
225 struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
226
227 tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value);
228}
229
230static int tz1090_gpio_request(struct gpio_chip *chip, unsigned int offset)
231{
232 struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
233 int ret;
234
235 ret = pinctrl_request_gpio(chip->base + offset);
236 if (ret)
237 return ret;
238
239 tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset);
240 tz1090_gpio_set_bit(bank, REG_GPIO_BIT_EN, offset);
241
242 return 0;
243}
244
245static void tz1090_gpio_free(struct gpio_chip *chip, unsigned int offset)
246{
247 struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
248
249 pinctrl_free_gpio(chip->base + offset);
250
251 tz1090_gpio_clear_bit(bank, REG_GPIO_BIT_EN, offset);
252}
253
254static int tz1090_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
255{
256 struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
257
258 if (!bank->domain)
259 return -EINVAL;
260
261 return irq_create_mapping(bank->domain, offset);
262}
263
264/* IRQ chip handlers */
265
266/* Get TZ1090 GPIO chip from irq data provided to generic IRQ callbacks */
267static inline struct tz1090_gpio_bank *irqd_to_gpio_bank(struct irq_data *data)
268{
269 return (struct tz1090_gpio_bank *)data->domain->host_data;
270}
271
272static void tz1090_gpio_irq_polarity(struct tz1090_gpio_bank *bank,
273 unsigned int offset, unsigned int polarity)
274{
275 tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_PLRT, offset, polarity);
276}
277
278static void tz1090_gpio_irq_type(struct tz1090_gpio_bank *bank,
279 unsigned int offset, unsigned int type)
280{
281 tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_TYPE, offset, type);
282}
283
284/* set polarity to trigger on next edge, whether rising or falling */
285static void tz1090_gpio_irq_next_edge(struct tz1090_gpio_bank *bank,
286 unsigned int offset)
287{
288 unsigned int value_p, value_i;
289 int lstat;
290
291 /*
292 * Set the GPIO's interrupt polarity to the opposite of the current
293 * input value so that the next edge triggers an interrupt.
294 */
295 __global_lock2(lstat);
296 value_i = ~tz1090_gpio_read(bank, REG_GPIO_DIN);
297 value_p = tz1090_gpio_read(bank, REG_GPIO_IRQ_PLRT);
298 value_p &= ~BIT(offset);
299 value_p |= value_i & BIT(offset);
300 tz1090_gpio_write(bank, REG_GPIO_IRQ_PLRT, value_p);
301 __global_unlock2(lstat);
302}
303
304static unsigned int gpio_startup_irq(struct irq_data *data)
305{
306 /*
307 * This warning indicates that the type of the irq hasn't been set
308 * before enabling the irq. This would normally be done by passing some
309 * trigger flags to request_irq().
310 */
311 WARN(irqd_get_trigger_type(data) == IRQ_TYPE_NONE,
312 "irq type not set before enabling gpio irq %d", data->irq);
313
314 irq_gc_ack_clr_bit(data);
315 irq_gc_mask_set_bit(data);
316 return 0;
317}
318
319static int gpio_set_irq_type(struct irq_data *data, unsigned int flow_type)
320{
321 struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
322 unsigned int type;
323 unsigned int polarity;
324
325 switch (flow_type) {
326 case IRQ_TYPE_EDGE_BOTH:
327 type = REG_GPIO_IRQ_TYPE_EDGE;
328 polarity = REG_GPIO_IRQ_PLRT_LOW;
329 break;
330 case IRQ_TYPE_EDGE_RISING:
331 type = REG_GPIO_IRQ_TYPE_EDGE;
332 polarity = REG_GPIO_IRQ_PLRT_HIGH;
333 break;
334 case IRQ_TYPE_EDGE_FALLING:
335 type = REG_GPIO_IRQ_TYPE_EDGE;
336 polarity = REG_GPIO_IRQ_PLRT_LOW;
337 break;
338 case IRQ_TYPE_LEVEL_HIGH:
339 type = REG_GPIO_IRQ_TYPE_LEVEL;
340 polarity = REG_GPIO_IRQ_PLRT_HIGH;
341 break;
342 case IRQ_TYPE_LEVEL_LOW:
343 type = REG_GPIO_IRQ_TYPE_LEVEL;
344 polarity = REG_GPIO_IRQ_PLRT_LOW;
345 break;
346 default:
347 return -EINVAL;
348 }
349
350 tz1090_gpio_irq_type(bank, data->hwirq, type);
351 irq_setup_alt_chip(data, flow_type);
352
353 if (flow_type == IRQ_TYPE_EDGE_BOTH)
354 tz1090_gpio_irq_next_edge(bank, data->hwirq);
355 else
356 tz1090_gpio_irq_polarity(bank, data->hwirq, polarity);
357
358 return 0;
359}
360
361#ifdef CONFIG_SUSPEND
362static int gpio_set_irq_wake(struct irq_data *data, unsigned int on)
363{
364 struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
365
366#ifdef CONFIG_PM_DEBUG
367 pr_info("irq_wake irq%d state:%d\n", data->irq, on);
368#endif
369
370 /* wake on gpio block interrupt */
371 return irq_set_irq_wake(bank->irq, on);
372}
373#else
374#define gpio_set_irq_wake NULL
375#endif
376
377static void tz1090_gpio_irq_handler(struct irq_desc *desc)
378{
379 irq_hw_number_t hw;
380 unsigned int irq_stat, irq_no;
381 struct tz1090_gpio_bank *bank;
382 struct irq_desc *child_desc;
383
384 bank = (struct tz1090_gpio_bank *)irq_desc_get_handler_data(desc);
385 irq_stat = tz1090_gpio_read(bank, REG_GPIO_DIR) &
386 tz1090_gpio_read(bank, REG_GPIO_IRQ_STS) &
387 tz1090_gpio_read(bank, REG_GPIO_IRQ_EN) &
388 0x3FFFFFFF; /* 30 bits only */
389
390 for (hw = 0; irq_stat; irq_stat >>= 1, ++hw) {
391 if (!(irq_stat & 1))
392 continue;
393
394 irq_no = irq_linear_revmap(bank->domain, hw);
395 child_desc = irq_to_desc(irq_no);
396
397 /* Toggle edge for pin with both edges triggering enabled */
398 if (irqd_get_trigger_type(&child_desc->irq_data)
399 == IRQ_TYPE_EDGE_BOTH)
400 tz1090_gpio_irq_next_edge(bank, hw);
401
402 generic_handle_irq_desc(child_desc);
403 }
404}
405
406static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info)
407{
408 struct device_node *np = info->node;
409 struct device *dev = info->priv->dev;
410 struct tz1090_gpio_bank *bank;
411 struct irq_chip_generic *gc;
412 int err;
413
414 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
415 if (!bank) {
416 dev_err(dev, "unable to allocate driver data\n");
417 return -ENOMEM;
418 }
419
420 /* Offset the main registers to the first register in this bank */
421 bank->reg = info->priv->reg + info->index * 4;
422
423 /* Set up GPIO chip */
424 snprintf(bank->label, sizeof(bank->label), "tz1090-gpio-%u",
425 info->index);
426 bank->chip.label = bank->label;
427 bank->chip.parent = dev;
428 bank->chip.direction_input = tz1090_gpio_direction_input;
429 bank->chip.direction_output = tz1090_gpio_direction_output;
430 bank->chip.get = tz1090_gpio_get;
431 bank->chip.set = tz1090_gpio_set;
432 bank->chip.free = tz1090_gpio_free;
433 bank->chip.request = tz1090_gpio_request;
434 bank->chip.to_irq = tz1090_gpio_to_irq;
435 bank->chip.of_node = np;
436
437 /* GPIO numbering from 0 */
438 bank->chip.base = info->index * 30;
439 bank->chip.ngpio = 30;
440
441 /* Add the GPIO bank */
442 gpiochip_add_data(&bank->chip, bank);
443
444 /* Get the GPIO bank IRQ if provided */
445 bank->irq = irq_of_parse_and_map(np, 0);
446
447 /* The interrupt is optional (it may be used by another core on chip) */
448 if (!bank->irq) {
449 dev_info(dev, "IRQ not provided for bank %u, IRQs disabled\n",
450 info->index);
451 return 0;
452 }
453
454 dev_info(dev, "Setting up IRQs for GPIO bank %u\n",
455 info->index);
456
457 /*
458 * Initialise all interrupts to disabled so we don't get
459 * spurious ones on a dirty boot and hit the BUG_ON in the
460 * handler.
461 */
462 tz1090_gpio_write(bank, REG_GPIO_IRQ_EN, 0);
463
464 /* Add a virtual IRQ for each GPIO */
465 bank->domain = irq_domain_add_linear(np,
466 bank->chip.ngpio,
467 &irq_generic_chip_ops,
468 bank);
469
470 /* Set up a generic irq chip with 2 chip types (level and edge) */
471 err = irq_alloc_domain_generic_chips(bank->domain, bank->chip.ngpio, 2,
472 bank->label, handle_bad_irq, 0, 0,
473 IRQ_GC_INIT_NESTED_LOCK);
474 if (err) {
475 dev_info(dev,
476 "irq_alloc_domain_generic_chips failed for bank %u, IRQs disabled\n",
477 info->index);
478 irq_domain_remove(bank->domain);
479 return 0;
480 }
481
482 gc = irq_get_domain_generic_chip(bank->domain, 0);
483 gc->reg_base = bank->reg;
484
485 /* level chip type */
486 gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
487 gc->chip_types[0].handler = handle_level_irq;
488 gc->chip_types[0].regs.ack = REG_GPIO_IRQ_STS;
489 gc->chip_types[0].regs.mask = REG_GPIO_IRQ_EN;
490 gc->chip_types[0].chip.irq_startup = gpio_startup_irq;
491 gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit;
492 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
493 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
494 gc->chip_types[0].chip.irq_set_type = gpio_set_irq_type;
495 gc->chip_types[0].chip.irq_set_wake = gpio_set_irq_wake;
496 gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
497
498 /* edge chip type */
499 gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
500 gc->chip_types[1].handler = handle_edge_irq;
501 gc->chip_types[1].regs.ack = REG_GPIO_IRQ_STS;
502 gc->chip_types[1].regs.mask = REG_GPIO_IRQ_EN;
503 gc->chip_types[1].chip.irq_startup = gpio_startup_irq;
504 gc->chip_types[1].chip.irq_ack = irq_gc_ack_clr_bit;
505 gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
506 gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
507 gc->chip_types[1].chip.irq_set_type = gpio_set_irq_type;
508 gc->chip_types[1].chip.irq_set_wake = gpio_set_irq_wake;
509 gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
510
511 /* Setup chained handler for this GPIO bank */
512 irq_set_chained_handler_and_data(bank->irq, tz1090_gpio_irq_handler,
513 bank);
514
515 return 0;
516}
517
518static void tz1090_gpio_register_banks(struct tz1090_gpio *priv)
519{
520 struct device_node *np = priv->dev->of_node;
521 struct device_node *node;
522
523 for_each_available_child_of_node(np, node) {
524 struct tz1090_gpio_bank_info info;
525 u32 addr;
526 int ret;
527
528 ret = of_property_read_u32(node, "reg", &addr);
529 if (ret) {
530 dev_err(priv->dev, "invalid reg on %s\n",
531 node->full_name);
532 continue;
533 }
534 if (addr >= 3) {
535 dev_err(priv->dev, "index %u in %s out of range\n",
536 addr, node->full_name);
537 continue;
538 }
539
540 info.index = addr;
541 info.node = of_node_get(node);
542 info.priv = priv;
543
544 ret = tz1090_gpio_bank_probe(&info);
545 if (ret) {
546 dev_err(priv->dev, "failure registering %s\n",
547 node->full_name);
548 of_node_put(node);
549 continue;
550 }
551 }
552}
553
554static int tz1090_gpio_probe(struct platform_device *pdev)
555{
556 struct device_node *np = pdev->dev.of_node;
557 struct resource *res_regs;
558 struct tz1090_gpio priv;
559
560 if (!np) {
561 dev_err(&pdev->dev, "must be instantiated via devicetree\n");
562 return -ENOENT;
563 }
564
565 res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
566 if (!res_regs) {
567 dev_err(&pdev->dev, "cannot find registers resource\n");
568 return -ENOENT;
569 }
570
571 priv.dev = &pdev->dev;
572
573 /* Ioremap the registers */
574 priv.reg = devm_ioremap(&pdev->dev, res_regs->start,
575 resource_size(res_regs));
576 if (!priv.reg) {
577 dev_err(&pdev->dev, "unable to ioremap registers\n");
578 return -ENOMEM;
579 }
580
581 /* Look for banks */
582 tz1090_gpio_register_banks(&priv);
583
584 return 0;
585}
586
587static struct of_device_id tz1090_gpio_of_match[] = {
588 { .compatible = "img,tz1090-gpio" },
589 { },
590};
591
592static struct platform_driver tz1090_gpio_driver = {
593 .driver = {
594 .name = "tz1090-gpio",
595 .of_match_table = tz1090_gpio_of_match,
596 },
597 .probe = tz1090_gpio_probe,
598};
599
600static int __init tz1090_gpio_init(void)
601{
602 return platform_driver_register(&tz1090_gpio_driver);
603}
604subsys_initcall(tz1090_gpio_init);