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1// SPDX-License-Identifier: GPL-2.0
2/* smp.c: Sparc64 SMP support.
3 *
4 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
5 */
6
7#include <linux/export.h>
8#include <linux/kernel.h>
9#include <linux/sched/mm.h>
10#include <linux/sched/hotplug.h>
11#include <linux/mm.h>
12#include <linux/pagemap.h>
13#include <linux/threads.h>
14#include <linux/smp.h>
15#include <linux/interrupt.h>
16#include <linux/kernel_stat.h>
17#include <linux/delay.h>
18#include <linux/init.h>
19#include <linux/spinlock.h>
20#include <linux/fs.h>
21#include <linux/seq_file.h>
22#include <linux/cache.h>
23#include <linux/jiffies.h>
24#include <linux/profile.h>
25#include <linux/memblock.h>
26#include <linux/vmalloc.h>
27#include <linux/ftrace.h>
28#include <linux/cpu.h>
29#include <linux/slab.h>
30#include <linux/kgdb.h>
31
32#include <asm/head.h>
33#include <asm/ptrace.h>
34#include <linux/atomic.h>
35#include <asm/tlbflush.h>
36#include <asm/mmu_context.h>
37#include <asm/cpudata.h>
38#include <asm/hvtramp.h>
39#include <asm/io.h>
40#include <asm/timer.h>
41#include <asm/setup.h>
42
43#include <asm/irq.h>
44#include <asm/irq_regs.h>
45#include <asm/page.h>
46#include <asm/oplib.h>
47#include <linux/uaccess.h>
48#include <asm/starfire.h>
49#include <asm/tlb.h>
50#include <asm/pgalloc.h>
51#include <asm/sections.h>
52#include <asm/prom.h>
53#include <asm/mdesc.h>
54#include <asm/ldc.h>
55#include <asm/hypervisor.h>
56#include <asm/pcr.h>
57
58#include "cpumap.h"
59#include "kernel.h"
60
61DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
62cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
63 { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
64
65cpumask_t cpu_core_sib_map[NR_CPUS] __read_mostly = {
66 [0 ... NR_CPUS-1] = CPU_MASK_NONE };
67
68cpumask_t cpu_core_sib_cache_map[NR_CPUS] __read_mostly = {
69 [0 ... NR_CPUS - 1] = CPU_MASK_NONE };
70
71EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
72EXPORT_SYMBOL(cpu_core_map);
73EXPORT_SYMBOL(cpu_core_sib_map);
74EXPORT_SYMBOL(cpu_core_sib_cache_map);
75
76static cpumask_t smp_commenced_mask;
77
78static DEFINE_PER_CPU(bool, poke);
79static bool cpu_poke;
80
81void smp_info(struct seq_file *m)
82{
83 int i;
84
85 seq_printf(m, "State:\n");
86 for_each_online_cpu(i)
87 seq_printf(m, "CPU%d:\t\tonline\n", i);
88}
89
90void smp_bogo(struct seq_file *m)
91{
92 int i;
93
94 for_each_online_cpu(i)
95 seq_printf(m,
96 "Cpu%dClkTck\t: %016lx\n",
97 i, cpu_data(i).clock_tick);
98}
99
100extern void setup_sparc64_timer(void);
101
102static volatile unsigned long callin_flag = 0;
103
104void smp_callin(void)
105{
106 int cpuid = hard_smp_processor_id();
107
108 __local_per_cpu_offset = __per_cpu_offset(cpuid);
109
110 if (tlb_type == hypervisor)
111 sun4v_ktsb_register();
112
113 __flush_tlb_all();
114
115 setup_sparc64_timer();
116
117 if (cheetah_pcache_forced_on)
118 cheetah_enable_pcache();
119
120 callin_flag = 1;
121 __asm__ __volatile__("membar #Sync\n\t"
122 "flush %%g6" : : : "memory");
123
124 /* Clear this or we will die instantly when we
125 * schedule back to this idler...
126 */
127 current_thread_info()->new_child = 0;
128
129 /* Attach to the address space of init_task. */
130 mmgrab(&init_mm);
131 current->active_mm = &init_mm;
132
133 /* inform the notifiers about the new cpu */
134 notify_cpu_starting(cpuid);
135
136 while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
137 rmb();
138
139 set_cpu_online(cpuid, true);
140
141 local_irq_enable();
142
143 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
144}
145
146void cpu_panic(void)
147{
148 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
149 panic("SMP bolixed\n");
150}
151
152/* This tick register synchronization scheme is taken entirely from
153 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
154 *
155 * The only change I've made is to rework it so that the master
156 * initiates the synchonization instead of the slave. -DaveM
157 */
158
159#define MASTER 0
160#define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
161
162#define NUM_ROUNDS 64 /* magic value */
163#define NUM_ITERS 5 /* likewise */
164
165static DEFINE_RAW_SPINLOCK(itc_sync_lock);
166static unsigned long go[SLAVE + 1];
167
168#define DEBUG_TICK_SYNC 0
169
170static inline long get_delta (long *rt, long *master)
171{
172 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
173 unsigned long tcenter, t0, t1, tm;
174 unsigned long i;
175
176 for (i = 0; i < NUM_ITERS; i++) {
177 t0 = tick_ops->get_tick();
178 go[MASTER] = 1;
179 membar_safe("#StoreLoad");
180 while (!(tm = go[SLAVE]))
181 rmb();
182 go[SLAVE] = 0;
183 wmb();
184 t1 = tick_ops->get_tick();
185
186 if (t1 - t0 < best_t1 - best_t0)
187 best_t0 = t0, best_t1 = t1, best_tm = tm;
188 }
189
190 *rt = best_t1 - best_t0;
191 *master = best_tm - best_t0;
192
193 /* average best_t0 and best_t1 without overflow: */
194 tcenter = (best_t0/2 + best_t1/2);
195 if (best_t0 % 2 + best_t1 % 2 == 2)
196 tcenter++;
197 return tcenter - best_tm;
198}
199
200void smp_synchronize_tick_client(void)
201{
202 long i, delta, adj, adjust_latency = 0, done = 0;
203 unsigned long flags, rt, master_time_stamp;
204#if DEBUG_TICK_SYNC
205 struct {
206 long rt; /* roundtrip time */
207 long master; /* master's timestamp */
208 long diff; /* difference between midpoint and master's timestamp */
209 long lat; /* estimate of itc adjustment latency */
210 } t[NUM_ROUNDS];
211#endif
212
213 go[MASTER] = 1;
214
215 while (go[MASTER])
216 rmb();
217
218 local_irq_save(flags);
219 {
220 for (i = 0; i < NUM_ROUNDS; i++) {
221 delta = get_delta(&rt, &master_time_stamp);
222 if (delta == 0)
223 done = 1; /* let's lock on to this... */
224
225 if (!done) {
226 if (i > 0) {
227 adjust_latency += -delta;
228 adj = -delta + adjust_latency/4;
229 } else
230 adj = -delta;
231
232 tick_ops->add_tick(adj);
233 }
234#if DEBUG_TICK_SYNC
235 t[i].rt = rt;
236 t[i].master = master_time_stamp;
237 t[i].diff = delta;
238 t[i].lat = adjust_latency/4;
239#endif
240 }
241 }
242 local_irq_restore(flags);
243
244#if DEBUG_TICK_SYNC
245 for (i = 0; i < NUM_ROUNDS; i++)
246 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
247 t[i].rt, t[i].master, t[i].diff, t[i].lat);
248#endif
249
250 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
251 "(last diff %ld cycles, maxerr %lu cycles)\n",
252 smp_processor_id(), delta, rt);
253}
254
255static void smp_start_sync_tick_client(int cpu);
256
257static void smp_synchronize_one_tick(int cpu)
258{
259 unsigned long flags, i;
260
261 go[MASTER] = 0;
262
263 smp_start_sync_tick_client(cpu);
264
265 /* wait for client to be ready */
266 while (!go[MASTER])
267 rmb();
268
269 /* now let the client proceed into his loop */
270 go[MASTER] = 0;
271 membar_safe("#StoreLoad");
272
273 raw_spin_lock_irqsave(&itc_sync_lock, flags);
274 {
275 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
276 while (!go[MASTER])
277 rmb();
278 go[MASTER] = 0;
279 wmb();
280 go[SLAVE] = tick_ops->get_tick();
281 membar_safe("#StoreLoad");
282 }
283 }
284 raw_spin_unlock_irqrestore(&itc_sync_lock, flags);
285}
286
287#if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
288static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg,
289 void **descrp)
290{
291 extern unsigned long sparc64_ttable_tl0;
292 extern unsigned long kern_locked_tte_data;
293 struct hvtramp_descr *hdesc;
294 unsigned long trampoline_ra;
295 struct trap_per_cpu *tb;
296 u64 tte_vaddr, tte_data;
297 unsigned long hv_err;
298 int i;
299
300 hdesc = kzalloc(sizeof(*hdesc) +
301 (sizeof(struct hvtramp_mapping) *
302 num_kernel_image_mappings - 1),
303 GFP_KERNEL);
304 if (!hdesc) {
305 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
306 "hvtramp_descr.\n");
307 return;
308 }
309 *descrp = hdesc;
310
311 hdesc->cpu = cpu;
312 hdesc->num_mappings = num_kernel_image_mappings;
313
314 tb = &trap_block[cpu];
315
316 hdesc->fault_info_va = (unsigned long) &tb->fault_info;
317 hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
318
319 hdesc->thread_reg = thread_reg;
320
321 tte_vaddr = (unsigned long) KERNBASE;
322 tte_data = kern_locked_tte_data;
323
324 for (i = 0; i < hdesc->num_mappings; i++) {
325 hdesc->maps[i].vaddr = tte_vaddr;
326 hdesc->maps[i].tte = tte_data;
327 tte_vaddr += 0x400000;
328 tte_data += 0x400000;
329 }
330
331 trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
332
333 hv_err = sun4v_cpu_start(cpu, trampoline_ra,
334 kimage_addr_to_ra(&sparc64_ttable_tl0),
335 __pa(hdesc));
336 if (hv_err)
337 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
338 "gives error %lu\n", hv_err);
339}
340#endif
341
342extern unsigned long sparc64_cpu_startup;
343
344/* The OBP cpu startup callback truncates the 3rd arg cookie to
345 * 32-bits (I think) so to be safe we have it read the pointer
346 * contained here so we work on >4GB machines. -DaveM
347 */
348static struct thread_info *cpu_new_thread = NULL;
349
350static int smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle)
351{
352 unsigned long entry =
353 (unsigned long)(&sparc64_cpu_startup);
354 unsigned long cookie =
355 (unsigned long)(&cpu_new_thread);
356 void *descr = NULL;
357 int timeout, ret;
358
359 callin_flag = 0;
360 cpu_new_thread = task_thread_info(idle);
361
362 if (tlb_type == hypervisor) {
363#if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
364 if (ldom_domaining_enabled)
365 ldom_startcpu_cpuid(cpu,
366 (unsigned long) cpu_new_thread,
367 &descr);
368 else
369#endif
370 prom_startcpu_cpuid(cpu, entry, cookie);
371 } else {
372 struct device_node *dp = of_find_node_by_cpuid(cpu);
373
374 prom_startcpu(dp->phandle, entry, cookie);
375 }
376
377 for (timeout = 0; timeout < 50000; timeout++) {
378 if (callin_flag)
379 break;
380 udelay(100);
381 }
382
383 if (callin_flag) {
384 ret = 0;
385 } else {
386 printk("Processor %d is stuck.\n", cpu);
387 ret = -ENODEV;
388 }
389 cpu_new_thread = NULL;
390
391 kfree(descr);
392
393 return ret;
394}
395
396static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
397{
398 u64 result, target;
399 int stuck, tmp;
400
401 if (this_is_starfire) {
402 /* map to real upaid */
403 cpu = (((cpu & 0x3c) << 1) |
404 ((cpu & 0x40) >> 4) |
405 (cpu & 0x3));
406 }
407
408 target = (cpu << 14) | 0x70;
409again:
410 /* Ok, this is the real Spitfire Errata #54.
411 * One must read back from a UDB internal register
412 * after writes to the UDB interrupt dispatch, but
413 * before the membar Sync for that write.
414 * So we use the high UDB control register (ASI 0x7f,
415 * ADDR 0x20) for the dummy read. -DaveM
416 */
417 tmp = 0x40;
418 __asm__ __volatile__(
419 "wrpr %1, %2, %%pstate\n\t"
420 "stxa %4, [%0] %3\n\t"
421 "stxa %5, [%0+%8] %3\n\t"
422 "add %0, %8, %0\n\t"
423 "stxa %6, [%0+%8] %3\n\t"
424 "membar #Sync\n\t"
425 "stxa %%g0, [%7] %3\n\t"
426 "membar #Sync\n\t"
427 "mov 0x20, %%g1\n\t"
428 "ldxa [%%g1] 0x7f, %%g0\n\t"
429 "membar #Sync"
430 : "=r" (tmp)
431 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
432 "r" (data0), "r" (data1), "r" (data2), "r" (target),
433 "r" (0x10), "0" (tmp)
434 : "g1");
435
436 /* NOTE: PSTATE_IE is still clear. */
437 stuck = 100000;
438 do {
439 __asm__ __volatile__("ldxa [%%g0] %1, %0"
440 : "=r" (result)
441 : "i" (ASI_INTR_DISPATCH_STAT));
442 if (result == 0) {
443 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
444 : : "r" (pstate));
445 return;
446 }
447 stuck -= 1;
448 if (stuck == 0)
449 break;
450 } while (result & 0x1);
451 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
452 : : "r" (pstate));
453 if (stuck == 0) {
454 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
455 smp_processor_id(), result);
456 } else {
457 udelay(2);
458 goto again;
459 }
460}
461
462static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
463{
464 u64 *mondo, data0, data1, data2;
465 u16 *cpu_list;
466 u64 pstate;
467 int i;
468
469 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
470 cpu_list = __va(tb->cpu_list_pa);
471 mondo = __va(tb->cpu_mondo_block_pa);
472 data0 = mondo[0];
473 data1 = mondo[1];
474 data2 = mondo[2];
475 for (i = 0; i < cnt; i++)
476 spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
477}
478
479/* Cheetah now allows to send the whole 64-bytes of data in the interrupt
480 * packet, but we have no use for that. However we do take advantage of
481 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
482 */
483static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
484{
485 int nack_busy_id, is_jbus, need_more;
486 u64 *mondo, pstate, ver, busy_mask;
487 u16 *cpu_list;
488
489 cpu_list = __va(tb->cpu_list_pa);
490 mondo = __va(tb->cpu_mondo_block_pa);
491
492 /* Unfortunately, someone at Sun had the brilliant idea to make the
493 * busy/nack fields hard-coded by ITID number for this Ultra-III
494 * derivative processor.
495 */
496 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
497 is_jbus = ((ver >> 32) == __JALAPENO_ID ||
498 (ver >> 32) == __SERRANO_ID);
499
500 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
501
502retry:
503 need_more = 0;
504 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
505 : : "r" (pstate), "i" (PSTATE_IE));
506
507 /* Setup the dispatch data registers. */
508 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
509 "stxa %1, [%4] %6\n\t"
510 "stxa %2, [%5] %6\n\t"
511 "membar #Sync\n\t"
512 : /* no outputs */
513 : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
514 "r" (0x40), "r" (0x50), "r" (0x60),
515 "i" (ASI_INTR_W));
516
517 nack_busy_id = 0;
518 busy_mask = 0;
519 {
520 int i;
521
522 for (i = 0; i < cnt; i++) {
523 u64 target, nr;
524
525 nr = cpu_list[i];
526 if (nr == 0xffff)
527 continue;
528
529 target = (nr << 14) | 0x70;
530 if (is_jbus) {
531 busy_mask |= (0x1UL << (nr * 2));
532 } else {
533 target |= (nack_busy_id << 24);
534 busy_mask |= (0x1UL <<
535 (nack_busy_id * 2));
536 }
537 __asm__ __volatile__(
538 "stxa %%g0, [%0] %1\n\t"
539 "membar #Sync\n\t"
540 : /* no outputs */
541 : "r" (target), "i" (ASI_INTR_W));
542 nack_busy_id++;
543 if (nack_busy_id == 32) {
544 need_more = 1;
545 break;
546 }
547 }
548 }
549
550 /* Now, poll for completion. */
551 {
552 u64 dispatch_stat, nack_mask;
553 long stuck;
554
555 stuck = 100000 * nack_busy_id;
556 nack_mask = busy_mask << 1;
557 do {
558 __asm__ __volatile__("ldxa [%%g0] %1, %0"
559 : "=r" (dispatch_stat)
560 : "i" (ASI_INTR_DISPATCH_STAT));
561 if (!(dispatch_stat & (busy_mask | nack_mask))) {
562 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
563 : : "r" (pstate));
564 if (unlikely(need_more)) {
565 int i, this_cnt = 0;
566 for (i = 0; i < cnt; i++) {
567 if (cpu_list[i] == 0xffff)
568 continue;
569 cpu_list[i] = 0xffff;
570 this_cnt++;
571 if (this_cnt == 32)
572 break;
573 }
574 goto retry;
575 }
576 return;
577 }
578 if (!--stuck)
579 break;
580 } while (dispatch_stat & busy_mask);
581
582 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
583 : : "r" (pstate));
584
585 if (dispatch_stat & busy_mask) {
586 /* Busy bits will not clear, continue instead
587 * of freezing up on this cpu.
588 */
589 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
590 smp_processor_id(), dispatch_stat);
591 } else {
592 int i, this_busy_nack = 0;
593
594 /* Delay some random time with interrupts enabled
595 * to prevent deadlock.
596 */
597 udelay(2 * nack_busy_id);
598
599 /* Clear out the mask bits for cpus which did not
600 * NACK us.
601 */
602 for (i = 0; i < cnt; i++) {
603 u64 check_mask, nr;
604
605 nr = cpu_list[i];
606 if (nr == 0xffff)
607 continue;
608
609 if (is_jbus)
610 check_mask = (0x2UL << (2*nr));
611 else
612 check_mask = (0x2UL <<
613 this_busy_nack);
614 if ((dispatch_stat & check_mask) == 0)
615 cpu_list[i] = 0xffff;
616 this_busy_nack += 2;
617 if (this_busy_nack == 64)
618 break;
619 }
620
621 goto retry;
622 }
623 }
624}
625
626#define CPU_MONDO_COUNTER(cpuid) (cpu_mondo_counter[cpuid])
627#define MONDO_USEC_WAIT_MIN 2
628#define MONDO_USEC_WAIT_MAX 100
629#define MONDO_RETRY_LIMIT 500000
630
631/* Multi-cpu list version.
632 *
633 * Deliver xcalls to 'cnt' number of cpus in 'cpu_list'.
634 * Sometimes not all cpus receive the mondo, requiring us to re-send
635 * the mondo until all cpus have received, or cpus are truly stuck
636 * unable to receive mondo, and we timeout.
637 * Occasionally a target cpu strand is borrowed briefly by hypervisor to
638 * perform guest service, such as PCIe error handling. Consider the
639 * service time, 1 second overall wait is reasonable for 1 cpu.
640 * Here two in-between mondo check wait time are defined: 2 usec for
641 * single cpu quick turn around and up to 100usec for large cpu count.
642 * Deliver mondo to large number of cpus could take longer, we adjusts
643 * the retry count as long as target cpus are making forward progress.
644 */
645static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
646{
647 int this_cpu, tot_cpus, prev_sent, i, rem;
648 int usec_wait, retries, tot_retries;
649 u16 first_cpu = 0xffff;
650 unsigned long xc_rcvd = 0;
651 unsigned long status;
652 int ecpuerror_id = 0;
653 int enocpu_id = 0;
654 u16 *cpu_list;
655 u16 cpu;
656
657 this_cpu = smp_processor_id();
658 cpu_list = __va(tb->cpu_list_pa);
659 usec_wait = cnt * MONDO_USEC_WAIT_MIN;
660 if (usec_wait > MONDO_USEC_WAIT_MAX)
661 usec_wait = MONDO_USEC_WAIT_MAX;
662 retries = tot_retries = 0;
663 tot_cpus = cnt;
664 prev_sent = 0;
665
666 do {
667 int n_sent, mondo_delivered, target_cpu_busy;
668
669 status = sun4v_cpu_mondo_send(cnt,
670 tb->cpu_list_pa,
671 tb->cpu_mondo_block_pa);
672
673 /* HV_EOK means all cpus received the xcall, we're done. */
674 if (likely(status == HV_EOK))
675 goto xcall_done;
676
677 /* If not these non-fatal errors, panic */
678 if (unlikely((status != HV_EWOULDBLOCK) &&
679 (status != HV_ECPUERROR) &&
680 (status != HV_ENOCPU)))
681 goto fatal_errors;
682
683 /* First, see if we made any forward progress.
684 *
685 * Go through the cpu_list, count the target cpus that have
686 * received our mondo (n_sent), and those that did not (rem).
687 * Re-pack cpu_list with the cpus remain to be retried in the
688 * front - this simplifies tracking the truly stalled cpus.
689 *
690 * The hypervisor indicates successful sends by setting
691 * cpu list entries to the value 0xffff.
692 *
693 * EWOULDBLOCK means some target cpus did not receive the
694 * mondo and retry usually helps.
695 *
696 * ECPUERROR means at least one target cpu is in error state,
697 * it's usually safe to skip the faulty cpu and retry.
698 *
699 * ENOCPU means one of the target cpu doesn't belong to the
700 * domain, perhaps offlined which is unexpected, but not
701 * fatal and it's okay to skip the offlined cpu.
702 */
703 rem = 0;
704 n_sent = 0;
705 for (i = 0; i < cnt; i++) {
706 cpu = cpu_list[i];
707 if (likely(cpu == 0xffff)) {
708 n_sent++;
709 } else if ((status == HV_ECPUERROR) &&
710 (sun4v_cpu_state(cpu) == HV_CPU_STATE_ERROR)) {
711 ecpuerror_id = cpu + 1;
712 } else if (status == HV_ENOCPU && !cpu_online(cpu)) {
713 enocpu_id = cpu + 1;
714 } else {
715 cpu_list[rem++] = cpu;
716 }
717 }
718
719 /* No cpu remained, we're done. */
720 if (rem == 0)
721 break;
722
723 /* Otherwise, update the cpu count for retry. */
724 cnt = rem;
725
726 /* Record the overall number of mondos received by the
727 * first of the remaining cpus.
728 */
729 if (first_cpu != cpu_list[0]) {
730 first_cpu = cpu_list[0];
731 xc_rcvd = CPU_MONDO_COUNTER(first_cpu);
732 }
733
734 /* Was any mondo delivered successfully? */
735 mondo_delivered = (n_sent > prev_sent);
736 prev_sent = n_sent;
737
738 /* or, was any target cpu busy processing other mondos? */
739 target_cpu_busy = (xc_rcvd < CPU_MONDO_COUNTER(first_cpu));
740 xc_rcvd = CPU_MONDO_COUNTER(first_cpu);
741
742 /* Retry count is for no progress. If we're making progress,
743 * reset the retry count.
744 */
745 if (likely(mondo_delivered || target_cpu_busy)) {
746 tot_retries += retries;
747 retries = 0;
748 } else if (unlikely(retries > MONDO_RETRY_LIMIT)) {
749 goto fatal_mondo_timeout;
750 }
751
752 /* Delay a little bit to let other cpus catch up on
753 * their cpu mondo queue work.
754 */
755 if (!mondo_delivered)
756 udelay(usec_wait);
757
758 retries++;
759 } while (1);
760
761xcall_done:
762 if (unlikely(ecpuerror_id > 0)) {
763 pr_crit("CPU[%d]: SUN4V mondo cpu error, target cpu(%d) was in error state\n",
764 this_cpu, ecpuerror_id - 1);
765 } else if (unlikely(enocpu_id > 0)) {
766 pr_crit("CPU[%d]: SUN4V mondo cpu error, target cpu(%d) does not belong to the domain\n",
767 this_cpu, enocpu_id - 1);
768 }
769 return;
770
771fatal_errors:
772 /* fatal errors include bad alignment, etc */
773 pr_crit("CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) mondo_block_pa(%lx)\n",
774 this_cpu, tot_cpus, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
775 panic("Unexpected SUN4V mondo error %lu\n", status);
776
777fatal_mondo_timeout:
778 /* some cpus being non-responsive to the cpu mondo */
779 pr_crit("CPU[%d]: SUN4V mondo timeout, cpu(%d) made no forward progress after %d retries. Total target cpus(%d).\n",
780 this_cpu, first_cpu, (tot_retries + retries), tot_cpus);
781 panic("SUN4V mondo timeout panic\n");
782}
783
784static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
785
786static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
787{
788 struct trap_per_cpu *tb;
789 int this_cpu, i, cnt;
790 unsigned long flags;
791 u16 *cpu_list;
792 u64 *mondo;
793
794 /* We have to do this whole thing with interrupts fully disabled.
795 * Otherwise if we send an xcall from interrupt context it will
796 * corrupt both our mondo block and cpu list state.
797 *
798 * One consequence of this is that we cannot use timeout mechanisms
799 * that depend upon interrupts being delivered locally. So, for
800 * example, we cannot sample jiffies and expect it to advance.
801 *
802 * Fortunately, udelay() uses %stick/%tick so we can use that.
803 */
804 local_irq_save(flags);
805
806 this_cpu = smp_processor_id();
807 tb = &trap_block[this_cpu];
808
809 mondo = __va(tb->cpu_mondo_block_pa);
810 mondo[0] = data0;
811 mondo[1] = data1;
812 mondo[2] = data2;
813 wmb();
814
815 cpu_list = __va(tb->cpu_list_pa);
816
817 /* Setup the initial cpu list. */
818 cnt = 0;
819 for_each_cpu(i, mask) {
820 if (i == this_cpu || !cpu_online(i))
821 continue;
822 cpu_list[cnt++] = i;
823 }
824
825 if (cnt)
826 xcall_deliver_impl(tb, cnt);
827
828 local_irq_restore(flags);
829}
830
831/* Send cross call to all processors mentioned in MASK_P
832 * except self. Really, there are only two cases currently,
833 * "cpu_online_mask" and "mm_cpumask(mm)".
834 */
835static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask)
836{
837 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
838
839 xcall_deliver(data0, data1, data2, mask);
840}
841
842/* Send cross call to all processors except self. */
843static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
844{
845 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask);
846}
847
848extern unsigned long xcall_sync_tick;
849
850static void smp_start_sync_tick_client(int cpu)
851{
852 xcall_deliver((u64) &xcall_sync_tick, 0, 0,
853 cpumask_of(cpu));
854}
855
856extern unsigned long xcall_call_function;
857
858void arch_send_call_function_ipi_mask(const struct cpumask *mask)
859{
860 xcall_deliver((u64) &xcall_call_function, 0, 0, mask);
861}
862
863extern unsigned long xcall_call_function_single;
864
865void arch_send_call_function_single_ipi(int cpu)
866{
867 xcall_deliver((u64) &xcall_call_function_single, 0, 0,
868 cpumask_of(cpu));
869}
870
871void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs)
872{
873 clear_softint(1 << irq);
874 irq_enter();
875 generic_smp_call_function_interrupt();
876 irq_exit();
877}
878
879void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs)
880{
881 clear_softint(1 << irq);
882 irq_enter();
883 generic_smp_call_function_single_interrupt();
884 irq_exit();
885}
886
887static void tsb_sync(void *info)
888{
889 struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
890 struct mm_struct *mm = info;
891
892 /* It is not valid to test "current->active_mm == mm" here.
893 *
894 * The value of "current" is not changed atomically with
895 * switch_mm(). But that's OK, we just need to check the
896 * current cpu's trap block PGD physical address.
897 */
898 if (tp->pgd_paddr == __pa(mm->pgd))
899 tsb_context_switch(mm);
900}
901
902void smp_tsb_sync(struct mm_struct *mm)
903{
904 smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1);
905}
906
907extern unsigned long xcall_flush_tlb_mm;
908extern unsigned long xcall_flush_tlb_page;
909extern unsigned long xcall_flush_tlb_kernel_range;
910extern unsigned long xcall_fetch_glob_regs;
911extern unsigned long xcall_fetch_glob_pmu;
912extern unsigned long xcall_fetch_glob_pmu_n4;
913extern unsigned long xcall_receive_signal;
914extern unsigned long xcall_new_mmu_context_version;
915#ifdef CONFIG_KGDB
916extern unsigned long xcall_kgdb_capture;
917#endif
918
919#ifdef DCACHE_ALIASING_POSSIBLE
920extern unsigned long xcall_flush_dcache_page_cheetah;
921#endif
922extern unsigned long xcall_flush_dcache_page_spitfire;
923
924static inline void __local_flush_dcache_page(struct page *page)
925{
926#ifdef DCACHE_ALIASING_POSSIBLE
927 __flush_dcache_page(page_address(page),
928 ((tlb_type == spitfire) &&
929 page_mapping_file(page) != NULL));
930#else
931 if (page_mapping_file(page) != NULL &&
932 tlb_type == spitfire)
933 __flush_icache_page(__pa(page_address(page)));
934#endif
935}
936
937void smp_flush_dcache_page_impl(struct page *page, int cpu)
938{
939 int this_cpu;
940
941 if (tlb_type == hypervisor)
942 return;
943
944#ifdef CONFIG_DEBUG_DCFLUSH
945 atomic_inc(&dcpage_flushes);
946#endif
947
948 this_cpu = get_cpu();
949
950 if (cpu == this_cpu) {
951 __local_flush_dcache_page(page);
952 } else if (cpu_online(cpu)) {
953 void *pg_addr = page_address(page);
954 u64 data0 = 0;
955
956 if (tlb_type == spitfire) {
957 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
958 if (page_mapping_file(page) != NULL)
959 data0 |= ((u64)1 << 32);
960 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
961#ifdef DCACHE_ALIASING_POSSIBLE
962 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
963#endif
964 }
965 if (data0) {
966 xcall_deliver(data0, __pa(pg_addr),
967 (u64) pg_addr, cpumask_of(cpu));
968#ifdef CONFIG_DEBUG_DCFLUSH
969 atomic_inc(&dcpage_flushes_xcall);
970#endif
971 }
972 }
973
974 put_cpu();
975}
976
977void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
978{
979 void *pg_addr;
980 u64 data0;
981
982 if (tlb_type == hypervisor)
983 return;
984
985 preempt_disable();
986
987#ifdef CONFIG_DEBUG_DCFLUSH
988 atomic_inc(&dcpage_flushes);
989#endif
990 data0 = 0;
991 pg_addr = page_address(page);
992 if (tlb_type == spitfire) {
993 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
994 if (page_mapping_file(page) != NULL)
995 data0 |= ((u64)1 << 32);
996 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
997#ifdef DCACHE_ALIASING_POSSIBLE
998 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
999#endif
1000 }
1001 if (data0) {
1002 xcall_deliver(data0, __pa(pg_addr),
1003 (u64) pg_addr, cpu_online_mask);
1004#ifdef CONFIG_DEBUG_DCFLUSH
1005 atomic_inc(&dcpage_flushes_xcall);
1006#endif
1007 }
1008 __local_flush_dcache_page(page);
1009
1010 preempt_enable();
1011}
1012
1013#ifdef CONFIG_KGDB
1014void kgdb_roundup_cpus(void)
1015{
1016 smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
1017}
1018#endif
1019
1020void smp_fetch_global_regs(void)
1021{
1022 smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1023}
1024
1025void smp_fetch_global_pmu(void)
1026{
1027 if (tlb_type == hypervisor &&
1028 sun4v_chip_type >= SUN4V_CHIP_NIAGARA4)
1029 smp_cross_call(&xcall_fetch_glob_pmu_n4, 0, 0, 0);
1030 else
1031 smp_cross_call(&xcall_fetch_glob_pmu, 0, 0, 0);
1032}
1033
1034/* We know that the window frames of the user have been flushed
1035 * to the stack before we get here because all callers of us
1036 * are flush_tlb_*() routines, and these run after flush_cache_*()
1037 * which performs the flushw.
1038 *
1039 * mm->cpu_vm_mask is a bit mask of which cpus an address
1040 * space has (potentially) executed on, this is the heuristic
1041 * we use to limit cross calls.
1042 */
1043
1044/* This currently is only used by the hugetlb arch pre-fault
1045 * hook on UltraSPARC-III+ and later when changing the pagesize
1046 * bits of the context register for an address space.
1047 */
1048void smp_flush_tlb_mm(struct mm_struct *mm)
1049{
1050 u32 ctx = CTX_HWBITS(mm->context);
1051
1052 get_cpu();
1053
1054 smp_cross_call_masked(&xcall_flush_tlb_mm,
1055 ctx, 0, 0,
1056 mm_cpumask(mm));
1057
1058 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1059
1060 put_cpu();
1061}
1062
1063struct tlb_pending_info {
1064 unsigned long ctx;
1065 unsigned long nr;
1066 unsigned long *vaddrs;
1067};
1068
1069static void tlb_pending_func(void *info)
1070{
1071 struct tlb_pending_info *t = info;
1072
1073 __flush_tlb_pending(t->ctx, t->nr, t->vaddrs);
1074}
1075
1076void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1077{
1078 u32 ctx = CTX_HWBITS(mm->context);
1079 struct tlb_pending_info info;
1080
1081 get_cpu();
1082
1083 info.ctx = ctx;
1084 info.nr = nr;
1085 info.vaddrs = vaddrs;
1086
1087 smp_call_function_many(mm_cpumask(mm), tlb_pending_func,
1088 &info, 1);
1089
1090 __flush_tlb_pending(ctx, nr, vaddrs);
1091
1092 put_cpu();
1093}
1094
1095void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr)
1096{
1097 unsigned long context = CTX_HWBITS(mm->context);
1098
1099 get_cpu();
1100
1101 smp_cross_call_masked(&xcall_flush_tlb_page,
1102 context, vaddr, 0,
1103 mm_cpumask(mm));
1104
1105 __flush_tlb_page(context, vaddr);
1106
1107 put_cpu();
1108}
1109
1110void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1111{
1112 start &= PAGE_MASK;
1113 end = PAGE_ALIGN(end);
1114 if (start != end) {
1115 smp_cross_call(&xcall_flush_tlb_kernel_range,
1116 0, start, end);
1117
1118 __flush_tlb_kernel_range(start, end);
1119 }
1120}
1121
1122/* CPU capture. */
1123/* #define CAPTURE_DEBUG */
1124extern unsigned long xcall_capture;
1125
1126static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1127static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1128static unsigned long penguins_are_doing_time;
1129
1130void smp_capture(void)
1131{
1132 int result = atomic_add_return(1, &smp_capture_depth);
1133
1134 if (result == 1) {
1135 int ncpus = num_online_cpus();
1136
1137#ifdef CAPTURE_DEBUG
1138 printk("CPU[%d]: Sending penguins to jail...",
1139 smp_processor_id());
1140#endif
1141 penguins_are_doing_time = 1;
1142 atomic_inc(&smp_capture_registry);
1143 smp_cross_call(&xcall_capture, 0, 0, 0);
1144 while (atomic_read(&smp_capture_registry) != ncpus)
1145 rmb();
1146#ifdef CAPTURE_DEBUG
1147 printk("done\n");
1148#endif
1149 }
1150}
1151
1152void smp_release(void)
1153{
1154 if (atomic_dec_and_test(&smp_capture_depth)) {
1155#ifdef CAPTURE_DEBUG
1156 printk("CPU[%d]: Giving pardon to "
1157 "imprisoned penguins\n",
1158 smp_processor_id());
1159#endif
1160 penguins_are_doing_time = 0;
1161 membar_safe("#StoreLoad");
1162 atomic_dec(&smp_capture_registry);
1163 }
1164}
1165
1166/* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
1167 * set, so they can service tlb flush xcalls...
1168 */
1169extern void prom_world(int);
1170
1171void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs)
1172{
1173 clear_softint(1 << irq);
1174
1175 preempt_disable();
1176
1177 __asm__ __volatile__("flushw");
1178 prom_world(1);
1179 atomic_inc(&smp_capture_registry);
1180 membar_safe("#StoreLoad");
1181 while (penguins_are_doing_time)
1182 rmb();
1183 atomic_dec(&smp_capture_registry);
1184 prom_world(0);
1185
1186 preempt_enable();
1187}
1188
1189void __init smp_prepare_cpus(unsigned int max_cpus)
1190{
1191}
1192
1193void smp_prepare_boot_cpu(void)
1194{
1195}
1196
1197void __init smp_setup_processor_id(void)
1198{
1199 if (tlb_type == spitfire)
1200 xcall_deliver_impl = spitfire_xcall_deliver;
1201 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1202 xcall_deliver_impl = cheetah_xcall_deliver;
1203 else
1204 xcall_deliver_impl = hypervisor_xcall_deliver;
1205}
1206
1207void __init smp_fill_in_cpu_possible_map(void)
1208{
1209 int possible_cpus = num_possible_cpus();
1210 int i;
1211
1212 if (possible_cpus > nr_cpu_ids)
1213 possible_cpus = nr_cpu_ids;
1214
1215 for (i = 0; i < possible_cpus; i++)
1216 set_cpu_possible(i, true);
1217 for (; i < NR_CPUS; i++)
1218 set_cpu_possible(i, false);
1219}
1220
1221void smp_fill_in_sib_core_maps(void)
1222{
1223 unsigned int i;
1224
1225 for_each_present_cpu(i) {
1226 unsigned int j;
1227
1228 cpumask_clear(&cpu_core_map[i]);
1229 if (cpu_data(i).core_id == 0) {
1230 cpumask_set_cpu(i, &cpu_core_map[i]);
1231 continue;
1232 }
1233
1234 for_each_present_cpu(j) {
1235 if (cpu_data(i).core_id ==
1236 cpu_data(j).core_id)
1237 cpumask_set_cpu(j, &cpu_core_map[i]);
1238 }
1239 }
1240
1241 for_each_present_cpu(i) {
1242 unsigned int j;
1243
1244 for_each_present_cpu(j) {
1245 if (cpu_data(i).max_cache_id ==
1246 cpu_data(j).max_cache_id)
1247 cpumask_set_cpu(j, &cpu_core_sib_cache_map[i]);
1248
1249 if (cpu_data(i).sock_id == cpu_data(j).sock_id)
1250 cpumask_set_cpu(j, &cpu_core_sib_map[i]);
1251 }
1252 }
1253
1254 for_each_present_cpu(i) {
1255 unsigned int j;
1256
1257 cpumask_clear(&per_cpu(cpu_sibling_map, i));
1258 if (cpu_data(i).proc_id == -1) {
1259 cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i));
1260 continue;
1261 }
1262
1263 for_each_present_cpu(j) {
1264 if (cpu_data(i).proc_id ==
1265 cpu_data(j).proc_id)
1266 cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i));
1267 }
1268 }
1269}
1270
1271int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1272{
1273 int ret = smp_boot_one_cpu(cpu, tidle);
1274
1275 if (!ret) {
1276 cpumask_set_cpu(cpu, &smp_commenced_mask);
1277 while (!cpu_online(cpu))
1278 mb();
1279 if (!cpu_online(cpu)) {
1280 ret = -ENODEV;
1281 } else {
1282 /* On SUN4V, writes to %tick and %stick are
1283 * not allowed.
1284 */
1285 if (tlb_type != hypervisor)
1286 smp_synchronize_one_tick(cpu);
1287 }
1288 }
1289 return ret;
1290}
1291
1292#ifdef CONFIG_HOTPLUG_CPU
1293void cpu_play_dead(void)
1294{
1295 int cpu = smp_processor_id();
1296 unsigned long pstate;
1297
1298 idle_task_exit();
1299
1300 if (tlb_type == hypervisor) {
1301 struct trap_per_cpu *tb = &trap_block[cpu];
1302
1303 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1304 tb->cpu_mondo_pa, 0);
1305 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1306 tb->dev_mondo_pa, 0);
1307 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1308 tb->resum_mondo_pa, 0);
1309 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1310 tb->nonresum_mondo_pa, 0);
1311 }
1312
1313 cpumask_clear_cpu(cpu, &smp_commenced_mask);
1314 membar_safe("#Sync");
1315
1316 local_irq_disable();
1317
1318 __asm__ __volatile__(
1319 "rdpr %%pstate, %0\n\t"
1320 "wrpr %0, %1, %%pstate"
1321 : "=r" (pstate)
1322 : "i" (PSTATE_IE));
1323
1324 while (1)
1325 barrier();
1326}
1327
1328int __cpu_disable(void)
1329{
1330 int cpu = smp_processor_id();
1331 cpuinfo_sparc *c;
1332 int i;
1333
1334 for_each_cpu(i, &cpu_core_map[cpu])
1335 cpumask_clear_cpu(cpu, &cpu_core_map[i]);
1336 cpumask_clear(&cpu_core_map[cpu]);
1337
1338 for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu))
1339 cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i));
1340 cpumask_clear(&per_cpu(cpu_sibling_map, cpu));
1341
1342 c = &cpu_data(cpu);
1343
1344 c->core_id = 0;
1345 c->proc_id = -1;
1346
1347 smp_wmb();
1348
1349 /* Make sure no interrupts point to this cpu. */
1350 fixup_irqs();
1351
1352 local_irq_enable();
1353 mdelay(1);
1354 local_irq_disable();
1355
1356 set_cpu_online(cpu, false);
1357
1358 cpu_map_rebuild();
1359
1360 return 0;
1361}
1362
1363void __cpu_die(unsigned int cpu)
1364{
1365 int i;
1366
1367 for (i = 0; i < 100; i++) {
1368 smp_rmb();
1369 if (!cpumask_test_cpu(cpu, &smp_commenced_mask))
1370 break;
1371 msleep(100);
1372 }
1373 if (cpumask_test_cpu(cpu, &smp_commenced_mask)) {
1374 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1375 } else {
1376#if defined(CONFIG_SUN_LDOMS)
1377 unsigned long hv_err;
1378 int limit = 100;
1379
1380 do {
1381 hv_err = sun4v_cpu_stop(cpu);
1382 if (hv_err == HV_EOK) {
1383 set_cpu_present(cpu, false);
1384 break;
1385 }
1386 } while (--limit > 0);
1387 if (limit <= 0) {
1388 printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1389 hv_err);
1390 }
1391#endif
1392 }
1393}
1394#endif
1395
1396void __init smp_cpus_done(unsigned int max_cpus)
1397{
1398}
1399
1400static void send_cpu_ipi(int cpu)
1401{
1402 xcall_deliver((u64) &xcall_receive_signal,
1403 0, 0, cpumask_of(cpu));
1404}
1405
1406void scheduler_poke(void)
1407{
1408 if (!cpu_poke)
1409 return;
1410
1411 if (!__this_cpu_read(poke))
1412 return;
1413
1414 __this_cpu_write(poke, false);
1415 set_softint(1 << PIL_SMP_RECEIVE_SIGNAL);
1416}
1417
1418static unsigned long send_cpu_poke(int cpu)
1419{
1420 unsigned long hv_err;
1421
1422 per_cpu(poke, cpu) = true;
1423 hv_err = sun4v_cpu_poke(cpu);
1424 if (hv_err != HV_EOK) {
1425 per_cpu(poke, cpu) = false;
1426 pr_err_ratelimited("%s: sun4v_cpu_poke() fails err=%lu\n",
1427 __func__, hv_err);
1428 }
1429
1430 return hv_err;
1431}
1432
1433void smp_send_reschedule(int cpu)
1434{
1435 if (cpu == smp_processor_id()) {
1436 WARN_ON_ONCE(preemptible());
1437 set_softint(1 << PIL_SMP_RECEIVE_SIGNAL);
1438 return;
1439 }
1440
1441 /* Use cpu poke to resume idle cpu if supported. */
1442 if (cpu_poke && idle_cpu(cpu)) {
1443 unsigned long ret;
1444
1445 ret = send_cpu_poke(cpu);
1446 if (ret == HV_EOK)
1447 return;
1448 }
1449
1450 /* Use IPI in following cases:
1451 * - cpu poke not supported
1452 * - cpu not idle
1453 * - send_cpu_poke() returns with error
1454 */
1455 send_cpu_ipi(cpu);
1456}
1457
1458void smp_init_cpu_poke(void)
1459{
1460 unsigned long major;
1461 unsigned long minor;
1462 int ret;
1463
1464 if (tlb_type != hypervisor)
1465 return;
1466
1467 ret = sun4v_hvapi_get(HV_GRP_CORE, &major, &minor);
1468 if (ret) {
1469 pr_debug("HV_GRP_CORE is not registered\n");
1470 return;
1471 }
1472
1473 if (major == 1 && minor >= 6) {
1474 /* CPU POKE is registered. */
1475 cpu_poke = true;
1476 return;
1477 }
1478
1479 pr_debug("CPU_POKE not supported\n");
1480}
1481
1482void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs)
1483{
1484 clear_softint(1 << irq);
1485 scheduler_ipi();
1486}
1487
1488static void stop_this_cpu(void *dummy)
1489{
1490 set_cpu_online(smp_processor_id(), false);
1491 prom_stopself();
1492}
1493
1494void smp_send_stop(void)
1495{
1496 int cpu;
1497
1498 if (tlb_type == hypervisor) {
1499 int this_cpu = smp_processor_id();
1500#ifdef CONFIG_SERIAL_SUNHV
1501 sunhv_migrate_hvcons_irq(this_cpu);
1502#endif
1503 for_each_online_cpu(cpu) {
1504 if (cpu == this_cpu)
1505 continue;
1506
1507 set_cpu_online(cpu, false);
1508#ifdef CONFIG_SUN_LDOMS
1509 if (ldom_domaining_enabled) {
1510 unsigned long hv_err;
1511 hv_err = sun4v_cpu_stop(cpu);
1512 if (hv_err)
1513 printk(KERN_ERR "sun4v_cpu_stop() "
1514 "failed err=%lu\n", hv_err);
1515 } else
1516#endif
1517 prom_stopcpu_cpuid(cpu);
1518 }
1519 } else
1520 smp_call_function(stop_this_cpu, NULL, 0);
1521}
1522
1523static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
1524{
1525 if (cpu_to_node(from) == cpu_to_node(to))
1526 return LOCAL_DISTANCE;
1527 else
1528 return REMOTE_DISTANCE;
1529}
1530
1531static int __init pcpu_cpu_to_node(int cpu)
1532{
1533 return cpu_to_node(cpu);
1534}
1535
1536void __init setup_per_cpu_areas(void)
1537{
1538 unsigned long delta;
1539 unsigned int cpu;
1540 int rc = -EINVAL;
1541
1542 if (pcpu_chosen_fc != PCPU_FC_PAGE) {
1543 rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
1544 PERCPU_DYNAMIC_RESERVE, 4 << 20,
1545 pcpu_cpu_distance,
1546 pcpu_cpu_to_node);
1547 if (rc)
1548 pr_warn("PERCPU: %s allocator failed (%d), "
1549 "falling back to page size\n",
1550 pcpu_fc_names[pcpu_chosen_fc], rc);
1551 }
1552 if (rc < 0)
1553 rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE,
1554 pcpu_cpu_to_node);
1555 if (rc < 0)
1556 panic("cannot initialize percpu area (err=%d)", rc);
1557
1558 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
1559 for_each_possible_cpu(cpu)
1560 __per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu];
1561
1562 /* Setup %g5 for the boot cpu. */
1563 __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1564
1565 of_fill_in_cpu_data();
1566 if (tlb_type == hypervisor)
1567 mdesc_fill_in_cpu_data(cpu_all_mask);
1568}
1/* smp.c: Sparc64 SMP support.
2 *
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/export.h>
7#include <linux/kernel.h>
8#include <linux/sched.h>
9#include <linux/mm.h>
10#include <linux/pagemap.h>
11#include <linux/threads.h>
12#include <linux/smp.h>
13#include <linux/interrupt.h>
14#include <linux/kernel_stat.h>
15#include <linux/delay.h>
16#include <linux/init.h>
17#include <linux/spinlock.h>
18#include <linux/fs.h>
19#include <linux/seq_file.h>
20#include <linux/cache.h>
21#include <linux/jiffies.h>
22#include <linux/profile.h>
23#include <linux/bootmem.h>
24#include <linux/vmalloc.h>
25#include <linux/ftrace.h>
26#include <linux/cpu.h>
27#include <linux/slab.h>
28#include <linux/kgdb.h>
29
30#include <asm/head.h>
31#include <asm/ptrace.h>
32#include <linux/atomic.h>
33#include <asm/tlbflush.h>
34#include <asm/mmu_context.h>
35#include <asm/cpudata.h>
36#include <asm/hvtramp.h>
37#include <asm/io.h>
38#include <asm/timer.h>
39#include <asm/setup.h>
40
41#include <asm/irq.h>
42#include <asm/irq_regs.h>
43#include <asm/page.h>
44#include <asm/pgtable.h>
45#include <asm/oplib.h>
46#include <linux/uaccess.h>
47#include <asm/starfire.h>
48#include <asm/tlb.h>
49#include <asm/sections.h>
50#include <asm/prom.h>
51#include <asm/mdesc.h>
52#include <asm/ldc.h>
53#include <asm/hypervisor.h>
54#include <asm/pcr.h>
55
56#include "cpumap.h"
57#include "kernel.h"
58
59DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
60cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
61 { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
62
63cpumask_t cpu_core_sib_map[NR_CPUS] __read_mostly = {
64 [0 ... NR_CPUS-1] = CPU_MASK_NONE };
65
66cpumask_t cpu_core_sib_cache_map[NR_CPUS] __read_mostly = {
67 [0 ... NR_CPUS - 1] = CPU_MASK_NONE };
68
69EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
70EXPORT_SYMBOL(cpu_core_map);
71EXPORT_SYMBOL(cpu_core_sib_map);
72EXPORT_SYMBOL(cpu_core_sib_cache_map);
73
74static cpumask_t smp_commenced_mask;
75
76void smp_info(struct seq_file *m)
77{
78 int i;
79
80 seq_printf(m, "State:\n");
81 for_each_online_cpu(i)
82 seq_printf(m, "CPU%d:\t\tonline\n", i);
83}
84
85void smp_bogo(struct seq_file *m)
86{
87 int i;
88
89 for_each_online_cpu(i)
90 seq_printf(m,
91 "Cpu%dClkTck\t: %016lx\n",
92 i, cpu_data(i).clock_tick);
93}
94
95extern void setup_sparc64_timer(void);
96
97static volatile unsigned long callin_flag = 0;
98
99void smp_callin(void)
100{
101 int cpuid = hard_smp_processor_id();
102
103 __local_per_cpu_offset = __per_cpu_offset(cpuid);
104
105 if (tlb_type == hypervisor)
106 sun4v_ktsb_register();
107
108 __flush_tlb_all();
109
110 setup_sparc64_timer();
111
112 if (cheetah_pcache_forced_on)
113 cheetah_enable_pcache();
114
115 callin_flag = 1;
116 __asm__ __volatile__("membar #Sync\n\t"
117 "flush %%g6" : : : "memory");
118
119 /* Clear this or we will die instantly when we
120 * schedule back to this idler...
121 */
122 current_thread_info()->new_child = 0;
123
124 /* Attach to the address space of init_task. */
125 atomic_inc(&init_mm.mm_count);
126 current->active_mm = &init_mm;
127
128 /* inform the notifiers about the new cpu */
129 notify_cpu_starting(cpuid);
130
131 while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
132 rmb();
133
134 set_cpu_online(cpuid, true);
135
136 /* idle thread is expected to have preempt disabled */
137 preempt_disable();
138
139 local_irq_enable();
140
141 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
142}
143
144void cpu_panic(void)
145{
146 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
147 panic("SMP bolixed\n");
148}
149
150/* This tick register synchronization scheme is taken entirely from
151 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
152 *
153 * The only change I've made is to rework it so that the master
154 * initiates the synchonization instead of the slave. -DaveM
155 */
156
157#define MASTER 0
158#define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
159
160#define NUM_ROUNDS 64 /* magic value */
161#define NUM_ITERS 5 /* likewise */
162
163static DEFINE_RAW_SPINLOCK(itc_sync_lock);
164static unsigned long go[SLAVE + 1];
165
166#define DEBUG_TICK_SYNC 0
167
168static inline long get_delta (long *rt, long *master)
169{
170 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
171 unsigned long tcenter, t0, t1, tm;
172 unsigned long i;
173
174 for (i = 0; i < NUM_ITERS; i++) {
175 t0 = tick_ops->get_tick();
176 go[MASTER] = 1;
177 membar_safe("#StoreLoad");
178 while (!(tm = go[SLAVE]))
179 rmb();
180 go[SLAVE] = 0;
181 wmb();
182 t1 = tick_ops->get_tick();
183
184 if (t1 - t0 < best_t1 - best_t0)
185 best_t0 = t0, best_t1 = t1, best_tm = tm;
186 }
187
188 *rt = best_t1 - best_t0;
189 *master = best_tm - best_t0;
190
191 /* average best_t0 and best_t1 without overflow: */
192 tcenter = (best_t0/2 + best_t1/2);
193 if (best_t0 % 2 + best_t1 % 2 == 2)
194 tcenter++;
195 return tcenter - best_tm;
196}
197
198void smp_synchronize_tick_client(void)
199{
200 long i, delta, adj, adjust_latency = 0, done = 0;
201 unsigned long flags, rt, master_time_stamp;
202#if DEBUG_TICK_SYNC
203 struct {
204 long rt; /* roundtrip time */
205 long master; /* master's timestamp */
206 long diff; /* difference between midpoint and master's timestamp */
207 long lat; /* estimate of itc adjustment latency */
208 } t[NUM_ROUNDS];
209#endif
210
211 go[MASTER] = 1;
212
213 while (go[MASTER])
214 rmb();
215
216 local_irq_save(flags);
217 {
218 for (i = 0; i < NUM_ROUNDS; i++) {
219 delta = get_delta(&rt, &master_time_stamp);
220 if (delta == 0)
221 done = 1; /* let's lock on to this... */
222
223 if (!done) {
224 if (i > 0) {
225 adjust_latency += -delta;
226 adj = -delta + adjust_latency/4;
227 } else
228 adj = -delta;
229
230 tick_ops->add_tick(adj);
231 }
232#if DEBUG_TICK_SYNC
233 t[i].rt = rt;
234 t[i].master = master_time_stamp;
235 t[i].diff = delta;
236 t[i].lat = adjust_latency/4;
237#endif
238 }
239 }
240 local_irq_restore(flags);
241
242#if DEBUG_TICK_SYNC
243 for (i = 0; i < NUM_ROUNDS; i++)
244 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
245 t[i].rt, t[i].master, t[i].diff, t[i].lat);
246#endif
247
248 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
249 "(last diff %ld cycles, maxerr %lu cycles)\n",
250 smp_processor_id(), delta, rt);
251}
252
253static void smp_start_sync_tick_client(int cpu);
254
255static void smp_synchronize_one_tick(int cpu)
256{
257 unsigned long flags, i;
258
259 go[MASTER] = 0;
260
261 smp_start_sync_tick_client(cpu);
262
263 /* wait for client to be ready */
264 while (!go[MASTER])
265 rmb();
266
267 /* now let the client proceed into his loop */
268 go[MASTER] = 0;
269 membar_safe("#StoreLoad");
270
271 raw_spin_lock_irqsave(&itc_sync_lock, flags);
272 {
273 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
274 while (!go[MASTER])
275 rmb();
276 go[MASTER] = 0;
277 wmb();
278 go[SLAVE] = tick_ops->get_tick();
279 membar_safe("#StoreLoad");
280 }
281 }
282 raw_spin_unlock_irqrestore(&itc_sync_lock, flags);
283}
284
285#if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
286static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg,
287 void **descrp)
288{
289 extern unsigned long sparc64_ttable_tl0;
290 extern unsigned long kern_locked_tte_data;
291 struct hvtramp_descr *hdesc;
292 unsigned long trampoline_ra;
293 struct trap_per_cpu *tb;
294 u64 tte_vaddr, tte_data;
295 unsigned long hv_err;
296 int i;
297
298 hdesc = kzalloc(sizeof(*hdesc) +
299 (sizeof(struct hvtramp_mapping) *
300 num_kernel_image_mappings - 1),
301 GFP_KERNEL);
302 if (!hdesc) {
303 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
304 "hvtramp_descr.\n");
305 return;
306 }
307 *descrp = hdesc;
308
309 hdesc->cpu = cpu;
310 hdesc->num_mappings = num_kernel_image_mappings;
311
312 tb = &trap_block[cpu];
313
314 hdesc->fault_info_va = (unsigned long) &tb->fault_info;
315 hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
316
317 hdesc->thread_reg = thread_reg;
318
319 tte_vaddr = (unsigned long) KERNBASE;
320 tte_data = kern_locked_tte_data;
321
322 for (i = 0; i < hdesc->num_mappings; i++) {
323 hdesc->maps[i].vaddr = tte_vaddr;
324 hdesc->maps[i].tte = tte_data;
325 tte_vaddr += 0x400000;
326 tte_data += 0x400000;
327 }
328
329 trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
330
331 hv_err = sun4v_cpu_start(cpu, trampoline_ra,
332 kimage_addr_to_ra(&sparc64_ttable_tl0),
333 __pa(hdesc));
334 if (hv_err)
335 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
336 "gives error %lu\n", hv_err);
337}
338#endif
339
340extern unsigned long sparc64_cpu_startup;
341
342/* The OBP cpu startup callback truncates the 3rd arg cookie to
343 * 32-bits (I think) so to be safe we have it read the pointer
344 * contained here so we work on >4GB machines. -DaveM
345 */
346static struct thread_info *cpu_new_thread = NULL;
347
348static int smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle)
349{
350 unsigned long entry =
351 (unsigned long)(&sparc64_cpu_startup);
352 unsigned long cookie =
353 (unsigned long)(&cpu_new_thread);
354 void *descr = NULL;
355 int timeout, ret;
356
357 callin_flag = 0;
358 cpu_new_thread = task_thread_info(idle);
359
360 if (tlb_type == hypervisor) {
361#if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
362 if (ldom_domaining_enabled)
363 ldom_startcpu_cpuid(cpu,
364 (unsigned long) cpu_new_thread,
365 &descr);
366 else
367#endif
368 prom_startcpu_cpuid(cpu, entry, cookie);
369 } else {
370 struct device_node *dp = of_find_node_by_cpuid(cpu);
371
372 prom_startcpu(dp->phandle, entry, cookie);
373 }
374
375 for (timeout = 0; timeout < 50000; timeout++) {
376 if (callin_flag)
377 break;
378 udelay(100);
379 }
380
381 if (callin_flag) {
382 ret = 0;
383 } else {
384 printk("Processor %d is stuck.\n", cpu);
385 ret = -ENODEV;
386 }
387 cpu_new_thread = NULL;
388
389 kfree(descr);
390
391 return ret;
392}
393
394static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
395{
396 u64 result, target;
397 int stuck, tmp;
398
399 if (this_is_starfire) {
400 /* map to real upaid */
401 cpu = (((cpu & 0x3c) << 1) |
402 ((cpu & 0x40) >> 4) |
403 (cpu & 0x3));
404 }
405
406 target = (cpu << 14) | 0x70;
407again:
408 /* Ok, this is the real Spitfire Errata #54.
409 * One must read back from a UDB internal register
410 * after writes to the UDB interrupt dispatch, but
411 * before the membar Sync for that write.
412 * So we use the high UDB control register (ASI 0x7f,
413 * ADDR 0x20) for the dummy read. -DaveM
414 */
415 tmp = 0x40;
416 __asm__ __volatile__(
417 "wrpr %1, %2, %%pstate\n\t"
418 "stxa %4, [%0] %3\n\t"
419 "stxa %5, [%0+%8] %3\n\t"
420 "add %0, %8, %0\n\t"
421 "stxa %6, [%0+%8] %3\n\t"
422 "membar #Sync\n\t"
423 "stxa %%g0, [%7] %3\n\t"
424 "membar #Sync\n\t"
425 "mov 0x20, %%g1\n\t"
426 "ldxa [%%g1] 0x7f, %%g0\n\t"
427 "membar #Sync"
428 : "=r" (tmp)
429 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
430 "r" (data0), "r" (data1), "r" (data2), "r" (target),
431 "r" (0x10), "0" (tmp)
432 : "g1");
433
434 /* NOTE: PSTATE_IE is still clear. */
435 stuck = 100000;
436 do {
437 __asm__ __volatile__("ldxa [%%g0] %1, %0"
438 : "=r" (result)
439 : "i" (ASI_INTR_DISPATCH_STAT));
440 if (result == 0) {
441 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
442 : : "r" (pstate));
443 return;
444 }
445 stuck -= 1;
446 if (stuck == 0)
447 break;
448 } while (result & 0x1);
449 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
450 : : "r" (pstate));
451 if (stuck == 0) {
452 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
453 smp_processor_id(), result);
454 } else {
455 udelay(2);
456 goto again;
457 }
458}
459
460static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
461{
462 u64 *mondo, data0, data1, data2;
463 u16 *cpu_list;
464 u64 pstate;
465 int i;
466
467 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
468 cpu_list = __va(tb->cpu_list_pa);
469 mondo = __va(tb->cpu_mondo_block_pa);
470 data0 = mondo[0];
471 data1 = mondo[1];
472 data2 = mondo[2];
473 for (i = 0; i < cnt; i++)
474 spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
475}
476
477/* Cheetah now allows to send the whole 64-bytes of data in the interrupt
478 * packet, but we have no use for that. However we do take advantage of
479 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
480 */
481static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
482{
483 int nack_busy_id, is_jbus, need_more;
484 u64 *mondo, pstate, ver, busy_mask;
485 u16 *cpu_list;
486
487 cpu_list = __va(tb->cpu_list_pa);
488 mondo = __va(tb->cpu_mondo_block_pa);
489
490 /* Unfortunately, someone at Sun had the brilliant idea to make the
491 * busy/nack fields hard-coded by ITID number for this Ultra-III
492 * derivative processor.
493 */
494 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
495 is_jbus = ((ver >> 32) == __JALAPENO_ID ||
496 (ver >> 32) == __SERRANO_ID);
497
498 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
499
500retry:
501 need_more = 0;
502 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
503 : : "r" (pstate), "i" (PSTATE_IE));
504
505 /* Setup the dispatch data registers. */
506 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
507 "stxa %1, [%4] %6\n\t"
508 "stxa %2, [%5] %6\n\t"
509 "membar #Sync\n\t"
510 : /* no outputs */
511 : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
512 "r" (0x40), "r" (0x50), "r" (0x60),
513 "i" (ASI_INTR_W));
514
515 nack_busy_id = 0;
516 busy_mask = 0;
517 {
518 int i;
519
520 for (i = 0; i < cnt; i++) {
521 u64 target, nr;
522
523 nr = cpu_list[i];
524 if (nr == 0xffff)
525 continue;
526
527 target = (nr << 14) | 0x70;
528 if (is_jbus) {
529 busy_mask |= (0x1UL << (nr * 2));
530 } else {
531 target |= (nack_busy_id << 24);
532 busy_mask |= (0x1UL <<
533 (nack_busy_id * 2));
534 }
535 __asm__ __volatile__(
536 "stxa %%g0, [%0] %1\n\t"
537 "membar #Sync\n\t"
538 : /* no outputs */
539 : "r" (target), "i" (ASI_INTR_W));
540 nack_busy_id++;
541 if (nack_busy_id == 32) {
542 need_more = 1;
543 break;
544 }
545 }
546 }
547
548 /* Now, poll for completion. */
549 {
550 u64 dispatch_stat, nack_mask;
551 long stuck;
552
553 stuck = 100000 * nack_busy_id;
554 nack_mask = busy_mask << 1;
555 do {
556 __asm__ __volatile__("ldxa [%%g0] %1, %0"
557 : "=r" (dispatch_stat)
558 : "i" (ASI_INTR_DISPATCH_STAT));
559 if (!(dispatch_stat & (busy_mask | nack_mask))) {
560 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
561 : : "r" (pstate));
562 if (unlikely(need_more)) {
563 int i, this_cnt = 0;
564 for (i = 0; i < cnt; i++) {
565 if (cpu_list[i] == 0xffff)
566 continue;
567 cpu_list[i] = 0xffff;
568 this_cnt++;
569 if (this_cnt == 32)
570 break;
571 }
572 goto retry;
573 }
574 return;
575 }
576 if (!--stuck)
577 break;
578 } while (dispatch_stat & busy_mask);
579
580 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
581 : : "r" (pstate));
582
583 if (dispatch_stat & busy_mask) {
584 /* Busy bits will not clear, continue instead
585 * of freezing up on this cpu.
586 */
587 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
588 smp_processor_id(), dispatch_stat);
589 } else {
590 int i, this_busy_nack = 0;
591
592 /* Delay some random time with interrupts enabled
593 * to prevent deadlock.
594 */
595 udelay(2 * nack_busy_id);
596
597 /* Clear out the mask bits for cpus which did not
598 * NACK us.
599 */
600 for (i = 0; i < cnt; i++) {
601 u64 check_mask, nr;
602
603 nr = cpu_list[i];
604 if (nr == 0xffff)
605 continue;
606
607 if (is_jbus)
608 check_mask = (0x2UL << (2*nr));
609 else
610 check_mask = (0x2UL <<
611 this_busy_nack);
612 if ((dispatch_stat & check_mask) == 0)
613 cpu_list[i] = 0xffff;
614 this_busy_nack += 2;
615 if (this_busy_nack == 64)
616 break;
617 }
618
619 goto retry;
620 }
621 }
622}
623
624/* Multi-cpu list version. */
625static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
626{
627 int retries, this_cpu, prev_sent, i, saw_cpu_error;
628 unsigned long status;
629 u16 *cpu_list;
630
631 this_cpu = smp_processor_id();
632
633 cpu_list = __va(tb->cpu_list_pa);
634
635 saw_cpu_error = 0;
636 retries = 0;
637 prev_sent = 0;
638 do {
639 int forward_progress, n_sent;
640
641 status = sun4v_cpu_mondo_send(cnt,
642 tb->cpu_list_pa,
643 tb->cpu_mondo_block_pa);
644
645 /* HV_EOK means all cpus received the xcall, we're done. */
646 if (likely(status == HV_EOK))
647 break;
648
649 /* First, see if we made any forward progress.
650 *
651 * The hypervisor indicates successful sends by setting
652 * cpu list entries to the value 0xffff.
653 */
654 n_sent = 0;
655 for (i = 0; i < cnt; i++) {
656 if (likely(cpu_list[i] == 0xffff))
657 n_sent++;
658 }
659
660 forward_progress = 0;
661 if (n_sent > prev_sent)
662 forward_progress = 1;
663
664 prev_sent = n_sent;
665
666 /* If we get a HV_ECPUERROR, then one or more of the cpus
667 * in the list are in error state. Use the cpu_state()
668 * hypervisor call to find out which cpus are in error state.
669 */
670 if (unlikely(status == HV_ECPUERROR)) {
671 for (i = 0; i < cnt; i++) {
672 long err;
673 u16 cpu;
674
675 cpu = cpu_list[i];
676 if (cpu == 0xffff)
677 continue;
678
679 err = sun4v_cpu_state(cpu);
680 if (err == HV_CPU_STATE_ERROR) {
681 saw_cpu_error = (cpu + 1);
682 cpu_list[i] = 0xffff;
683 }
684 }
685 } else if (unlikely(status != HV_EWOULDBLOCK))
686 goto fatal_mondo_error;
687
688 /* Don't bother rewriting the CPU list, just leave the
689 * 0xffff and non-0xffff entries in there and the
690 * hypervisor will do the right thing.
691 *
692 * Only advance timeout state if we didn't make any
693 * forward progress.
694 */
695 if (unlikely(!forward_progress)) {
696 if (unlikely(++retries > 10000))
697 goto fatal_mondo_timeout;
698
699 /* Delay a little bit to let other cpus catch up
700 * on their cpu mondo queue work.
701 */
702 udelay(2 * cnt);
703 }
704 } while (1);
705
706 if (unlikely(saw_cpu_error))
707 goto fatal_mondo_cpu_error;
708
709 return;
710
711fatal_mondo_cpu_error:
712 printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
713 "(including %d) were in error state\n",
714 this_cpu, saw_cpu_error - 1);
715 return;
716
717fatal_mondo_timeout:
718 printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
719 " progress after %d retries.\n",
720 this_cpu, retries);
721 goto dump_cpu_list_and_out;
722
723fatal_mondo_error:
724 printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
725 this_cpu, status);
726 printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
727 "mondo_block_pa(%lx)\n",
728 this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
729
730dump_cpu_list_and_out:
731 printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
732 for (i = 0; i < cnt; i++)
733 printk("%u ", cpu_list[i]);
734 printk("]\n");
735}
736
737static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
738
739static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
740{
741 struct trap_per_cpu *tb;
742 int this_cpu, i, cnt;
743 unsigned long flags;
744 u16 *cpu_list;
745 u64 *mondo;
746
747 /* We have to do this whole thing with interrupts fully disabled.
748 * Otherwise if we send an xcall from interrupt context it will
749 * corrupt both our mondo block and cpu list state.
750 *
751 * One consequence of this is that we cannot use timeout mechanisms
752 * that depend upon interrupts being delivered locally. So, for
753 * example, we cannot sample jiffies and expect it to advance.
754 *
755 * Fortunately, udelay() uses %stick/%tick so we can use that.
756 */
757 local_irq_save(flags);
758
759 this_cpu = smp_processor_id();
760 tb = &trap_block[this_cpu];
761
762 mondo = __va(tb->cpu_mondo_block_pa);
763 mondo[0] = data0;
764 mondo[1] = data1;
765 mondo[2] = data2;
766 wmb();
767
768 cpu_list = __va(tb->cpu_list_pa);
769
770 /* Setup the initial cpu list. */
771 cnt = 0;
772 for_each_cpu(i, mask) {
773 if (i == this_cpu || !cpu_online(i))
774 continue;
775 cpu_list[cnt++] = i;
776 }
777
778 if (cnt)
779 xcall_deliver_impl(tb, cnt);
780
781 local_irq_restore(flags);
782}
783
784/* Send cross call to all processors mentioned in MASK_P
785 * except self. Really, there are only two cases currently,
786 * "cpu_online_mask" and "mm_cpumask(mm)".
787 */
788static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask)
789{
790 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
791
792 xcall_deliver(data0, data1, data2, mask);
793}
794
795/* Send cross call to all processors except self. */
796static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
797{
798 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask);
799}
800
801extern unsigned long xcall_sync_tick;
802
803static void smp_start_sync_tick_client(int cpu)
804{
805 xcall_deliver((u64) &xcall_sync_tick, 0, 0,
806 cpumask_of(cpu));
807}
808
809extern unsigned long xcall_call_function;
810
811void arch_send_call_function_ipi_mask(const struct cpumask *mask)
812{
813 xcall_deliver((u64) &xcall_call_function, 0, 0, mask);
814}
815
816extern unsigned long xcall_call_function_single;
817
818void arch_send_call_function_single_ipi(int cpu)
819{
820 xcall_deliver((u64) &xcall_call_function_single, 0, 0,
821 cpumask_of(cpu));
822}
823
824void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs)
825{
826 clear_softint(1 << irq);
827 irq_enter();
828 generic_smp_call_function_interrupt();
829 irq_exit();
830}
831
832void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs)
833{
834 clear_softint(1 << irq);
835 irq_enter();
836 generic_smp_call_function_single_interrupt();
837 irq_exit();
838}
839
840static void tsb_sync(void *info)
841{
842 struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
843 struct mm_struct *mm = info;
844
845 /* It is not valid to test "current->active_mm == mm" here.
846 *
847 * The value of "current" is not changed atomically with
848 * switch_mm(). But that's OK, we just need to check the
849 * current cpu's trap block PGD physical address.
850 */
851 if (tp->pgd_paddr == __pa(mm->pgd))
852 tsb_context_switch(mm);
853}
854
855void smp_tsb_sync(struct mm_struct *mm)
856{
857 smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1);
858}
859
860extern unsigned long xcall_flush_tlb_mm;
861extern unsigned long xcall_flush_tlb_page;
862extern unsigned long xcall_flush_tlb_kernel_range;
863extern unsigned long xcall_fetch_glob_regs;
864extern unsigned long xcall_fetch_glob_pmu;
865extern unsigned long xcall_fetch_glob_pmu_n4;
866extern unsigned long xcall_receive_signal;
867extern unsigned long xcall_new_mmu_context_version;
868#ifdef CONFIG_KGDB
869extern unsigned long xcall_kgdb_capture;
870#endif
871
872#ifdef DCACHE_ALIASING_POSSIBLE
873extern unsigned long xcall_flush_dcache_page_cheetah;
874#endif
875extern unsigned long xcall_flush_dcache_page_spitfire;
876
877static inline void __local_flush_dcache_page(struct page *page)
878{
879#ifdef DCACHE_ALIASING_POSSIBLE
880 __flush_dcache_page(page_address(page),
881 ((tlb_type == spitfire) &&
882 page_mapping(page) != NULL));
883#else
884 if (page_mapping(page) != NULL &&
885 tlb_type == spitfire)
886 __flush_icache_page(__pa(page_address(page)));
887#endif
888}
889
890void smp_flush_dcache_page_impl(struct page *page, int cpu)
891{
892 int this_cpu;
893
894 if (tlb_type == hypervisor)
895 return;
896
897#ifdef CONFIG_DEBUG_DCFLUSH
898 atomic_inc(&dcpage_flushes);
899#endif
900
901 this_cpu = get_cpu();
902
903 if (cpu == this_cpu) {
904 __local_flush_dcache_page(page);
905 } else if (cpu_online(cpu)) {
906 void *pg_addr = page_address(page);
907 u64 data0 = 0;
908
909 if (tlb_type == spitfire) {
910 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
911 if (page_mapping(page) != NULL)
912 data0 |= ((u64)1 << 32);
913 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
914#ifdef DCACHE_ALIASING_POSSIBLE
915 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
916#endif
917 }
918 if (data0) {
919 xcall_deliver(data0, __pa(pg_addr),
920 (u64) pg_addr, cpumask_of(cpu));
921#ifdef CONFIG_DEBUG_DCFLUSH
922 atomic_inc(&dcpage_flushes_xcall);
923#endif
924 }
925 }
926
927 put_cpu();
928}
929
930void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
931{
932 void *pg_addr;
933 u64 data0;
934
935 if (tlb_type == hypervisor)
936 return;
937
938 preempt_disable();
939
940#ifdef CONFIG_DEBUG_DCFLUSH
941 atomic_inc(&dcpage_flushes);
942#endif
943 data0 = 0;
944 pg_addr = page_address(page);
945 if (tlb_type == spitfire) {
946 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
947 if (page_mapping(page) != NULL)
948 data0 |= ((u64)1 << 32);
949 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
950#ifdef DCACHE_ALIASING_POSSIBLE
951 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
952#endif
953 }
954 if (data0) {
955 xcall_deliver(data0, __pa(pg_addr),
956 (u64) pg_addr, cpu_online_mask);
957#ifdef CONFIG_DEBUG_DCFLUSH
958 atomic_inc(&dcpage_flushes_xcall);
959#endif
960 }
961 __local_flush_dcache_page(page);
962
963 preempt_enable();
964}
965
966void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
967{
968 struct mm_struct *mm;
969 unsigned long flags;
970
971 clear_softint(1 << irq);
972
973 /* See if we need to allocate a new TLB context because
974 * the version of the one we are using is now out of date.
975 */
976 mm = current->active_mm;
977 if (unlikely(!mm || (mm == &init_mm)))
978 return;
979
980 spin_lock_irqsave(&mm->context.lock, flags);
981
982 if (unlikely(!CTX_VALID(mm->context)))
983 get_new_mmu_context(mm);
984
985 spin_unlock_irqrestore(&mm->context.lock, flags);
986
987 load_secondary_context(mm);
988 __flush_tlb_mm(CTX_HWBITS(mm->context),
989 SECONDARY_CONTEXT);
990}
991
992void smp_new_mmu_context_version(void)
993{
994 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
995}
996
997#ifdef CONFIG_KGDB
998void kgdb_roundup_cpus(unsigned long flags)
999{
1000 smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
1001}
1002#endif
1003
1004void smp_fetch_global_regs(void)
1005{
1006 smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1007}
1008
1009void smp_fetch_global_pmu(void)
1010{
1011 if (tlb_type == hypervisor &&
1012 sun4v_chip_type >= SUN4V_CHIP_NIAGARA4)
1013 smp_cross_call(&xcall_fetch_glob_pmu_n4, 0, 0, 0);
1014 else
1015 smp_cross_call(&xcall_fetch_glob_pmu, 0, 0, 0);
1016}
1017
1018/* We know that the window frames of the user have been flushed
1019 * to the stack before we get here because all callers of us
1020 * are flush_tlb_*() routines, and these run after flush_cache_*()
1021 * which performs the flushw.
1022 *
1023 * The SMP TLB coherency scheme we use works as follows:
1024 *
1025 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1026 * space has (potentially) executed on, this is the heuristic
1027 * we use to avoid doing cross calls.
1028 *
1029 * Also, for flushing from kswapd and also for clones, we
1030 * use cpu_vm_mask as the list of cpus to make run the TLB.
1031 *
1032 * 2) TLB context numbers are shared globally across all processors
1033 * in the system, this allows us to play several games to avoid
1034 * cross calls.
1035 *
1036 * One invariant is that when a cpu switches to a process, and
1037 * that processes tsk->active_mm->cpu_vm_mask does not have the
1038 * current cpu's bit set, that tlb context is flushed locally.
1039 *
1040 * If the address space is non-shared (ie. mm->count == 1) we avoid
1041 * cross calls when we want to flush the currently running process's
1042 * tlb state. This is done by clearing all cpu bits except the current
1043 * processor's in current->mm->cpu_vm_mask and performing the
1044 * flush locally only. This will force any subsequent cpus which run
1045 * this task to flush the context from the local tlb if the process
1046 * migrates to another cpu (again).
1047 *
1048 * 3) For shared address spaces (threads) and swapping we bite the
1049 * bullet for most cases and perform the cross call (but only to
1050 * the cpus listed in cpu_vm_mask).
1051 *
1052 * The performance gain from "optimizing" away the cross call for threads is
1053 * questionable (in theory the big win for threads is the massive sharing of
1054 * address space state across processors).
1055 */
1056
1057/* This currently is only used by the hugetlb arch pre-fault
1058 * hook on UltraSPARC-III+ and later when changing the pagesize
1059 * bits of the context register for an address space.
1060 */
1061void smp_flush_tlb_mm(struct mm_struct *mm)
1062{
1063 u32 ctx = CTX_HWBITS(mm->context);
1064 int cpu = get_cpu();
1065
1066 if (atomic_read(&mm->mm_users) == 1) {
1067 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1068 goto local_flush_and_out;
1069 }
1070
1071 smp_cross_call_masked(&xcall_flush_tlb_mm,
1072 ctx, 0, 0,
1073 mm_cpumask(mm));
1074
1075local_flush_and_out:
1076 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1077
1078 put_cpu();
1079}
1080
1081struct tlb_pending_info {
1082 unsigned long ctx;
1083 unsigned long nr;
1084 unsigned long *vaddrs;
1085};
1086
1087static void tlb_pending_func(void *info)
1088{
1089 struct tlb_pending_info *t = info;
1090
1091 __flush_tlb_pending(t->ctx, t->nr, t->vaddrs);
1092}
1093
1094void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1095{
1096 u32 ctx = CTX_HWBITS(mm->context);
1097 struct tlb_pending_info info;
1098 int cpu = get_cpu();
1099
1100 info.ctx = ctx;
1101 info.nr = nr;
1102 info.vaddrs = vaddrs;
1103
1104 if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1105 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1106 else
1107 smp_call_function_many(mm_cpumask(mm), tlb_pending_func,
1108 &info, 1);
1109
1110 __flush_tlb_pending(ctx, nr, vaddrs);
1111
1112 put_cpu();
1113}
1114
1115void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr)
1116{
1117 unsigned long context = CTX_HWBITS(mm->context);
1118 int cpu = get_cpu();
1119
1120 if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1121 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1122 else
1123 smp_cross_call_masked(&xcall_flush_tlb_page,
1124 context, vaddr, 0,
1125 mm_cpumask(mm));
1126 __flush_tlb_page(context, vaddr);
1127
1128 put_cpu();
1129}
1130
1131void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1132{
1133 start &= PAGE_MASK;
1134 end = PAGE_ALIGN(end);
1135 if (start != end) {
1136 smp_cross_call(&xcall_flush_tlb_kernel_range,
1137 0, start, end);
1138
1139 __flush_tlb_kernel_range(start, end);
1140 }
1141}
1142
1143/* CPU capture. */
1144/* #define CAPTURE_DEBUG */
1145extern unsigned long xcall_capture;
1146
1147static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1148static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1149static unsigned long penguins_are_doing_time;
1150
1151void smp_capture(void)
1152{
1153 int result = atomic_add_return(1, &smp_capture_depth);
1154
1155 if (result == 1) {
1156 int ncpus = num_online_cpus();
1157
1158#ifdef CAPTURE_DEBUG
1159 printk("CPU[%d]: Sending penguins to jail...",
1160 smp_processor_id());
1161#endif
1162 penguins_are_doing_time = 1;
1163 atomic_inc(&smp_capture_registry);
1164 smp_cross_call(&xcall_capture, 0, 0, 0);
1165 while (atomic_read(&smp_capture_registry) != ncpus)
1166 rmb();
1167#ifdef CAPTURE_DEBUG
1168 printk("done\n");
1169#endif
1170 }
1171}
1172
1173void smp_release(void)
1174{
1175 if (atomic_dec_and_test(&smp_capture_depth)) {
1176#ifdef CAPTURE_DEBUG
1177 printk("CPU[%d]: Giving pardon to "
1178 "imprisoned penguins\n",
1179 smp_processor_id());
1180#endif
1181 penguins_are_doing_time = 0;
1182 membar_safe("#StoreLoad");
1183 atomic_dec(&smp_capture_registry);
1184 }
1185}
1186
1187/* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
1188 * set, so they can service tlb flush xcalls...
1189 */
1190extern void prom_world(int);
1191
1192void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs)
1193{
1194 clear_softint(1 << irq);
1195
1196 preempt_disable();
1197
1198 __asm__ __volatile__("flushw");
1199 prom_world(1);
1200 atomic_inc(&smp_capture_registry);
1201 membar_safe("#StoreLoad");
1202 while (penguins_are_doing_time)
1203 rmb();
1204 atomic_dec(&smp_capture_registry);
1205 prom_world(0);
1206
1207 preempt_enable();
1208}
1209
1210/* /proc/profile writes can call this, don't __init it please. */
1211int setup_profiling_timer(unsigned int multiplier)
1212{
1213 return -EINVAL;
1214}
1215
1216void __init smp_prepare_cpus(unsigned int max_cpus)
1217{
1218}
1219
1220void smp_prepare_boot_cpu(void)
1221{
1222}
1223
1224void __init smp_setup_processor_id(void)
1225{
1226 if (tlb_type == spitfire)
1227 xcall_deliver_impl = spitfire_xcall_deliver;
1228 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1229 xcall_deliver_impl = cheetah_xcall_deliver;
1230 else
1231 xcall_deliver_impl = hypervisor_xcall_deliver;
1232}
1233
1234void __init smp_fill_in_cpu_possible_map(void)
1235{
1236 int possible_cpus = num_possible_cpus();
1237 int i;
1238
1239 if (possible_cpus > nr_cpu_ids)
1240 possible_cpus = nr_cpu_ids;
1241
1242 for (i = 0; i < possible_cpus; i++)
1243 set_cpu_possible(i, true);
1244 for (; i < NR_CPUS; i++)
1245 set_cpu_possible(i, false);
1246}
1247
1248void smp_fill_in_sib_core_maps(void)
1249{
1250 unsigned int i;
1251
1252 for_each_present_cpu(i) {
1253 unsigned int j;
1254
1255 cpumask_clear(&cpu_core_map[i]);
1256 if (cpu_data(i).core_id == 0) {
1257 cpumask_set_cpu(i, &cpu_core_map[i]);
1258 continue;
1259 }
1260
1261 for_each_present_cpu(j) {
1262 if (cpu_data(i).core_id ==
1263 cpu_data(j).core_id)
1264 cpumask_set_cpu(j, &cpu_core_map[i]);
1265 }
1266 }
1267
1268 for_each_present_cpu(i) {
1269 unsigned int j;
1270
1271 for_each_present_cpu(j) {
1272 if (cpu_data(i).max_cache_id ==
1273 cpu_data(j).max_cache_id)
1274 cpumask_set_cpu(j, &cpu_core_sib_cache_map[i]);
1275
1276 if (cpu_data(i).sock_id == cpu_data(j).sock_id)
1277 cpumask_set_cpu(j, &cpu_core_sib_map[i]);
1278 }
1279 }
1280
1281 for_each_present_cpu(i) {
1282 unsigned int j;
1283
1284 cpumask_clear(&per_cpu(cpu_sibling_map, i));
1285 if (cpu_data(i).proc_id == -1) {
1286 cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i));
1287 continue;
1288 }
1289
1290 for_each_present_cpu(j) {
1291 if (cpu_data(i).proc_id ==
1292 cpu_data(j).proc_id)
1293 cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i));
1294 }
1295 }
1296}
1297
1298int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1299{
1300 int ret = smp_boot_one_cpu(cpu, tidle);
1301
1302 if (!ret) {
1303 cpumask_set_cpu(cpu, &smp_commenced_mask);
1304 while (!cpu_online(cpu))
1305 mb();
1306 if (!cpu_online(cpu)) {
1307 ret = -ENODEV;
1308 } else {
1309 /* On SUN4V, writes to %tick and %stick are
1310 * not allowed.
1311 */
1312 if (tlb_type != hypervisor)
1313 smp_synchronize_one_tick(cpu);
1314 }
1315 }
1316 return ret;
1317}
1318
1319#ifdef CONFIG_HOTPLUG_CPU
1320void cpu_play_dead(void)
1321{
1322 int cpu = smp_processor_id();
1323 unsigned long pstate;
1324
1325 idle_task_exit();
1326
1327 if (tlb_type == hypervisor) {
1328 struct trap_per_cpu *tb = &trap_block[cpu];
1329
1330 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1331 tb->cpu_mondo_pa, 0);
1332 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1333 tb->dev_mondo_pa, 0);
1334 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1335 tb->resum_mondo_pa, 0);
1336 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1337 tb->nonresum_mondo_pa, 0);
1338 }
1339
1340 cpumask_clear_cpu(cpu, &smp_commenced_mask);
1341 membar_safe("#Sync");
1342
1343 local_irq_disable();
1344
1345 __asm__ __volatile__(
1346 "rdpr %%pstate, %0\n\t"
1347 "wrpr %0, %1, %%pstate"
1348 : "=r" (pstate)
1349 : "i" (PSTATE_IE));
1350
1351 while (1)
1352 barrier();
1353}
1354
1355int __cpu_disable(void)
1356{
1357 int cpu = smp_processor_id();
1358 cpuinfo_sparc *c;
1359 int i;
1360
1361 for_each_cpu(i, &cpu_core_map[cpu])
1362 cpumask_clear_cpu(cpu, &cpu_core_map[i]);
1363 cpumask_clear(&cpu_core_map[cpu]);
1364
1365 for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu))
1366 cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i));
1367 cpumask_clear(&per_cpu(cpu_sibling_map, cpu));
1368
1369 c = &cpu_data(cpu);
1370
1371 c->core_id = 0;
1372 c->proc_id = -1;
1373
1374 smp_wmb();
1375
1376 /* Make sure no interrupts point to this cpu. */
1377 fixup_irqs();
1378
1379 local_irq_enable();
1380 mdelay(1);
1381 local_irq_disable();
1382
1383 set_cpu_online(cpu, false);
1384
1385 cpu_map_rebuild();
1386
1387 return 0;
1388}
1389
1390void __cpu_die(unsigned int cpu)
1391{
1392 int i;
1393
1394 for (i = 0; i < 100; i++) {
1395 smp_rmb();
1396 if (!cpumask_test_cpu(cpu, &smp_commenced_mask))
1397 break;
1398 msleep(100);
1399 }
1400 if (cpumask_test_cpu(cpu, &smp_commenced_mask)) {
1401 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1402 } else {
1403#if defined(CONFIG_SUN_LDOMS)
1404 unsigned long hv_err;
1405 int limit = 100;
1406
1407 do {
1408 hv_err = sun4v_cpu_stop(cpu);
1409 if (hv_err == HV_EOK) {
1410 set_cpu_present(cpu, false);
1411 break;
1412 }
1413 } while (--limit > 0);
1414 if (limit <= 0) {
1415 printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1416 hv_err);
1417 }
1418#endif
1419 }
1420}
1421#endif
1422
1423void __init smp_cpus_done(unsigned int max_cpus)
1424{
1425}
1426
1427void smp_send_reschedule(int cpu)
1428{
1429 if (cpu == smp_processor_id()) {
1430 WARN_ON_ONCE(preemptible());
1431 set_softint(1 << PIL_SMP_RECEIVE_SIGNAL);
1432 } else {
1433 xcall_deliver((u64) &xcall_receive_signal,
1434 0, 0, cpumask_of(cpu));
1435 }
1436}
1437
1438void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs)
1439{
1440 clear_softint(1 << irq);
1441 scheduler_ipi();
1442}
1443
1444static void stop_this_cpu(void *dummy)
1445{
1446 prom_stopself();
1447}
1448
1449void smp_send_stop(void)
1450{
1451 int cpu;
1452
1453 if (tlb_type == hypervisor) {
1454 for_each_online_cpu(cpu) {
1455 if (cpu == smp_processor_id())
1456 continue;
1457#ifdef CONFIG_SUN_LDOMS
1458 if (ldom_domaining_enabled) {
1459 unsigned long hv_err;
1460 hv_err = sun4v_cpu_stop(cpu);
1461 if (hv_err)
1462 printk(KERN_ERR "sun4v_cpu_stop() "
1463 "failed err=%lu\n", hv_err);
1464 } else
1465#endif
1466 prom_stopcpu_cpuid(cpu);
1467 }
1468 } else
1469 smp_call_function(stop_this_cpu, NULL, 0);
1470}
1471
1472/**
1473 * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu
1474 * @cpu: cpu to allocate for
1475 * @size: size allocation in bytes
1476 * @align: alignment
1477 *
1478 * Allocate @size bytes aligned at @align for cpu @cpu. This wrapper
1479 * does the right thing for NUMA regardless of the current
1480 * configuration.
1481 *
1482 * RETURNS:
1483 * Pointer to the allocated area on success, NULL on failure.
1484 */
1485static void * __init pcpu_alloc_bootmem(unsigned int cpu, size_t size,
1486 size_t align)
1487{
1488 const unsigned long goal = __pa(MAX_DMA_ADDRESS);
1489#ifdef CONFIG_NEED_MULTIPLE_NODES
1490 int node = cpu_to_node(cpu);
1491 void *ptr;
1492
1493 if (!node_online(node) || !NODE_DATA(node)) {
1494 ptr = __alloc_bootmem(size, align, goal);
1495 pr_info("cpu %d has no node %d or node-local memory\n",
1496 cpu, node);
1497 pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n",
1498 cpu, size, __pa(ptr));
1499 } else {
1500 ptr = __alloc_bootmem_node(NODE_DATA(node),
1501 size, align, goal);
1502 pr_debug("per cpu data for cpu%d %lu bytes on node%d at "
1503 "%016lx\n", cpu, size, node, __pa(ptr));
1504 }
1505 return ptr;
1506#else
1507 return __alloc_bootmem(size, align, goal);
1508#endif
1509}
1510
1511static void __init pcpu_free_bootmem(void *ptr, size_t size)
1512{
1513 free_bootmem(__pa(ptr), size);
1514}
1515
1516static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
1517{
1518 if (cpu_to_node(from) == cpu_to_node(to))
1519 return LOCAL_DISTANCE;
1520 else
1521 return REMOTE_DISTANCE;
1522}
1523
1524static void __init pcpu_populate_pte(unsigned long addr)
1525{
1526 pgd_t *pgd = pgd_offset_k(addr);
1527 pud_t *pud;
1528 pmd_t *pmd;
1529
1530 if (pgd_none(*pgd)) {
1531 pud_t *new;
1532
1533 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1534 pgd_populate(&init_mm, pgd, new);
1535 }
1536
1537 pud = pud_offset(pgd, addr);
1538 if (pud_none(*pud)) {
1539 pmd_t *new;
1540
1541 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1542 pud_populate(&init_mm, pud, new);
1543 }
1544
1545 pmd = pmd_offset(pud, addr);
1546 if (!pmd_present(*pmd)) {
1547 pte_t *new;
1548
1549 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1550 pmd_populate_kernel(&init_mm, pmd, new);
1551 }
1552}
1553
1554void __init setup_per_cpu_areas(void)
1555{
1556 unsigned long delta;
1557 unsigned int cpu;
1558 int rc = -EINVAL;
1559
1560 if (pcpu_chosen_fc != PCPU_FC_PAGE) {
1561 rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
1562 PERCPU_DYNAMIC_RESERVE, 4 << 20,
1563 pcpu_cpu_distance,
1564 pcpu_alloc_bootmem,
1565 pcpu_free_bootmem);
1566 if (rc)
1567 pr_warning("PERCPU: %s allocator failed (%d), "
1568 "falling back to page size\n",
1569 pcpu_fc_names[pcpu_chosen_fc], rc);
1570 }
1571 if (rc < 0)
1572 rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE,
1573 pcpu_alloc_bootmem,
1574 pcpu_free_bootmem,
1575 pcpu_populate_pte);
1576 if (rc < 0)
1577 panic("cannot initialize percpu area (err=%d)", rc);
1578
1579 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
1580 for_each_possible_cpu(cpu)
1581 __per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu];
1582
1583 /* Setup %g5 for the boot cpu. */
1584 __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1585
1586 of_fill_in_cpu_data();
1587 if (tlb_type == hypervisor)
1588 mdesc_fill_in_cpu_data(cpu_all_mask);
1589}