1/*
  2 *  linux/arch/arm/mach-integrator/integrator_ap.c
  3 *
  4 *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
  5 *
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License as published by
  8 * the Free Software Foundation; either version 2 of the License, or
  9 * (at your option) any later version.
 10 *
 11 * This program is distributed in the hope that it will be useful,
 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14 * GNU General Public License for more details.
 15 *
 16 * You should have received a copy of the GNU General Public License
 17 * along with this program; if not, write to the Free Software
 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 19 */
 20#include <linux/kernel.h>
 21#include <linux/init.h>
 22#include <linux/syscore_ops.h>
 23#include <linux/amba/bus.h>
 24#include <linux/io.h>
 25#include <linux/irqchip.h>
 26#include <linux/of_irq.h>
 27#include <linux/of_address.h>
 28#include <linux/of_platform.h>
 29#include <linux/termios.h>
 30#include <linux/mfd/syscon.h>
 31#include <linux/regmap.h>
 32
 33#include <asm/mach/arch.h>
 34#include <asm/mach/map.h>
 35
 36#include "hardware.h"
 37#include "cm.h"
 38#include "common.h"
 39#include "pci_v3.h"
 40#include "lm.h"
 41
 42/* Regmap to the AP system controller */
 43static struct regmap *ap_syscon_map;
 44
 45/*
 46 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
 47 * is the (PA >> 12).
 48 *
 49 * Setup a VA for the Integrator interrupt controller (for header #0,
 50 * just for now).
 51 */
 52#define VA_IC_BASE	__io_address(INTEGRATOR_IC_BASE)
 53
 54/*
 55 * Logical      Physical
 56 * f1400000	14000000	Interrupt controller
 57 * f1600000	16000000	UART 0
 58 */
 59
 60static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
 61	{
 62		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
 63		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
 64		.length		= SZ_4K,
 65		.type		= MT_DEVICE
 66	}, {
 67		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
 68		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
 69		.length		= SZ_4K,
 70		.type		= MT_DEVICE
 71	}
 72};
 73
 74static void __init ap_map_io(void)
 75{
 76	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
 77	pci_v3_early_init();
 78}
 79
 80#ifdef CONFIG_PM
 81static unsigned long ic_irq_enable;
 82
 83static int irq_suspend(void)
 84{
 85	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
 86	return 0;
 87}
 88
 89static void irq_resume(void)
 90{
 91	/* disable all irq sources */
 92	cm_clear_irqs();
 93	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 94	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 95
 96	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
 97}
 98#else
 99#define irq_suspend NULL
100#define irq_resume NULL
101#endif
102
103static struct syscore_ops irq_syscore_ops = {
104	.suspend	= irq_suspend,
105	.resume		= irq_resume,
106};
107
108static int __init irq_syscore_init(void)
109{
110	register_syscore_ops(&irq_syscore_ops);
111
112	return 0;
113}
114
115device_initcall(irq_syscore_init);
116
117/*
118 * For the PL010 found in the Integrator/AP some of the UART control is
119 * implemented in the system controller and accessed using a callback
120 * from the driver.
121 */
122static void integrator_uart_set_mctrl(struct amba_device *dev,
123				void __iomem *base, unsigned int mctrl)
124{
125	unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
126	u32 phybase = dev->res.start;
127	int ret;
128
129	if (phybase == INTEGRATOR_UART0_BASE) {
130		/* UART0 */
131		rts_mask = 1 << 4;
132		dtr_mask = 1 << 5;
133	} else {
134		/* UART1 */
135		rts_mask = 1 << 6;
136		dtr_mask = 1 << 7;
137	}
138
139	if (mctrl & TIOCM_RTS)
140		ctrlc |= rts_mask;
141	else
142		ctrls |= rts_mask;
143
144	if (mctrl & TIOCM_DTR)
145		ctrlc |= dtr_mask;
146	else
147		ctrls |= dtr_mask;
148
149	ret = regmap_write(ap_syscon_map,
150			   INTEGRATOR_SC_CTRLS_OFFSET,
151			   ctrls);
152	if (ret)
153		pr_err("MODEM: unable to write PL010 UART CTRLS\n");
154
155	ret = regmap_write(ap_syscon_map,
156			   INTEGRATOR_SC_CTRLC_OFFSET,
157			   ctrlc);
158	if (ret)
159		pr_err("MODEM: unable to write PL010 UART CRTLC\n");
160}
161
162struct amba_pl010_data ap_uart_data = {
163	.set_mctrl = integrator_uart_set_mctrl,
164};
165
166void __init ap_init_early(void)
167{
168}
169
170static void __init ap_init_irq_of(void)
171{
172	cm_init();
173	irqchip_init();
174}
175
176/* For the Device Tree, add in the UART callbacks as AUXDATA */
177static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
178	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
179		"uart0", &ap_uart_data),
180	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
181		"uart1", &ap_uart_data),
182	{ /* sentinel */ },
183};
184
185static const struct of_device_id ap_syscon_match[] = {
186	{ .compatible = "arm,integrator-ap-syscon"},
187	{ },
188};
189
190static void __init ap_init_of(void)
191{
192	u32 sc_dec;
193	struct device_node *syscon;
194	int ret;
195	int i;
196
197	of_platform_default_populate(NULL, ap_auxdata_lookup, NULL);
198
199	syscon = of_find_matching_node(NULL, ap_syscon_match);
200	if (!syscon)
201		return;
202	ap_syscon_map = syscon_node_to_regmap(syscon);
203	if (IS_ERR(ap_syscon_map)) {
204		pr_crit("could not find Integrator/AP system controller\n");
205		return;
206	}
207
208	ret = regmap_read(ap_syscon_map,
209			  INTEGRATOR_SC_DEC_OFFSET,
210			  &sc_dec);
211	if (ret) {
212		pr_crit("could not read from Integrator/AP syscon\n");
213		return;
214	}
215
216	for (i = 0; i < 4; i++) {
217		struct lm_device *lmdev;
218
219		if ((sc_dec & (16 << i)) == 0)
220			continue;
221
222		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
223		if (!lmdev)
224			continue;
225
226		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
227		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
228		lmdev->resource.flags = IORESOURCE_MEM;
229		lmdev->irq = irq_of_parse_and_map(syscon, i);
230		lmdev->id = i;
231
232		lm_device_register(lmdev);
233	}
234}
235
236static const char * ap_dt_board_compat[] = {
237	"arm,integrator-ap",
238	NULL,
239};
240
241DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
242	.reserve	= integrator_reserve,
243	.map_io		= ap_map_io,
244	.init_early	= ap_init_early,
245	.init_irq	= ap_init_irq_of,
246	.init_machine	= ap_init_of,
247	.dt_compat      = ap_dt_board_compat,
248MACHINE_END