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1/*
2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "sunxi-h3-h5.dtsi"
44#include <dt-bindings/thermal/thermal.h>
45
46/ {
47 cpu0_opp_table: opp-table-cpu {
48 compatible = "operating-points-v2";
49 opp-shared;
50
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
55 };
56
57 opp-816000000 {
58 opp-hz = /bits/ 64 <816000000>;
59 opp-microvolt = <1100000 1100000 1300000>;
60 clock-latency-ns = <244144>; /* 8 32k periods */
61 };
62
63 opp-1008000000 {
64 opp-hz = /bits/ 64 <1008000000>;
65 opp-microvolt = <1200000 1200000 1300000>;
66 clock-latency-ns = <244144>; /* 8 32k periods */
67 };
68 };
69
70 cpus {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 cpu0: cpu@0 {
75 compatible = "arm,cortex-a7";
76 device_type = "cpu";
77 reg = <0>;
78 clocks = <&ccu CLK_CPUX>;
79 clock-names = "cpu";
80 operating-points-v2 = <&cpu0_opp_table>;
81 #cooling-cells = <2>;
82 };
83
84 cpu1: cpu@1 {
85 compatible = "arm,cortex-a7";
86 device_type = "cpu";
87 reg = <1>;
88 clocks = <&ccu CLK_CPUX>;
89 clock-names = "cpu";
90 operating-points-v2 = <&cpu0_opp_table>;
91 #cooling-cells = <2>;
92 };
93
94 cpu2: cpu@2 {
95 compatible = "arm,cortex-a7";
96 device_type = "cpu";
97 reg = <2>;
98 clocks = <&ccu CLK_CPUX>;
99 clock-names = "cpu";
100 operating-points-v2 = <&cpu0_opp_table>;
101 #cooling-cells = <2>;
102 };
103
104 cpu3: cpu@3 {
105 compatible = "arm,cortex-a7";
106 device_type = "cpu";
107 reg = <3>;
108 clocks = <&ccu CLK_CPUX>;
109 clock-names = "cpu";
110 operating-points-v2 = <&cpu0_opp_table>;
111 #cooling-cells = <2>;
112 };
113 };
114
115 gpu_opp_table: opp-table-gpu {
116 compatible = "operating-points-v2";
117
118 opp-120000000 {
119 opp-hz = /bits/ 64 <120000000>;
120 };
121
122 opp-312000000 {
123 opp-hz = /bits/ 64 <312000000>;
124 };
125
126 opp-432000000 {
127 opp-hz = /bits/ 64 <432000000>;
128 };
129
130 opp-576000000 {
131 opp-hz = /bits/ 64 <576000000>;
132 };
133 };
134
135 pmu {
136 compatible = "arm,cortex-a7-pmu";
137 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
141 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
142 };
143
144 timer {
145 compatible = "arm,armv7-timer";
146 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
147 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
148 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
149 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
150 };
151
152 soc {
153 deinterlace: deinterlace@1400000 {
154 compatible = "allwinner,sun8i-h3-deinterlace";
155 reg = <0x01400000 0x20000>;
156 clocks = <&ccu CLK_BUS_DEINTERLACE>,
157 <&ccu CLK_DEINTERLACE>,
158 <&ccu CLK_DRAM_DEINTERLACE>;
159 clock-names = "bus", "mod", "ram";
160 resets = <&ccu RST_BUS_DEINTERLACE>;
161 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
162 interconnects = <&mbus 9>;
163 interconnect-names = "dma-mem";
164 };
165
166 syscon: system-control@1c00000 {
167 compatible = "allwinner,sun8i-h3-system-control";
168 reg = <0x01c00000 0x1000>;
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges;
172
173 sram_c: sram@1d00000 {
174 compatible = "mmio-sram";
175 reg = <0x01d00000 0x80000>;
176 #address-cells = <1>;
177 #size-cells = <1>;
178 ranges = <0 0x01d00000 0x80000>;
179
180 ve_sram: sram-section@0 {
181 compatible = "allwinner,sun8i-h3-sram-c1",
182 "allwinner,sun4i-a10-sram-c1";
183 reg = <0x000000 0x80000>;
184 };
185 };
186 };
187
188 video-codec@1c0e000 {
189 compatible = "allwinner,sun8i-h3-video-engine";
190 reg = <0x01c0e000 0x1000>;
191 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
192 <&ccu CLK_DRAM_VE>;
193 clock-names = "ahb", "mod", "ram";
194 resets = <&ccu RST_BUS_VE>;
195 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
196 allwinner,sram = <&ve_sram 1>;
197 };
198
199 crypto: crypto@1c15000 {
200 compatible = "allwinner,sun8i-h3-crypto";
201 reg = <0x01c15000 0x1000>;
202 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
204 clock-names = "bus", "mod";
205 resets = <&ccu RST_BUS_CE>;
206 };
207
208 mali: gpu@1c40000 {
209 compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
210 reg = <0x01c40000 0x10000>;
211 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
218 interrupt-names = "gp",
219 "gpmmu",
220 "pp0",
221 "ppmmu0",
222 "pp1",
223 "ppmmu1",
224 "pmu";
225 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
226 clock-names = "bus", "core";
227 resets = <&ccu RST_BUS_GPU>;
228 operating-points-v2 = <&gpu_opp_table>;
229 };
230
231 ths: thermal-sensor@1c25000 {
232 compatible = "allwinner,sun8i-h3-ths";
233 reg = <0x01c25000 0x400>;
234 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
235 resets = <&ccu RST_BUS_THS>;
236 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
237 clock-names = "bus", "mod";
238 nvmem-cells = <&ths_calibration>;
239 nvmem-cell-names = "calibration";
240 #thermal-sensor-cells = <0>;
241 };
242 };
243
244 thermal-zones {
245 cpu_thermal: cpu-thermal {
246 polling-delay-passive = <0>;
247 polling-delay = <0>;
248 thermal-sensors = <&ths>;
249
250 trips {
251 cpu_hot_trip: cpu-hot {
252 temperature = <80000>;
253 hysteresis = <2000>;
254 type = "passive";
255 };
256
257 cpu_very_hot_trip: cpu-very-hot {
258 temperature = <100000>;
259 hysteresis = <0>;
260 type = "critical";
261 };
262 };
263
264 cooling-maps {
265 cpu-hot-limit {
266 trip = <&cpu_hot_trip>;
267 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
268 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
269 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
270 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
271 };
272 };
273 };
274 };
275};
276
277&ccu {
278 compatible = "allwinner,sun8i-h3-ccu";
279};
280
281&display_clocks {
282 compatible = "allwinner,sun8i-h3-de2-clk";
283};
284
285&mbus {
286 compatible = "allwinner,sun8i-h3-mbus";
287};
288
289&mmc0 {
290 compatible = "allwinner,sun7i-a20-mmc";
291 clocks = <&ccu CLK_BUS_MMC0>,
292 <&ccu CLK_MMC0>,
293 <&ccu CLK_MMC0_OUTPUT>,
294 <&ccu CLK_MMC0_SAMPLE>;
295 clock-names = "ahb",
296 "mmc",
297 "output",
298 "sample";
299};
300
301&mmc1 {
302 compatible = "allwinner,sun7i-a20-mmc";
303 clocks = <&ccu CLK_BUS_MMC1>,
304 <&ccu CLK_MMC1>,
305 <&ccu CLK_MMC1_OUTPUT>,
306 <&ccu CLK_MMC1_SAMPLE>;
307 clock-names = "ahb",
308 "mmc",
309 "output",
310 "sample";
311};
312
313&mmc2 {
314 compatible = "allwinner,sun7i-a20-mmc";
315 clocks = <&ccu CLK_BUS_MMC2>,
316 <&ccu CLK_MMC2>,
317 <&ccu CLK_MMC2_OUTPUT>,
318 <&ccu CLK_MMC2_SAMPLE>;
319 clock-names = "ahb",
320 "mmc",
321 "output",
322 "sample";
323};
324
325&pio {
326 compatible = "allwinner,sun8i-h3-pinctrl";
327};
328
329&rtc {
330 compatible = "allwinner,sun8i-h3-rtc";
331};
332
333&sid {
334 compatible = "allwinner,sun8i-h3-sid";
335};
1/*
2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "skeleton.dtsi"
44
45#include <dt-bindings/clock/sun8i-h3-ccu.h>
46#include <dt-bindings/interrupt-controller/arm-gic.h>
47#include <dt-bindings/pinctrl/sun4i-a10.h>
48#include <dt-bindings/reset/sun8i-h3-ccu.h>
49
50/ {
51 interrupt-parent = <&gic>;
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 cpu@0 {
58 compatible = "arm,cortex-a7";
59 device_type = "cpu";
60 reg = <0>;
61 };
62
63 cpu@1 {
64 compatible = "arm,cortex-a7";
65 device_type = "cpu";
66 reg = <1>;
67 };
68
69 cpu@2 {
70 compatible = "arm,cortex-a7";
71 device_type = "cpu";
72 reg = <2>;
73 };
74
75 cpu@3 {
76 compatible = "arm,cortex-a7";
77 device_type = "cpu";
78 reg = <3>;
79 };
80 };
81
82 timer {
83 compatible = "arm,armv7-timer";
84 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
85 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
86 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
87 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
88 };
89
90 clocks {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 ranges;
94
95 osc24M: osc24M_clk {
96 #clock-cells = <0>;
97 compatible = "fixed-clock";
98 clock-frequency = <24000000>;
99 clock-output-names = "osc24M";
100 };
101
102 osc32k: osc32k_clk {
103 #clock-cells = <0>;
104 compatible = "fixed-clock";
105 clock-frequency = <32768>;
106 clock-output-names = "osc32k";
107 };
108
109 apb0: apb0_clk {
110 compatible = "fixed-factor-clock";
111 #clock-cells = <0>;
112 clock-div = <1>;
113 clock-mult = <1>;
114 clocks = <&osc24M>;
115 clock-output-names = "apb0";
116 };
117
118 apb0_gates: clk@01f01428 {
119 compatible = "allwinner,sun8i-h3-apb0-gates-clk",
120 "allwinner,sun4i-a10-gates-clk";
121 reg = <0x01f01428 0x4>;
122 #clock-cells = <1>;
123 clocks = <&apb0>;
124 clock-indices = <0>, <1>;
125 clock-output-names = "apb0_pio", "apb0_ir";
126 };
127
128 ir_clk: ir_clk@01f01454 {
129 compatible = "allwinner,sun4i-a10-mod0-clk";
130 reg = <0x01f01454 0x4>;
131 #clock-cells = <0>;
132 clocks = <&osc32k>, <&osc24M>;
133 clock-output-names = "ir";
134 };
135 };
136
137 soc {
138 compatible = "simple-bus";
139 #address-cells = <1>;
140 #size-cells = <1>;
141 ranges;
142
143 dma: dma-controller@01c02000 {
144 compatible = "allwinner,sun8i-h3-dma";
145 reg = <0x01c02000 0x1000>;
146 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&ccu CLK_BUS_DMA>;
148 resets = <&ccu RST_BUS_DMA>;
149 #dma-cells = <1>;
150 };
151
152 mmc0: mmc@01c0f000 {
153 compatible = "allwinner,sun7i-a20-mmc";
154 reg = <0x01c0f000 0x1000>;
155 clocks = <&ccu CLK_BUS_MMC0>,
156 <&ccu CLK_MMC0>,
157 <&ccu CLK_MMC0_OUTPUT>,
158 <&ccu CLK_MMC0_SAMPLE>;
159 clock-names = "ahb",
160 "mmc",
161 "output",
162 "sample";
163 resets = <&ccu RST_BUS_MMC0>;
164 reset-names = "ahb";
165 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
166 status = "disabled";
167 #address-cells = <1>;
168 #size-cells = <0>;
169 };
170
171 mmc1: mmc@01c10000 {
172 compatible = "allwinner,sun7i-a20-mmc";
173 reg = <0x01c10000 0x1000>;
174 clocks = <&ccu CLK_BUS_MMC1>,
175 <&ccu CLK_MMC1>,
176 <&ccu CLK_MMC1_OUTPUT>,
177 <&ccu CLK_MMC1_SAMPLE>;
178 clock-names = "ahb",
179 "mmc",
180 "output",
181 "sample";
182 resets = <&ccu RST_BUS_MMC1>;
183 reset-names = "ahb";
184 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
185 status = "disabled";
186 #address-cells = <1>;
187 #size-cells = <0>;
188 };
189
190 mmc2: mmc@01c11000 {
191 compatible = "allwinner,sun7i-a20-mmc";
192 reg = <0x01c11000 0x1000>;
193 clocks = <&ccu CLK_BUS_MMC2>,
194 <&ccu CLK_MMC2>,
195 <&ccu CLK_MMC2_OUTPUT>,
196 <&ccu CLK_MMC2_SAMPLE>;
197 clock-names = "ahb",
198 "mmc",
199 "output",
200 "sample";
201 resets = <&ccu RST_BUS_MMC2>;
202 reset-names = "ahb";
203 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
204 status = "disabled";
205 #address-cells = <1>;
206 #size-cells = <0>;
207 };
208
209 usbphy: phy@01c19400 {
210 compatible = "allwinner,sun8i-h3-usb-phy";
211 reg = <0x01c19400 0x2c>,
212 <0x01c1a800 0x4>,
213 <0x01c1b800 0x4>,
214 <0x01c1c800 0x4>,
215 <0x01c1d800 0x4>;
216 reg-names = "phy_ctrl",
217 "pmu0",
218 "pmu1",
219 "pmu2",
220 "pmu3";
221 clocks = <&ccu CLK_USB_PHY0>,
222 <&ccu CLK_USB_PHY1>,
223 <&ccu CLK_USB_PHY2>,
224 <&ccu CLK_USB_PHY3>;
225 clock-names = "usb0_phy",
226 "usb1_phy",
227 "usb2_phy",
228 "usb3_phy";
229 resets = <&ccu RST_USB_PHY0>,
230 <&ccu RST_USB_PHY1>,
231 <&ccu RST_USB_PHY2>,
232 <&ccu RST_USB_PHY3>;
233 reset-names = "usb0_reset",
234 "usb1_reset",
235 "usb2_reset",
236 "usb3_reset";
237 status = "disabled";
238 #phy-cells = <1>;
239 };
240
241 ehci1: usb@01c1b000 {
242 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
243 reg = <0x01c1b000 0x100>;
244 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
246 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
247 phys = <&usbphy 1>;
248 phy-names = "usb";
249 status = "disabled";
250 };
251
252 ohci1: usb@01c1b400 {
253 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
254 reg = <0x01c1b400 0x100>;
255 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
257 <&ccu CLK_USB_OHCI1>;
258 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
259 phys = <&usbphy 1>;
260 phy-names = "usb";
261 status = "disabled";
262 };
263
264 ehci2: usb@01c1c000 {
265 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
266 reg = <0x01c1c000 0x100>;
267 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
269 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
270 phys = <&usbphy 2>;
271 phy-names = "usb";
272 status = "disabled";
273 };
274
275 ohci2: usb@01c1c400 {
276 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
277 reg = <0x01c1c400 0x100>;
278 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
280 <&ccu CLK_USB_OHCI2>;
281 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
282 phys = <&usbphy 2>;
283 phy-names = "usb";
284 status = "disabled";
285 };
286
287 ehci3: usb@01c1d000 {
288 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
289 reg = <0x01c1d000 0x100>;
290 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
292 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
293 phys = <&usbphy 3>;
294 phy-names = "usb";
295 status = "disabled";
296 };
297
298 ohci3: usb@01c1d400 {
299 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
300 reg = <0x01c1d400 0x100>;
301 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
303 <&ccu CLK_USB_OHCI3>;
304 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
305 phys = <&usbphy 3>;
306 phy-names = "usb";
307 status = "disabled";
308 };
309
310 ccu: clock@01c20000 {
311 compatible = "allwinner,sun8i-h3-ccu";
312 reg = <0x01c20000 0x400>;
313 clocks = <&osc24M>, <&osc32k>;
314 clock-names = "hosc", "losc";
315 #clock-cells = <1>;
316 #reset-cells = <1>;
317 };
318
319 pio: pinctrl@01c20800 {
320 compatible = "allwinner,sun8i-h3-pinctrl";
321 reg = <0x01c20800 0x400>;
322 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
325 clock-names = "apb", "hosc", "losc";
326 gpio-controller;
327 #gpio-cells = <3>;
328 interrupt-controller;
329 #interrupt-cells = <3>;
330
331 i2c0_pins: i2c0 {
332 allwinner,pins = "PA11", "PA12";
333 allwinner,function = "i2c0";
334 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
335 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
336 };
337
338 i2c1_pins: i2c1 {
339 allwinner,pins = "PA18", "PA19";
340 allwinner,function = "i2c1";
341 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
342 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
343 };
344
345 i2c2_pins: i2c2 {
346 allwinner,pins = "PE12", "PE13";
347 allwinner,function = "i2c2";
348 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
349 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
350 };
351
352 mmc0_pins_a: mmc0@0 {
353 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
354 "PF4", "PF5";
355 allwinner,function = "mmc0";
356 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
357 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
358 };
359
360 mmc0_cd_pin: mmc0_cd_pin@0 {
361 allwinner,pins = "PF6";
362 allwinner,function = "gpio_in";
363 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
364 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
365 };
366
367 mmc1_pins_a: mmc1@0 {
368 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
369 "PG4", "PG5";
370 allwinner,function = "mmc1";
371 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
372 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
373 };
374
375 mmc2_8bit_pins: mmc2_8bit {
376 allwinner,pins = "PC5", "PC6", "PC8",
377 "PC9", "PC10", "PC11",
378 "PC12", "PC13", "PC14",
379 "PC15", "PC16";
380 allwinner,function = "mmc2";
381 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
382 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
383 };
384
385 spi0_pins: spi0 {
386 allwinner,pins = "PC0", "PC1", "PC2", "PC3";
387 allwinner,function = "spi0";
388 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
389 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
390 };
391
392 spi1_pins: spi1 {
393 allwinner,pins = "PA15", "PA16", "PA14", "PA13";
394 allwinner,function = "spi1";
395 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
396 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
397 };
398
399 uart0_pins_a: uart0@0 {
400 allwinner,pins = "PA4", "PA5";
401 allwinner,function = "uart0";
402 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
403 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
404 };
405
406 uart1_pins: uart1 {
407 allwinner,pins = "PG6", "PG7";
408 allwinner,function = "uart1";
409 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
410 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
411 };
412
413 uart1_rts_cts_pins: uart1_rts_cts {
414 allwinner,pins = "PG8", "PG9";
415 allwinner,function = "uart1";
416 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
417 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
418 };
419
420 uart2_pins: uart2 {
421 allwinner,pins = "PA0", "PA1";
422 allwinner,function = "uart2";
423 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
424 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
425 };
426
427 uart3_pins: uart3 {
428 allwinner,pins = "PA13", "PA14";
429 allwinner,function = "uart3";
430 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
431 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
432 };
433 };
434
435 timer@01c20c00 {
436 compatible = "allwinner,sun4i-a10-timer";
437 reg = <0x01c20c00 0xa0>;
438 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&osc24M>;
441 };
442
443 spi0: spi@01c68000 {
444 compatible = "allwinner,sun8i-h3-spi";
445 reg = <0x01c68000 0x1000>;
446 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
448 clock-names = "ahb", "mod";
449 dmas = <&dma 23>, <&dma 23>;
450 dma-names = "rx", "tx";
451 pinctrl-names = "default";
452 pinctrl-0 = <&spi0_pins>;
453 resets = <&ccu RST_BUS_SPI0>;
454 status = "disabled";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 };
458
459 spi1: spi@01c69000 {
460 compatible = "allwinner,sun8i-h3-spi";
461 reg = <0x01c69000 0x1000>;
462 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
464 clock-names = "ahb", "mod";
465 dmas = <&dma 24>, <&dma 24>;
466 dma-names = "rx", "tx";
467 pinctrl-names = "default";
468 pinctrl-0 = <&spi1_pins>;
469 resets = <&ccu RST_BUS_SPI1>;
470 status = "disabled";
471 #address-cells = <1>;
472 #size-cells = <0>;
473 };
474
475 wdt0: watchdog@01c20ca0 {
476 compatible = "allwinner,sun6i-a31-wdt";
477 reg = <0x01c20ca0 0x20>;
478 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
479 };
480
481 pwm: pwm@01c21400 {
482 compatible = "allwinner,sun8i-h3-pwm";
483 reg = <0x01c21400 0x8>;
484 clocks = <&osc24M>;
485 #pwm-cells = <3>;
486 status = "disabled";
487 };
488
489 uart0: serial@01c28000 {
490 compatible = "snps,dw-apb-uart";
491 reg = <0x01c28000 0x400>;
492 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
493 reg-shift = <2>;
494 reg-io-width = <4>;
495 clocks = <&ccu CLK_BUS_UART0>;
496 resets = <&ccu RST_BUS_UART0>;
497 dmas = <&dma 6>, <&dma 6>;
498 dma-names = "rx", "tx";
499 status = "disabled";
500 };
501
502 uart1: serial@01c28400 {
503 compatible = "snps,dw-apb-uart";
504 reg = <0x01c28400 0x400>;
505 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
506 reg-shift = <2>;
507 reg-io-width = <4>;
508 clocks = <&ccu CLK_BUS_UART1>;
509 resets = <&ccu RST_BUS_UART1>;
510 dmas = <&dma 7>, <&dma 7>;
511 dma-names = "rx", "tx";
512 status = "disabled";
513 };
514
515 uart2: serial@01c28800 {
516 compatible = "snps,dw-apb-uart";
517 reg = <0x01c28800 0x400>;
518 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
519 reg-shift = <2>;
520 reg-io-width = <4>;
521 clocks = <&ccu CLK_BUS_UART2>;
522 resets = <&ccu RST_BUS_UART2>;
523 dmas = <&dma 8>, <&dma 8>;
524 dma-names = "rx", "tx";
525 status = "disabled";
526 };
527
528 uart3: serial@01c28c00 {
529 compatible = "snps,dw-apb-uart";
530 reg = <0x01c28c00 0x400>;
531 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
532 reg-shift = <2>;
533 reg-io-width = <4>;
534 clocks = <&ccu CLK_BUS_UART3>;
535 resets = <&ccu RST_BUS_UART3>;
536 dmas = <&dma 9>, <&dma 9>;
537 dma-names = "rx", "tx";
538 status = "disabled";
539 };
540
541 i2c0: i2c@01c2ac00 {
542 compatible = "allwinner,sun6i-a31-i2c";
543 reg = <0x01c2ac00 0x400>;
544 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&ccu CLK_BUS_I2C0>;
546 resets = <&ccu RST_BUS_I2C0>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&i2c0_pins>;
549 status = "disabled";
550 #address-cells = <1>;
551 #size-cells = <0>;
552 };
553
554 i2c1: i2c@01c2b000 {
555 compatible = "allwinner,sun6i-a31-i2c";
556 reg = <0x01c2b000 0x400>;
557 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&ccu CLK_BUS_I2C1>;
559 resets = <&ccu RST_BUS_I2C1>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&i2c1_pins>;
562 status = "disabled";
563 #address-cells = <1>;
564 #size-cells = <0>;
565 };
566
567 i2c2: i2c@01c2b400 {
568 compatible = "allwinner,sun6i-a31-i2c";
569 reg = <0x01c2b000 0x400>;
570 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&ccu CLK_BUS_I2C2>;
572 resets = <&ccu RST_BUS_I2C2>;
573 pinctrl-names = "default";
574 pinctrl-0 = <&i2c2_pins>;
575 status = "disabled";
576 #address-cells = <1>;
577 #size-cells = <0>;
578 };
579
580 gic: interrupt-controller@01c81000 {
581 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
582 reg = <0x01c81000 0x1000>,
583 <0x01c82000 0x1000>,
584 <0x01c84000 0x2000>,
585 <0x01c86000 0x2000>;
586 interrupt-controller;
587 #interrupt-cells = <3>;
588 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
589 };
590
591 rtc: rtc@01f00000 {
592 compatible = "allwinner,sun6i-a31-rtc";
593 reg = <0x01f00000 0x54>;
594 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
596 };
597
598 apb0_reset: reset@01f014b0 {
599 reg = <0x01f014b0 0x4>;
600 compatible = "allwinner,sun6i-a31-clock-reset";
601 #reset-cells = <1>;
602 };
603
604 ir: ir@01f02000 {
605 compatible = "allwinner,sun5i-a13-ir";
606 clocks = <&apb0_gates 1>, <&ir_clk>;
607 clock-names = "apb", "ir";
608 resets = <&apb0_reset 1>;
609 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
610 reg = <0x01f02000 0x40>;
611 status = "disabled";
612 };
613
614 r_pio: pinctrl@01f02c00 {
615 compatible = "allwinner,sun8i-h3-r-pinctrl";
616 reg = <0x01f02c00 0x400>;
617 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
619 clock-names = "apb", "hosc", "losc";
620 resets = <&apb0_reset 0>;
621 gpio-controller;
622 #gpio-cells = <3>;
623 interrupt-controller;
624 #interrupt-cells = <3>;
625
626 ir_pins_a: ir@0 {
627 allwinner,pins = "PL11";
628 allwinner,function = "s_cir_rx";
629 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
630 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
631 };
632 };
633 };
634};