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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 STMicroelectronics Limited.
4 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
5 */
6#include "stih407-pinctrl.dtsi"
7#include <dt-bindings/mfd/st-lpc.h>
8#include <dt-bindings/phy/phy.h>
9#include <dt-bindings/reset/stih407-resets.h>
10#include <dt-bindings/interrupt-controller/irq-st.h>
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 reserved-memory {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges;
19
20 gp0_reserved: rproc@45000000 {
21 compatible = "shared-dma-pool";
22 reg = <0x45000000 0x00400000>;
23 no-map;
24 };
25
26 delta_reserved: rproc@44000000 {
27 compatible = "shared-dma-pool";
28 reg = <0x44000000 0x01000000>;
29 no-map;
30 };
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36 cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <0>;
40
41 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
42 cpu-release-addr = <0x94100A4>;
43
44 /* kHz uV */
45 operating-points = <1500000 0
46 1200000 0
47 800000 0
48 500000 0>;
49
50 clocks = <&clk_m_a9>;
51 clock-names = "cpu";
52 clock-latency = <100000>;
53 cpu0-supply = <&pwm_regulator>;
54 st,syscfg = <&syscfg_core 0x8e0>;
55 };
56 cpu@1 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a9";
59 reg = <1>;
60
61 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
62 cpu-release-addr = <0x94100A4>;
63
64 /* kHz uV */
65 operating-points = <1500000 0
66 1200000 0
67 800000 0
68 500000 0>;
69 };
70 };
71
72 intc: interrupt-controller@8761000 {
73 compatible = "arm,cortex-a9-gic";
74 #interrupt-cells = <3>;
75 interrupt-controller;
76 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
77 };
78
79 scu@8760000 {
80 compatible = "arm,cortex-a9-scu";
81 reg = <0x08760000 0x1000>;
82 };
83
84 timer@8760200 {
85 interrupt-parent = <&intc>;
86 compatible = "arm,cortex-a9-global-timer";
87 reg = <0x08760200 0x100>;
88 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&arm_periph_clk>;
90 };
91
92 l2: cache-controller@8762000 {
93 compatible = "arm,pl310-cache";
94 reg = <0x08762000 0x1000>;
95 arm,data-latency = <3 3 3>;
96 arm,tag-latency = <2 2 2>;
97 cache-unified;
98 cache-level = <2>;
99 };
100
101 arm-pmu {
102 interrupt-parent = <&intc>;
103 compatible = "arm,cortex-a9-pmu";
104 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
105 };
106
107 pwm_regulator: pwm-regulator {
108 compatible = "pwm-regulator";
109 pwms = <&pwm1 3 8448>;
110 regulator-name = "CPU_1V0_AVS";
111 regulator-min-microvolt = <784000>;
112 regulator-max-microvolt = <1299000>;
113 regulator-always-on;
114 max-duty-cycle = <255>;
115 status = "okay";
116 };
117
118 restart: restart-controller {
119 compatible = "st,stih407-restart";
120 st,syscfg = <&syscfg_sbc_reg>;
121 status = "okay";
122 };
123
124 powerdown: powerdown-controller {
125 compatible = "st,stih407-powerdown";
126 #reset-cells = <1>;
127 };
128
129 softreset: softreset-controller {
130 compatible = "st,stih407-softreset";
131 #reset-cells = <1>;
132 };
133
134 picophyreset: picophyreset-controller {
135 compatible = "st,stih407-picophyreset";
136 #reset-cells = <1>;
137 };
138
139 irq-syscfg {
140 compatible = "st,stih407-irq-syscfg";
141 st,syscfg = <&syscfg_core>;
142 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
143 <ST_IRQ_SYSCFG_PMU_1>;
144 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
145 <ST_IRQ_SYSCFG_DISABLED>;
146 };
147
148 usb2_picophy0: phy1 {
149 compatible = "st,stih407-usb2-phy";
150 #phy-cells = <0>;
151 st,syscfg = <&syscfg_core 0x100 0xf4>;
152 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
153 <&picophyreset STIH407_PICOPHY2_RESET>;
154 reset-names = "global", "port";
155 };
156
157 miphy28lp_phy: miphy28lp {
158 compatible = "st,miphy28lp-phy";
159 st,syscfg = <&syscfg_core>;
160 #address-cells = <1>;
161 #size-cells = <1>;
162 ranges;
163
164 phy_port0: port@9b22000 {
165 reg = <0x9b22000 0xff>,
166 <0x9b09000 0xff>,
167 <0x9b04000 0xff>;
168 reg-names = "sata-up",
169 "pcie-up",
170 "pipew";
171
172 st,syscfg = <0x114 0x818 0xe0 0xec>;
173 #phy-cells = <1>;
174
175 reset-names = "miphy-sw-rst";
176 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
177 };
178
179 phy_port1: port@9b2a000 {
180 reg = <0x9b2a000 0xff>,
181 <0x9b19000 0xff>,
182 <0x9b14000 0xff>;
183 reg-names = "sata-up",
184 "pcie-up",
185 "pipew";
186
187 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
188
189 #phy-cells = <1>;
190
191 reset-names = "miphy-sw-rst";
192 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
193 };
194
195 phy_port2: port@8f95000 {
196 reg = <0x8f95000 0xff>,
197 <0x8f90000 0xff>;
198 reg-names = "pipew",
199 "usb3-up";
200
201 st,syscfg = <0x11c 0x820>;
202
203 #phy-cells = <1>;
204
205 reset-names = "miphy-sw-rst";
206 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
207 };
208 };
209
210 st231_gp0: st231-gp0 {
211 compatible = "st,st231-rproc";
212 memory-region = <&gp0_reserved>;
213 resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
214 reset-names = "sw_reset";
215 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
216 clock-frequency = <600000000>;
217 st,syscfg = <&syscfg_core 0x22c>;
218 #mbox-cells = <1>;
219 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
220 mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
221 };
222
223 st231_delta: st231-delta {
224 compatible = "st,st231-rproc";
225 memory-region = <&delta_reserved>;
226 resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
227 reset-names = "sw_reset";
228 clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
229 clock-frequency = <600000000>;
230 st,syscfg = <&syscfg_core 0x224>;
231 #mbox-cells = <1>;
232 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
233 mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
234 };
235
236 delta0 {
237 compatible = "st,st-delta";
238 clock-names = "delta",
239 "delta-st231",
240 "delta-flash-promip";
241 clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
242 <&clk_s_c0_flexgen CLK_ST231_DMU>,
243 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
244 };
245
246 soc {
247 #address-cells = <1>;
248 #size-cells = <1>;
249 interrupt-parent = <&intc>;
250 ranges;
251 compatible = "simple-bus";
252
253 syscfg_sbc: sbc-syscfg@9620000 {
254 compatible = "st,stih407-sbc-syscfg", "syscon";
255 reg = <0x9620000 0x1000>;
256 };
257
258 syscfg_front: front-syscfg@9280000 {
259 compatible = "st,stih407-front-syscfg", "syscon";
260 reg = <0x9280000 0x1000>;
261 };
262
263 syscfg_rear: rear-syscfg@9290000 {
264 compatible = "st,stih407-rear-syscfg", "syscon";
265 reg = <0x9290000 0x1000>;
266 };
267
268 syscfg_flash: flash-syscfg@92a0000 {
269 compatible = "st,stih407-flash-syscfg", "syscon";
270 reg = <0x92a0000 0x1000>;
271 };
272
273 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
274 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
275 reg = <0x9600000 0x1000>;
276 };
277
278 syscfg_core: core-syscfg@92b0000 {
279 compatible = "st,stih407-core-syscfg", "syscon";
280 reg = <0x92b0000 0x1000>;
281
282 sti_sasg_codec: sti-sasg-codec {
283 compatible = "st,stih407-sas-codec";
284 #sound-dai-cells = <1>;
285 status = "disabled";
286 st,syscfg = <&syscfg_core>;
287 };
288 };
289
290 syscfg_lpm: lpm-syscfg@94b5100 {
291 compatible = "st,stih407-lpm-syscfg", "syscon";
292 reg = <0x94b5100 0x1000>;
293 };
294
295 /* Display */
296 vtg_main: sti-vtg-main@8d02800 {
297 compatible = "st,vtg";
298 reg = <0x8d02800 0x200>;
299 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
300 };
301
302 vtg_aux: sti-vtg-aux@8d00200 {
303 compatible = "st,vtg";
304 reg = <0x8d00200 0x100>;
305 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
306 };
307
308 serial@9830000 {
309 compatible = "st,asc";
310 reg = <0x9830000 0x2c>;
311 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
313 /* Pinctrl moved out to a per-board configuration */
314
315 status = "disabled";
316 };
317
318 serial@9831000 {
319 compatible = "st,asc";
320 reg = <0x9831000 0x2c>;
321 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_serial1>;
324 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
325
326 status = "disabled";
327 };
328
329 serial@9832000 {
330 compatible = "st,asc";
331 reg = <0x9832000 0x2c>;
332 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_serial2>;
335 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
336
337 status = "disabled";
338 };
339
340 /* SBC_ASC0 - UART10 */
341 sbc_serial0: serial@9530000 {
342 compatible = "st,asc";
343 reg = <0x9530000 0x2c>;
344 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_sbc_serial0>;
347 clocks = <&clk_sysin>;
348
349 status = "disabled";
350 };
351
352 serial@9531000 {
353 compatible = "st,asc";
354 reg = <0x9531000 0x2c>;
355 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_sbc_serial1>;
358 clocks = <&clk_sysin>;
359
360 status = "disabled";
361 };
362
363 i2c@9840000 {
364 compatible = "st,comms-ssc4-i2c";
365 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
366 reg = <0x9840000 0x110>;
367 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
368 clock-names = "ssc";
369 clock-frequency = <400000>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_i2c0_default>;
372 #address-cells = <1>;
373 #size-cells = <0>;
374
375 status = "disabled";
376 };
377
378 i2c@9841000 {
379 compatible = "st,comms-ssc4-i2c";
380 reg = <0x9841000 0x110>;
381 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
383 clock-names = "ssc";
384 clock-frequency = <400000>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_i2c1_default>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389
390 status = "disabled";
391 };
392
393 i2c@9842000 {
394 compatible = "st,comms-ssc4-i2c";
395 reg = <0x9842000 0x110>;
396 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
398 clock-names = "ssc";
399 clock-frequency = <400000>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_i2c2_default>;
402 #address-cells = <1>;
403 #size-cells = <0>;
404
405 status = "disabled";
406 };
407
408 i2c@9843000 {
409 compatible = "st,comms-ssc4-i2c";
410 reg = <0x9843000 0x110>;
411 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
413 clock-names = "ssc";
414 clock-frequency = <400000>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_i2c3_default>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419
420 status = "disabled";
421 };
422
423 i2c@9844000 {
424 compatible = "st,comms-ssc4-i2c";
425 reg = <0x9844000 0x110>;
426 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
428 clock-names = "ssc";
429 clock-frequency = <400000>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_i2c4_default>;
432 #address-cells = <1>;
433 #size-cells = <0>;
434
435 status = "disabled";
436 };
437
438 i2c@9845000 {
439 compatible = "st,comms-ssc4-i2c";
440 reg = <0x9845000 0x110>;
441 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
443 clock-names = "ssc";
444 clock-frequency = <400000>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_i2c5_default>;
447 #address-cells = <1>;
448 #size-cells = <0>;
449
450 status = "disabled";
451 };
452
453
454 /* SSCs on SBC */
455 i2c@9540000 {
456 compatible = "st,comms-ssc4-i2c";
457 reg = <0x9540000 0x110>;
458 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&clk_sysin>;
460 clock-names = "ssc";
461 clock-frequency = <400000>;
462 pinctrl-names = "default";
463 pinctrl-0 = <&pinctrl_i2c10_default>;
464 #address-cells = <1>;
465 #size-cells = <0>;
466
467 status = "disabled";
468 };
469
470 i2c@9541000 {
471 compatible = "st,comms-ssc4-i2c";
472 reg = <0x9541000 0x110>;
473 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&clk_sysin>;
475 clock-names = "ssc";
476 clock-frequency = <400000>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&pinctrl_i2c11_default>;
479 #address-cells = <1>;
480 #size-cells = <0>;
481
482 status = "disabled";
483 };
484
485 spi@9840000 {
486 compatible = "st,comms-ssc4-spi";
487 reg = <0x9840000 0x110>;
488 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
490 clock-names = "ssc";
491 pinctrl-0 = <&pinctrl_spi0_default>;
492 pinctrl-names = "default";
493 #address-cells = <1>;
494 #size-cells = <0>;
495
496 status = "disabled";
497 };
498
499 spi@9841000 {
500 compatible = "st,comms-ssc4-spi";
501 reg = <0x9841000 0x110>;
502 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
504 clock-names = "ssc";
505 pinctrl-names = "default";
506 pinctrl-0 = <&pinctrl_spi1_default>;
507 #address-cells = <1>;
508 #size-cells = <0>;
509
510 status = "disabled";
511 };
512
513 spi@9842000 {
514 compatible = "st,comms-ssc4-spi";
515 reg = <0x9842000 0x110>;
516 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
518 clock-names = "ssc";
519 pinctrl-names = "default";
520 pinctrl-0 = <&pinctrl_spi2_default>;
521 #address-cells = <1>;
522 #size-cells = <0>;
523
524 status = "disabled";
525 };
526
527 spi@9843000 {
528 compatible = "st,comms-ssc4-spi";
529 reg = <0x9843000 0x110>;
530 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
532 clock-names = "ssc";
533 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_spi3_default>;
535 #address-cells = <1>;
536 #size-cells = <0>;
537
538 status = "disabled";
539 };
540
541 spi@9844000 {
542 compatible = "st,comms-ssc4-spi";
543 reg = <0x9844000 0x110>;
544 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
546 clock-names = "ssc";
547 pinctrl-names = "default";
548 pinctrl-0 = <&pinctrl_spi4_default>;
549 #address-cells = <1>;
550 #size-cells = <0>;
551
552 status = "disabled";
553 };
554
555 /* SBC SSC */
556 spi@9540000 {
557 compatible = "st,comms-ssc4-spi";
558 reg = <0x9540000 0x110>;
559 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&clk_sysin>;
561 clock-names = "ssc";
562 pinctrl-names = "default";
563 pinctrl-0 = <&pinctrl_spi10_default>;
564 #address-cells = <1>;
565 #size-cells = <0>;
566
567 status = "disabled";
568 };
569
570 spi@9541000 {
571 compatible = "st,comms-ssc4-spi";
572 reg = <0x9541000 0x110>;
573 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&clk_sysin>;
575 clock-names = "ssc";
576 pinctrl-names = "default";
577 pinctrl-0 = <&pinctrl_spi11_default>;
578 #address-cells = <1>;
579 #size-cells = <0>;
580
581 status = "disabled";
582 };
583
584 spi@9542000 {
585 compatible = "st,comms-ssc4-spi";
586 reg = <0x9542000 0x110>;
587 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&clk_sysin>;
589 clock-names = "ssc";
590 pinctrl-names = "default";
591 pinctrl-0 = <&pinctrl_spi12_default>;
592 #address-cells = <1>;
593 #size-cells = <0>;
594
595 status = "disabled";
596 };
597
598 mmc0: sdhci@9060000 {
599 compatible = "st,sdhci-stih407", "st,sdhci";
600 status = "disabled";
601 reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
602 reg-names = "mmc", "top-mmc-delay";
603 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
604 interrupt-names = "mmcirq";
605 pinctrl-names = "default";
606 pinctrl-0 = <&pinctrl_mmc0>;
607 clock-names = "mmc", "icn";
608 clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
609 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
610 bus-width = <8>;
611 };
612
613 mmc1: sdhci@9080000 {
614 compatible = "st,sdhci-stih407", "st,sdhci";
615 status = "disabled";
616 reg = <0x09080000 0x7ff>;
617 reg-names = "mmc";
618 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
619 interrupt-names = "mmcirq";
620 pinctrl-names = "default";
621 pinctrl-0 = <&pinctrl_sd1>;
622 clock-names = "mmc", "icn";
623 clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
624 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
625 resets = <&softreset STIH407_MMC1_SOFTRESET>;
626 bus-width = <4>;
627 };
628
629 /* Watchdog and Real-Time Clock */
630 lpc@8787000 {
631 compatible = "st,stih407-lpc";
632 reg = <0x8787000 0x1000>;
633 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
634 clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
635 timeout-sec = <120>;
636 st,syscfg = <&syscfg_core>;
637 st,lpc-mode = <ST_LPC_MODE_WDT>;
638 };
639
640 lpc@8788000 {
641 compatible = "st,stih407-lpc";
642 reg = <0x8788000 0x1000>;
643 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
644 clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
645 st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
646 };
647
648 spifsm: spifsm@9022000{
649 compatible = "st,spi-fsm";
650 reg = <0x9022000 0x1000>;
651 reg-names = "spi-fsm";
652 clocks = <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
653 clock-names = "emi_clk";
654 pinctrl-names = "default";
655 pinctrl-0 = <&pinctrl_fsm>;
656 st,syscfg = <&syscfg_core>;
657 st,boot-device-reg = <0x8c4>;
658 st,boot-device-spi = <0x68>;
659
660 status = "disabled";
661 };
662
663 sata0: sata@9b20000 {
664 compatible = "st,ahci";
665 reg = <0x9b20000 0x1000>;
666
667 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
668 interrupt-names = "hostc";
669
670 phys = <&phy_port0 PHY_TYPE_SATA>;
671 phy-names = "ahci_phy";
672
673 resets = <&powerdown STIH407_SATA0_POWERDOWN>,
674 <&softreset STIH407_SATA0_SOFTRESET>,
675 <&softreset STIH407_SATA0_PWR_SOFTRESET>;
676 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
677
678 clock-names = "ahci_clk";
679 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
680
681 ports-implemented = <0x1>;
682
683 status = "disabled";
684 };
685
686 sata1: sata@9b28000 {
687 compatible = "st,ahci";
688 reg = <0x9b28000 0x1000>;
689
690 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
691 interrupt-names = "hostc";
692
693 phys = <&phy_port1 PHY_TYPE_SATA>;
694 phy-names = "ahci_phy";
695
696 resets = <&powerdown STIH407_SATA1_POWERDOWN>,
697 <&softreset STIH407_SATA1_SOFTRESET>,
698 <&softreset STIH407_SATA1_PWR_SOFTRESET>;
699 reset-names = "pwr-dwn",
700 "sw-rst",
701 "pwr-rst";
702
703 clock-names = "ahci_clk";
704 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
705
706 ports-implemented = <0x1>;
707
708 status = "disabled";
709 };
710
711
712 st_dwc3: dwc3@8f94000 {
713 compatible = "st,stih407-dwc3";
714 reg = <0x08f94000 0x1000>, <0x110 0x4>;
715 reg-names = "reg-glue", "syscfg-reg";
716 st,syscfg = <&syscfg_core>;
717 resets = <&powerdown STIH407_USB3_POWERDOWN>,
718 <&softreset STIH407_MIPHY2_SOFTRESET>;
719 reset-names = "powerdown", "softreset";
720 #address-cells = <1>;
721 #size-cells = <1>;
722 pinctrl-names = "default";
723 pinctrl-0 = <&pinctrl_usb3>;
724 ranges;
725
726 status = "disabled";
727
728 dwc3: usb@9900000 {
729 compatible = "snps,dwc3";
730 reg = <0x09900000 0x100000>;
731 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
732 dr_mode = "host";
733 phy-names = "usb2-phy", "usb3-phy";
734 phys = <&usb2_picophy0>,
735 <&phy_port2 PHY_TYPE_USB3>;
736 snps,dis_u3_susphy_quirk;
737 };
738 };
739
740 /* COMMS PWM Module */
741 pwm0: pwm@9810000 {
742 compatible = "st,sti-pwm";
743 #pwm-cells = <2>;
744 reg = <0x9810000 0x68>;
745 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
746 pinctrl-names = "default";
747 pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
748 clock-names = "pwm";
749 clocks = <&clk_sysin>;
750 st,pwm-num-chan = <1>;
751
752 status = "disabled";
753 };
754
755 /* SBC PWM Module */
756 pwm1: pwm@9510000 {
757 compatible = "st,sti-pwm";
758 #pwm-cells = <2>;
759 reg = <0x9510000 0x68>;
760 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
761 pinctrl-names = "default";
762 pinctrl-0 = <&pinctrl_pwm1_chan0_default
763 &pinctrl_pwm1_chan1_default
764 &pinctrl_pwm1_chan2_default
765 &pinctrl_pwm1_chan3_default>;
766 clock-names = "pwm";
767 clocks = <&clk_sysin>;
768 st,pwm-num-chan = <4>;
769
770 status = "disabled";
771 };
772
773 rng10: rng@8a89000 {
774 compatible = "st,rng";
775 reg = <0x08a89000 0x1000>;
776 clocks = <&clk_sysin>;
777 status = "okay";
778 };
779
780 rng11: rng@8a8a000 {
781 compatible = "st,rng";
782 reg = <0x08a8a000 0x1000>;
783 clocks = <&clk_sysin>;
784 status = "okay";
785 };
786
787 ethernet0: dwmac@9630000 {
788 device_type = "network";
789 status = "disabled";
790 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
791 reg = <0x9630000 0x8000>, <0x80 0x4>;
792 reg-names = "stmmaceth", "sti-ethconf";
793
794 st,syscon = <&syscfg_sbc_reg 0x80>;
795 st,gmac_en;
796 resets = <&softreset STIH407_ETH1_SOFTRESET>;
797 reset-names = "stmmaceth";
798
799 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
800 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
801 interrupt-names = "macirq", "eth_wake_irq";
802
803 /* DMA Bus Mode */
804 snps,pbl = <8>;
805
806 pinctrl-names = "default";
807 pinctrl-0 = <&pinctrl_rgmii1>;
808
809 clock-names = "stmmaceth", "sti-ethclk";
810 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
811 <&clk_s_c0_flexgen CLK_ETH_PHY>;
812 };
813
814 mailbox0: mailbox@8f00000 {
815 compatible = "st,stih407-mailbox";
816 reg = <0x8f00000 0x1000>;
817 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
818 #mbox-cells = <2>;
819 mbox-name = "a9";
820 status = "okay";
821 };
822
823 mailbox1: mailbox@8f01000 {
824 compatible = "st,stih407-mailbox";
825 reg = <0x8f01000 0x1000>;
826 #mbox-cells = <2>;
827 mbox-name = "st231_gp_1";
828 status = "okay";
829 };
830
831 mailbox2: mailbox@8f02000 {
832 compatible = "st,stih407-mailbox";
833 reg = <0x8f02000 0x1000>;
834 #mbox-cells = <2>;
835 mbox-name = "st231_gp_0";
836 status = "okay";
837 };
838
839 mailbox3: mailbox@8f03000 {
840 compatible = "st,stih407-mailbox";
841 reg = <0x8f03000 0x1000>;
842 #mbox-cells = <2>;
843 mbox-name = "st231_audio_video";
844 status = "okay";
845 };
846
847 /* fdma audio */
848 fdma0: dma-controller@8e20000 {
849 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
850 reg = <0x8e20000 0x8000>,
851 <0x8e30000 0x3000>,
852 <0x8e37000 0x1000>,
853 <0x8e38000 0x8000>;
854 reg-names = "slimcore", "dmem", "peripherals", "imem";
855 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
856 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
857 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
858 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
859 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
860 dma-channels = <16>;
861 #dma-cells = <3>;
862 };
863
864 /* fdma app */
865 fdma1: dma-controller@8e40000 {
866 compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
867 reg = <0x8e40000 0x8000>,
868 <0x8e50000 0x3000>,
869 <0x8e57000 0x1000>,
870 <0x8e58000 0x8000>;
871 reg-names = "slimcore", "dmem", "peripherals", "imem";
872 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
873 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
874 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
875 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
876
877 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
878 dma-channels = <16>;
879 #dma-cells = <3>;
880
881 status = "disabled";
882 };
883
884 /* fdma free running */
885 fdma2: dma-controller@8e60000 {
886 compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
887 reg = <0x8e60000 0x8000>,
888 <0x8e70000 0x3000>,
889 <0x8e77000 0x1000>,
890 <0x8e78000 0x8000>;
891 reg-names = "slimcore", "dmem", "peripherals", "imem";
892 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
893 dma-channels = <16>;
894 #dma-cells = <3>;
895 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
896 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
897 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
898 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
899
900 status = "disabled";
901 };
902
903 sti_uni_player0: sti-uni-player@8d80000 {
904 compatible = "st,stih407-uni-player-hdmi";
905 #sound-dai-cells = <0>;
906 st,syscfg = <&syscfg_core>;
907 clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
908 assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
909 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
910 assigned-clock-rates = <50000000>;
911 reg = <0x8d80000 0x158>;
912 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
913 dmas = <&fdma0 2 0 1>;
914 dma-names = "tx";
915
916 status = "disabled";
917 };
918
919 sti_uni_player1: sti-uni-player@8d81000 {
920 compatible = "st,stih407-uni-player-pcm-out";
921 #sound-dai-cells = <0>;
922 st,syscfg = <&syscfg_core>;
923 clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
924 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
925 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
926 assigned-clock-rates = <50000000>;
927 reg = <0x8d81000 0x158>;
928 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
929 dmas = <&fdma0 3 0 1>;
930 dma-names = "tx";
931
932 status = "disabled";
933 };
934
935 sti_uni_player2: sti-uni-player@8d82000 {
936 compatible = "st,stih407-uni-player-dac";
937 #sound-dai-cells = <0>;
938 st,syscfg = <&syscfg_core>;
939 clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
940 assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
941 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
942 assigned-clock-rates = <50000000>;
943 reg = <0x8d82000 0x158>;
944 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
945 dmas = <&fdma0 4 0 1>;
946 dma-names = "tx";
947
948 status = "disabled";
949 };
950
951 sti_uni_player3: sti-uni-player@8d85000 {
952 compatible = "st,stih407-uni-player-spdif";
953 #sound-dai-cells = <0>;
954 st,syscfg = <&syscfg_core>;
955 clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
956 assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
957 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
958 assigned-clock-rates = <50000000>;
959 reg = <0x8d85000 0x158>;
960 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
961 dmas = <&fdma0 7 0 1>;
962 dma-names = "tx";
963
964 status = "disabled";
965 };
966
967 sti_uni_reader0: sti-uni-reader@8d83000 {
968 compatible = "st,stih407-uni-reader-pcm_in";
969 #sound-dai-cells = <0>;
970 st,syscfg = <&syscfg_core>;
971 reg = <0x8d83000 0x158>;
972 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
973 dmas = <&fdma0 5 0 1>;
974 dma-names = "rx";
975
976 status = "disabled";
977 };
978
979 sti_uni_reader1: sti-uni-reader@8d84000 {
980 compatible = "st,stih407-uni-reader-hdmi";
981 #sound-dai-cells = <0>;
982 st,syscfg = <&syscfg_core>;
983 reg = <0x8d84000 0x158>;
984 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
985 dmas = <&fdma0 6 0 1>;
986 dma-names = "rx";
987
988 status = "disabled";
989 };
990 };
991};
1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih407-pinctrl.dtsi"
10#include <dt-bindings/mfd/st-lpc.h>
11#include <dt-bindings/phy/phy.h>
12#include <dt-bindings/reset/stih407-resets.h>
13#include <dt-bindings/interrupt-controller/irq-st.h>
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges;
22
23 gp0_reserved: rproc@40000000 {
24 compatible = "shared-dma-pool";
25 reg = <0x40000000 0x01000000>;
26 no-map;
27 status = "disabled";
28 };
29
30 gp1_reserved: rproc@41000000 {
31 compatible = "shared-dma-pool";
32 reg = <0x41000000 0x01000000>;
33 no-map;
34 status = "disabled";
35 };
36
37 audio_reserved: rproc@42000000 {
38 compatible = "shared-dma-pool";
39 reg = <0x42000000 0x01000000>;
40 no-map;
41 status = "disabled";
42 };
43
44 dmu_reserved: rproc@43000000 {
45 compatible = "shared-dma-pool";
46 reg = <0x43000000 0x01000000>;
47 no-map;
48 };
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54 cpu@0 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a9";
57 reg = <0>;
58
59 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
60 cpu-release-addr = <0x94100A4>;
61
62 /* kHz uV */
63 operating-points = <1500000 0
64 1200000 0
65 800000 0
66 500000 0>;
67
68 clocks = <&clk_m_a9>;
69 clock-names = "cpu";
70 clock-latency = <100000>;
71 cpu0-supply = <&pwm_regulator>;
72 st,syscfg = <&syscfg_core 0x8e0>;
73 };
74 cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a9";
77 reg = <1>;
78
79 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
80 cpu-release-addr = <0x94100A4>;
81
82 /* kHz uV */
83 operating-points = <1500000 0
84 1200000 0
85 800000 0
86 500000 0>;
87 };
88 };
89
90 intc: interrupt-controller@08761000 {
91 compatible = "arm,cortex-a9-gic";
92 #interrupt-cells = <3>;
93 interrupt-controller;
94 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
95 };
96
97 scu@08760000 {
98 compatible = "arm,cortex-a9-scu";
99 reg = <0x08760000 0x1000>;
100 };
101
102 timer@08760200 {
103 interrupt-parent = <&intc>;
104 compatible = "arm,cortex-a9-global-timer";
105 reg = <0x08760200 0x100>;
106 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&arm_periph_clk>;
108 };
109
110 l2: cache-controller {
111 compatible = "arm,pl310-cache";
112 reg = <0x08762000 0x1000>;
113 arm,data-latency = <3 3 3>;
114 arm,tag-latency = <2 2 2>;
115 cache-unified;
116 cache-level = <2>;
117 };
118
119 arm-pmu {
120 interrupt-parent = <&intc>;
121 compatible = "arm,cortex-a9-pmu";
122 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
123 };
124
125 pwm_regulator: pwm-regulator {
126 compatible = "pwm-regulator";
127 pwms = <&pwm1 3 8448>;
128 regulator-name = "CPU_1V0_AVS";
129 regulator-min-microvolt = <784000>;
130 regulator-max-microvolt = <1299000>;
131 regulator-always-on;
132 max-duty-cycle = <255>;
133 status = "okay";
134 };
135
136 soc {
137 #address-cells = <1>;
138 #size-cells = <1>;
139 interrupt-parent = <&intc>;
140 ranges;
141 compatible = "simple-bus";
142
143 restart {
144 compatible = "st,stih407-restart";
145 st,syscfg = <&syscfg_sbc_reg>;
146 status = "okay";
147 };
148
149 powerdown: powerdown-controller {
150 compatible = "st,stih407-powerdown";
151 #reset-cells = <1>;
152 };
153
154 softreset: softreset-controller {
155 compatible = "st,stih407-softreset";
156 #reset-cells = <1>;
157 };
158
159 picophyreset: picophyreset-controller {
160 compatible = "st,stih407-picophyreset";
161 #reset-cells = <1>;
162 };
163
164 syscfg_sbc: sbc-syscfg@9620000 {
165 compatible = "st,stih407-sbc-syscfg", "syscon";
166 reg = <0x9620000 0x1000>;
167 };
168
169 syscfg_front: front-syscfg@9280000 {
170 compatible = "st,stih407-front-syscfg", "syscon";
171 reg = <0x9280000 0x1000>;
172 };
173
174 syscfg_rear: rear-syscfg@9290000 {
175 compatible = "st,stih407-rear-syscfg", "syscon";
176 reg = <0x9290000 0x1000>;
177 };
178
179 syscfg_flash: flash-syscfg@92a0000 {
180 compatible = "st,stih407-flash-syscfg", "syscon";
181 reg = <0x92a0000 0x1000>;
182 };
183
184 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
185 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
186 reg = <0x9600000 0x1000>;
187 };
188
189 syscfg_core: core-syscfg@92b0000 {
190 compatible = "st,stih407-core-syscfg", "syscon";
191 reg = <0x92b0000 0x1000>;
192 };
193
194 syscfg_lpm: lpm-syscfg@94b5100 {
195 compatible = "st,stih407-lpm-syscfg", "syscon";
196 reg = <0x94b5100 0x1000>;
197 };
198
199 irq-syscfg {
200 compatible = "st,stih407-irq-syscfg";
201 st,syscfg = <&syscfg_core>;
202 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
203 <ST_IRQ_SYSCFG_PMU_1>;
204 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
205 <ST_IRQ_SYSCFG_DISABLED>;
206 };
207
208 /* Display */
209 vtg_main: sti-vtg-main@8d02800 {
210 compatible = "st,vtg";
211 reg = <0x8d02800 0x200>;
212 interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
213 };
214
215 vtg_aux: sti-vtg-aux@8d00200 {
216 compatible = "st,vtg";
217 reg = <0x8d00200 0x100>;
218 interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
219 };
220
221 serial@9830000 {
222 compatible = "st,asc";
223 reg = <0x9830000 0x2c>;
224 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_serial0>;
227 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
228
229 status = "disabled";
230 };
231
232 serial@9831000 {
233 compatible = "st,asc";
234 reg = <0x9831000 0x2c>;
235 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_serial1>;
238 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
239
240 status = "disabled";
241 };
242
243 serial@9832000 {
244 compatible = "st,asc";
245 reg = <0x9832000 0x2c>;
246 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_serial2>;
249 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
250
251 status = "disabled";
252 };
253
254 /* SBC_ASC0 - UART10 */
255 sbc_serial0: serial@9530000 {
256 compatible = "st,asc";
257 reg = <0x9530000 0x2c>;
258 interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_sbc_serial0>;
261 clocks = <&clk_sysin>;
262
263 status = "disabled";
264 };
265
266 serial@9531000 {
267 compatible = "st,asc";
268 reg = <0x9531000 0x2c>;
269 interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_sbc_serial1>;
272 clocks = <&clk_sysin>;
273
274 status = "disabled";
275 };
276
277 i2c@9840000 {
278 compatible = "st,comms-ssc4-i2c";
279 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
280 reg = <0x9840000 0x110>;
281 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
282 clock-names = "ssc";
283 clock-frequency = <400000>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_i2c0_default>;
286 #address-cells = <1>;
287 #size-cells = <0>;
288
289 status = "disabled";
290 };
291
292 i2c@9841000 {
293 compatible = "st,comms-ssc4-i2c";
294 reg = <0x9841000 0x110>;
295 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
297 clock-names = "ssc";
298 clock-frequency = <400000>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_i2c1_default>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303
304 status = "disabled";
305 };
306
307 i2c@9842000 {
308 compatible = "st,comms-ssc4-i2c";
309 reg = <0x9842000 0x110>;
310 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
312 clock-names = "ssc";
313 clock-frequency = <400000>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_i2c2_default>;
316 #address-cells = <1>;
317 #size-cells = <0>;
318
319 status = "disabled";
320 };
321
322 i2c@9843000 {
323 compatible = "st,comms-ssc4-i2c";
324 reg = <0x9843000 0x110>;
325 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
327 clock-names = "ssc";
328 clock-frequency = <400000>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_i2c3_default>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333
334 status = "disabled";
335 };
336
337 i2c@9844000 {
338 compatible = "st,comms-ssc4-i2c";
339 reg = <0x9844000 0x110>;
340 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
342 clock-names = "ssc";
343 clock-frequency = <400000>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_i2c4_default>;
346 #address-cells = <1>;
347 #size-cells = <0>;
348
349 status = "disabled";
350 };
351
352 i2c@9845000 {
353 compatible = "st,comms-ssc4-i2c";
354 reg = <0x9845000 0x110>;
355 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
357 clock-names = "ssc";
358 clock-frequency = <400000>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_i2c5_default>;
361 #address-cells = <1>;
362 #size-cells = <0>;
363
364 status = "disabled";
365 };
366
367
368 /* SSCs on SBC */
369 i2c@9540000 {
370 compatible = "st,comms-ssc4-i2c";
371 reg = <0x9540000 0x110>;
372 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&clk_sysin>;
374 clock-names = "ssc";
375 clock-frequency = <400000>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_i2c10_default>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380
381 status = "disabled";
382 };
383
384 i2c@9541000 {
385 compatible = "st,comms-ssc4-i2c";
386 reg = <0x9541000 0x110>;
387 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&clk_sysin>;
389 clock-names = "ssc";
390 clock-frequency = <400000>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_i2c11_default>;
393 #address-cells = <1>;
394 #size-cells = <0>;
395
396 status = "disabled";
397 };
398
399 usb2_picophy0: phy1 {
400 compatible = "st,stih407-usb2-phy";
401 #phy-cells = <0>;
402 st,syscfg = <&syscfg_core 0x100 0xf4>;
403 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
404 <&picophyreset STIH407_PICOPHY2_RESET>;
405 reset-names = "global", "port";
406 };
407
408 miphy28lp_phy: miphy28lp@9b22000 {
409 compatible = "st,miphy28lp-phy";
410 st,syscfg = <&syscfg_core>;
411 #address-cells = <1>;
412 #size-cells = <1>;
413 ranges;
414
415 phy_port0: port@9b22000 {
416 reg = <0x9b22000 0xff>,
417 <0x9b09000 0xff>,
418 <0x9b04000 0xff>;
419 reg-names = "sata-up",
420 "pcie-up",
421 "pipew";
422
423 st,syscfg = <0x114 0x818 0xe0 0xec>;
424 #phy-cells = <1>;
425
426 reset-names = "miphy-sw-rst";
427 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
428 };
429
430 phy_port1: port@9b2a000 {
431 reg = <0x9b2a000 0xff>,
432 <0x9b19000 0xff>,
433 <0x9b14000 0xff>;
434 reg-names = "sata-up",
435 "pcie-up",
436 "pipew";
437
438 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
439
440 #phy-cells = <1>;
441
442 reset-names = "miphy-sw-rst";
443 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
444 };
445
446 phy_port2: port@8f95000 {
447 reg = <0x8f95000 0xff>,
448 <0x8f90000 0xff>;
449 reg-names = "pipew",
450 "usb3-up";
451
452 st,syscfg = <0x11c 0x820>;
453
454 #phy-cells = <1>;
455
456 reset-names = "miphy-sw-rst";
457 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
458 };
459 };
460
461 spi@9840000 {
462 compatible = "st,comms-ssc4-spi";
463 reg = <0x9840000 0x110>;
464 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
466 clock-names = "ssc";
467 pinctrl-0 = <&pinctrl_spi0_default>;
468 pinctrl-names = "default";
469 #address-cells = <1>;
470 #size-cells = <0>;
471
472 status = "disabled";
473 };
474
475 spi@9841000 {
476 compatible = "st,comms-ssc4-spi";
477 reg = <0x9841000 0x110>;
478 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
480 clock-names = "ssc";
481 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_spi1_default>;
483
484 status = "disabled";
485 };
486
487 spi@9842000 {
488 compatible = "st,comms-ssc4-spi";
489 reg = <0x9842000 0x110>;
490 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
492 clock-names = "ssc";
493 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_spi2_default>;
495
496 status = "disabled";
497 };
498
499 spi@9843000 {
500 compatible = "st,comms-ssc4-spi";
501 reg = <0x9843000 0x110>;
502 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
504 clock-names = "ssc";
505 pinctrl-names = "default";
506 pinctrl-0 = <&pinctrl_spi3_default>;
507
508 status = "disabled";
509 };
510
511 spi@9844000 {
512 compatible = "st,comms-ssc4-spi";
513 reg = <0x9844000 0x110>;
514 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
516 clock-names = "ssc";
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_spi4_default>;
519
520 status = "disabled";
521 };
522
523 /* SBC SSC */
524 spi@9540000 {
525 compatible = "st,comms-ssc4-spi";
526 reg = <0x9540000 0x110>;
527 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&clk_sysin>;
529 clock-names = "ssc";
530 pinctrl-names = "default";
531 pinctrl-0 = <&pinctrl_spi10_default>;
532
533 status = "disabled";
534 };
535
536 spi@9541000 {
537 compatible = "st,comms-ssc4-spi";
538 reg = <0x9541000 0x110>;
539 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&clk_sysin>;
541 clock-names = "ssc";
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_spi11_default>;
544
545 status = "disabled";
546 };
547
548 spi@9542000 {
549 compatible = "st,comms-ssc4-spi";
550 reg = <0x9542000 0x110>;
551 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&clk_sysin>;
553 clock-names = "ssc";
554 pinctrl-names = "default";
555 pinctrl-0 = <&pinctrl_spi12_default>;
556
557 status = "disabled";
558 };
559
560 mmc0: sdhci@09060000 {
561 compatible = "st,sdhci-stih407", "st,sdhci";
562 status = "disabled";
563 reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
564 reg-names = "mmc", "top-mmc-delay";
565 interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
566 interrupt-names = "mmcirq";
567 pinctrl-names = "default";
568 pinctrl-0 = <&pinctrl_mmc0>;
569 clock-names = "mmc", "icn";
570 clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
571 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
572 bus-width = <8>;
573 };
574
575 mmc1: sdhci@09080000 {
576 compatible = "st,sdhci-stih407", "st,sdhci";
577 status = "disabled";
578 reg = <0x09080000 0x7ff>;
579 reg-names = "mmc";
580 interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
581 interrupt-names = "mmcirq";
582 pinctrl-names = "default";
583 pinctrl-0 = <&pinctrl_sd1>;
584 clock-names = "mmc", "icn";
585 clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
586 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
587 resets = <&softreset STIH407_MMC1_SOFTRESET>;
588 bus-width = <4>;
589 };
590
591 /* Watchdog and Real-Time Clock */
592 lpc@8787000 {
593 compatible = "st,stih407-lpc";
594 reg = <0x8787000 0x1000>;
595 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
596 clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
597 timeout-sec = <120>;
598 st,syscfg = <&syscfg_core>;
599 st,lpc-mode = <ST_LPC_MODE_WDT>;
600 };
601
602 lpc@8788000 {
603 compatible = "st,stih407-lpc";
604 reg = <0x8788000 0x1000>;
605 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
606 clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
607 st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
608 };
609
610 sata0: sata@9b20000 {
611 compatible = "st,ahci";
612 reg = <0x9b20000 0x1000>;
613
614 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
615 interrupt-names = "hostc";
616
617 phys = <&phy_port0 PHY_TYPE_SATA>;
618 phy-names = "ahci_phy";
619
620 resets = <&powerdown STIH407_SATA0_POWERDOWN>,
621 <&softreset STIH407_SATA0_SOFTRESET>,
622 <&softreset STIH407_SATA0_PWR_SOFTRESET>;
623 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
624
625 clock-names = "ahci_clk";
626 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
627
628 ports-implemented = <0x1>;
629
630 status = "disabled";
631 };
632
633 sata1: sata@9b28000 {
634 compatible = "st,ahci";
635 reg = <0x9b28000 0x1000>;
636
637 interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
638 interrupt-names = "hostc";
639
640 phys = <&phy_port1 PHY_TYPE_SATA>;
641 phy-names = "ahci_phy";
642
643 resets = <&powerdown STIH407_SATA1_POWERDOWN>,
644 <&softreset STIH407_SATA1_SOFTRESET>,
645 <&softreset STIH407_SATA1_PWR_SOFTRESET>;
646 reset-names = "pwr-dwn",
647 "sw-rst",
648 "pwr-rst";
649
650 clock-names = "ahci_clk";
651 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
652
653 ports-implemented = <0x1>;
654
655 status = "disabled";
656 };
657
658
659 st_dwc3: dwc3@8f94000 {
660 compatible = "st,stih407-dwc3";
661 reg = <0x08f94000 0x1000>, <0x110 0x4>;
662 reg-names = "reg-glue", "syscfg-reg";
663 st,syscfg = <&syscfg_core>;
664 resets = <&powerdown STIH407_USB3_POWERDOWN>,
665 <&softreset STIH407_MIPHY2_SOFTRESET>;
666 reset-names = "powerdown", "softreset";
667 #address-cells = <1>;
668 #size-cells = <1>;
669 pinctrl-names = "default";
670 pinctrl-0 = <&pinctrl_usb3>;
671 ranges;
672
673 status = "disabled";
674
675 dwc3: dwc3@9900000 {
676 compatible = "snps,dwc3";
677 reg = <0x09900000 0x100000>;
678 interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
679 dr_mode = "host";
680 phy-names = "usb2-phy", "usb3-phy";
681 phys = <&usb2_picophy0>,
682 <&phy_port2 PHY_TYPE_USB3>;
683 snps,dis_u3_susphy_quirk;
684 };
685 };
686
687 /* COMMS PWM Module */
688 pwm0: pwm@9810000 {
689 compatible = "st,sti-pwm";
690 #pwm-cells = <2>;
691 reg = <0x9810000 0x68>;
692 interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
693 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
695 clock-names = "pwm";
696 clocks = <&clk_sysin>;
697 st,pwm-num-chan = <1>;
698
699 status = "disabled";
700 };
701
702 /* SBC PWM Module */
703 pwm1: pwm@9510000 {
704 compatible = "st,sti-pwm";
705 #pwm-cells = <2>;
706 reg = <0x9510000 0x68>;
707 pinctrl-names = "default";
708 pinctrl-0 = <&pinctrl_pwm1_chan0_default
709 &pinctrl_pwm1_chan1_default
710 &pinctrl_pwm1_chan2_default
711 &pinctrl_pwm1_chan3_default>;
712 clock-names = "pwm";
713 clocks = <&clk_sysin>;
714 st,pwm-num-chan = <4>;
715
716 status = "disabled";
717 };
718
719 rng10: rng@08a89000 {
720 compatible = "st,rng";
721 reg = <0x08a89000 0x1000>;
722 clocks = <&clk_sysin>;
723 status = "okay";
724 };
725
726 rng11: rng@08a8a000 {
727 compatible = "st,rng";
728 reg = <0x08a8a000 0x1000>;
729 clocks = <&clk_sysin>;
730 status = "okay";
731 };
732
733 ethernet0: dwmac@9630000 {
734 device_type = "network";
735 status = "disabled";
736 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
737 reg = <0x9630000 0x8000>, <0x80 0x4>;
738 reg-names = "stmmaceth", "sti-ethconf";
739
740 st,syscon = <&syscfg_sbc_reg 0x80>;
741 st,gmac_en;
742 resets = <&softreset STIH407_ETH1_SOFTRESET>;
743 reset-names = "stmmaceth";
744
745 interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
746 <GIC_SPI 99 IRQ_TYPE_NONE>;
747 interrupt-names = "macirq", "eth_wake_irq";
748
749 /* DMA Bus Mode */
750 snps,pbl = <8>;
751
752 pinctrl-names = "default";
753 pinctrl-0 = <&pinctrl_rgmii1>;
754
755 clock-names = "stmmaceth", "sti-ethclk";
756 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
757 <&clk_s_c0_flexgen CLK_ETH_PHY>;
758 };
759
760 cec: sti-cec@094a087c {
761 compatible = "st,stih-cec";
762 reg = <0x94a087c 0x64>;
763 clocks = <&clk_sysin>;
764 clock-names = "cec-clk";
765 interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
766 interrupt-names = "cec-irq";
767 pinctrl-names = "default";
768 pinctrl-0 = <&pinctrl_cec0_default>;
769 resets = <&softreset STIH407_LPM_SOFTRESET>;
770 };
771
772 rng10: rng@08a89000 {
773 compatible = "st,rng";
774 reg = <0x08a89000 0x1000>;
775 clocks = <&clk_sysin>;
776 status = "okay";
777 };
778
779 rng11: rng@08a8a000 {
780 compatible = "st,rng";
781 reg = <0x08a8a000 0x1000>;
782 clocks = <&clk_sysin>;
783 status = "okay";
784 };
785
786 mailbox0: mailbox@8f00000 {
787 compatible = "st,stih407-mailbox";
788 reg = <0x8f00000 0x1000>;
789 interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>;
790 #mbox-cells = <2>;
791 mbox-name = "a9";
792 status = "okay";
793 };
794
795 mailbox1: mailbox@8f01000 {
796 compatible = "st,stih407-mailbox";
797 reg = <0x8f01000 0x1000>;
798 #mbox-cells = <2>;
799 mbox-name = "st231_gp_1";
800 status = "okay";
801 };
802
803 mailbox2: mailbox@8f02000 {
804 compatible = "st,stih407-mailbox";
805 reg = <0x8f02000 0x1000>;
806 #mbox-cells = <2>;
807 mbox-name = "st231_gp_0";
808 status = "okay";
809 };
810
811 mailbox3: mailbox@8f03000 {
812 compatible = "st,stih407-mailbox";
813 reg = <0x8f03000 0x1000>;
814 #mbox-cells = <2>;
815 mbox-name = "st231_audio_video";
816 status = "okay";
817 };
818
819 st231_gp0: remote-processor {
820 compatible = "st,st231-rproc";
821 memory-region = <&gp0_reserved>;
822 resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
823 reset-names = "sw_reset";
824 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
825 clock-frequency = <600000000>;
826 st,syscfg = <&syscfg_core 0x22c>;
827 };
828
829
830 st231_gp1: remote-processor {
831 compatible = "st,st231-rproc";
832 memory-region = <&gp1_reserved>;
833 resets = <&softreset STIH407_ST231_GP1_SOFTRESET>;
834 reset-names = "sw_reset";
835 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_1>;
836 clock-frequency = <600000000>;
837 st,syscfg = <&syscfg_core 0x220>;
838 };
839
840 st231_audio: remote-processor {
841 compatible = "st,st231-rproc";
842 memory-region = <&audio_reserved>;
843 resets = <&softreset STIH407_ST231_AUD_SOFTRESET>;
844 reset-names = "sw_reset";
845 clocks = <&clk_s_c0_flexgen CLK_ST231_AUD_0>;
846 clock-frequency = <600000000>;
847 st,syscfg = <&syscfg_core 0x228>;
848 };
849
850 st231_dmu: remote-processor {
851 compatible = "st,st231-rproc";
852 memory-region = <&dmu_reserved>;
853 resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
854 reset-names = "sw_reset";
855 clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
856 clock-frequency = <600000000>;
857 st,syscfg = <&syscfg_core 0x224>;
858 };
859
860 /* fdma audio */
861 fdma0: dma-controller@8e20000 {
862 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
863 reg = <0x8e20000 0x8000>,
864 <0x8e30000 0x3000>,
865 <0x8e37000 0x1000>,
866 <0x8e38000 0x8000>;
867 reg-names = "slimcore", "dmem", "peripherals", "imem";
868 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
869 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
870 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
871 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
872 interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
873 dma-channels = <16>;
874 #dma-cells = <3>;
875 };
876
877 /* fdma app */
878 fdma1: dma-controller@8e40000 {
879 compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
880 reg = <0x8e40000 0x8000>,
881 <0x8e50000 0x3000>,
882 <0x8e57000 0x1000>,
883 <0x8e58000 0x8000>;
884 reg-names = "slimcore", "dmem", "peripherals", "imem";
885 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
886 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
887 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
888 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
889
890 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>;
891 dma-channels = <16>;
892 #dma-cells = <3>;
893 };
894
895 /* fdma free running */
896 fdma2: dma-controller@8e60000 {
897 compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
898 reg = <0x8e60000 0x8000>,
899 <0x8e70000 0x3000>,
900 <0x8e77000 0x1000>,
901 <0x8e78000 0x8000>;
902 reg-names = "slimcore", "dmem", "peripherals", "imem";
903 interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>;
904 dma-channels = <16>;
905 #dma-cells = <3>;
906 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
907 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
908 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
909 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
910 };
911
912 sti_sasg_codec: sti-sasg-codec {
913 compatible = "st,stih407-sas-codec";
914 #sound-dai-cells = <1>;
915 status = "disabled";
916 st,syscfg = <&syscfg_core>;
917 };
918
919 sti_uni_player0: sti-uni-player@8d80000 {
920 compatible = "st,stih407-uni-player-hdmi";
921 #sound-dai-cells = <0>;
922 st,syscfg = <&syscfg_core>;
923 clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
924 assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
925 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
926 assigned-clock-rates = <50000000>;
927 reg = <0x8d80000 0x158>;
928 interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>;
929 dmas = <&fdma0 2 0 1>;
930 dma-names = "tx";
931
932 status = "disabled";
933 };
934
935 sti_uni_player1: sti-uni-player@8d81000 {
936 compatible = "st,stih407-uni-player-pcm-out";
937 #sound-dai-cells = <0>;
938 st,syscfg = <&syscfg_core>;
939 clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
940 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
941 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
942 assigned-clock-rates = <50000000>;
943 reg = <0x8d81000 0x158>;
944 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
945 dmas = <&fdma0 3 0 1>;
946 dma-names = "tx";
947
948 status = "disabled";
949 };
950
951 sti_uni_player2: sti-uni-player@8d82000 {
952 compatible = "st,stih407-uni-player-dac";
953 #sound-dai-cells = <0>;
954 st,syscfg = <&syscfg_core>;
955 clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
956 assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
957 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
958 assigned-clock-rates = <50000000>;
959 reg = <0x8d82000 0x158>;
960 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
961 dmas = <&fdma0 4 0 1>;
962 dma-names = "tx";
963
964 status = "disabled";
965 };
966
967 sti_uni_player3: sti-uni-player@8d85000 {
968 compatible = "st,stih407-uni-player-spdif";
969 #sound-dai-cells = <0>;
970 st,syscfg = <&syscfg_core>;
971 clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
972 assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
973 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
974 assigned-clock-rates = <50000000>;
975 reg = <0x8d85000 0x158>;
976 interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
977 dmas = <&fdma0 7 0 1>;
978 dma-names = "tx";
979
980 status = "disabled";
981 };
982
983 sti_uni_reader0: sti-uni-reader@8d83000 {
984 compatible = "st,stih407-uni-reader-pcm_in";
985 #sound-dai-cells = <0>;
986 st,syscfg = <&syscfg_core>;
987 reg = <0x8d83000 0x158>;
988 interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>;
989 dmas = <&fdma0 5 0 1>;
990 dma-names = "rx";
991
992 status = "disabled";
993 };
994
995 sti_uni_reader1: sti-uni-reader@8d84000 {
996 compatible = "st,stih407-uni-reader-hdmi";
997 #sound-dai-cells = <0>;
998 st,syscfg = <&syscfg_core>;
999 reg = <0x8d84000 0x158>;
1000 interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>;
1001 dmas = <&fdma0 6 0 1>;
1002 dma-names = "rx";
1003
1004 status = "disabled";
1005 };
1006 };
1007};