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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 STMicroelectronics R&D Limited
4 */
5#include <dt-bindings/clock/stih407-clks.h>
6/ {
7 /*
8 * Fixed 30MHz oscillator inputs to SoC
9 */
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 };
15
16 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <0>;
20 };
21
22 clocks {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges;
26
27 /*
28 * A9 PLL.
29 */
30 clockgen-a9@92b0000 {
31 compatible = "st,clkgen-c32";
32 reg = <0x92b0000 0x10000>;
33
34 clockgen_a9_pll: clockgen-a9-pll {
35 #clock-cells = <1>;
36 compatible = "st,stih407-clkgen-plla9";
37
38 clocks = <&clk_sysin>;
39 };
40
41 clk_m_a9: clk-m-a9 {
42 #clock-cells = <0>;
43 compatible = "st,stih407-clkgen-a9-mux";
44
45 clocks = <&clockgen_a9_pll 0>,
46 <&clockgen_a9_pll 0>,
47 <&clk_s_c0_flexgen 13>,
48 <&clk_m_a9_ext2f_div2>;
49
50 /*
51 * ARM Peripheral clock for timers
52 */
53 arm_periph_clk: clk-m-a9-periphs {
54 #clock-cells = <0>;
55 compatible = "fixed-factor-clock";
56
57 clocks = <&clk_m_a9>;
58 clock-div = <2>;
59 clock-mult = <1>;
60 };
61 };
62 };
63
64 clockgen-a@90ff000 {
65 compatible = "st,clkgen-c32";
66 reg = <0x90ff000 0x1000>;
67
68 clk_s_a0_pll: clk-s-a0-pll {
69 #clock-cells = <1>;
70 compatible = "st,clkgen-pll0-a0";
71
72 clocks = <&clk_sysin>;
73 };
74
75 clk_s_a0_flexgen: clk-s-a0-flexgen {
76 compatible = "st,flexgen", "st,flexgen-stih407-a0";
77
78 #clock-cells = <1>;
79
80 clocks = <&clk_s_a0_pll 0>,
81 <&clk_sysin>;
82 };
83 };
84
85 clk_s_c0: clockgen-c@9103000 {
86 compatible = "st,clkgen-c32";
87 reg = <0x9103000 0x1000>;
88
89 clk_s_c0_pll0: clk-s-c0-pll0 {
90 #clock-cells = <1>;
91 compatible = "st,clkgen-pll0-c0";
92
93 clocks = <&clk_sysin>;
94 };
95
96 clk_s_c0_pll1: clk-s-c0-pll1 {
97 #clock-cells = <1>;
98 compatible = "st,clkgen-pll1-c0";
99
100 clocks = <&clk_sysin>;
101 };
102
103 clk_s_c0_quadfs: clk-s-c0-quadfs {
104 #clock-cells = <1>;
105 compatible = "st,quadfs-pll";
106
107 clocks = <&clk_sysin>;
108 };
109
110 clk_s_c0_flexgen: clk-s-c0-flexgen {
111 #clock-cells = <1>;
112 compatible = "st,flexgen", "st,flexgen-stih407-c0";
113
114 clocks = <&clk_s_c0_pll0 0>,
115 <&clk_s_c0_pll1 0>,
116 <&clk_s_c0_quadfs 0>,
117 <&clk_s_c0_quadfs 1>,
118 <&clk_s_c0_quadfs 2>,
119 <&clk_s_c0_quadfs 3>,
120 <&clk_sysin>;
121
122 /*
123 * ARM Peripheral clock for timers
124 */
125 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
126 #clock-cells = <0>;
127 compatible = "fixed-factor-clock";
128
129 clocks = <&clk_s_c0_flexgen 13>;
130
131 clock-output-names = "clk-m-a9-ext2f-div2";
132
133 clock-div = <2>;
134 clock-mult = <1>;
135 };
136 };
137 };
138
139 clockgen-d0@9104000 {
140 compatible = "st,clkgen-c32";
141 reg = <0x9104000 0x1000>;
142
143 clk_s_d0_quadfs: clk-s-d0-quadfs {
144 #clock-cells = <1>;
145 compatible = "st,quadfs-d0";
146
147 clocks = <&clk_sysin>;
148 };
149
150 clk_s_d0_flexgen: clk-s-d0-flexgen {
151 #clock-cells = <1>;
152 compatible = "st,flexgen", "st,flexgen-stih407-d0";
153
154 clocks = <&clk_s_d0_quadfs 0>,
155 <&clk_s_d0_quadfs 1>,
156 <&clk_s_d0_quadfs 2>,
157 <&clk_s_d0_quadfs 3>,
158 <&clk_sysin>;
159 };
160 };
161
162 clockgen-d2@9106000 {
163 compatible = "st,clkgen-c32";
164 reg = <0x9106000 0x1000>;
165
166 clk_s_d2_quadfs: clk-s-d2-quadfs {
167 #clock-cells = <1>;
168 compatible = "st,quadfs-d2";
169
170 clocks = <&clk_sysin>;
171 };
172
173 clk_s_d2_flexgen: clk-s-d2-flexgen {
174 #clock-cells = <1>;
175 compatible = "st,flexgen", "st,flexgen-stih407-d2";
176
177 clocks = <&clk_s_d2_quadfs 0>,
178 <&clk_s_d2_quadfs 1>,
179 <&clk_s_d2_quadfs 2>,
180 <&clk_s_d2_quadfs 3>,
181 <&clk_sysin>,
182 <&clk_sysin>,
183 <&clk_tmdsout_hdmi>;
184 };
185 };
186
187 clockgen-d3@9107000 {
188 compatible = "st,clkgen-c32";
189 reg = <0x9107000 0x1000>;
190
191 clk_s_d3_quadfs: clk-s-d3-quadfs {
192 #clock-cells = <1>;
193 compatible = "st,quadfs-d3";
194
195 clocks = <&clk_sysin>;
196 };
197
198 clk_s_d3_flexgen: clk-s-d3-flexgen {
199 #clock-cells = <1>;
200 compatible = "st,flexgen", "st,flexgen-stih407-d3";
201
202 clocks = <&clk_s_d3_quadfs 0>,
203 <&clk_s_d3_quadfs 1>,
204 <&clk_s_d3_quadfs 2>,
205 <&clk_s_d3_quadfs 3>,
206 <&clk_sysin>;
207 };
208 };
209 };
210};
1/*
2 * Copyright (C) 2014 STMicroelectronics R&D Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <dt-bindings/clock/stih407-clks.h>
9/ {
10 clocks {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges;
14
15 /*
16 * Fixed 30MHz oscillator inputs to SoC
17 */
18 clk_sysin: clk-sysin {
19 #clock-cells = <0>;
20 compatible = "fixed-clock";
21 clock-frequency = <30000000>;
22 };
23
24 /*
25 * ARM Peripheral clock for timers
26 */
27 arm_periph_clk: clk-m-a9-periphs {
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
30
31 clocks = <&clk_m_a9>;
32 clock-div = <2>;
33 clock-mult = <1>;
34 };
35
36 /*
37 * A9 PLL.
38 */
39 clockgen-a9@92b0000 {
40 compatible = "st,clkgen-c32";
41 reg = <0x92b0000 0xffff>;
42
43 clockgen_a9_pll: clockgen-a9-pll {
44 #clock-cells = <1>;
45 compatible = "st,stih407-clkgen-plla9";
46
47 clocks = <&clk_sysin>;
48
49 clock-output-names = "clockgen-a9-pll-odf";
50 };
51 };
52
53 /*
54 * ARM CPU related clocks.
55 */
56 clk_m_a9: clk-m-a9@92b0000 {
57 #clock-cells = <0>;
58 compatible = "st,stih407-clkgen-a9-mux";
59 reg = <0x92b0000 0x10000>;
60
61 clocks = <&clockgen_a9_pll 0>,
62 <&clockgen_a9_pll 0>,
63 <&clk_s_c0_flexgen 13>,
64 <&clk_m_a9_ext2f_div2>;
65 };
66
67 /*
68 * ARM Peripheral clock for timers
69 */
70 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
71 #clock-cells = <0>;
72 compatible = "fixed-factor-clock";
73
74 clocks = <&clk_s_c0_flexgen 13>;
75
76 clock-output-names = "clk-m-a9-ext2f-div2";
77
78 clock-div = <2>;
79 clock-mult = <1>;
80 };
81
82 /*
83 * Bootloader initialized system infrastructure clock for
84 * serial devices.
85 */
86 clk_ext2f_a9: clockgen-c0@13 {
87 #clock-cells = <0>;
88 compatible = "fixed-clock";
89 clock-frequency = <200000000>;
90 clock-output-names = "clk-s-icn-reg-0";
91 };
92
93 clockgen-a@090ff000 {
94 compatible = "st,clkgen-c32";
95 reg = <0x90ff000 0x1000>;
96
97 clk_s_a0_pll: clk-s-a0-pll {
98 #clock-cells = <1>;
99 compatible = "st,clkgen-pll0";
100
101 clocks = <&clk_sysin>;
102
103 clock-output-names = "clk-s-a0-pll-ofd-0";
104 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
105 };
106
107 clk_s_a0_flexgen: clk-s-a0-flexgen {
108 compatible = "st,flexgen";
109
110 #clock-cells = <1>;
111
112 clocks = <&clk_s_a0_pll 0>,
113 <&clk_sysin>;
114
115 clock-output-names = "clk-ic-lmi0";
116 clock-critical = <CLK_IC_LMI0>;
117 };
118 };
119
120 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
121 #clock-cells = <1>;
122 compatible = "st,quadfs-pll";
123 reg = <0x9103000 0x1000>;
124
125 clocks = <&clk_sysin>;
126
127 clock-output-names = "clk-s-c0-fs0-ch0",
128 "clk-s-c0-fs0-ch1",
129 "clk-s-c0-fs0-ch2",
130 "clk-s-c0-fs0-ch3";
131 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
132 };
133
134 clk_s_c0: clockgen-c@09103000 {
135 compatible = "st,clkgen-c32";
136 reg = <0x9103000 0x1000>;
137
138 clk_s_c0_pll0: clk-s-c0-pll0 {
139 #clock-cells = <1>;
140 compatible = "st,clkgen-pll0";
141
142 clocks = <&clk_sysin>;
143
144 clock-output-names = "clk-s-c0-pll0-odf-0";
145 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
146 };
147
148 clk_s_c0_pll1: clk-s-c0-pll1 {
149 #clock-cells = <1>;
150 compatible = "st,clkgen-pll1";
151
152 clocks = <&clk_sysin>;
153
154 clock-output-names = "clk-s-c0-pll1-odf-0";
155 };
156
157 clk_s_c0_flexgen: clk-s-c0-flexgen {
158 #clock-cells = <1>;
159 compatible = "st,flexgen";
160
161 clocks = <&clk_s_c0_pll0 0>,
162 <&clk_s_c0_pll1 0>,
163 <&clk_s_c0_quadfs 0>,
164 <&clk_s_c0_quadfs 1>,
165 <&clk_s_c0_quadfs 2>,
166 <&clk_s_c0_quadfs 3>,
167 <&clk_sysin>;
168
169 clock-output-names = "clk-icn-gpu",
170 "clk-fdma",
171 "clk-nand",
172 "clk-hva",
173 "clk-proc-stfe",
174 "clk-proc-tp",
175 "clk-rx-icn-dmu",
176 "clk-rx-icn-hva",
177 "clk-icn-cpu",
178 "clk-tx-icn-dmu",
179 "clk-mmc-0",
180 "clk-mmc-1",
181 "clk-jpegdec",
182 "clk-ext2fa9",
183 "clk-ic-bdisp-0",
184 "clk-ic-bdisp-1",
185 "clk-pp-dmu",
186 "clk-vid-dmu",
187 "clk-dss-lpc",
188 "clk-st231-aud-0",
189 "clk-st231-gp-1",
190 "clk-st231-dmu",
191 "clk-icn-lmi",
192 "clk-tx-icn-disp-1",
193 "clk-icn-sbc",
194 "clk-stfe-frc2",
195 "clk-eth-phy",
196 "clk-eth-ref-phyclk",
197 "clk-flash-promip",
198 "clk-main-disp",
199 "clk-aux-disp",
200 "clk-compo-dvp";
201 clock-critical = <CLK_PROC_STFE>,
202 <CLK_ICN_CPU>,
203 <CLK_TX_ICN_DMU>,
204 <CLK_EXT2F_A9>,
205 <CLK_ICN_LMI>,
206 <CLK_ICN_SBC>;
207 };
208 };
209
210 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
211 #clock-cells = <1>;
212 compatible = "st,quadfs";
213 reg = <0x9104000 0x1000>;
214
215 clocks = <&clk_sysin>;
216
217 clock-output-names = "clk-s-d0-fs0-ch0",
218 "clk-s-d0-fs0-ch1",
219 "clk-s-d0-fs0-ch2",
220 "clk-s-d0-fs0-ch3";
221 };
222
223 clockgen-d0@09104000 {
224 compatible = "st,clkgen-c32";
225 reg = <0x9104000 0x1000>;
226
227 clk_s_d0_flexgen: clk-s-d0-flexgen {
228 #clock-cells = <1>;
229 compatible = "st,flexgen-audio", "st,flexgen";
230
231 clocks = <&clk_s_d0_quadfs 0>,
232 <&clk_s_d0_quadfs 1>,
233 <&clk_s_d0_quadfs 2>,
234 <&clk_s_d0_quadfs 3>,
235 <&clk_sysin>;
236
237 clock-output-names = "clk-pcm-0",
238 "clk-pcm-1",
239 "clk-pcm-2",
240 "clk-spdiff";
241 };
242 };
243
244 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
245 #clock-cells = <1>;
246 compatible = "st,quadfs";
247 reg = <0x9106000 0x1000>;
248
249 clocks = <&clk_sysin>;
250
251 clock-output-names = "clk-s-d2-fs0-ch0",
252 "clk-s-d2-fs0-ch1",
253 "clk-s-d2-fs0-ch2",
254 "clk-s-d2-fs0-ch3";
255 };
256
257 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
258 #clock-cells = <0>;
259 compatible = "fixed-clock";
260 clock-frequency = <0>;
261 };
262
263 clockgen-d2@x9106000 {
264 compatible = "st,clkgen-c32";
265 reg = <0x9106000 0x1000>;
266
267 clk_s_d2_flexgen: clk-s-d2-flexgen {
268 #clock-cells = <1>;
269 compatible = "st,flexgen-video", "st,flexgen";
270
271 clocks = <&clk_s_d2_quadfs 0>,
272 <&clk_s_d2_quadfs 1>,
273 <&clk_s_d2_quadfs 2>,
274 <&clk_s_d2_quadfs 3>,
275 <&clk_sysin>,
276 <&clk_sysin>,
277 <&clk_tmdsout_hdmi>;
278
279 clock-output-names = "clk-pix-main-disp",
280 "clk-pix-pip",
281 "clk-pix-gdp1",
282 "clk-pix-gdp2",
283 "clk-pix-gdp3",
284 "clk-pix-gdp4",
285 "clk-pix-aux-disp",
286 "clk-denc",
287 "clk-pix-hddac",
288 "clk-hddac",
289 "clk-sddac",
290 "clk-pix-dvo",
291 "clk-dvo",
292 "clk-pix-hdmi",
293 "clk-tmds-hdmi",
294 "clk-ref-hdmiphy";
295 };
296 };
297
298 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
299 #clock-cells = <1>;
300 compatible = "st,quadfs";
301 reg = <0x9107000 0x1000>;
302
303 clocks = <&clk_sysin>;
304
305 clock-output-names = "clk-s-d3-fs0-ch0",
306 "clk-s-d3-fs0-ch1",
307 "clk-s-d3-fs0-ch2",
308 "clk-s-d3-fs0-ch3";
309 };
310
311 clockgen-d3@9107000 {
312 compatible = "st,clkgen-c32";
313 reg = <0x9107000 0x1000>;
314
315 clk_s_d3_flexgen: clk-s-d3-flexgen {
316 #clock-cells = <1>;
317 compatible = "st,flexgen";
318
319 clocks = <&clk_s_d3_quadfs 0>,
320 <&clk_s_d3_quadfs 1>,
321 <&clk_s_d3_quadfs 2>,
322 <&clk_s_d3_quadfs 3>,
323 <&clk_sysin>;
324
325 clock-output-names = "clk-stfe-frc1",
326 "clk-tsout-0",
327 "clk-tsout-1",
328 "clk-mchi",
329 "clk-vsens-compo",
330 "clk-frc1-remote",
331 "clk-lpc-0",
332 "clk-lpc-1";
333 };
334 };
335 };
336};