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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright Altera Corporation (C) 2014. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/reset/altr,rst-mgr-a10.h>
8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a9";
20 device_type = "cpu";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 };
24 cpu1: cpu@1 {
25 compatible = "arm,cortex-a9";
26 device_type = "cpu";
27 reg = <1>;
28 next-level-cache = <&L2>;
29 };
30 };
31
32 pmu: pmu@ff111000 {
33 compatible = "arm,cortex-a9-pmu";
34 interrupt-parent = <&intc>;
35 interrupts = <0 124 4>, <0 125 4>;
36 interrupt-affinity = <&cpu0>, <&cpu1>;
37 reg = <0xff111000 0x1000>,
38 <0xff113000 0x1000>;
39 };
40
41 intc: interrupt-controller@ffffd000 {
42 compatible = "arm,cortex-a9-gic";
43 #interrupt-cells = <3>;
44 interrupt-controller;
45 reg = <0xffffd000 0x1000>,
46 <0xffffc100 0x100>;
47 };
48
49 soc {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 compatible = "simple-bus";
53 device_type = "soc";
54 interrupt-parent = <&intc>;
55 ranges;
56
57 amba {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62
63 pdma: pdma@ffda1000 {
64 compatible = "arm,pl330", "arm,primecell";
65 reg = <0xffda1000 0x1000>;
66 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
67 <0 84 IRQ_TYPE_LEVEL_HIGH>,
68 <0 85 IRQ_TYPE_LEVEL_HIGH>,
69 <0 86 IRQ_TYPE_LEVEL_HIGH>,
70 <0 87 IRQ_TYPE_LEVEL_HIGH>,
71 <0 88 IRQ_TYPE_LEVEL_HIGH>,
72 <0 89 IRQ_TYPE_LEVEL_HIGH>,
73 <0 90 IRQ_TYPE_LEVEL_HIGH>,
74 <0 91 IRQ_TYPE_LEVEL_HIGH>;
75 #dma-cells = <1>;
76 clocks = <&l4_main_clk>;
77 clock-names = "apb_pclk";
78 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
79 reset-names = "dma", "dma-ocp";
80 };
81 };
82
83 base_fpga_region {
84 #address-cells = <0x1>;
85 #size-cells = <0x1>;
86
87 compatible = "fpga-region";
88 fpga-mgr = <&fpga_mgr>;
89 };
90
91 clkmgr@ffd04000 {
92 compatible = "altr,clk-mgr";
93 reg = <0xffd04000 0x1000>;
94
95 clocks {
96 #address-cells = <1>;
97 #size-cells = <0>;
98
99 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
100 #clock-cells = <0>;
101 compatible = "fixed-clock";
102 };
103
104 cb_intosc_ls_clk: cb_intosc_ls_clk {
105 #clock-cells = <0>;
106 compatible = "fixed-clock";
107 };
108
109 f2s_free_clk: f2s_free_clk {
110 #clock-cells = <0>;
111 compatible = "fixed-clock";
112 };
113
114 osc1: osc1 {
115 #clock-cells = <0>;
116 compatible = "fixed-clock";
117 };
118
119 main_pll: main_pll@40 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 #clock-cells = <0>;
123 compatible = "altr,socfpga-a10-pll-clock";
124 clocks = <&osc1>, <&cb_intosc_ls_clk>,
125 <&f2s_free_clk>;
126 reg = <0x40>;
127
128 main_mpu_base_clk: main_mpu_base_clk {
129 #clock-cells = <0>;
130 compatible = "altr,socfpga-a10-perip-clk";
131 clocks = <&main_pll>;
132 div-reg = <0x140 0 11>;
133 };
134
135 main_noc_base_clk: main_noc_base_clk {
136 #clock-cells = <0>;
137 compatible = "altr,socfpga-a10-perip-clk";
138 clocks = <&main_pll>;
139 div-reg = <0x144 0 11>;
140 };
141
142 main_emaca_clk: main_emaca_clk@68 {
143 #clock-cells = <0>;
144 compatible = "altr,socfpga-a10-perip-clk";
145 clocks = <&main_pll>;
146 reg = <0x68>;
147 };
148
149 main_emacb_clk: main_emacb_clk@6c {
150 #clock-cells = <0>;
151 compatible = "altr,socfpga-a10-perip-clk";
152 clocks = <&main_pll>;
153 reg = <0x6C>;
154 };
155
156 main_emac_ptp_clk: main_emac_ptp_clk@70 {
157 #clock-cells = <0>;
158 compatible = "altr,socfpga-a10-perip-clk";
159 clocks = <&main_pll>;
160 reg = <0x70>;
161 };
162
163 main_gpio_db_clk: main_gpio_db_clk@74 {
164 #clock-cells = <0>;
165 compatible = "altr,socfpga-a10-perip-clk";
166 clocks = <&main_pll>;
167 reg = <0x74>;
168 };
169
170 main_sdmmc_clk: main_sdmmc_clk@78 {
171 #clock-cells = <0>;
172 compatible = "altr,socfpga-a10-perip-clk"
173;
174 clocks = <&main_pll>;
175 reg = <0x78>;
176 };
177
178 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
179 #clock-cells = <0>;
180 compatible = "altr,socfpga-a10-perip-clk";
181 clocks = <&main_pll>;
182 reg = <0x7C>;
183 };
184
185 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
186 #clock-cells = <0>;
187 compatible = "altr,socfpga-a10-perip-clk";
188 clocks = <&main_pll>;
189 reg = <0x80>;
190 };
191
192 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
193 #clock-cells = <0>;
194 compatible = "altr,socfpga-a10-perip-clk";
195 clocks = <&main_pll>;
196 reg = <0x84>;
197 };
198
199 main_periph_ref_clk: main_periph_ref_clk@9c {
200 #clock-cells = <0>;
201 compatible = "altr,socfpga-a10-perip-clk";
202 clocks = <&main_pll>;
203 reg = <0x9C>;
204 };
205 };
206
207 periph_pll: periph_pll@c0 {
208 #address-cells = <1>;
209 #size-cells = <0>;
210 #clock-cells = <0>;
211 compatible = "altr,socfpga-a10-pll-clock";
212 clocks = <&osc1>, <&cb_intosc_ls_clk>,
213 <&f2s_free_clk>, <&main_periph_ref_clk>;
214 reg = <0xC0>;
215
216 peri_mpu_base_clk: peri_mpu_base_clk {
217 #clock-cells = <0>;
218 compatible = "altr,socfpga-a10-perip-clk";
219 clocks = <&periph_pll>;
220 div-reg = <0x140 16 11>;
221 };
222
223 peri_noc_base_clk: peri_noc_base_clk {
224 #clock-cells = <0>;
225 compatible = "altr,socfpga-a10-perip-clk";
226 clocks = <&periph_pll>;
227 div-reg = <0x144 16 11>;
228 };
229
230 peri_emaca_clk: peri_emaca_clk@e8 {
231 #clock-cells = <0>;
232 compatible = "altr,socfpga-a10-perip-clk";
233 clocks = <&periph_pll>;
234 reg = <0xE8>;
235 };
236
237 peri_emacb_clk: peri_emacb_clk@ec {
238 #clock-cells = <0>;
239 compatible = "altr,socfpga-a10-perip-clk";
240 clocks = <&periph_pll>;
241 reg = <0xEC>;
242 };
243
244 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
245 #clock-cells = <0>;
246 compatible = "altr,socfpga-a10-perip-clk";
247 clocks = <&periph_pll>;
248 reg = <0xF0>;
249 };
250
251 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
252 #clock-cells = <0>;
253 compatible = "altr,socfpga-a10-perip-clk";
254 clocks = <&periph_pll>;
255 reg = <0xF4>;
256 };
257
258 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
259 #clock-cells = <0>;
260 compatible = "altr,socfpga-a10-perip-clk";
261 clocks = <&periph_pll>;
262 reg = <0xF8>;
263 };
264
265 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
266 #clock-cells = <0>;
267 compatible = "altr,socfpga-a10-perip-clk";
268 clocks = <&periph_pll>;
269 reg = <0xFC>;
270 };
271
272 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
273 #clock-cells = <0>;
274 compatible = "altr,socfpga-a10-perip-clk";
275 clocks = <&periph_pll>;
276 reg = <0x100>;
277 };
278
279 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
280 #clock-cells = <0>;
281 compatible = "altr,socfpga-a10-perip-clk";
282 clocks = <&periph_pll>;
283 reg = <0x104>;
284 };
285 };
286
287 mpu_free_clk: mpu_free_clk@60 {
288 #clock-cells = <0>;
289 compatible = "altr,socfpga-a10-perip-clk";
290 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
291 <&osc1>, <&cb_intosc_hs_div2_clk>,
292 <&f2s_free_clk>;
293 reg = <0x60>;
294 };
295
296 noc_free_clk: noc_free_clk@64 {
297 #clock-cells = <0>;
298 compatible = "altr,socfpga-a10-perip-clk";
299 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
300 <&osc1>, <&cb_intosc_hs_div2_clk>,
301 <&f2s_free_clk>;
302 reg = <0x64>;
303 };
304
305 s2f_user1_free_clk: s2f_user1_free_clk@104 {
306 #clock-cells = <0>;
307 compatible = "altr,socfpga-a10-perip-clk";
308 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
309 <&osc1>, <&cb_intosc_hs_div2_clk>,
310 <&f2s_free_clk>;
311 reg = <0x104>;
312 };
313
314 sdmmc_free_clk: sdmmc_free_clk@f8 {
315 #clock-cells = <0>;
316 compatible = "altr,socfpga-a10-perip-clk";
317 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
318 <&osc1>, <&cb_intosc_hs_div2_clk>,
319 <&f2s_free_clk>;
320 fixed-divider = <4>;
321 reg = <0xF8>;
322 };
323
324 l4_sys_free_clk: l4_sys_free_clk {
325 #clock-cells = <0>;
326 compatible = "altr,socfpga-a10-perip-clk";
327 clocks = <&noc_free_clk>;
328 fixed-divider = <4>;
329 };
330
331 l4_main_clk: l4_main_clk {
332 #clock-cells = <0>;
333 compatible = "altr,socfpga-a10-gate-clk";
334 clocks = <&noc_free_clk>;
335 div-reg = <0xA8 0 2>;
336 clk-gate = <0x48 1>;
337 };
338
339 l4_mp_clk: l4_mp_clk {
340 #clock-cells = <0>;
341 compatible = "altr,socfpga-a10-gate-clk";
342 clocks = <&noc_free_clk>;
343 div-reg = <0xA8 8 2>;
344 clk-gate = <0x48 2>;
345 };
346
347 l4_sp_clk: l4_sp_clk {
348 #clock-cells = <0>;
349 compatible = "altr,socfpga-a10-gate-clk";
350 clocks = <&noc_free_clk>;
351 div-reg = <0xA8 16 2>;
352 clk-gate = <0x48 3>;
353 };
354
355 mpu_periph_clk: mpu_periph_clk {
356 #clock-cells = <0>;
357 compatible = "altr,socfpga-a10-gate-clk";
358 clocks = <&mpu_free_clk>;
359 fixed-divider = <4>;
360 clk-gate = <0x48 0>;
361 };
362
363 sdmmc_clk: sdmmc_clk {
364 #clock-cells = <0>;
365 compatible = "altr,socfpga-a10-gate-clk";
366 clocks = <&sdmmc_free_clk>;
367 clk-gate = <0xC8 5>;
368 };
369
370 qspi_clk: qspi_clk {
371 #clock-cells = <0>;
372 compatible = "altr,socfpga-a10-gate-clk";
373 clocks = <&l4_main_clk>;
374 clk-gate = <0xC8 11>;
375 };
376
377 nand_x_clk: nand_x_clk {
378 #clock-cells = <0>;
379 compatible = "altr,socfpga-a10-gate-clk";
380 clocks = <&l4_mp_clk>;
381 clk-gate = <0xC8 10>;
382 };
383
384 nand_ecc_clk: nand_ecc_clk {
385 #clock-cells = <0>;
386 compatible = "altr,socfpga-a10-gate-clk";
387 clocks = <&nand_x_clk>;
388 clk-gate = <0xC8 10>;
389 };
390
391 nand_clk: nand_clk {
392 #clock-cells = <0>;
393 compatible = "altr,socfpga-a10-gate-clk";
394 clocks = <&nand_x_clk>;
395 fixed-divider = <4>;
396 clk-gate = <0xC8 10>;
397 };
398
399 spi_m_clk: spi_m_clk {
400 #clock-cells = <0>;
401 compatible = "altr,socfpga-a10-gate-clk";
402 clocks = <&l4_main_clk>;
403 clk-gate = <0xC8 9>;
404 };
405
406 usb_clk: usb_clk {
407 #clock-cells = <0>;
408 compatible = "altr,socfpga-a10-gate-clk";
409 clocks = <&l4_mp_clk>;
410 clk-gate = <0xC8 8>;
411 };
412
413 s2f_usr1_clk: s2f_usr1_clk {
414 #clock-cells = <0>;
415 compatible = "altr,socfpga-a10-gate-clk";
416 clocks = <&peri_s2f_usr1_clk>;
417 clk-gate = <0xC8 6>;
418 };
419 };
420 };
421
422 socfpga_axi_setup: stmmac-axi-config {
423 snps,wr_osr_lmt = <0xf>;
424 snps,rd_osr_lmt = <0xf>;
425 snps,blen = <0 0 0 0 16 0 0>;
426 };
427
428 gmac0: ethernet@ff800000 {
429 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
430 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
431 reg = <0xff800000 0x2000>;
432 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
433 interrupt-names = "macirq";
434 /* Filled in by bootloader */
435 mac-address = [00 00 00 00 00 00];
436 snps,multicast-filter-bins = <256>;
437 snps,perfect-filter-entries = <128>;
438 tx-fifo-depth = <4096>;
439 rx-fifo-depth = <16384>;
440 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
441 clock-names = "stmmaceth", "ptp_ref";
442 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
443 reset-names = "stmmaceth", "stmmaceth-ocp";
444 snps,axi-config = <&socfpga_axi_setup>;
445 status = "disabled";
446 };
447
448 gmac1: ethernet@ff802000 {
449 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
450 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
451 reg = <0xff802000 0x2000>;
452 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
453 interrupt-names = "macirq";
454 /* Filled in by bootloader */
455 mac-address = [00 00 00 00 00 00];
456 snps,multicast-filter-bins = <256>;
457 snps,perfect-filter-entries = <128>;
458 tx-fifo-depth = <4096>;
459 rx-fifo-depth = <16384>;
460 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
461 clock-names = "stmmaceth", "ptp_ref";
462 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
463 reset-names = "stmmaceth", "stmmaceth-ocp";
464 snps,axi-config = <&socfpga_axi_setup>;
465 status = "disabled";
466 };
467
468 gmac2: ethernet@ff804000 {
469 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
470 altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
471 reg = <0xff804000 0x2000>;
472 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
473 interrupt-names = "macirq";
474 /* Filled in by bootloader */
475 mac-address = [00 00 00 00 00 00];
476 snps,multicast-filter-bins = <256>;
477 snps,perfect-filter-entries = <128>;
478 tx-fifo-depth = <4096>;
479 rx-fifo-depth = <16384>;
480 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
481 clock-names = "stmmaceth", "ptp_ref";
482 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
483 reset-names = "stmmaceth", "stmmaceth-ocp";
484 snps,axi-config = <&socfpga_axi_setup>;
485 status = "disabled";
486 };
487
488 gpio0: gpio@ffc02900 {
489 #address-cells = <1>;
490 #size-cells = <0>;
491 compatible = "snps,dw-apb-gpio";
492 reg = <0xffc02900 0x100>;
493 resets = <&rst GPIO0_RESET>;
494 status = "disabled";
495
496 porta: gpio-controller@0 {
497 compatible = "snps,dw-apb-gpio-port";
498 gpio-controller;
499 #gpio-cells = <2>;
500 snps,nr-gpios = <29>;
501 reg = <0>;
502 interrupt-controller;
503 #interrupt-cells = <2>;
504 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
505 };
506 };
507
508 gpio1: gpio@ffc02a00 {
509 #address-cells = <1>;
510 #size-cells = <0>;
511 compatible = "snps,dw-apb-gpio";
512 reg = <0xffc02a00 0x100>;
513 resets = <&rst GPIO1_RESET>;
514 status = "disabled";
515
516 portb: gpio-controller@0 {
517 compatible = "snps,dw-apb-gpio-port";
518 gpio-controller;
519 #gpio-cells = <2>;
520 snps,nr-gpios = <29>;
521 reg = <0>;
522 interrupt-controller;
523 #interrupt-cells = <2>;
524 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
525 };
526 };
527
528 gpio2: gpio@ffc02b00 {
529 #address-cells = <1>;
530 #size-cells = <0>;
531 compatible = "snps,dw-apb-gpio";
532 reg = <0xffc02b00 0x100>;
533 resets = <&rst GPIO2_RESET>;
534 status = "disabled";
535
536 portc: gpio-controller@0 {
537 compatible = "snps,dw-apb-gpio-port";
538 gpio-controller;
539 #gpio-cells = <2>;
540 snps,nr-gpios = <27>;
541 reg = <0>;
542 interrupt-controller;
543 #interrupt-cells = <2>;
544 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
545 };
546 };
547
548 fpga_mgr: fpga-mgr@ffd03000 {
549 compatible = "altr,socfpga-a10-fpga-mgr";
550 reg = <0xffd03000 0x100
551 0xffcfe400 0x20>;
552 clocks = <&l4_mp_clk>;
553 resets = <&rst FPGAMGR_RESET>;
554 reset-names = "fpgamgr";
555 };
556
557 i2c0: i2c@ffc02200 {
558 #address-cells = <1>;
559 #size-cells = <0>;
560 compatible = "snps,designware-i2c";
561 reg = <0xffc02200 0x100>;
562 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&l4_sp_clk>;
564 resets = <&rst I2C0_RESET>;
565 status = "disabled";
566 };
567
568 i2c1: i2c@ffc02300 {
569 #address-cells = <1>;
570 #size-cells = <0>;
571 compatible = "snps,designware-i2c";
572 reg = <0xffc02300 0x100>;
573 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&l4_sp_clk>;
575 resets = <&rst I2C1_RESET>;
576 status = "disabled";
577 };
578
579 i2c2: i2c@ffc02400 {
580 #address-cells = <1>;
581 #size-cells = <0>;
582 compatible = "snps,designware-i2c";
583 reg = <0xffc02400 0x100>;
584 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&l4_sp_clk>;
586 resets = <&rst I2C2_RESET>;
587 status = "disabled";
588 };
589
590 i2c3: i2c@ffc02500 {
591 #address-cells = <1>;
592 #size-cells = <0>;
593 compatible = "snps,designware-i2c";
594 reg = <0xffc02500 0x100>;
595 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&l4_sp_clk>;
597 resets = <&rst I2C3_RESET>;
598 status = "disabled";
599 };
600
601 i2c4: i2c@ffc02600 {
602 #address-cells = <1>;
603 #size-cells = <0>;
604 compatible = "snps,designware-i2c";
605 reg = <0xffc02600 0x100>;
606 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&l4_sp_clk>;
608 resets = <&rst I2C4_RESET>;
609 status = "disabled";
610 };
611
612 spi0: spi@ffda4000 {
613 compatible = "snps,dw-apb-ssi";
614 #address-cells = <1>;
615 #size-cells = <0>;
616 reg = <0xffda4000 0x100>;
617 interrupts = <0 101 4>;
618 num-cs = <4>;
619 /*32bit_access;*/
620 clocks = <&spi_m_clk>;
621 resets = <&rst SPIM0_RESET>;
622 reset-names = "spi";
623 status = "disabled";
624 };
625
626 spi1: spi@ffda5000 {
627 compatible = "snps,dw-apb-ssi";
628 #address-cells = <1>;
629 #size-cells = <0>;
630 reg = <0xffda5000 0x100>;
631 interrupts = <0 102 4>;
632 num-cs = <4>;
633 /*32bit_access;*/
634 tx-dma-channel = <&pdma 16>;
635 rx-dma-channel = <&pdma 17>;
636 clocks = <&spi_m_clk>;
637 resets = <&rst SPIM1_RESET>;
638 reset-names = "spi";
639 status = "disabled";
640 };
641
642 sdr: sdr@ffcfb100 {
643 compatible = "altr,sdr-ctl", "syscon";
644 reg = <0xffcfb100 0x80>;
645 };
646
647 L2: cache-controller@fffff000 {
648 compatible = "arm,pl310-cache";
649 reg = <0xfffff000 0x1000>;
650 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
651 cache-unified;
652 cache-level = <2>;
653 prefetch-data = <1>;
654 prefetch-instr = <1>;
655 arm,shared-override;
656 };
657
658 mmc: mmc@ff808000 {
659 #address-cells = <1>;
660 #size-cells = <0>;
661 compatible = "altr,socfpga-dw-mshc";
662 reg = <0xff808000 0x1000>;
663 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
664 fifo-depth = <0x400>;
665 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
666 clock-names = "biu", "ciu";
667 resets = <&rst SDMMC_RESET>;
668 altr,sysmgr-syscon = <&sysmgr 0x28 4>;
669 status = "disabled";
670 };
671
672 nand: nand@ffb90000 {
673 #address-cells = <1>;
674 #size-cells = <0>;
675 compatible = "altr,socfpga-denali-nand";
676 reg = <0xffb90000 0x72000>,
677 <0xffb80000 0x10000>;
678 reg-names = "nand_data", "denali_reg";
679 interrupts = <0 99 4>;
680 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
681 clock-names = "nand", "nand_x", "ecc";
682 resets = <&rst NAND_RESET>;
683 status = "disabled";
684 };
685
686 ocram: sram@ffe00000 {
687 compatible = "mmio-sram";
688 reg = <0xffe00000 0x40000>;
689 };
690
691 eccmgr: eccmgr {
692 compatible = "altr,socfpga-a10-ecc-manager";
693 altr,sysmgr-syscon = <&sysmgr>;
694 #address-cells = <1>;
695 #size-cells = <1>;
696 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
697 <0 0 IRQ_TYPE_LEVEL_HIGH>;
698 interrupt-controller;
699 #interrupt-cells = <2>;
700 ranges;
701
702 sdramedac {
703 compatible = "altr,sdram-edac-a10";
704 altr,sdr-syscon = <&sdr>;
705 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
706 <49 IRQ_TYPE_LEVEL_HIGH>;
707 };
708
709 l2-ecc@ffd06010 {
710 compatible = "altr,socfpga-a10-l2-ecc";
711 reg = <0xffd06010 0x4>;
712 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
713 <32 IRQ_TYPE_LEVEL_HIGH>;
714 };
715
716 ocram-ecc@ff8c3000 {
717 compatible = "altr,socfpga-a10-ocram-ecc";
718 reg = <0xff8c3000 0x400>;
719 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
720 <33 IRQ_TYPE_LEVEL_HIGH>;
721 };
722
723 emac0-rx-ecc@ff8c0800 {
724 compatible = "altr,socfpga-eth-mac-ecc";
725 reg = <0xff8c0800 0x400>;
726 altr,ecc-parent = <&gmac0>;
727 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
728 <36 IRQ_TYPE_LEVEL_HIGH>;
729 };
730
731 emac0-tx-ecc@ff8c0c00 {
732 compatible = "altr,socfpga-eth-mac-ecc";
733 reg = <0xff8c0c00 0x400>;
734 altr,ecc-parent = <&gmac0>;
735 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
736 <37 IRQ_TYPE_LEVEL_HIGH>;
737 };
738
739 sdmmca-ecc@ff8c2c00 {
740 compatible = "altr,socfpga-sdmmc-ecc";
741 reg = <0xff8c2c00 0x400>;
742 altr,ecc-parent = <&mmc>;
743 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
744 <47 IRQ_TYPE_LEVEL_HIGH>,
745 <16 IRQ_TYPE_LEVEL_HIGH>,
746 <48 IRQ_TYPE_LEVEL_HIGH>;
747 };
748
749 dma-ecc@ff8c8000 {
750 compatible = "altr,socfpga-dma-ecc";
751 reg = <0xff8c8000 0x400>;
752 altr,ecc-parent = <&pdma>;
753 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
754 <42 IRQ_TYPE_LEVEL_HIGH>;
755 };
756
757 usb0-ecc@ff8c8800 {
758 compatible = "altr,socfpga-usb-ecc";
759 reg = <0xff8c8800 0x400>;
760 altr,ecc-parent = <&usb0>;
761 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
762 <34 IRQ_TYPE_LEVEL_HIGH>;
763 };
764 };
765
766 qspi: spi@ff809000 {
767 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
768 #address-cells = <1>;
769 #size-cells = <0>;
770 reg = <0xff809000 0x100>,
771 <0xffa00000 0x100000>;
772 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
773 cdns,fifo-depth = <128>;
774 cdns,fifo-width = <4>;
775 cdns,trigger-address = <0x00000000>;
776 clocks = <&qspi_clk>;
777 resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
778 reset-names = "qspi", "qspi-ocp";
779 status = "disabled";
780 };
781
782 rst: rstmgr@ffd05000 {
783 #reset-cells = <1>;
784 compatible = "altr,rst-mgr";
785 reg = <0xffd05000 0x100>;
786 altr,modrst-offset = <0x20>;
787 };
788
789 scu: snoop-control-unit@ffffc000 {
790 compatible = "arm,cortex-a9-scu";
791 reg = <0xffffc000 0x100>;
792 };
793
794 sysmgr: sysmgr@ffd06000 {
795 compatible = "altr,sys-mgr", "syscon";
796 reg = <0xffd06000 0x300>;
797 cpu1-start-addr = <0xffd06230>;
798 };
799
800 /* Local timer */
801 timer@ffffc600 {
802 compatible = "arm,cortex-a9-twd-timer";
803 reg = <0xffffc600 0x100>;
804 interrupts = <1 13 0xf01>;
805 clocks = <&mpu_periph_clk>;
806 };
807
808 timer0: timer0@ffc02700 {
809 compatible = "snps,dw-apb-timer";
810 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
811 reg = <0xffc02700 0x100>;
812 clocks = <&l4_sp_clk>;
813 clock-names = "timer";
814 resets = <&rst SPTIMER0_RESET>;
815 reset-names = "timer";
816 };
817
818 timer1: timer1@ffc02800 {
819 compatible = "snps,dw-apb-timer";
820 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
821 reg = <0xffc02800 0x100>;
822 clocks = <&l4_sp_clk>;
823 clock-names = "timer";
824 resets = <&rst SPTIMER1_RESET>;
825 reset-names = "timer";
826 };
827
828 timer2: timer2@ffd00000 {
829 compatible = "snps,dw-apb-timer";
830 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
831 reg = <0xffd00000 0x100>;
832 clocks = <&l4_sys_free_clk>;
833 clock-names = "timer";
834 resets = <&rst L4SYSTIMER0_RESET>;
835 reset-names = "timer";
836 };
837
838 timer3: timer3@ffd00100 {
839 compatible = "snps,dw-apb-timer";
840 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
841 reg = <0xffd00100 0x100>;
842 clocks = <&l4_sys_free_clk>;
843 clock-names = "timer";
844 resets = <&rst L4SYSTIMER1_RESET>;
845 reset-names = "timer";
846 };
847
848 uart0: serial0@ffc02000 {
849 compatible = "snps,dw-apb-uart";
850 reg = <0xffc02000 0x100>;
851 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
852 reg-shift = <2>;
853 reg-io-width = <4>;
854 clocks = <&l4_sp_clk>;
855 resets = <&rst UART0_RESET>;
856 status = "disabled";
857 };
858
859 uart1: serial1@ffc02100 {
860 compatible = "snps,dw-apb-uart";
861 reg = <0xffc02100 0x100>;
862 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
863 reg-shift = <2>;
864 reg-io-width = <4>;
865 clocks = <&l4_sp_clk>;
866 resets = <&rst UART1_RESET>;
867 status = "disabled";
868 };
869
870 usbphy0: usbphy {
871 #phy-cells = <0>;
872 compatible = "usb-nop-xceiv";
873 status = "okay";
874 };
875
876 usb0: usb@ffb00000 {
877 compatible = "snps,dwc2";
878 reg = <0xffb00000 0xffff>;
879 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&usb_clk>;
881 clock-names = "otg";
882 resets = <&rst USB0_RESET>;
883 reset-names = "dwc2";
884 phys = <&usbphy0>;
885 phy-names = "usb2-phy";
886 status = "disabled";
887 };
888
889 usb1: usb@ffb40000 {
890 compatible = "snps,dwc2";
891 reg = <0xffb40000 0xffff>;
892 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&usb_clk>;
894 clock-names = "otg";
895 resets = <&rst USB1_RESET>;
896 reset-names = "dwc2";
897 phys = <&usbphy0>;
898 phy-names = "usb2-phy";
899 status = "disabled";
900 };
901
902 watchdog0: watchdog@ffd00200 {
903 compatible = "snps,dw-wdt";
904 reg = <0xffd00200 0x100>;
905 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
906 clocks = <&l4_sys_free_clk>;
907 resets = <&rst L4WD0_RESET>;
908 status = "disabled";
909 };
910
911 watchdog1: watchdog@ffd00300 {
912 compatible = "snps,dw-wdt";
913 reg = <0xffd00300 0x100>;
914 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
915 clocks = <&l4_sys_free_clk>;
916 resets = <&rst L4WD1_RESET>;
917 status = "disabled";
918 };
919 };
920};
1/*
2 * Copyright Altera Corporation (C) 2014. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "skeleton.dtsi"
18#include <dt-bindings/interrupt-controller/arm-gic.h>
19#include <dt-bindings/reset/altr,rst-mgr-a10.h>
20
21/ {
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "altr,socfpga-a10-smp";
29
30 cpu@0 {
31 compatible = "arm,cortex-a9";
32 device_type = "cpu";
33 reg = <0>;
34 next-level-cache = <&L2>;
35 };
36 cpu@1 {
37 compatible = "arm,cortex-a9";
38 device_type = "cpu";
39 reg = <1>;
40 next-level-cache = <&L2>;
41 };
42 };
43
44 intc: intc@ffffd000 {
45 compatible = "arm,cortex-a9-gic";
46 #interrupt-cells = <3>;
47 interrupt-controller;
48 reg = <0xffffd000 0x1000>,
49 <0xffffc100 0x100>;
50 };
51
52 soc {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 compatible = "simple-bus";
56 device_type = "soc";
57 interrupt-parent = <&intc>;
58 ranges;
59
60 amba {
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges;
65
66 pdma: pdma@ffda1000 {
67 compatible = "arm,pl330", "arm,primecell";
68 reg = <0xffda1000 0x1000>;
69 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
70 <0 84 IRQ_TYPE_LEVEL_HIGH>,
71 <0 85 IRQ_TYPE_LEVEL_HIGH>,
72 <0 86 IRQ_TYPE_LEVEL_HIGH>,
73 <0 87 IRQ_TYPE_LEVEL_HIGH>,
74 <0 88 IRQ_TYPE_LEVEL_HIGH>,
75 <0 89 IRQ_TYPE_LEVEL_HIGH>,
76 <0 90 IRQ_TYPE_LEVEL_HIGH>,
77 <0 91 IRQ_TYPE_LEVEL_HIGH>;
78 #dma-cells = <1>;
79 #dma-channels = <8>;
80 #dma-requests = <32>;
81 clocks = <&l4_main_clk>;
82 clock-names = "apb_pclk";
83 };
84 };
85
86 clkmgr@ffd04000 {
87 compatible = "altr,clk-mgr";
88 reg = <0xffd04000 0x1000>;
89
90 clocks {
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
95 #clock-cells = <0>;
96 compatible = "fixed-clock";
97 };
98
99 cb_intosc_ls_clk: cb_intosc_ls_clk {
100 #clock-cells = <0>;
101 compatible = "fixed-clock";
102 };
103
104 f2s_free_clk: f2s_free_clk {
105 #clock-cells = <0>;
106 compatible = "fixed-clock";
107 };
108
109 osc1: osc1 {
110 #clock-cells = <0>;
111 compatible = "fixed-clock";
112 };
113
114 main_pll: main_pll {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 #clock-cells = <0>;
118 compatible = "altr,socfpga-a10-pll-clock";
119 clocks = <&osc1>, <&cb_intosc_ls_clk>,
120 <&f2s_free_clk>;
121 reg = <0x40>;
122
123 main_mpu_base_clk: main_mpu_base_clk {
124 #clock-cells = <0>;
125 compatible = "altr,socfpga-a10-perip-clk";
126 clocks = <&main_pll>;
127 div-reg = <0x140 0 11>;
128 };
129
130 main_noc_base_clk: main_noc_base_clk {
131 #clock-cells = <0>;
132 compatible = "altr,socfpga-a10-perip-clk";
133 clocks = <&main_pll>;
134 div-reg = <0x144 0 11>;
135 };
136
137 main_emaca_clk: main_emaca_clk {
138 #clock-cells = <0>;
139 compatible = "altr,socfpga-a10-perip-clk";
140 clocks = <&main_pll>;
141 reg = <0x68>;
142 };
143
144 main_emacb_clk: main_emacb_clk {
145 #clock-cells = <0>;
146 compatible = "altr,socfpga-a10-perip-clk";
147 clocks = <&main_pll>;
148 reg = <0x6C>;
149 };
150
151 main_emac_ptp_clk: main_emac_ptp_clk {
152 #clock-cells = <0>;
153 compatible = "altr,socfpga-a10-perip-clk";
154 clocks = <&main_pll>;
155 reg = <0x70>;
156 };
157
158 main_gpio_db_clk: main_gpio_db_clk {
159 #clock-cells = <0>;
160 compatible = "altr,socfpga-a10-perip-clk";
161 clocks = <&main_pll>;
162 reg = <0x74>;
163 };
164
165 main_sdmmc_clk: main_sdmmc_clk {
166 #clock-cells = <0>;
167 compatible = "altr,socfpga-a10-perip-clk"
168;
169 clocks = <&main_pll>;
170 reg = <0x78>;
171 };
172
173 main_s2f_usr0_clk: main_s2f_usr0_clk {
174 #clock-cells = <0>;
175 compatible = "altr,socfpga-a10-perip-clk";
176 clocks = <&main_pll>;
177 reg = <0x7C>;
178 };
179
180 main_s2f_usr1_clk: main_s2f_usr1_clk {
181 #clock-cells = <0>;
182 compatible = "altr,socfpga-a10-perip-clk";
183 clocks = <&main_pll>;
184 reg = <0x80>;
185 };
186
187 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
188 #clock-cells = <0>;
189 compatible = "altr,socfpga-a10-perip-clk";
190 clocks = <&main_pll>;
191 reg = <0x84>;
192 };
193
194 main_periph_ref_clk: main_periph_ref_clk {
195 #clock-cells = <0>;
196 compatible = "altr,socfpga-a10-perip-clk";
197 clocks = <&main_pll>;
198 reg = <0x9C>;
199 };
200 };
201
202 periph_pll: periph_pll {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 #clock-cells = <0>;
206 compatible = "altr,socfpga-a10-pll-clock";
207 clocks = <&osc1>, <&cb_intosc_ls_clk>,
208 <&f2s_free_clk>, <&main_periph_ref_clk>;
209 reg = <0xC0>;
210
211 peri_mpu_base_clk: peri_mpu_base_clk {
212 #clock-cells = <0>;
213 compatible = "altr,socfpga-a10-perip-clk";
214 clocks = <&periph_pll>;
215 div-reg = <0x140 16 11>;
216 };
217
218 peri_noc_base_clk: peri_noc_base_clk {
219 #clock-cells = <0>;
220 compatible = "altr,socfpga-a10-perip-clk";
221 clocks = <&periph_pll>;
222 div-reg = <0x144 16 11>;
223 };
224
225 peri_emaca_clk: peri_emaca_clk {
226 #clock-cells = <0>;
227 compatible = "altr,socfpga-a10-perip-clk";
228 clocks = <&periph_pll>;
229 reg = <0xE8>;
230 };
231
232 peri_emacb_clk: peri_emacb_clk {
233 #clock-cells = <0>;
234 compatible = "altr,socfpga-a10-perip-clk";
235 clocks = <&periph_pll>;
236 reg = <0xEC>;
237 };
238
239 peri_emac_ptp_clk: peri_emac_ptp_clk {
240 #clock-cells = <0>;
241 compatible = "altr,socfpga-a10-perip-clk";
242 clocks = <&periph_pll>;
243 reg = <0xF0>;
244 };
245
246 peri_gpio_db_clk: peri_gpio_db_clk {
247 #clock-cells = <0>;
248 compatible = "altr,socfpga-a10-perip-clk";
249 clocks = <&periph_pll>;
250 reg = <0xF4>;
251 };
252
253 peri_sdmmc_clk: peri_sdmmc_clk {
254 #clock-cells = <0>;
255 compatible = "altr,socfpga-a10-perip-clk";
256 clocks = <&periph_pll>;
257 reg = <0xF8>;
258 };
259
260 peri_s2f_usr0_clk: peri_s2f_usr0_clk {
261 #clock-cells = <0>;
262 compatible = "altr,socfpga-a10-perip-clk";
263 clocks = <&periph_pll>;
264 reg = <0xFC>;
265 };
266
267 peri_s2f_usr1_clk: peri_s2f_usr1_clk {
268 #clock-cells = <0>;
269 compatible = "altr,socfpga-a10-perip-clk";
270 clocks = <&periph_pll>;
271 reg = <0x100>;
272 };
273
274 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
275 #clock-cells = <0>;
276 compatible = "altr,socfpga-a10-perip-clk";
277 clocks = <&periph_pll>;
278 reg = <0x104>;
279 };
280 };
281
282 mpu_free_clk: mpu_free_clk {
283 #clock-cells = <0>;
284 compatible = "altr,socfpga-a10-perip-clk";
285 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
286 <&osc1>, <&cb_intosc_hs_div2_clk>,
287 <&f2s_free_clk>;
288 reg = <0x60>;
289 };
290
291 noc_free_clk: noc_free_clk {
292 #clock-cells = <0>;
293 compatible = "altr,socfpga-a10-perip-clk";
294 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
295 <&osc1>, <&cb_intosc_hs_div2_clk>,
296 <&f2s_free_clk>;
297 reg = <0x64>;
298 };
299
300 s2f_user1_free_clk: s2f_user1_free_clk {
301 #clock-cells = <0>;
302 compatible = "altr,socfpga-a10-perip-clk";
303 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
304 <&osc1>, <&cb_intosc_hs_div2_clk>,
305 <&f2s_free_clk>;
306 reg = <0x104>;
307 };
308
309 sdmmc_free_clk: sdmmc_free_clk {
310 #clock-cells = <0>;
311 compatible = "altr,socfpga-a10-perip-clk";
312 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
313 <&osc1>, <&cb_intosc_hs_div2_clk>,
314 <&f2s_free_clk>;
315 fixed-divider = <4>;
316 reg = <0xF8>;
317 };
318
319 l4_sys_free_clk: l4_sys_free_clk {
320 #clock-cells = <0>;
321 compatible = "altr,socfpga-a10-perip-clk";
322 clocks = <&noc_free_clk>;
323 fixed-divider = <4>;
324 };
325
326 l4_main_clk: l4_main_clk {
327 #clock-cells = <0>;
328 compatible = "altr,socfpga-a10-gate-clk";
329 clocks = <&noc_free_clk>;
330 div-reg = <0xA8 0 2>;
331 clk-gate = <0x48 1>;
332 };
333
334 l4_mp_clk: l4_mp_clk {
335 #clock-cells = <0>;
336 compatible = "altr,socfpga-a10-gate-clk";
337 clocks = <&noc_free_clk>;
338 div-reg = <0xA8 8 2>;
339 clk-gate = <0x48 2>;
340 };
341
342 l4_sp_clk: l4_sp_clk {
343 #clock-cells = <0>;
344 compatible = "altr,socfpga-a10-gate-clk";
345 clocks = <&noc_free_clk>;
346 div-reg = <0xA8 16 2>;
347 clk-gate = <0x48 3>;
348 };
349
350 mpu_periph_clk: mpu_periph_clk {
351 #clock-cells = <0>;
352 compatible = "altr,socfpga-a10-gate-clk";
353 clocks = <&mpu_free_clk>;
354 fixed-divider = <4>;
355 clk-gate = <0x48 0>;
356 };
357
358 sdmmc_clk: sdmmc_clk {
359 #clock-cells = <0>;
360 compatible = "altr,socfpga-a10-gate-clk";
361 clocks = <&sdmmc_free_clk>;
362 clk-gate = <0xC8 5>;
363 clk-phase = <0 135>;
364 };
365
366 qspi_clk: qspi_clk {
367 #clock-cells = <0>;
368 compatible = "altr,socfpga-a10-gate-clk";
369 clocks = <&l4_main_clk>;
370 clk-gate = <0xC8 11>;
371 };
372
373 nand_clk: nand_clk {
374 #clock-cells = <0>;
375 compatible = "altr,socfpga-a10-gate-clk";
376 clocks = <&l4_mp_clk>;
377 clk-gate = <0xC8 10>;
378 };
379
380 spi_m_clk: spi_m_clk {
381 #clock-cells = <0>;
382 compatible = "altr,socfpga-a10-gate-clk";
383 clocks = <&l4_main_clk>;
384 clk-gate = <0xC8 9>;
385 };
386
387 usb_clk: usb_clk {
388 #clock-cells = <0>;
389 compatible = "altr,socfpga-a10-gate-clk";
390 clocks = <&l4_mp_clk>;
391 clk-gate = <0xC8 8>;
392 };
393
394 s2f_usr1_clk: s2f_usr1_clk {
395 #clock-cells = <0>;
396 compatible = "altr,socfpga-a10-gate-clk";
397 clocks = <&peri_s2f_usr1_clk>;
398 clk-gate = <0xC8 6>;
399 };
400 };
401 };
402
403 gmac0: ethernet@ff800000 {
404 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
405 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
406 reg = <0xff800000 0x2000>;
407 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
408 interrupt-names = "macirq";
409 /* Filled in by bootloader */
410 mac-address = [00 00 00 00 00 00];
411 snps,multicast-filter-bins = <256>;
412 snps,perfect-filter-entries = <128>;
413 tx-fifo-depth = <4096>;
414 rx-fifo-depth = <16384>;
415 clocks = <&l4_mp_clk>;
416 clock-names = "stmmaceth";
417 resets = <&rst EMAC0_RESET>;
418 reset-names = "stmmaceth";
419 status = "disabled";
420 };
421
422 gmac1: ethernet@ff802000 {
423 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
424 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
425 reg = <0xff802000 0x2000>;
426 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
427 interrupt-names = "macirq";
428 /* Filled in by bootloader */
429 mac-address = [00 00 00 00 00 00];
430 snps,multicast-filter-bins = <256>;
431 snps,perfect-filter-entries = <128>;
432 tx-fifo-depth = <4096>;
433 rx-fifo-depth = <16384>;
434 clocks = <&l4_mp_clk>;
435 clock-names = "stmmaceth";
436 resets = <&rst EMAC1_RESET>;
437 reset-names = "stmmaceth";
438 status = "disabled";
439 };
440
441 gmac2: ethernet@ff804000 {
442 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
443 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
444 reg = <0xff804000 0x2000>;
445 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
446 interrupt-names = "macirq";
447 /* Filled in by bootloader */
448 mac-address = [00 00 00 00 00 00];
449 snps,multicast-filter-bins = <256>;
450 snps,perfect-filter-entries = <128>;
451 tx-fifo-depth = <4096>;
452 rx-fifo-depth = <16384>;
453 clocks = <&l4_mp_clk>;
454 clock-names = "stmmaceth";
455 status = "disabled";
456 };
457
458 gpio0: gpio@ffc02900 {
459 #address-cells = <1>;
460 #size-cells = <0>;
461 compatible = "snps,dw-apb-gpio";
462 reg = <0xffc02900 0x100>;
463 status = "disabled";
464
465 porta: gpio-controller@0 {
466 compatible = "snps,dw-apb-gpio-port";
467 gpio-controller;
468 #gpio-cells = <2>;
469 snps,nr-gpios = <29>;
470 reg = <0>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
473 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
474 };
475 };
476
477 gpio1: gpio@ffc02a00 {
478 #address-cells = <1>;
479 #size-cells = <0>;
480 compatible = "snps,dw-apb-gpio";
481 reg = <0xffc02a00 0x100>;
482 status = "disabled";
483
484 portb: gpio-controller@0 {
485 compatible = "snps,dw-apb-gpio-port";
486 gpio-controller;
487 #gpio-cells = <2>;
488 snps,nr-gpios = <29>;
489 reg = <0>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
493 };
494 };
495
496 gpio2: gpio@ffc02b00 {
497 #address-cells = <1>;
498 #size-cells = <0>;
499 compatible = "snps,dw-apb-gpio";
500 reg = <0xffc02b00 0x100>;
501 status = "disabled";
502
503 portc: gpio-controller@0 {
504 compatible = "snps,dw-apb-gpio-port";
505 gpio-controller;
506 #gpio-cells = <2>;
507 snps,nr-gpios = <27>;
508 reg = <0>;
509 interrupt-controller;
510 #interrupt-cells = <2>;
511 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
512 };
513 };
514
515 i2c0: i2c@ffc02200 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "snps,designware-i2c";
519 reg = <0xffc02200 0x100>;
520 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&l4_sp_clk>;
522 status = "disabled";
523 };
524
525 i2c1: i2c@ffc02300 {
526 #address-cells = <1>;
527 #size-cells = <0>;
528 compatible = "snps,designware-i2c";
529 reg = <0xffc02300 0x100>;
530 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&l4_sp_clk>;
532 status = "disabled";
533 };
534
535 i2c2: i2c@ffc02400 {
536 #address-cells = <1>;
537 #size-cells = <0>;
538 compatible = "snps,designware-i2c";
539 reg = <0xffc02400 0x100>;
540 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&l4_sp_clk>;
542 status = "disabled";
543 };
544
545 i2c3: i2c@ffc02500 {
546 #address-cells = <1>;
547 #size-cells = <0>;
548 compatible = "snps,designware-i2c";
549 reg = <0xffc02500 0x100>;
550 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&l4_sp_clk>;
552 status = "disabled";
553 };
554
555 i2c4: i2c@ffc02600 {
556 #address-cells = <1>;
557 #size-cells = <0>;
558 compatible = "snps,designware-i2c";
559 reg = <0xffc02600 0x100>;
560 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&l4_sp_clk>;
562 status = "disabled";
563 };
564
565 spi1: spi@ffda5000 {
566 compatible = "snps,dw-apb-ssi";
567 #address-cells = <1>;
568 #size-cells = <0>;
569 reg = <0xffda5000 0x100>;
570 interrupts = <0 102 4>;
571 num-chipselect = <4>;
572 bus-num = <0>;
573 /*32bit_access;*/
574 tx-dma-channel = <&pdma 16>;
575 rx-dma-channel = <&pdma 17>;
576 clocks = <&spi_m_clk>;
577 status = "disabled";
578 };
579
580 sdr: sdr@ffc25000 {
581 compatible = "syscon";
582 reg = <0xffcfb100 0x80>;
583 };
584
585 L2: l2-cache@fffff000 {
586 compatible = "arm,pl310-cache";
587 reg = <0xfffff000 0x1000>;
588 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
589 cache-unified;
590 cache-level = <2>;
591 prefetch-data = <1>;
592 prefetch-instr = <1>;
593 arm,shared-override;
594 };
595
596 mmc: dwmmc0@ff808000 {
597 #address-cells = <1>;
598 #size-cells = <0>;
599 compatible = "altr,socfpga-dw-mshc";
600 reg = <0xff808000 0x1000>;
601 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
602 fifo-depth = <0x400>;
603 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
604 clock-names = "biu", "ciu";
605 status = "disabled";
606 };
607
608 ocram: sram@ffe00000 {
609 compatible = "mmio-sram";
610 reg = <0xffe00000 0x40000>;
611 };
612
613 eccmgr: eccmgr@ffd06000 {
614 compatible = "altr,socfpga-a10-ecc-manager";
615 altr,sysmgr-syscon = <&sysmgr>;
616 #address-cells = <1>;
617 #size-cells = <1>;
618 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
619 <0 0 IRQ_TYPE_LEVEL_HIGH>;
620 interrupt-controller;
621 #interrupt-cells = <2>;
622 ranges;
623
624 sdramedac {
625 compatible = "altr,sdram-edac-a10";
626 altr,sdr-syscon = <&sdr>;
627 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
628 <49 IRQ_TYPE_LEVEL_HIGH>;
629 };
630
631 l2-ecc@ffd06010 {
632 compatible = "altr,socfpga-a10-l2-ecc";
633 reg = <0xffd06010 0x4>;
634 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
635 <32 IRQ_TYPE_LEVEL_HIGH>;
636 };
637
638 ocram-ecc@ff8c3000 {
639 compatible = "altr,socfpga-a10-ocram-ecc";
640 reg = <0xff8c3000 0x400>;
641 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
642 <33 IRQ_TYPE_LEVEL_HIGH>;
643 };
644
645 emac0-rx-ecc@ff8c0800 {
646 compatible = "altr,socfpga-eth-mac-ecc";
647 reg = <0xff8c0800 0x400>;
648 altr,ecc-parent = <&gmac0>;
649 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
650 <36 IRQ_TYPE_LEVEL_HIGH>;
651 };
652
653 emac0-tx-ecc@ff8c0c00 {
654 compatible = "altr,socfpga-eth-mac-ecc";
655 reg = <0xff8c0c00 0x400>;
656 altr,ecc-parent = <&gmac0>;
657 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
658 <37 IRQ_TYPE_LEVEL_HIGH>;
659 };
660
661 dma-ecc@ff8c8000 {
662 compatible = "altr,socfpga-dma-ecc";
663 reg = <0xff8c8000 0x400>;
664 altr,ecc-parent = <&pdma>;
665 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
666 <42 IRQ_TYPE_LEVEL_HIGH>;
667 };
668
669 usb0-ecc@ff8c8800 {
670 compatible = "altr,socfpga-usb-ecc";
671 reg = <0xff8c8800 0x400>;
672 altr,ecc-parent = <&usb0>;
673 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
674 <34 IRQ_TYPE_LEVEL_HIGH>;
675 };
676 };
677
678 qspi: spi@ff809000 {
679 compatible = "cdns,qspi-nor";
680 #address-cells = <1>;
681 #size-cells = <0>;
682 reg = <0xff809000 0x100>,
683 <0xffa00000 0x100000>;
684 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
685 cdns,fifo-depth = <128>;
686 cdns,fifo-width = <4>;
687 cdns,trigger-address = <0x00000000>;
688 clocks = <&qspi_clk>;
689 status = "disabled";
690 };
691
692 rst: rstmgr@ffd05000 {
693 #reset-cells = <1>;
694 compatible = "altr,rst-mgr";
695 reg = <0xffd05000 0x100>;
696 altr,modrst-offset = <0x20>;
697 };
698
699 scu: snoop-control-unit@ffffc000 {
700 compatible = "arm,cortex-a9-scu";
701 reg = <0xffffc000 0x100>;
702 };
703
704 sysmgr: sysmgr@ffd06000 {
705 compatible = "altr,sys-mgr", "syscon";
706 reg = <0xffd06000 0x300>;
707 cpu1-start-addr = <0xffd06230>;
708 };
709
710 /* Local timer */
711 timer@ffffc600 {
712 compatible = "arm,cortex-a9-twd-timer";
713 reg = <0xffffc600 0x100>;
714 interrupts = <1 13 0xf04>;
715 clocks = <&mpu_periph_clk>;
716 };
717
718 timer0: timer0@ffc02700 {
719 compatible = "snps,dw-apb-timer";
720 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
721 reg = <0xffc02700 0x100>;
722 clocks = <&l4_sp_clk>;
723 clock-names = "timer";
724 };
725
726 timer1: timer1@ffc02800 {
727 compatible = "snps,dw-apb-timer";
728 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
729 reg = <0xffc02800 0x100>;
730 clocks = <&l4_sp_clk>;
731 clock-names = "timer";
732 };
733
734 timer2: timer2@ffd00000 {
735 compatible = "snps,dw-apb-timer";
736 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
737 reg = <0xffd00000 0x100>;
738 clocks = <&l4_sys_free_clk>;
739 clock-names = "timer";
740 };
741
742 timer3: timer3@ffd00100 {
743 compatible = "snps,dw-apb-timer";
744 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
745 reg = <0xffd01000 0x100>;
746 clocks = <&l4_sys_free_clk>;
747 clock-names = "timer";
748 };
749
750 uart0: serial0@ffc02000 {
751 compatible = "snps,dw-apb-uart";
752 reg = <0xffc02000 0x100>;
753 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
754 reg-shift = <2>;
755 reg-io-width = <4>;
756 clocks = <&l4_sp_clk>;
757 status = "disabled";
758 };
759
760 uart1: serial1@ffc02100 {
761 compatible = "snps,dw-apb-uart";
762 reg = <0xffc02100 0x100>;
763 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
764 reg-shift = <2>;
765 reg-io-width = <4>;
766 clocks = <&l4_sp_clk>;
767 status = "disabled";
768 };
769
770 usbphy0: usbphy@0 {
771 #phy-cells = <0>;
772 compatible = "usb-nop-xceiv";
773 status = "okay";
774 };
775
776 usb0: usb@ffb00000 {
777 compatible = "snps,dwc2";
778 reg = <0xffb00000 0xffff>;
779 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&usb_clk>;
781 clock-names = "otg";
782 resets = <&rst USB0_RESET>;
783 reset-names = "dwc2";
784 phys = <&usbphy0>;
785 phy-names = "usb2-phy";
786 status = "disabled";
787 };
788
789 usb1: usb@ffb40000 {
790 compatible = "snps,dwc2";
791 reg = <0xffb40000 0xffff>;
792 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&usb_clk>;
794 clock-names = "otg";
795 resets = <&rst USB1_RESET>;
796 reset-names = "dwc2";
797 phys = <&usbphy0>;
798 phy-names = "usb2-phy";
799 status = "disabled";
800 };
801
802 watchdog0: watchdog@ffd00200 {
803 compatible = "snps,dw-wdt";
804 reg = <0xffd00200 0x100>;
805 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&l4_sys_free_clk>;
807 status = "disabled";
808 };
809
810 watchdog1: watchdog@ffd00300 {
811 compatible = "snps,dw-wdt";
812 reg = <0xffd00300 0x100>;
813 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&l4_sys_free_clk>;
815 status = "disabled";
816 };
817 };
818};