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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8960.h>
6#include <dt-bindings/clock/qcom,lcc-msm8960.h>
7#include <dt-bindings/mfd/qcom-rpm.h>
8#include <dt-bindings/soc/qcom,gsbi.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 model = "Qualcomm MSM8960";
14 compatible = "qcom,msm8960";
15 interrupt-parent = <&intc>;
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20 interrupts = <GIC_PPI 14 0x304>;
21
22 cpu@0 {
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
25 device_type = "cpu";
26 reg = <0>;
27 next-level-cache = <&L2>;
28 qcom,acc = <&acc0>;
29 qcom,saw = <&saw0>;
30 };
31
32 cpu@1 {
33 compatible = "qcom,krait";
34 enable-method = "qcom,kpss-acc-v1";
35 device_type = "cpu";
36 reg = <1>;
37 next-level-cache = <&L2>;
38 qcom,acc = <&acc1>;
39 qcom,saw = <&saw1>;
40 };
41
42 L2: l2-cache {
43 compatible = "cache";
44 cache-level = <2>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 reg = <0x0 0x0>;
51 };
52
53 cpu-pmu {
54 compatible = "qcom,krait-pmu";
55 interrupts = <GIC_PPI 10 0x304>;
56 qcom,no-pc-write;
57 };
58
59 clocks {
60 cxo_board: cxo_board {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <19200000>;
64 clock-output-names = "cxo_board";
65 };
66
67 pxo_board: pxo_board {
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <27000000>;
71 clock-output-names = "pxo_board";
72 };
73
74 sleep_clk {
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <32768>;
78 clock-output-names = "sleep_clk";
79 };
80 };
81
82 /* Temporary fixed regulator */
83 vsdcc_fixed: vsdcc-regulator {
84 compatible = "regulator-fixed";
85 regulator-name = "SDCC Power";
86 regulator-min-microvolt = <2700000>;
87 regulator-max-microvolt = <2700000>;
88 regulator-always-on;
89 };
90
91 soc: soc {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges;
95 compatible = "simple-bus";
96
97 intc: interrupt-controller@2000000 {
98 compatible = "qcom,msm-qgic2";
99 interrupt-controller;
100 #interrupt-cells = <3>;
101 reg = <0x02000000 0x1000>,
102 <0x02002000 0x1000>;
103 };
104
105 timer@200a000 {
106 compatible = "qcom,kpss-timer",
107 "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
108 interrupts = <GIC_PPI 1 0x301>,
109 <GIC_PPI 2 0x301>,
110 <GIC_PPI 3 0x301>;
111 reg = <0x0200a000 0x100>;
112 clock-frequency = <27000000>,
113 <32768>;
114 cpu-offset = <0x80000>;
115 };
116
117 msmgpio: pinctrl@800000 {
118 compatible = "qcom,msm8960-pinctrl";
119 gpio-controller;
120 gpio-ranges = <&msmgpio 0 0 152>;
121 #gpio-cells = <2>;
122 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
123 interrupt-controller;
124 #interrupt-cells = <2>;
125 reg = <0x800000 0x4000>;
126 };
127
128 gcc: clock-controller@900000 {
129 compatible = "qcom,gcc-msm8960";
130 #clock-cells = <1>;
131 #power-domain-cells = <1>;
132 #reset-cells = <1>;
133 reg = <0x900000 0x4000>;
134 clocks = <&cxo_board>,
135 <&pxo_board>,
136 <&lcc PLL4>;
137 clock-names = "cxo", "pxo", "pll4";
138 };
139
140 lcc: clock-controller@28000000 {
141 compatible = "qcom,lcc-msm8960";
142 reg = <0x28000000 0x1000>;
143 #clock-cells = <1>;
144 #reset-cells = <1>;
145 clocks = <&pxo_board>,
146 <&gcc PLL4_VOTE>,
147 <0>,
148 <0>, <0>,
149 <0>, <0>,
150 <0>;
151 clock-names = "pxo",
152 "pll4_vote",
153 "mi2s_codec_clk",
154 "codec_i2s_mic_codec_clk",
155 "spare_i2s_mic_codec_clk",
156 "codec_i2s_spkr_codec_clk",
157 "spare_i2s_spkr_codec_clk",
158 "pcm_codec_clk";
159 };
160
161 clock-controller@4000000 {
162 compatible = "qcom,mmcc-msm8960";
163 reg = <0x4000000 0x1000>;
164 #clock-cells = <1>;
165 #power-domain-cells = <1>;
166 #reset-cells = <1>;
167 clocks = <&pxo_board>,
168 <&gcc PLL3>,
169 <&gcc PLL8_VOTE>,
170 <0>,
171 <0>,
172 <0>,
173 <0>,
174 <0>;
175 clock-names = "pxo",
176 "pll3",
177 "pll8_vote",
178 "dsi1pll",
179 "dsi1pllbyte",
180 "dsi2pll",
181 "dsi2pllbyte",
182 "hdmipll";
183 };
184
185 l2cc: clock-controller@2011000 {
186 compatible = "qcom,kpss-gcc", "syscon";
187 reg = <0x2011000 0x1000>;
188 };
189
190 rpm: rpm@108000 {
191 compatible = "qcom,rpm-msm8960";
192 reg = <0x108000 0x1000>;
193 qcom,ipc = <&l2cc 0x8 2>;
194
195 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
196 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
197 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
198 interrupt-names = "ack", "err", "wakeup";
199
200 regulators {
201 compatible = "qcom,rpm-pm8921-regulators";
202 };
203 };
204
205 acc0: clock-controller@2088000 {
206 compatible = "qcom,kpss-acc-v1";
207 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
208 };
209
210 acc1: clock-controller@2098000 {
211 compatible = "qcom,kpss-acc-v1";
212 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
213 };
214
215 saw0: regulator@2089000 {
216 compatible = "qcom,saw2";
217 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
218 regulator;
219 };
220
221 saw1: regulator@2099000 {
222 compatible = "qcom,saw2";
223 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
224 regulator;
225 };
226
227 gsbi5: gsbi@16400000 {
228 compatible = "qcom,gsbi-v1.0.0";
229 cell-index = <5>;
230 reg = <0x16400000 0x100>;
231 clocks = <&gcc GSBI5_H_CLK>;
232 clock-names = "iface";
233 #address-cells = <1>;
234 #size-cells = <1>;
235 ranges;
236
237 syscon-tcsr = <&tcsr>;
238
239 gsbi5_serial: serial@16440000 {
240 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
241 reg = <0x16440000 0x1000>,
242 <0x16400000 0x1000>;
243 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
245 clock-names = "core", "iface";
246 status = "disabled";
247 };
248 };
249
250 ssbi@500000 {
251 compatible = "qcom,ssbi";
252 reg = <0x500000 0x1000>;
253 qcom,controller-type = "pmic-arbiter";
254
255 pmicintc: pmic {
256 compatible = "qcom,pm8921";
257 interrupt-parent = <&msmgpio>;
258 interrupts = <104 IRQ_TYPE_LEVEL_LOW>;
259 #interrupt-cells = <2>;
260 interrupt-controller;
261 #address-cells = <1>;
262 #size-cells = <0>;
263
264 pwrkey@1c {
265 compatible = "qcom,pm8921-pwrkey";
266 reg = <0x1c>;
267 interrupt-parent = <&pmicintc>;
268 interrupts = <50 IRQ_TYPE_EDGE_RISING>,
269 <51 IRQ_TYPE_EDGE_RISING>;
270 debounce = <15625>;
271 pull-up;
272 };
273
274 keypad@148 {
275 compatible = "qcom,pm8921-keypad";
276 reg = <0x148>;
277 interrupt-parent = <&pmicintc>;
278 interrupts = <74 IRQ_TYPE_EDGE_RISING>,
279 <75 IRQ_TYPE_EDGE_RISING>;
280 debounce = <15>;
281 scan-delay = <32>;
282 row-hold = <91500>;
283 };
284
285 rtc@11d {
286 compatible = "qcom,pm8921-rtc";
287 interrupt-parent = <&pmicintc>;
288 interrupts = <39 IRQ_TYPE_EDGE_RISING>;
289 reg = <0x11d>;
290 allow-set-time;
291 };
292 };
293 };
294
295 rng@1a500000 {
296 compatible = "qcom,prng";
297 reg = <0x1a500000 0x200>;
298 clocks = <&gcc PRNG_CLK>;
299 clock-names = "core";
300 };
301
302 sdcc3: mmc@12180000 {
303 compatible = "arm,pl18x", "arm,primecell";
304 arm,primecell-periphid = <0x00051180>;
305 status = "disabled";
306 reg = <0x12180000 0x8000>;
307 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
309 clock-names = "mclk", "apb_pclk";
310 bus-width = <4>;
311 cap-sd-highspeed;
312 cap-mmc-highspeed;
313 max-frequency = <192000000>;
314 no-1-8-v;
315 vmmc-supply = <&vsdcc_fixed>;
316 };
317
318 sdcc1: mmc@12400000 {
319 status = "disabled";
320 compatible = "arm,pl18x", "arm,primecell";
321 arm,primecell-periphid = <0x00051180>;
322 reg = <0x12400000 0x8000>;
323 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
325 clock-names = "mclk", "apb_pclk";
326 bus-width = <8>;
327 max-frequency = <96000000>;
328 non-removable;
329 cap-sd-highspeed;
330 cap-mmc-highspeed;
331 vmmc-supply = <&vsdcc_fixed>;
332 };
333
334 tcsr: syscon@1a400000 {
335 compatible = "qcom,tcsr-msm8960", "syscon";
336 reg = <0x1a400000 0x100>;
337 };
338
339 gsbi1: gsbi@16000000 {
340 compatible = "qcom,gsbi-v1.0.0";
341 cell-index = <1>;
342 reg = <0x16000000 0x100>;
343 clocks = <&gcc GSBI1_H_CLK>;
344 clock-names = "iface";
345 #address-cells = <1>;
346 #size-cells = <1>;
347 ranges;
348
349 gsbi1_spi: spi@16080000 {
350 compatible = "qcom,spi-qup-v1.1.1";
351 #address-cells = <1>;
352 #size-cells = <0>;
353 reg = <0x16080000 0x1000>;
354 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
355 spi-max-frequency = <24000000>;
356 cs-gpios = <&msmgpio 8 0>;
357
358 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
359 clock-names = "core", "iface";
360 status = "disabled";
361 };
362 };
363 };
364};
1/dts-v1/;
2
3/include/ "skeleton.dtsi"
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8960.h>
7#include <dt-bindings/mfd/qcom-rpm.h>
8#include <dt-bindings/soc/qcom,gsbi.h>
9
10/ {
11 model = "Qualcomm MSM8960";
12 compatible = "qcom,msm8960";
13 interrupt-parent = <&intc>;
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18 interrupts = <1 14 0x304>;
19
20 cpu@0 {
21 compatible = "qcom,krait";
22 enable-method = "qcom,kpss-acc-v1";
23 device_type = "cpu";
24 reg = <0>;
25 next-level-cache = <&L2>;
26 qcom,acc = <&acc0>;
27 qcom,saw = <&saw0>;
28 };
29
30 cpu@1 {
31 compatible = "qcom,krait";
32 enable-method = "qcom,kpss-acc-v1";
33 device_type = "cpu";
34 reg = <1>;
35 next-level-cache = <&L2>;
36 qcom,acc = <&acc1>;
37 qcom,saw = <&saw1>;
38 };
39
40 L2: l2-cache {
41 compatible = "cache";
42 cache-level = <2>;
43 };
44 };
45
46 cpu-pmu {
47 compatible = "qcom,krait-pmu";
48 interrupts = <1 10 0x304>;
49 qcom,no-pc-write;
50 };
51
52 clocks {
53 cxo_board {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <19200000>;
57 clock-output-names = "cxo_board";
58 };
59
60 pxo_board {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <27000000>;
64 clock-output-names = "pxo_board";
65 };
66
67 sleep_clk {
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <32768>;
71 clock-output-names = "sleep_clk";
72 };
73 };
74
75 soc: soc {
76 #address-cells = <1>;
77 #size-cells = <1>;
78 ranges;
79 compatible = "simple-bus";
80
81 intc: interrupt-controller@2000000 {
82 compatible = "qcom,msm-qgic2";
83 interrupt-controller;
84 #interrupt-cells = <3>;
85 reg = <0x02000000 0x1000>,
86 <0x02002000 0x1000>;
87 };
88
89 timer@200a000 {
90 compatible = "qcom,kpss-timer",
91 "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
92 interrupts = <1 1 0x301>,
93 <1 2 0x301>,
94 <1 3 0x301>;
95 reg = <0x0200a000 0x100>;
96 clock-frequency = <27000000>,
97 <32768>;
98 cpu-offset = <0x80000>;
99 };
100
101 msmgpio: pinctrl@800000 {
102 compatible = "qcom,msm8960-pinctrl";
103 gpio-controller;
104 #gpio-cells = <2>;
105 interrupts = <0 16 0x4>;
106 interrupt-controller;
107 #interrupt-cells = <2>;
108 reg = <0x800000 0x4000>;
109 };
110
111 gcc: clock-controller@900000 {
112 compatible = "qcom,gcc-msm8960";
113 #clock-cells = <1>;
114 #reset-cells = <1>;
115 reg = <0x900000 0x4000>;
116 };
117
118 lcc: clock-controller@28000000 {
119 compatible = "qcom,lcc-msm8960";
120 reg = <0x28000000 0x1000>;
121 #clock-cells = <1>;
122 #reset-cells = <1>;
123 };
124
125 clock-controller@4000000 {
126 compatible = "qcom,mmcc-msm8960";
127 reg = <0x4000000 0x1000>;
128 #clock-cells = <1>;
129 #reset-cells = <1>;
130 };
131
132 l2cc: clock-controller@2011000 {
133 compatible = "syscon";
134 reg = <0x2011000 0x1000>;
135 };
136
137 rpm@108000 {
138 compatible = "qcom,rpm-msm8960";
139 reg = <0x108000 0x1000>;
140 qcom,ipc = <&l2cc 0x8 2>;
141
142 interrupts = <0 19 0>, <0 21 0>, <0 22 0>;
143 interrupt-names = "ack", "err", "wakeup";
144
145 regulators {
146 compatible = "qcom,rpm-pm8921-regulators";
147 };
148 };
149
150 acc0: clock-controller@2088000 {
151 compatible = "qcom,kpss-acc-v1";
152 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
153 };
154
155 acc1: clock-controller@2098000 {
156 compatible = "qcom,kpss-acc-v1";
157 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
158 };
159
160 saw0: regulator@2089000 {
161 compatible = "qcom,saw2";
162 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
163 regulator;
164 };
165
166 saw1: regulator@2099000 {
167 compatible = "qcom,saw2";
168 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
169 regulator;
170 };
171
172 gsbi5: gsbi@16400000 {
173 compatible = "qcom,gsbi-v1.0.0";
174 cell-index = <5>;
175 reg = <0x16400000 0x100>;
176 clocks = <&gcc GSBI5_H_CLK>;
177 clock-names = "iface";
178 #address-cells = <1>;
179 #size-cells = <1>;
180 ranges;
181
182 syscon-tcsr = <&tcsr>;
183
184 gsbi5_serial: serial@16440000 {
185 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
186 reg = <0x16440000 0x1000>,
187 <0x16400000 0x1000>;
188 interrupts = <0 154 0x0>;
189 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
190 clock-names = "core", "iface";
191 status = "disabled";
192 };
193 };
194
195 qcom,ssbi@500000 {
196 compatible = "qcom,ssbi";
197 reg = <0x500000 0x1000>;
198 qcom,controller-type = "pmic-arbiter";
199
200 pmicintc: pmic@0 {
201 compatible = "qcom,pm8921";
202 interrupt-parent = <&msmgpio>;
203 interrupts = <104 8>;
204 #interrupt-cells = <2>;
205 interrupt-controller;
206 #address-cells = <1>;
207 #size-cells = <0>;
208
209 pwrkey@1c {
210 compatible = "qcom,pm8921-pwrkey";
211 reg = <0x1c>;
212 interrupt-parent = <&pmicintc>;
213 interrupts = <50 1>, <51 1>;
214 debounce = <15625>;
215 pull-up;
216 };
217
218 keypad@148 {
219 compatible = "qcom,pm8921-keypad";
220 reg = <0x148>;
221 interrupt-parent = <&pmicintc>;
222 interrupts = <74 1>, <75 1>;
223 debounce = <15>;
224 scan-delay = <32>;
225 row-hold = <91500>;
226 };
227
228 rtc@11d {
229 compatible = "qcom,pm8921-rtc";
230 interrupt-parent = <&pmicintc>;
231 interrupts = <39 1>;
232 reg = <0x11d>;
233 allow-set-time;
234 };
235 };
236 };
237
238 rng@1a500000 {
239 compatible = "qcom,prng";
240 reg = <0x1a500000 0x200>;
241 clocks = <&gcc PRNG_CLK>;
242 clock-names = "core";
243 };
244
245 /* Temporary fixed regulator */
246 vsdcc_fixed: vsdcc-regulator {
247 compatible = "regulator-fixed";
248 regulator-name = "SDCC Power";
249 regulator-min-microvolt = <2700000>;
250 regulator-max-microvolt = <2700000>;
251 regulator-always-on;
252 };
253
254 amba {
255 compatible = "simple-bus";
256 #address-cells = <1>;
257 #size-cells = <1>;
258 ranges;
259 sdcc1: sdcc@12400000 {
260 status = "disabled";
261 compatible = "arm,pl18x", "arm,primecell";
262 arm,primecell-periphid = <0x00051180>;
263 reg = <0x12400000 0x8000>;
264 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
265 interrupt-names = "cmd_irq";
266 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
267 clock-names = "mclk", "apb_pclk";
268 bus-width = <8>;
269 max-frequency = <96000000>;
270 non-removable;
271 cap-sd-highspeed;
272 cap-mmc-highspeed;
273 vmmc-supply = <&vsdcc_fixed>;
274 };
275
276 sdcc3: sdcc@12180000 {
277 compatible = "arm,pl18x", "arm,primecell";
278 arm,primecell-periphid = <0x00051180>;
279 status = "disabled";
280 reg = <0x12180000 0x8000>;
281 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
282 interrupt-names = "cmd_irq";
283 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
284 clock-names = "mclk", "apb_pclk";
285 bus-width = <4>;
286 cap-sd-highspeed;
287 cap-mmc-highspeed;
288 max-frequency = <192000000>;
289 no-1-8-v;
290 vmmc-supply = <&vsdcc_fixed>;
291 };
292 };
293
294 tcsr: syscon@1a400000 {
295 compatible = "qcom,tcsr-msm8960", "syscon";
296 reg = <0x1a400000 0x100>;
297 };
298
299 gsbi@16000000 {
300 compatible = "qcom,gsbi-v1.0.0";
301 cell-index = <1>;
302 reg = <0x16000000 0x100>;
303 clocks = <&gcc GSBI1_H_CLK>;
304 clock-names = "iface";
305 #address-cells = <1>;
306 #size-cells = <1>;
307 ranges;
308
309 spi@16080000 {
310 compatible = "qcom,spi-qup-v1.1.1";
311 #address-cells = <1>;
312 #size-cells = <0>;
313 reg = <0x16080000 0x1000>;
314 interrupts = <0 147 0>;
315 spi-max-frequency = <24000000>;
316 cs-gpios = <&msmgpio 8 0>;
317
318 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
319 clock-names = "core", "iface";
320 status = "disabled";
321 };
322 };
323 };
324};