Loading...
Note: File does not exist in v4.10.11.
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/qcom,gcc-msm8974.h>
10#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/power/qcom-rpmpd.h>
13#include <dt-bindings/reset/qcom,gcc-msm8974.h>
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 interrupt-parent = <&intc>;
19
20 chosen { };
21
22 memory@0 {
23 device_type = "memory";
24 reg = <0x0 0x0>;
25 };
26
27 clocks {
28 xo_board: xo_board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <19200000>;
32 };
33
34 sleep_clk: sleep_clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <32768>;
38 };
39 };
40
41 firmware {
42 scm {
43 compatible = "qcom,scm-msm8226", "qcom,scm";
44 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
45 clock-names = "core", "bus", "iface";
46 };
47 };
48
49 reserved-memory {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53
54 smem_region: smem@3000000 {
55 reg = <0x3000000 0x100000>;
56 no-map;
57 };
58
59 adsp_region: adsp@dc00000 {
60 reg = <0x0dc00000 0x1900000>;
61 no-map;
62 };
63 };
64
65 smd {
66 compatible = "qcom,smd";
67
68 rpm {
69 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
70 qcom,ipc = <&apcs 8 0>;
71 qcom,smd-edge = <15>;
72
73 rpm_requests: rpm-requests {
74 compatible = "qcom,rpm-msm8226";
75 qcom,smd-channels = "rpm_requests";
76
77 rpmpd: power-controller {
78 compatible = "qcom,msm8226-rpmpd";
79 #power-domain-cells = <1>;
80 operating-points-v2 = <&rpmpd_opp_table>;
81
82 rpmpd_opp_table: opp-table {
83 compatible = "operating-points-v2";
84
85 rpmpd_opp_ret: opp1 {
86 opp-level = <1>;
87 };
88 rpmpd_opp_svs_krait: opp2 {
89 opp-level = <2>;
90 };
91 rpmpd_opp_svs_soc: opp3 {
92 opp-level = <3>;
93 };
94 rpmpd_opp_nom: opp4 {
95 opp-level = <4>;
96 };
97 rpmpd_opp_turbo: opp5 {
98 opp-level = <5>;
99 };
100 rpmpd_opp_super_turbo: opp6 {
101 opp-level = <6>;
102 };
103 };
104 };
105 };
106 };
107 };
108
109 smem {
110 compatible = "qcom,smem";
111
112 memory-region = <&smem_region>;
113 qcom,rpm-msg-ram = <&rpm_msg_ram>;
114
115 hwlocks = <&tcsr_mutex 3>;
116 };
117
118 smp2p-adsp {
119 compatible = "qcom,smp2p";
120 qcom,smem = <443>, <429>;
121
122 interrupt-parent = <&intc>;
123 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
124
125 qcom,ipc = <&apcs 8 10>;
126
127 qcom,local-pid = <0>;
128 qcom,remote-pid = <2>;
129
130 adsp_smp2p_out: master-kernel {
131 qcom,entry-name = "master-kernel";
132 #qcom,smem-state-cells = <1>;
133 };
134
135 adsp_smp2p_in: slave-kernel {
136 qcom,entry-name = "slave-kernel";
137
138 interrupt-controller;
139 #interrupt-cells = <2>;
140 };
141 };
142
143 soc: soc {
144 compatible = "simple-bus";
145 #address-cells = <1>;
146 #size-cells = <1>;
147 ranges;
148
149 intc: interrupt-controller@f9000000 {
150 compatible = "qcom,msm-qgic2";
151 reg = <0xf9000000 0x1000>,
152 <0xf9002000 0x1000>;
153 interrupt-controller;
154 #interrupt-cells = <3>;
155 };
156
157 apcs: syscon@f9011000 {
158 compatible = "syscon";
159 reg = <0xf9011000 0x1000>;
160 };
161
162 sdhc_1: mmc@f9824900 {
163 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
164 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
165 reg-names = "hc", "core";
166 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
168 interrupt-names = "hc_irq", "pwr_irq";
169 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
170 <&gcc GCC_SDCC1_APPS_CLK>,
171 <&xo_board>;
172 clock-names = "iface", "core", "xo";
173 pinctrl-names = "default";
174 pinctrl-0 = <&sdhc1_default_state>;
175 status = "disabled";
176 };
177
178 sdhc_2: mmc@f98a4900 {
179 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
180 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
181 reg-names = "hc", "core";
182 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
184 interrupt-names = "hc_irq", "pwr_irq";
185 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
186 <&gcc GCC_SDCC2_APPS_CLK>,
187 <&xo_board>;
188 clock-names = "iface", "core", "xo";
189 pinctrl-names = "default";
190 pinctrl-0 = <&sdhc2_default_state>;
191 status = "disabled";
192 };
193
194 sdhc_3: mmc@f9864900 {
195 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
196 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
197 reg-names = "hc", "core";
198 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
200 interrupt-names = "hc_irq", "pwr_irq";
201 clocks = <&gcc GCC_SDCC3_AHB_CLK>,
202 <&gcc GCC_SDCC3_APPS_CLK>,
203 <&xo_board>;
204 clock-names = "iface", "core", "xo";
205 pinctrl-names = "default";
206 pinctrl-0 = <&sdhc3_default_state>;
207 status = "disabled";
208 };
209
210 blsp1_uart1: serial@f991d000 {
211 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
212 reg = <0xf991d000 0x1000>;
213 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
215 clock-names = "core", "iface";
216 status = "disabled";
217 };
218
219 blsp1_uart3: serial@f991f000 {
220 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
221 reg = <0xf991f000 0x1000>;
222 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
224 clock-names = "core", "iface";
225 status = "disabled";
226 };
227
228 blsp1_uart4: serial@f9920000 {
229 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
230 reg = <0xf9920000 0x1000>;
231 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
233 clock-names = "core", "iface";
234 status = "disabled";
235 };
236
237 blsp1_i2c1: i2c@f9923000 {
238 status = "disabled";
239 compatible = "qcom,i2c-qup-v2.1.1";
240 reg = <0xf9923000 0x1000>;
241 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
243 clock-names = "core", "iface";
244 pinctrl-names = "default";
245 pinctrl-0 = <&blsp1_i2c1_pins>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 };
249
250 blsp1_i2c2: i2c@f9924000 {
251 status = "disabled";
252 compatible = "qcom,i2c-qup-v2.1.1";
253 reg = <0xf9924000 0x1000>;
254 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
256 clock-names = "core", "iface";
257 pinctrl-names = "default";
258 pinctrl-0 = <&blsp1_i2c2_pins>;
259 #address-cells = <1>;
260 #size-cells = <0>;
261 };
262
263 blsp1_i2c3: i2c@f9925000 {
264 status = "disabled";
265 compatible = "qcom,i2c-qup-v2.1.1";
266 reg = <0xf9925000 0x1000>;
267 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
269 clock-names = "core", "iface";
270 pinctrl-names = "default";
271 pinctrl-0 = <&blsp1_i2c3_pins>;
272 #address-cells = <1>;
273 #size-cells = <0>;
274 };
275
276 blsp1_i2c4: i2c@f9926000 {
277 status = "disabled";
278 compatible = "qcom,i2c-qup-v2.1.1";
279 reg = <0xf9926000 0x1000>;
280 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
282 clock-names = "core", "iface";
283 pinctrl-names = "default";
284 pinctrl-0 = <&blsp1_i2c4_pins>;
285 #address-cells = <1>;
286 #size-cells = <0>;
287 };
288
289 blsp1_i2c5: i2c@f9927000 {
290 status = "disabled";
291 compatible = "qcom,i2c-qup-v2.1.1";
292 reg = <0xf9927000 0x1000>;
293 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
295 clock-names = "core", "iface";
296 pinctrl-names = "default";
297 pinctrl-0 = <&blsp1_i2c5_pins>;
298 #address-cells = <1>;
299 #size-cells = <0>;
300 };
301
302 cci: cci@fda0c000 {
303 compatible = "qcom,msm8226-cci";
304 #address-cells = <1>;
305 #size-cells = <0>;
306 reg = <0xfda0c000 0x1000>;
307 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
308 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
309 <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
310 <&mmcc CAMSS_CCI_CCI_CLK>;
311 clock-names = "camss_top_ahb",
312 "cci_ahb",
313 "cci";
314
315 pinctrl-names = "default", "sleep";
316 pinctrl-0 = <&cci_default>;
317 pinctrl-1 = <&cci_sleep>;
318
319 status = "disabled";
320
321 cci_i2c0: i2c-bus@0 {
322 reg = <0>;
323 clock-frequency = <400000>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326 };
327 };
328
329 usb: usb@f9a55000 {
330 compatible = "qcom,ci-hdrc";
331 reg = <0xf9a55000 0x200>,
332 <0xf9a55200 0x200>;
333 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
335 <&gcc GCC_USB_HS_SYSTEM_CLK>;
336 clock-names = "iface", "core";
337 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
338 assigned-clock-rates = <75000000>;
339 resets = <&gcc GCC_USB_HS_BCR>;
340 reset-names = "core";
341 phy_type = "ulpi";
342 dr_mode = "otg";
343 hnp-disable;
344 srp-disable;
345 adp-disable;
346 ahb-burst-config = <0>;
347 phy-names = "usb-phy";
348 phys = <&usb_hs_phy>;
349 status = "disabled";
350 #reset-cells = <1>;
351
352 ulpi {
353 usb_hs_phy: phy {
354 compatible = "qcom,usb-hs-phy-msm8226",
355 "qcom,usb-hs-phy";
356 #phy-cells = <0>;
357 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
358 clock-names = "ref", "sleep";
359 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
360 reset-names = "phy", "por";
361 qcom,init-seq = /bits/ 8 <0x0 0x44
362 0x1 0x68 0x2 0x24 0x3 0x13>;
363 };
364 };
365 };
366
367 gcc: clock-controller@fc400000 {
368 compatible = "qcom,gcc-msm8226";
369 reg = <0xfc400000 0x4000>;
370 #clock-cells = <1>;
371 #reset-cells = <1>;
372 #power-domain-cells = <1>;
373 };
374
375 mmcc: clock-controller@fd8c0000 {
376 compatible = "qcom,mmcc-msm8226";
377 reg = <0xfd8c0000 0x6000>;
378 #clock-cells = <1>;
379 #reset-cells = <1>;
380 #power-domain-cells = <1>;
381 };
382
383 tlmm: pinctrl@fd510000 {
384 compatible = "qcom,msm8226-pinctrl";
385 reg = <0xfd510000 0x4000>;
386 gpio-controller;
387 #gpio-cells = <2>;
388 gpio-ranges = <&tlmm 0 0 117>;
389 interrupt-controller;
390 #interrupt-cells = <2>;
391 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
392
393 blsp1_i2c1_pins: blsp1-i2c1-state {
394 pins = "gpio2", "gpio3";
395 function = "blsp_i2c1";
396 drive-strength = <2>;
397 bias-disable;
398 };
399
400 blsp1_i2c2_pins: blsp1-i2c2-state {
401 pins = "gpio6", "gpio7";
402 function = "blsp_i2c2";
403 drive-strength = <2>;
404 bias-disable;
405 };
406
407 blsp1_i2c3_pins: blsp1-i2c3-state {
408 pins = "gpio10", "gpio11";
409 function = "blsp_i2c3";
410 drive-strength = <2>;
411 bias-disable;
412 };
413
414 blsp1_i2c4_pins: blsp1-i2c4-state {
415 pins = "gpio14", "gpio15";
416 function = "blsp_i2c4";
417 drive-strength = <2>;
418 bias-disable;
419 };
420
421 blsp1_i2c5_pins: blsp1-i2c5-state {
422 pins = "gpio18", "gpio19";
423 function = "blsp_i2c5";
424 drive-strength = <2>;
425 bias-disable;
426 };
427
428 cci_default: cci-default-state {
429 pins = "gpio29", "gpio30";
430 function = "cci_i2c0";
431
432 drive-strength = <2>;
433 bias-disable;
434 };
435
436 cci_sleep: cci-sleep-state {
437 pins = "gpio29", "gpio30";
438 function = "gpio";
439
440 drive-strength = <2>;
441 bias-disable;
442 };
443
444 sdhc1_default_state: sdhc1-default-state {
445 clk-pins {
446 pins = "sdc1_clk";
447 drive-strength = <10>;
448 bias-disable;
449 };
450
451 cmd-data-pins {
452 pins = "sdc1_cmd", "sdc1_data";
453 drive-strength = <10>;
454 bias-pull-up;
455 };
456 };
457
458 sdhc2_default_state: sdhc2-default-state {
459 clk-pins {
460 pins = "sdc2_clk";
461 drive-strength = <10>;
462 bias-disable;
463 };
464
465 cmd-data-pins {
466 pins = "sdc2_cmd", "sdc2_data";
467 drive-strength = <10>;
468 bias-pull-up;
469 };
470 };
471
472 sdhc3_default_state: sdhc3-default-state {
473 clk-pins {
474 pins = "gpio44";
475 function = "sdc3";
476 drive-strength = <8>;
477 bias-disable;
478 };
479
480 cmd-pins {
481 pins = "gpio43";
482 function = "sdc3";
483 drive-strength = <8>;
484 bias-pull-up;
485 };
486
487 data-pins {
488 pins = "gpio39", "gpio40", "gpio41", "gpio42";
489 function = "sdc3";
490 drive-strength = <8>;
491 bias-pull-up;
492 };
493 };
494 };
495
496 restart@fc4ab000 {
497 compatible = "qcom,pshold";
498 reg = <0xfc4ab000 0x4>;
499 };
500
501 spmi_bus: spmi@fc4cf000 {
502 compatible = "qcom,spmi-pmic-arb";
503 reg-names = "core", "intr", "cnfg";
504 reg = <0xfc4cf000 0x1000>,
505 <0xfc4cb000 0x1000>,
506 <0xfc4ca000 0x1000>;
507 interrupt-names = "periph_irq";
508 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
509 qcom,ee = <0>;
510 qcom,channel = <0>;
511 #address-cells = <2>;
512 #size-cells = <0>;
513 interrupt-controller;
514 #interrupt-cells = <4>;
515 };
516
517 rng@f9bff000 {
518 compatible = "qcom,prng";
519 reg = <0xf9bff000 0x200>;
520 clocks = <&gcc GCC_PRNG_AHB_CLK>;
521 clock-names = "core";
522 };
523
524 timer@f9020000 {
525 compatible = "arm,armv7-timer-mem";
526 reg = <0xf9020000 0x1000>;
527 #address-cells = <1>;
528 #size-cells = <1>;
529 ranges;
530
531 frame@f9021000 {
532 frame-number = <0>;
533 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
535 reg = <0xf9021000 0x1000>,
536 <0xf9022000 0x1000>;
537 };
538
539 frame@f9023000 {
540 frame-number = <1>;
541 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
542 reg = <0xf9023000 0x1000>;
543 status = "disabled";
544 };
545
546 frame@f9024000 {
547 frame-number = <2>;
548 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
549 reg = <0xf9024000 0x1000>;
550 status = "disabled";
551 };
552
553 frame@f9025000 {
554 frame-number = <3>;
555 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
556 reg = <0xf9025000 0x1000>;
557 status = "disabled";
558 };
559
560 frame@f9026000 {
561 frame-number = <4>;
562 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
563 reg = <0xf9026000 0x1000>;
564 status = "disabled";
565 };
566
567 frame@f9027000 {
568 frame-number = <5>;
569 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
570 reg = <0xf9027000 0x1000>;
571 status = "disabled";
572 };
573
574 frame@f9028000 {
575 frame-number = <6>;
576 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
577 reg = <0xf9028000 0x1000>;
578 status = "disabled";
579 };
580 };
581
582 rpm_msg_ram: sram@fc428000 {
583 compatible = "qcom,rpm-msg-ram";
584 reg = <0xfc428000 0x4000>;
585 };
586
587 tcsr_mutex: hwlock@fd484000 {
588 compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
589 reg = <0xfd484000 0x1000>;
590 #hwlock-cells = <1>;
591 };
592
593 adsp: remoteproc@fe200000 {
594 compatible = "qcom,msm8226-adsp-pil";
595 reg = <0xfe200000 0x100>;
596
597 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
598 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
599 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
600 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
601 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
602 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
603
604 power-domains = <&rpmpd MSM8226_VDDCX>;
605 power-domain-names = "cx";
606
607 clocks = <&xo_board>;
608 clock-names = "xo";
609
610 memory-region = <&adsp_region>;
611
612 qcom,smem-states = <&adsp_smp2p_out 0>;
613 qcom,smem-state-names = "stop";
614
615 status = "disabled";
616
617 smd-edge {
618 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
619
620 qcom,ipc = <&apcs 8 8>;
621 qcom,smd-edge = <1>;
622
623 label = "lpass";
624 };
625 };
626 };
627
628 timer {
629 compatible = "arm,armv7-timer";
630 interrupts = <GIC_PPI 2
631 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
632 <GIC_PPI 3
633 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
634 <GIC_PPI 4
635 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
636 <GIC_PPI 1
637 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
638 };
639};