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v6.2
  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Device Tree for the ARM Integrator/CP platform
  4 */
  5
  6/dts-v1/;
  7/include/ "integrator.dtsi"
  8
  9/ {
 10	model = "ARM Integrator/CP";
 11	compatible = "arm,integrator-cp";
 12
 13	chosen {
 14		bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
 15	};
 16
 17	cpus {
 18		#address-cells = <1>;
 19		#size-cells = <0>;
 20
 21		cpu@0 {
 22			device_type = "cpu";
 23			/*
 24			 * Since the board has pluggable CPU modules, we
 25			 * cannot define a proper compatible here. Let the
 26			 * boot loader fill in the apropriate compatible
 27			 * string if necessary.
 28			 */
 29			/* compatible = "arm,arm920t"; */
 30			reg = <0>;
 31			/*
 32			 * TBD comment.
 33			 */
 34					 /* kHz     uV   */
 35			operating-points = <50000  0
 36					    48000  0>;
 37			clocks = <&cmcore>;
 38			clock-names = "cpu";
 39			clock-latency = <1000000>; /* 1 ms */
 40		};
 41	};
 42
 43	/*
 44	 * The Integrator/CP overall clocking architecture can be found in
 45	 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
 46	 * appear to illustrate the layout used in most configurations.
 47	 */
 48
 49	/* The codec chrystal operates at 24.576 MHz */
 50	xtal_codec: xtal24.576@24.576M {
 51		#clock-cells = <0>;
 52		compatible = "fixed-clock";
 53		clock-frequency = <24576000>;
 54	};
 55
 56	/* The chrystal is divided by 2 by the codec for the AACI bit clock */
 57	aaci_bitclk: aaci_bitclk@12.288M {
 58		#clock-cells = <0>;
 59		compatible = "fixed-factor-clock";
 60		clock-div = <2>;
 61		clock-mult = <1>;
 62		clocks = <&xtal_codec>;
 63	};
 64
 65	/* This is a 25MHz chrystal on the base board */
 66	xtal25mhz: xtal25mhz@25M {
 67		#clock-cells = <0>;
 68		compatible = "fixed-clock";
 69		clock-frequency = <25000000>;
 70	};
 71
 72	/* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
 73	uartclk: uartclk@14.74M {
 74		#clock-cells = <0>;
 75		compatible = "fixed-clock";
 76		clock-frequency = <14745600>;
 77	};
 78
 79	/* Actually sysclk I think */
 80	pclk: pclk@0 {
 81		#clock-cells = <0>;
 82		compatible = "fixed-clock";
 83		clock-frequency = <0>;
 84	};
 85
 86	core-module@10000000 {
 87		/* 24 MHz chrystal on the core module */
 88		cm24mhz: cm24mhz@24M {
 89			#clock-cells = <0>;
 90			compatible = "fixed-clock";
 91			clock-frequency = <24000000>;
 92		};
 93
 94		/* Oscillator on the core module, clocks the CPU core */
 95		cmcore: clock-controller@8 {
 96			compatible = "arm,syscon-icst525-integratorcp-cm-core";
 97			reg = <0x08 0x04>;
 98			#clock-cells = <0>;
 99			lock-offset = <0x14>;
100			vco-offset = <0x08>;
101			clocks = <&cm24mhz>;
102		};
103
104		/* Oscillator on the core module, clocks the memory bus */
105		cmmem: clock-controller@8,12 {
106			compatible = "arm,syscon-icst525-integratorcp-cm-mem";
107			reg = <0x08 0x04>;
108			#clock-cells = <0>;
109			lock-offset = <0x14>;
110			vco-offset = <0x08>;
111			clocks = <&cm24mhz>;
112		};
113
114		/* Auxilary oscillator on the core module, clocks the CLCD */
115		auxosc: clock-controller@1c {
116			compatible = "arm,syscon-icst525";
117			reg = <0x1c 0x04>;
118			#clock-cells = <0>;
119			lock-offset = <0x14>;
120			vco-offset = <0x1c>;
121			clocks = <&cm24mhz>;
122		};
123
124		/* The KMI clock is the 24 MHz oscillator divided to 8MHz */
125		kmiclk: kmiclk@1M {
126			#clock-cells = <0>;
127			compatible = "fixed-factor-clock";
128			clock-div = <3>;
129			clock-mult = <1>;
130			clocks = <&cm24mhz>;
131		};
132
133		/* The timer clock is the 24 MHz oscillator divided to 1MHz */
134		timclk: timclk@1M {
135			#clock-cells = <0>;
136			compatible = "fixed-factor-clock";
137			clock-div = <24>;
138			clock-mult = <1>;
139			clocks = <&cm24mhz>;
140		};
141	};
142
143	syscon {
144		compatible = "arm,integrator-cp-syscon", "syscon";
145		reg = <0xcb000000 0x100>;
146	};
147
148	timer0: timer@13000000 {
149		/* TIMER0 runs directly on the 25MHz chrystal */
150		compatible = "arm,integrator-cp-timer";
151		clocks = <&xtal25mhz>;
152	};
153
154	timer1: timer@13000100 {
155		/* TIMER1 runs @ 1MHz */
156		compatible = "arm,integrator-cp-timer";
157		clocks = <&timclk>;
158	};
159
160	timer2: timer@13000200 {
161		/* TIMER2 runs @ 1MHz */
162		compatible = "arm,integrator-cp-timer";
163		clocks = <&timclk>;
164	};
165
166	pic: pic@14000000 {
167		valid-mask = <0x1fc003ff>;
168	};
169
170	cic: cic@10000040 {
171		compatible = "arm,versatile-fpga-irq";
172		#interrupt-cells = <1>;
173		interrupt-controller;
174		reg = <0x10000040 0x100>;
175		clear-mask = <0xffffffff>;
176		valid-mask = <0x00000007>;
177	};
178
179	/* The SIC is cascaded off IRQ 26 on the PIC */
180	sic: sic@ca000000 {
181		compatible = "arm,versatile-fpga-irq";
182		interrupt-parent = <&pic>;
183		interrupts = <26>;
184		#interrupt-cells = <1>;
185		interrupt-controller;
186		reg = <0xca000000 0x100>;
187		clear-mask = <0x00000fff>;
188		valid-mask = <0x00000fff>;
189	};
190
191	ethernet@c8000000 {
192		compatible = "smsc,lan91c111";
193		reg = <0xc8000000 0x10>;
194		interrupt-parent = <&pic>;
195		interrupts = <27>;
196	};
197
198	bridge {
199		compatible = "ti,ths8134a", "ti,ths8134";
200		#address-cells = <1>;
201		#size-cells = <0>;
202
203		ports {
204			#address-cells = <1>;
205			#size-cells = <0>;
206
207			port@0 {
208				reg = <0>;
209
210				vga_bridge_in: endpoint {
211					remote-endpoint = <&clcd_pads_vga_dac>;
212				};
213			};
214
215			port@1 {
216				reg = <1>;
217
218				vga_bridge_out: endpoint {
219					remote-endpoint = <&vga_con_in>;
220				};
221			};
222		};
223	};
224
225	vga {
226		compatible = "vga-connector";
227
228		port {
229			vga_con_in: endpoint {
230				remote-endpoint = <&vga_bridge_out>;
231			};
232		};
233	};
234
235	fpga {
236		/*
237		 * These PrimeCells are at the same location and using
238		 * the same interrupts in all Integrators, but in the CP
239		 * slightly newer versions are deployed.
240		 */
241		rtc@15000000 {
242			compatible = "arm,pl031", "arm,primecell";
243			clocks = <&pclk>;
244			clock-names = "apb_pclk";
245		};
246
247		uart@16000000 {
248			compatible = "arm,pl011", "arm,primecell";
249			clocks = <&uartclk>, <&pclk>;
250			clock-names = "uartclk", "apb_pclk";
251		};
252
253		uart@17000000 {
254			compatible = "arm,pl011", "arm,primecell";
255			clocks = <&uartclk>, <&pclk>;
256			clock-names = "uartclk", "apb_pclk";
257		};
258
259		kmi@18000000 {
260			compatible = "arm,pl050", "arm,primecell";
261			clocks = <&kmiclk>, <&pclk>;
262			clock-names = "KMIREFCLK", "apb_pclk";
263		};
264
265		kmi@19000000 {
266			compatible = "arm,pl050", "arm,primecell";
267			clocks = <&kmiclk>, <&pclk>;
268			clock-names = "KMIREFCLK", "apb_pclk";
269		};
270
271		/*
272		 * These PrimeCells are only available on the Integrator/CP
273		 */
274		mmc@1c000000 {
275			compatible = "arm,pl180", "arm,primecell";
276			reg = <0x1c000000 0x1000>;
277			interrupts = <23 24>;
278			max-frequency = <515633>;
279			clocks = <&uartclk>, <&pclk>;
280			clock-names = "mclk", "apb_pclk";
281		};
282
283		aaci@1d000000 {
284			compatible = "arm,pl041", "arm,primecell";
285			reg = <0x1d000000 0x1000>;
286			interrupts = <25>;
287			clocks = <&pclk>;
288			clock-names = "apb_pclk";
289		};
290
291		clcd@c0000000 {
292			compatible = "arm,pl110", "arm,primecell";
293			reg = <0xC0000000 0x1000>;
294			interrupts = <22>;
295			clocks = <&auxosc>, <&pclk>;
296			clock-names = "clcdclk", "apb_pclk";
297			/* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
298			max-memory-bandwidth = <40000000>;
299
300			/*
301			 * This port is routed through a PLD (Programmable
302			 * Logic Device) that routes the output from the CLCD
303			 * (after transformations) to the VGA DAC and also an
304			 * external panel connector. The PLD is essential for
305			 * supporting RGB565/BGR565.
306			 *
307			 * The signals from the port thus reaches two endpoints.
308			 * The PLD is managed through a few special bits in the
309			 * FPGA "sysreg".
310			 *
311			 * This arrangement can be clearly seen in
312			 * ARM DUI 0225D, page 3-41, figure 3-19.
313			 */
314			port@0 {
315				clcd_pads_vga_dac: endpoint {
316					remote-endpoint = <&vga_bridge_in>;
317					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
318				};
319			};
320		};
321	};
322};
v4.10.11
 
  1/*
  2 * Device Tree for the ARM Integrator/CP platform
  3 */
  4
  5/dts-v1/;
  6/include/ "integrator.dtsi"
  7
  8/ {
  9	model = "ARM Integrator/CP";
 10	compatible = "arm,integrator-cp";
 11
 12	chosen {
 13		bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
 14	};
 15
 16	cpus {
 17		#address-cells = <1>;
 18		#size-cells = <0>;
 19
 20		cpu@0 {
 21			device_type = "cpu";
 22			/*
 23			 * Since the board has pluggable CPU modules, we
 24			 * cannot define a proper compatible here. Let the
 25			 * boot loader fill in the apropriate compatible
 26			 * string if necessary.
 27			 */
 28			/* compatible = "arm,arm920t"; */
 29			reg = <0>;
 30			/*
 31			 * TBD comment.
 32			 */
 33					 /* kHz     uV   */
 34			operating-points = <50000  0
 35					    48000  0>;
 36			clocks = <&cmcore>;
 37			clock-names = "cpu";
 38			clock-latency = <1000000>; /* 1 ms */
 39		};
 40	};
 41
 42	/*
 43	 * The Integrator/CP overall clocking architecture can be found in
 44	 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
 45	 * appear to illustrate the layout used in most configurations.
 46	 */
 47
 48	/* The codec chrystal operates at 24.576 MHz */
 49	xtal_codec: xtal24.576@24.576M {
 50		#clock-cells = <0>;
 51		compatible = "fixed-clock";
 52		clock-frequency = <24576000>;
 53	};
 54
 55	/* The chrystal is divided by 2 by the codec for the AACI bit clock */
 56	aaci_bitclk: aaci_bitclk@12.288M {
 57		#clock-cells = <0>;
 58		compatible = "fixed-factor-clock";
 59		clock-div = <2>;
 60		clock-mult = <1>;
 61		clocks = <&xtal_codec>;
 62	};
 63
 64	/* This is a 25MHz chrystal on the base board */
 65	xtal25mhz: xtal25mhz@25M {
 66		#clock-cells = <0>;
 67		compatible = "fixed-clock";
 68		clock-frequency = <25000000>;
 69	};
 70
 71	/* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
 72	uartclk: uartclk@14.74M {
 73		#clock-cells = <0>;
 74		compatible = "fixed-clock";
 75		clock-frequency = <14745600>;
 76	};
 77
 78	/* Actually sysclk I think */
 79	pclk: pclk@0 {
 80		#clock-cells = <0>;
 81		compatible = "fixed-clock";
 82		clock-frequency = <0>;
 83	};
 84
 85	core-module@10000000 {
 86		/* 24 MHz chrystal on the core module */
 87		cm24mhz: cm24mhz@24M {
 88			#clock-cells = <0>;
 89			compatible = "fixed-clock";
 90			clock-frequency = <24000000>;
 91		};
 92
 93		/* Oscillator on the core module, clocks the CPU core */
 94		cmcore: cmosc@24M {
 95			compatible = "arm,syscon-icst525-integratorcp-cm-core";
 
 96			#clock-cells = <0>;
 97			lock-offset = <0x14>;
 98			vco-offset = <0x08>;
 99			clocks = <&cm24mhz>;
100		};
101
102		/* Oscillator on the core module, clocks the memory bus */
103		cmmem: cmosc@24M {
104			compatible = "arm,syscon-icst525-integratorcp-cm-mem";
 
105			#clock-cells = <0>;
106			lock-offset = <0x14>;
107			vco-offset = <0x08>;
108			clocks = <&cm24mhz>;
109		};
110
111		/* Auxilary oscillator on the core module, clocks the CLCD */
112		auxosc: auxosc@24M {
113			compatible = "arm,syscon-icst525";
 
114			#clock-cells = <0>;
115			lock-offset = <0x14>;
116			vco-offset = <0x1c>;
117			clocks = <&cm24mhz>;
118		};
119
120		/* The KMI clock is the 24 MHz oscillator divided to 8MHz */
121		kmiclk: kmiclk@1M {
122			#clock-cells = <0>;
123			compatible = "fixed-factor-clock";
124			clock-div = <3>;
125			clock-mult = <1>;
126			clocks = <&cm24mhz>;
127		};
128
129		/* The timer clock is the 24 MHz oscillator divided to 1MHz */
130		timclk: timclk@1M {
131			#clock-cells = <0>;
132			compatible = "fixed-factor-clock";
133			clock-div = <24>;
134			clock-mult = <1>;
135			clocks = <&cm24mhz>;
136		};
137	};
138
139	syscon {
140		compatible = "arm,integrator-cp-syscon", "syscon";
141		reg = <0xcb000000 0x100>;
142	};
143
144	timer0: timer@13000000 {
145		/* TIMER0 runs directly on the 25MHz chrystal */
146		compatible = "arm,integrator-cp-timer";
147		clocks = <&xtal25mhz>;
148	};
149
150	timer1: timer@13000100 {
151		/* TIMER1 runs @ 1MHz */
152		compatible = "arm,integrator-cp-timer";
153		clocks = <&timclk>;
154	};
155
156	timer2: timer@13000200 {
157		/* TIMER2 runs @ 1MHz */
158		compatible = "arm,integrator-cp-timer";
159		clocks = <&timclk>;
160	};
161
162	pic: pic@14000000 {
163		valid-mask = <0x1fc003ff>;
164	};
165
166	cic: cic@10000040 {
167		compatible = "arm,versatile-fpga-irq";
168		#interrupt-cells = <1>;
169		interrupt-controller;
170		reg = <0x10000040 0x100>;
171		clear-mask = <0xffffffff>;
172		valid-mask = <0x00000007>;
173	};
174
175	/* The SIC is cascaded off IRQ 26 on the PIC */
176	sic: sic@ca000000 {
177		compatible = "arm,versatile-fpga-irq";
178		interrupt-parent = <&pic>;
179		interrupts = <26>;
180		#interrupt-cells = <1>;
181		interrupt-controller;
182		reg = <0xca000000 0x100>;
183		clear-mask = <0x00000fff>;
184		valid-mask = <0x00000fff>;
185	};
186
187	ethernet@c8000000 {
188		compatible = "smsc,lan91c111";
189		reg = <0xc8000000 0x10>;
190		interrupt-parent = <&pic>;
191		interrupts = <27>;
192	};
193
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
194	fpga {
195		/*
196		 * These PrimeCells are at the same location and using
197		 * the same interrupts in all Integrators, but in the CP
198		 * slightly newer versions are deployed.
199		 */
200		rtc@15000000 {
201			compatible = "arm,pl031", "arm,primecell";
202			clocks = <&pclk>;
203			clock-names = "apb_pclk";
204		};
205
206		uart@16000000 {
207			compatible = "arm,pl011", "arm,primecell";
208			clocks = <&uartclk>, <&pclk>;
209			clock-names = "uartclk", "apb_pclk";
210		};
211
212		uart@17000000 {
213			compatible = "arm,pl011", "arm,primecell";
214			clocks = <&uartclk>, <&pclk>;
215			clock-names = "uartclk", "apb_pclk";
216		};
217
218		kmi@18000000 {
219			compatible = "arm,pl050", "arm,primecell";
220			clocks = <&kmiclk>, <&pclk>;
221			clock-names = "KMIREFCLK", "apb_pclk";
222		};
223
224		kmi@19000000 {
225			compatible = "arm,pl050", "arm,primecell";
226			clocks = <&kmiclk>, <&pclk>;
227			clock-names = "KMIREFCLK", "apb_pclk";
228		};
229
230		/*
231		 * These PrimeCells are only available on the Integrator/CP
232		 */
233		mmc@1c000000 {
234			compatible = "arm,pl180", "arm,primecell";
235			reg = <0x1c000000 0x1000>;
236			interrupts = <23 24>;
237			max-frequency = <515633>;
238			clocks = <&uartclk>, <&pclk>;
239			clock-names = "mclk", "apb_pclk";
240		};
241
242		aaci@1d000000 {
243			compatible = "arm,pl041", "arm,primecell";
244			reg = <0x1d000000 0x1000>;
245			interrupts = <25>;
246			clocks = <&pclk>;
247			clock-names = "apb_pclk";
248		};
249
250		clcd@c0000000 {
251			compatible = "arm,pl110", "arm,primecell";
252			reg = <0xC0000000 0x1000>;
253			interrupts = <22>;
254			clocks = <&auxosc>, <&pclk>;
255			clock-names = "clcdclk", "apb_pclk";
 
 
256
257			port {
258				/*
259				 * The VGA connected is implemented with a
260				 * THS8134A triple DAC that can be run in 24bit
261				 * or 16bit RGB mode.
262				 */
263				clcd_pads: endpoint {
264					remote-endpoint = <&clcd_panel>;
265					arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
266				};
267			};
268
269			panel {
270				compatible = "panel-dpi";
271
272				port {
273					clcd_panel: endpoint {
274						remote-endpoint = <&clcd_pads>;
275					};
276				};
277
278				/* Standard 640x480 VGA timings */
279				panel-timing {
280					clock-frequency = <25175000>;
281					hactive = <640>;
282					hback-porch = <48>;
283					hfront-porch = <16>;
284					hsync-len = <96>;
285					vactive = <480>;
286					vback-porch = <33>;
287					vfront-porch = <10>;
288					vsync-len = <2>;
289				};
290			};
291		};
292	};
293};