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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2011 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include <dt-bindings/clock/imx6qdl-clock.h>
7#include <dt-bindings/input/input.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 /*
14 * The decompressor and also some bootloaders rely on a
15 * pre-existing /chosen node to be available to insert the
16 * command line and merge other ATAGS info.
17 */
18 chosen {};
19
20 aliases {
21 ethernet0 = &fec;
22 can0 = &can1;
23 can1 = &can2;
24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 gpio4 = &gpio5;
29 gpio5 = &gpio6;
30 gpio6 = &gpio7;
31 i2c0 = &i2c1;
32 i2c1 = &i2c2;
33 i2c2 = &i2c3;
34 ipu0 = &ipu1;
35 mmc0 = &usdhc1;
36 mmc1 = &usdhc2;
37 mmc2 = &usdhc3;
38 mmc3 = &usdhc4;
39 serial0 = &uart1;
40 serial1 = &uart2;
41 serial2 = &uart3;
42 serial3 = &uart4;
43 serial4 = &uart5;
44 spi0 = &ecspi1;
45 spi1 = &ecspi2;
46 spi2 = &ecspi3;
47 spi3 = &ecspi4;
48 usb0 = &usbotg;
49 usb1 = &usbh1;
50 usb2 = &usbh2;
51 usb3 = &usbh3;
52 usbphy0 = &usbphy1;
53 usbphy1 = &usbphy2;
54 };
55
56 clocks {
57 ckil {
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
61 };
62
63 ckih1 {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
67 };
68
69 osc {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <24000000>;
73 };
74 };
75
76 ldb: ldb {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
80 gpr = <&gpr>;
81 status = "disabled";
82
83 lvds-channel@0 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 reg = <0>;
87 status = "disabled";
88
89 port@0 {
90 reg = <0>;
91
92 lvds0_mux_0: endpoint {
93 remote-endpoint = <&ipu1_di0_lvds0>;
94 };
95 };
96
97 port@1 {
98 reg = <1>;
99
100 lvds0_mux_1: endpoint {
101 remote-endpoint = <&ipu1_di1_lvds0>;
102 };
103 };
104 };
105
106 lvds-channel@1 {
107 #address-cells = <1>;
108 #size-cells = <0>;
109 reg = <1>;
110 status = "disabled";
111
112 port@0 {
113 reg = <0>;
114
115 lvds1_mux_0: endpoint {
116 remote-endpoint = <&ipu1_di0_lvds1>;
117 };
118 };
119
120 port@1 {
121 reg = <1>;
122
123 lvds1_mux_1: endpoint {
124 remote-endpoint = <&ipu1_di1_lvds1>;
125 };
126 };
127 };
128 };
129
130 pmu: pmu {
131 compatible = "arm,cortex-a9-pmu";
132 interrupt-parent = <&gpc>;
133 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
134 };
135
136 usbphynop1: usbphynop1 {
137 compatible = "usb-nop-xceiv";
138 #phy-cells = <0>;
139 };
140
141 usbphynop2: usbphynop2 {
142 compatible = "usb-nop-xceiv";
143 #phy-cells = <0>;
144 };
145
146 soc: soc {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "simple-bus";
150 interrupt-parent = <&gpc>;
151 ranges;
152
153 dma_apbh: dma-apbh@110000 {
154 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
155 reg = <0x00110000 0x2000>;
156 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
157 <0 13 IRQ_TYPE_LEVEL_HIGH>,
158 <0 13 IRQ_TYPE_LEVEL_HIGH>,
159 <0 13 IRQ_TYPE_LEVEL_HIGH>;
160 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
161 #dma-cells = <1>;
162 dma-channels = <4>;
163 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
164 };
165
166 gpmi: nand-controller@112000 {
167 compatible = "fsl,imx6q-gpmi-nand";
168 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
169 reg-names = "gpmi-nand", "bch";
170 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
171 interrupt-names = "bch";
172 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
173 <&clks IMX6QDL_CLK_GPMI_APB>,
174 <&clks IMX6QDL_CLK_GPMI_BCH>,
175 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
176 <&clks IMX6QDL_CLK_PER1_BCH>;
177 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
178 "gpmi_bch_apb", "per1_bch";
179 dmas = <&dma_apbh 0>;
180 dma-names = "rx-tx";
181 status = "disabled";
182 };
183
184 hdmi: hdmi@120000 {
185 reg = <0x00120000 0x9000>;
186 interrupts = <0 115 0x04>;
187 gpr = <&gpr>;
188 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
189 <&clks IMX6QDL_CLK_HDMI_ISFR>;
190 clock-names = "iahb", "isfr";
191 status = "disabled";
192
193 ports {
194 #address-cells = <1>;
195 #size-cells = <0>;
196
197 port@0 {
198 reg = <0>;
199
200 hdmi_mux_0: endpoint {
201 remote-endpoint = <&ipu1_di0_hdmi>;
202 };
203 };
204
205 port@1 {
206 reg = <1>;
207
208 hdmi_mux_1: endpoint {
209 remote-endpoint = <&ipu1_di1_hdmi>;
210 };
211 };
212 };
213 };
214
215 gpu_3d: gpu@130000 {
216 compatible = "vivante,gc";
217 reg = <0x00130000 0x4000>;
218 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
220 <&clks IMX6QDL_CLK_GPU3D_CORE>,
221 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
222 clock-names = "bus", "core", "shader";
223 power-domains = <&pd_pu>;
224 #cooling-cells = <2>;
225 };
226
227 gpu_2d: gpu@134000 {
228 compatible = "vivante,gc";
229 reg = <0x00134000 0x4000>;
230 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
232 <&clks IMX6QDL_CLK_GPU2D_CORE>;
233 clock-names = "bus", "core";
234 power-domains = <&pd_pu>;
235 #cooling-cells = <2>;
236 };
237
238 timer@a00600 {
239 compatible = "arm,cortex-a9-twd-timer";
240 reg = <0x00a00600 0x20>;
241 interrupts = <1 13 0xf01>;
242 interrupt-parent = <&intc>;
243 clocks = <&clks IMX6QDL_CLK_TWD>;
244 };
245
246 intc: interrupt-controller@a01000 {
247 compatible = "arm,cortex-a9-gic";
248 #interrupt-cells = <3>;
249 interrupt-controller;
250 reg = <0x00a01000 0x1000>,
251 <0x00a00100 0x100>;
252 interrupt-parent = <&intc>;
253 };
254
255 L2: cache-controller@a02000 {
256 compatible = "arm,pl310-cache";
257 reg = <0x00a02000 0x1000>;
258 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
259 cache-unified;
260 cache-level = <2>;
261 arm,tag-latency = <4 2 3>;
262 arm,data-latency = <4 2 3>;
263 arm,shared-override;
264 };
265
266 pcie: pcie@1ffc000 {
267 compatible = "fsl,imx6q-pcie";
268 reg = <0x01ffc000 0x04000>,
269 <0x01f00000 0x80000>;
270 reg-names = "dbi", "config";
271 #address-cells = <3>;
272 #size-cells = <2>;
273 device_type = "pci";
274 bus-range = <0x00 0xff>;
275 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */
276 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
277 num-lanes = <1>;
278 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
279 interrupt-names = "msi";
280 #interrupt-cells = <1>;
281 interrupt-map-mask = <0 0 0 0x7>;
282 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
283 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
284 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
285 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
287 <&clks IMX6QDL_CLK_LVDS1_GATE>,
288 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
289 clock-names = "pcie", "pcie_bus", "pcie_phy";
290 status = "disabled";
291 };
292
293 aips1: bus@2000000 { /* AIPS1 */
294 compatible = "fsl,aips-bus", "simple-bus";
295 #address-cells = <1>;
296 #size-cells = <1>;
297 reg = <0x02000000 0x100000>;
298 ranges;
299
300 spba-bus@2000000 {
301 compatible = "fsl,spba-bus", "simple-bus";
302 #address-cells = <1>;
303 #size-cells = <1>;
304 reg = <0x02000000 0x40000>;
305 ranges;
306
307 spdif: spdif@2004000 {
308 compatible = "fsl,imx35-spdif";
309 reg = <0x02004000 0x4000>;
310 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
311 dmas = <&sdma 14 18 0>,
312 <&sdma 15 18 0>;
313 dma-names = "rx", "tx";
314 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
315 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
316 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
317 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
318 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
319 clock-names = "core", "rxtx0",
320 "rxtx1", "rxtx2",
321 "rxtx3", "rxtx4",
322 "rxtx5", "rxtx6",
323 "rxtx7", "spba";
324 status = "disabled";
325 };
326
327 ecspi1: spi@2008000 {
328 #address-cells = <1>;
329 #size-cells = <0>;
330 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
331 reg = <0x02008000 0x4000>;
332 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
334 <&clks IMX6QDL_CLK_ECSPI1>;
335 clock-names = "ipg", "per";
336 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
337 dma-names = "rx", "tx";
338 status = "disabled";
339 };
340
341 ecspi2: spi@200c000 {
342 #address-cells = <1>;
343 #size-cells = <0>;
344 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
345 reg = <0x0200c000 0x4000>;
346 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
348 <&clks IMX6QDL_CLK_ECSPI2>;
349 clock-names = "ipg", "per";
350 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
351 dma-names = "rx", "tx";
352 status = "disabled";
353 };
354
355 ecspi3: spi@2010000 {
356 #address-cells = <1>;
357 #size-cells = <0>;
358 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
359 reg = <0x02010000 0x4000>;
360 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
362 <&clks IMX6QDL_CLK_ECSPI3>;
363 clock-names = "ipg", "per";
364 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
365 dma-names = "rx", "tx";
366 status = "disabled";
367 };
368
369 ecspi4: spi@2014000 {
370 #address-cells = <1>;
371 #size-cells = <0>;
372 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
373 reg = <0x02014000 0x4000>;
374 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
376 <&clks IMX6QDL_CLK_ECSPI4>;
377 clock-names = "ipg", "per";
378 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
379 dma-names = "rx", "tx";
380 status = "disabled";
381 };
382
383 uart1: serial@2020000 {
384 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
385 reg = <0x02020000 0x4000>;
386 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
388 <&clks IMX6QDL_CLK_UART_SERIAL>;
389 clock-names = "ipg", "per";
390 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
391 dma-names = "rx", "tx";
392 status = "disabled";
393 };
394
395 esai: esai@2024000 {
396 #sound-dai-cells = <0>;
397 compatible = "fsl,imx35-esai";
398 reg = <0x02024000 0x4000>;
399 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
401 <&clks IMX6QDL_CLK_ESAI_MEM>,
402 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
403 <&clks IMX6QDL_CLK_ESAI_IPG>,
404 <&clks IMX6QDL_CLK_SPBA>;
405 clock-names = "core", "mem", "extal", "fsys", "spba";
406 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
407 dma-names = "rx", "tx";
408 status = "disabled";
409 };
410
411 ssi1: ssi@2028000 {
412 #sound-dai-cells = <0>;
413 compatible = "fsl,imx6q-ssi",
414 "fsl,imx51-ssi";
415 reg = <0x02028000 0x4000>;
416 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
418 <&clks IMX6QDL_CLK_SSI1>;
419 clock-names = "ipg", "baud";
420 dmas = <&sdma 37 1 0>,
421 <&sdma 38 1 0>;
422 dma-names = "rx", "tx";
423 fsl,fifo-depth = <15>;
424 status = "disabled";
425 };
426
427 ssi2: ssi@202c000 {
428 #sound-dai-cells = <0>;
429 compatible = "fsl,imx6q-ssi",
430 "fsl,imx51-ssi";
431 reg = <0x0202c000 0x4000>;
432 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
434 <&clks IMX6QDL_CLK_SSI2>;
435 clock-names = "ipg", "baud";
436 dmas = <&sdma 41 1 0>,
437 <&sdma 42 1 0>;
438 dma-names = "rx", "tx";
439 fsl,fifo-depth = <15>;
440 status = "disabled";
441 };
442
443 ssi3: ssi@2030000 {
444 #sound-dai-cells = <0>;
445 compatible = "fsl,imx6q-ssi",
446 "fsl,imx51-ssi";
447 reg = <0x02030000 0x4000>;
448 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
450 <&clks IMX6QDL_CLK_SSI3>;
451 clock-names = "ipg", "baud";
452 dmas = <&sdma 45 1 0>,
453 <&sdma 46 1 0>;
454 dma-names = "rx", "tx";
455 fsl,fifo-depth = <15>;
456 status = "disabled";
457 };
458
459 asrc: asrc@2034000 {
460 compatible = "fsl,imx53-asrc";
461 reg = <0x02034000 0x4000>;
462 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
464 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
465 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
466 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
467 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
468 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
469 <&clks IMX6QDL_CLK_SPBA>;
470 clock-names = "mem", "ipg", "asrck_0",
471 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
472 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
473 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
474 "asrck_d", "asrck_e", "asrck_f", "spba";
475 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
476 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
477 dma-names = "rxa", "rxb", "rxc",
478 "txa", "txb", "txc";
479 fsl,asrc-rate = <48000>;
480 fsl,asrc-width = <16>;
481 status = "okay";
482 };
483
484 spba-bus@203c000 {
485 reg = <0x0203c000 0x4000>;
486 };
487 };
488
489 vpu: vpu@2040000 {
490 compatible = "cnm,coda960";
491 reg = <0x02040000 0x3c000>;
492 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
493 <0 3 IRQ_TYPE_LEVEL_HIGH>;
494 interrupt-names = "bit", "jpeg";
495 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
496 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
497 clock-names = "per", "ahb";
498 power-domains = <&pd_pu>;
499 resets = <&src 1>;
500 iram = <&ocram>;
501 };
502
503 aipstz@207c000 { /* AIPSTZ1 */
504 reg = <0x0207c000 0x4000>;
505 };
506
507 pwm1: pwm@2080000 {
508 #pwm-cells = <3>;
509 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
510 reg = <0x02080000 0x4000>;
511 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clks IMX6QDL_CLK_IPG>,
513 <&clks IMX6QDL_CLK_PWM1>;
514 clock-names = "ipg", "per";
515 status = "disabled";
516 };
517
518 pwm2: pwm@2084000 {
519 #pwm-cells = <3>;
520 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
521 reg = <0x02084000 0x4000>;
522 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&clks IMX6QDL_CLK_IPG>,
524 <&clks IMX6QDL_CLK_PWM2>;
525 clock-names = "ipg", "per";
526 status = "disabled";
527 };
528
529 pwm3: pwm@2088000 {
530 #pwm-cells = <3>;
531 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
532 reg = <0x02088000 0x4000>;
533 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&clks IMX6QDL_CLK_IPG>,
535 <&clks IMX6QDL_CLK_PWM3>;
536 clock-names = "ipg", "per";
537 status = "disabled";
538 };
539
540 pwm4: pwm@208c000 {
541 #pwm-cells = <3>;
542 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
543 reg = <0x0208c000 0x4000>;
544 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&clks IMX6QDL_CLK_IPG>,
546 <&clks IMX6QDL_CLK_PWM4>;
547 clock-names = "ipg", "per";
548 status = "disabled";
549 };
550
551 can1: can@2090000 {
552 compatible = "fsl,imx6q-flexcan";
553 reg = <0x02090000 0x4000>;
554 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
556 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
557 clock-names = "ipg", "per";
558 fsl,stop-mode = <&gpr 0x34 28>;
559 status = "disabled";
560 };
561
562 can2: can@2094000 {
563 compatible = "fsl,imx6q-flexcan";
564 reg = <0x02094000 0x4000>;
565 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
567 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
568 clock-names = "ipg", "per";
569 fsl,stop-mode = <&gpr 0x34 29>;
570 status = "disabled";
571 };
572
573 gpt: timer@2098000 {
574 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
575 reg = <0x02098000 0x4000>;
576 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
578 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
579 <&clks IMX6QDL_CLK_GPT_3M>;
580 clock-names = "ipg", "per", "osc_per";
581 };
582
583 gpio1: gpio@209c000 {
584 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
585 reg = <0x0209c000 0x4000>;
586 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
587 <0 67 IRQ_TYPE_LEVEL_HIGH>;
588 gpio-controller;
589 #gpio-cells = <2>;
590 interrupt-controller;
591 #interrupt-cells = <2>;
592 };
593
594 gpio2: gpio@20a0000 {
595 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
596 reg = <0x020a0000 0x4000>;
597 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
598 <0 69 IRQ_TYPE_LEVEL_HIGH>;
599 gpio-controller;
600 #gpio-cells = <2>;
601 interrupt-controller;
602 #interrupt-cells = <2>;
603 };
604
605 gpio3: gpio@20a4000 {
606 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
607 reg = <0x020a4000 0x4000>;
608 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
609 <0 71 IRQ_TYPE_LEVEL_HIGH>;
610 gpio-controller;
611 #gpio-cells = <2>;
612 interrupt-controller;
613 #interrupt-cells = <2>;
614 };
615
616 gpio4: gpio@20a8000 {
617 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
618 reg = <0x020a8000 0x4000>;
619 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
620 <0 73 IRQ_TYPE_LEVEL_HIGH>;
621 gpio-controller;
622 #gpio-cells = <2>;
623 interrupt-controller;
624 #interrupt-cells = <2>;
625 };
626
627 gpio5: gpio@20ac000 {
628 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
629 reg = <0x020ac000 0x4000>;
630 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
631 <0 75 IRQ_TYPE_LEVEL_HIGH>;
632 gpio-controller;
633 #gpio-cells = <2>;
634 interrupt-controller;
635 #interrupt-cells = <2>;
636 };
637
638 gpio6: gpio@20b0000 {
639 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
640 reg = <0x020b0000 0x4000>;
641 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
642 <0 77 IRQ_TYPE_LEVEL_HIGH>;
643 gpio-controller;
644 #gpio-cells = <2>;
645 interrupt-controller;
646 #interrupt-cells = <2>;
647 };
648
649 gpio7: gpio@20b4000 {
650 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
651 reg = <0x020b4000 0x4000>;
652 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
653 <0 79 IRQ_TYPE_LEVEL_HIGH>;
654 gpio-controller;
655 #gpio-cells = <2>;
656 interrupt-controller;
657 #interrupt-cells = <2>;
658 };
659
660 kpp: keypad@20b8000 {
661 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
662 reg = <0x020b8000 0x4000>;
663 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&clks IMX6QDL_CLK_IPG>;
665 status = "disabled";
666 };
667
668 wdog1: watchdog@20bc000 {
669 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
670 reg = <0x020bc000 0x4000>;
671 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&clks IMX6QDL_CLK_IPG>;
673 };
674
675 wdog2: watchdog@20c0000 {
676 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
677 reg = <0x020c0000 0x4000>;
678 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&clks IMX6QDL_CLK_IPG>;
680 status = "disabled";
681 };
682
683 clks: clock-controller@20c4000 {
684 compatible = "fsl,imx6q-ccm";
685 reg = <0x020c4000 0x4000>;
686 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
687 <0 88 IRQ_TYPE_LEVEL_HIGH>;
688 #clock-cells = <1>;
689 };
690
691 anatop: anatop@20c8000 {
692 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
693 reg = <0x020c8000 0x1000>;
694 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
695 <0 54 IRQ_TYPE_LEVEL_HIGH>,
696 <0 127 IRQ_TYPE_LEVEL_HIGH>;
697
698 reg_vdd1p1: regulator-1p1 {
699 compatible = "fsl,anatop-regulator";
700 regulator-name = "vdd1p1";
701 regulator-min-microvolt = <1000000>;
702 regulator-max-microvolt = <1200000>;
703 regulator-always-on;
704 anatop-reg-offset = <0x110>;
705 anatop-vol-bit-shift = <8>;
706 anatop-vol-bit-width = <5>;
707 anatop-min-bit-val = <4>;
708 anatop-min-voltage = <800000>;
709 anatop-max-voltage = <1375000>;
710 anatop-enable-bit = <0>;
711 };
712
713 reg_vdd3p0: regulator-3p0 {
714 compatible = "fsl,anatop-regulator";
715 regulator-name = "vdd3p0";
716 regulator-min-microvolt = <2800000>;
717 regulator-max-microvolt = <3150000>;
718 regulator-always-on;
719 anatop-reg-offset = <0x120>;
720 anatop-vol-bit-shift = <8>;
721 anatop-vol-bit-width = <5>;
722 anatop-min-bit-val = <0>;
723 anatop-min-voltage = <2625000>;
724 anatop-max-voltage = <3400000>;
725 anatop-enable-bit = <0>;
726 };
727
728 reg_vdd2p5: regulator-2p5 {
729 compatible = "fsl,anatop-regulator";
730 regulator-name = "vdd2p5";
731 regulator-min-microvolt = <2250000>;
732 regulator-max-microvolt = <2750000>;
733 regulator-always-on;
734 anatop-reg-offset = <0x130>;
735 anatop-vol-bit-shift = <8>;
736 anatop-vol-bit-width = <5>;
737 anatop-min-bit-val = <0>;
738 anatop-min-voltage = <2100000>;
739 anatop-max-voltage = <2875000>;
740 anatop-enable-bit = <0>;
741 };
742
743 reg_arm: regulator-vddcore {
744 compatible = "fsl,anatop-regulator";
745 regulator-name = "vddarm";
746 regulator-min-microvolt = <725000>;
747 regulator-max-microvolt = <1450000>;
748 regulator-always-on;
749 anatop-reg-offset = <0x140>;
750 anatop-vol-bit-shift = <0>;
751 anatop-vol-bit-width = <5>;
752 anatop-delay-reg-offset = <0x170>;
753 anatop-delay-bit-shift = <24>;
754 anatop-delay-bit-width = <2>;
755 anatop-min-bit-val = <1>;
756 anatop-min-voltage = <725000>;
757 anatop-max-voltage = <1450000>;
758 };
759
760 reg_pu: regulator-vddpu {
761 compatible = "fsl,anatop-regulator";
762 regulator-name = "vddpu";
763 regulator-min-microvolt = <725000>;
764 regulator-max-microvolt = <1450000>;
765 regulator-enable-ramp-delay = <380>;
766 anatop-reg-offset = <0x140>;
767 anatop-vol-bit-shift = <9>;
768 anatop-vol-bit-width = <5>;
769 anatop-delay-reg-offset = <0x170>;
770 anatop-delay-bit-shift = <26>;
771 anatop-delay-bit-width = <2>;
772 anatop-min-bit-val = <1>;
773 anatop-min-voltage = <725000>;
774 anatop-max-voltage = <1450000>;
775 };
776
777 reg_soc: regulator-vddsoc {
778 compatible = "fsl,anatop-regulator";
779 regulator-name = "vddsoc";
780 regulator-min-microvolt = <725000>;
781 regulator-max-microvolt = <1450000>;
782 regulator-always-on;
783 anatop-reg-offset = <0x140>;
784 anatop-vol-bit-shift = <18>;
785 anatop-vol-bit-width = <5>;
786 anatop-delay-reg-offset = <0x170>;
787 anatop-delay-bit-shift = <28>;
788 anatop-delay-bit-width = <2>;
789 anatop-min-bit-val = <1>;
790 anatop-min-voltage = <725000>;
791 anatop-max-voltage = <1450000>;
792 };
793
794 tempmon: tempmon {
795 compatible = "fsl,imx6q-tempmon";
796 interrupt-parent = <&gpc>;
797 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
798 fsl,tempmon = <&anatop>;
799 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
800 nvmem-cell-names = "calib", "temp_grade";
801 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
802 #thermal-sensor-cells = <0>;
803 };
804 };
805
806 usbphy1: usbphy@20c9000 {
807 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
808 reg = <0x020c9000 0x1000>;
809 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
811 fsl,anatop = <&anatop>;
812 };
813
814 usbphy2: usbphy@20ca000 {
815 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
816 reg = <0x020ca000 0x1000>;
817 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
819 fsl,anatop = <&anatop>;
820 };
821
822 snvs: snvs@20cc000 {
823 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
824 reg = <0x020cc000 0x4000>;
825
826 snvs_rtc: snvs-rtc-lp {
827 compatible = "fsl,sec-v4.0-mon-rtc-lp";
828 regmap = <&snvs>;
829 offset = <0x34>;
830 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
831 <0 20 IRQ_TYPE_LEVEL_HIGH>;
832 };
833
834 snvs_poweroff: snvs-poweroff {
835 compatible = "syscon-poweroff";
836 regmap = <&snvs>;
837 offset = <0x38>;
838 value = <0x60>;
839 mask = <0x60>;
840 status = "disabled";
841 };
842
843 snvs_pwrkey: snvs-powerkey {
844 compatible = "fsl,sec-v4.0-pwrkey";
845 regmap = <&snvs>;
846 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
847 linux,keycode = <KEY_POWER>;
848 wakeup-source;
849 status = "disabled";
850 };
851
852 snvs_lpgpr: snvs-lpgpr {
853 compatible = "fsl,imx6q-snvs-lpgpr";
854 };
855 };
856
857 epit1: epit@20d0000 { /* EPIT1 */
858 reg = <0x020d0000 0x4000>;
859 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
860 };
861
862 epit2: epit@20d4000 { /* EPIT2 */
863 reg = <0x020d4000 0x4000>;
864 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
865 };
866
867 src: reset-controller@20d8000 {
868 compatible = "fsl,imx6q-src", "fsl,imx51-src";
869 reg = <0x020d8000 0x4000>;
870 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
871 <0 96 IRQ_TYPE_LEVEL_HIGH>;
872 #reset-cells = <1>;
873 };
874
875 gpc: gpc@20dc000 {
876 compatible = "fsl,imx6q-gpc";
877 reg = <0x020dc000 0x4000>;
878 interrupt-controller;
879 #interrupt-cells = <3>;
880 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
881 interrupt-parent = <&intc>;
882 clocks = <&clks IMX6QDL_CLK_IPG>;
883 clock-names = "ipg";
884
885 pgc {
886 #address-cells = <1>;
887 #size-cells = <0>;
888
889 power-domain@0 {
890 reg = <0>;
891 #power-domain-cells = <0>;
892 };
893 pd_pu: power-domain@1 {
894 reg = <1>;
895 #power-domain-cells = <0>;
896 power-supply = <®_pu>;
897 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
898 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
899 <&clks IMX6QDL_CLK_GPU2D_CORE>,
900 <&clks IMX6QDL_CLK_GPU2D_AXI>,
901 <&clks IMX6QDL_CLK_OPENVG_AXI>,
902 <&clks IMX6QDL_CLK_VPU_AXI>;
903 };
904 };
905 };
906
907 gpr: iomuxc-gpr@20e0000 {
908 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
909 reg = <0x20e0000 0x38>;
910
911 mux: mux-controller {
912 compatible = "mmio-mux";
913 #mux-control-cells = <1>;
914 };
915 };
916
917 iomuxc: pinctrl@20e0000 {
918 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
919 reg = <0x20e0000 0x4000>;
920 };
921
922 dcic1: dcic@20e4000 {
923 reg = <0x020e4000 0x4000>;
924 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
925 };
926
927 dcic2: dcic@20e8000 {
928 reg = <0x020e8000 0x4000>;
929 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
930 };
931
932 sdma: dma-controller@20ec000 {
933 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
934 reg = <0x020ec000 0x4000>;
935 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clks IMX6QDL_CLK_IPG>,
937 <&clks IMX6QDL_CLK_SDMA>;
938 clock-names = "ipg", "ahb";
939 #dma-cells = <3>;
940 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
941 };
942 };
943
944 aips2: bus@2100000 { /* AIPS2 */
945 compatible = "fsl,aips-bus", "simple-bus";
946 #address-cells = <1>;
947 #size-cells = <1>;
948 reg = <0x02100000 0x100000>;
949 ranges;
950
951 crypto: crypto@2100000 {
952 compatible = "fsl,sec-v4.0";
953 #address-cells = <1>;
954 #size-cells = <1>;
955 reg = <0x2100000 0x10000>;
956 ranges = <0 0x2100000 0x10000>;
957 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
958 <&clks IMX6QDL_CLK_CAAM_ACLK>,
959 <&clks IMX6QDL_CLK_CAAM_IPG>,
960 <&clks IMX6QDL_CLK_EIM_SLOW>;
961 clock-names = "mem", "aclk", "ipg", "emi_slow";
962
963 sec_jr0: jr@1000 {
964 compatible = "fsl,sec-v4.0-job-ring";
965 reg = <0x1000 0x1000>;
966 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
967 };
968
969 sec_jr1: jr@2000 {
970 compatible = "fsl,sec-v4.0-job-ring";
971 reg = <0x2000 0x1000>;
972 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
973 };
974 };
975
976 aipstz@217c000 { /* AIPSTZ2 */
977 reg = <0x0217c000 0x4000>;
978 };
979
980 usbotg: usb@2184000 {
981 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
982 reg = <0x02184000 0x200>;
983 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&clks IMX6QDL_CLK_USBOH3>;
985 fsl,usbphy = <&usbphy1>;
986 fsl,usbmisc = <&usbmisc 0>;
987 ahb-burst-config = <0x0>;
988 tx-burst-size-dword = <0x10>;
989 rx-burst-size-dword = <0x10>;
990 status = "disabled";
991 };
992
993 usbh1: usb@2184200 {
994 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
995 reg = <0x02184200 0x200>;
996 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&clks IMX6QDL_CLK_USBOH3>;
998 fsl,usbphy = <&usbphy2>;
999 fsl,usbmisc = <&usbmisc 1>;
1000 dr_mode = "host";
1001 ahb-burst-config = <0x0>;
1002 tx-burst-size-dword = <0x10>;
1003 rx-burst-size-dword = <0x10>;
1004 status = "disabled";
1005 };
1006
1007 usbh2: usb@2184400 {
1008 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1009 reg = <0x02184400 0x200>;
1010 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1011 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1012 fsl,usbphy = <&usbphynop1>;
1013 phy_type = "hsic";
1014 fsl,usbmisc = <&usbmisc 2>;
1015 dr_mode = "host";
1016 ahb-burst-config = <0x0>;
1017 tx-burst-size-dword = <0x10>;
1018 rx-burst-size-dword = <0x10>;
1019 status = "disabled";
1020 };
1021
1022 usbh3: usb@2184600 {
1023 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1024 reg = <0x02184600 0x200>;
1025 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1027 fsl,usbphy = <&usbphynop2>;
1028 phy_type = "hsic";
1029 fsl,usbmisc = <&usbmisc 3>;
1030 dr_mode = "host";
1031 ahb-burst-config = <0x0>;
1032 tx-burst-size-dword = <0x10>;
1033 rx-burst-size-dword = <0x10>;
1034 status = "disabled";
1035 };
1036
1037 usbmisc: usbmisc@2184800 {
1038 #index-cells = <1>;
1039 compatible = "fsl,imx6q-usbmisc";
1040 reg = <0x02184800 0x200>;
1041 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1042 };
1043
1044 fec: ethernet@2188000 {
1045 compatible = "fsl,imx6q-fec";
1046 reg = <0x02188000 0x4000>;
1047 interrupt-names = "int0", "pps";
1048 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
1049 <0 119 IRQ_TYPE_LEVEL_HIGH>;
1050 clocks = <&clks IMX6QDL_CLK_ENET>,
1051 <&clks IMX6QDL_CLK_ENET>,
1052 <&clks IMX6QDL_CLK_ENET_REF>,
1053 <&clks IMX6QDL_CLK_ENET_REF>;
1054 clock-names = "ipg", "ahb", "ptp", "enet_out";
1055 fsl,stop-mode = <&gpr 0x34 27>;
1056 status = "disabled";
1057 };
1058
1059 mlb@218c000 {
1060 reg = <0x0218c000 0x4000>;
1061 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1062 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1063 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1064 };
1065
1066 usdhc1: mmc@2190000 {
1067 compatible = "fsl,imx6q-usdhc";
1068 reg = <0x02190000 0x4000>;
1069 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1070 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1071 <&clks IMX6QDL_CLK_USDHC1>,
1072 <&clks IMX6QDL_CLK_USDHC1>;
1073 clock-names = "ipg", "ahb", "per";
1074 bus-width = <4>;
1075 status = "disabled";
1076 };
1077
1078 usdhc2: mmc@2194000 {
1079 compatible = "fsl,imx6q-usdhc";
1080 reg = <0x02194000 0x4000>;
1081 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1082 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1083 <&clks IMX6QDL_CLK_USDHC2>,
1084 <&clks IMX6QDL_CLK_USDHC2>;
1085 clock-names = "ipg", "ahb", "per";
1086 bus-width = <4>;
1087 status = "disabled";
1088 };
1089
1090 usdhc3: mmc@2198000 {
1091 compatible = "fsl,imx6q-usdhc";
1092 reg = <0x02198000 0x4000>;
1093 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1094 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1095 <&clks IMX6QDL_CLK_USDHC3>,
1096 <&clks IMX6QDL_CLK_USDHC3>;
1097 clock-names = "ipg", "ahb", "per";
1098 bus-width = <4>;
1099 status = "disabled";
1100 };
1101
1102 usdhc4: mmc@219c000 {
1103 compatible = "fsl,imx6q-usdhc";
1104 reg = <0x0219c000 0x4000>;
1105 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1107 <&clks IMX6QDL_CLK_USDHC4>,
1108 <&clks IMX6QDL_CLK_USDHC4>;
1109 clock-names = "ipg", "ahb", "per";
1110 bus-width = <4>;
1111 status = "disabled";
1112 };
1113
1114 i2c1: i2c@21a0000 {
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1117 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1118 reg = <0x021a0000 0x4000>;
1119 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&clks IMX6QDL_CLK_I2C1>;
1121 status = "disabled";
1122 };
1123
1124 i2c2: i2c@21a4000 {
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1127 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1128 reg = <0x021a4000 0x4000>;
1129 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&clks IMX6QDL_CLK_I2C2>;
1131 status = "disabled";
1132 };
1133
1134 i2c3: i2c@21a8000 {
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1137 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1138 reg = <0x021a8000 0x4000>;
1139 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&clks IMX6QDL_CLK_I2C3>;
1141 status = "disabled";
1142 };
1143
1144 romcp@21ac000 {
1145 reg = <0x021ac000 0x4000>;
1146 };
1147
1148 mmdc0: memory-controller@21b0000 { /* MMDC0 */
1149 compatible = "fsl,imx6q-mmdc";
1150 reg = <0x021b0000 0x4000>;
1151 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
1152 };
1153
1154 mmdc1: memory-controller@21b4000 { /* MMDC1 */
1155 compatible = "fsl,imx6q-mmdc";
1156 reg = <0x021b4000 0x4000>;
1157 status = "disabled";
1158 };
1159
1160 weim: weim@21b8000 {
1161 #address-cells = <2>;
1162 #size-cells = <1>;
1163 compatible = "fsl,imx6q-weim";
1164 reg = <0x021b8000 0x4000>;
1165 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1166 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1167 fsl,weim-cs-gpr = <&gpr>;
1168 status = "disabled";
1169 };
1170
1171 ocotp: efuse@21bc000 {
1172 compatible = "fsl,imx6q-ocotp", "syscon";
1173 reg = <0x021bc000 0x4000>;
1174 clocks = <&clks IMX6QDL_CLK_IIM>;
1175 #address-cells = <1>;
1176 #size-cells = <1>;
1177
1178 cpu_speed_grade: speed-grade@10 {
1179 reg = <0x10 4>;
1180 };
1181
1182 tempmon_calib: calib@38 {
1183 reg = <0x38 4>;
1184 };
1185
1186 tempmon_temp_grade: temp-grade@20 {
1187 reg = <0x20 4>;
1188 };
1189 };
1190
1191 tzasc@21d0000 { /* TZASC1 */
1192 reg = <0x021d0000 0x4000>;
1193 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1194 };
1195
1196 tzasc@21d4000 { /* TZASC2 */
1197 reg = <0x021d4000 0x4000>;
1198 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1199 };
1200
1201 audmux: audmux@21d8000 {
1202 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1203 reg = <0x021d8000 0x4000>;
1204 status = "disabled";
1205 };
1206
1207 mipi_csi: mipi@21dc000 {
1208 compatible = "fsl,imx6-mipi-csi2";
1209 reg = <0x021dc000 0x4000>;
1210 #address-cells = <1>;
1211 #size-cells = <0>;
1212 interrupts = <0 100 0x04>, <0 101 0x04>;
1213 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1214 <&clks IMX6QDL_CLK_VIDEO_27M>,
1215 <&clks IMX6QDL_CLK_EIM_PODF>;
1216 clock-names = "dphy", "ref", "pix";
1217 status = "disabled";
1218 };
1219
1220 mipi_dsi: mipi@21e0000 {
1221 reg = <0x021e0000 0x4000>;
1222 status = "disabled";
1223
1224 ports {
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1227
1228 port@0 {
1229 reg = <0>;
1230
1231 mipi_mux_0: endpoint {
1232 remote-endpoint = <&ipu1_di0_mipi>;
1233 };
1234 };
1235
1236 port@1 {
1237 reg = <1>;
1238
1239 mipi_mux_1: endpoint {
1240 remote-endpoint = <&ipu1_di1_mipi>;
1241 };
1242 };
1243 };
1244 };
1245
1246 vdoa@21e4000 {
1247 compatible = "fsl,imx6q-vdoa";
1248 reg = <0x021e4000 0x4000>;
1249 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&clks IMX6QDL_CLK_VDOA>;
1251 };
1252
1253 uart2: serial@21e8000 {
1254 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1255 reg = <0x021e8000 0x4000>;
1256 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1258 <&clks IMX6QDL_CLK_UART_SERIAL>;
1259 clock-names = "ipg", "per";
1260 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1261 dma-names = "rx", "tx";
1262 status = "disabled";
1263 };
1264
1265 uart3: serial@21ec000 {
1266 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1267 reg = <0x021ec000 0x4000>;
1268 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1269 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1270 <&clks IMX6QDL_CLK_UART_SERIAL>;
1271 clock-names = "ipg", "per";
1272 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1273 dma-names = "rx", "tx";
1274 status = "disabled";
1275 };
1276
1277 uart4: serial@21f0000 {
1278 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1279 reg = <0x021f0000 0x4000>;
1280 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1281 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1282 <&clks IMX6QDL_CLK_UART_SERIAL>;
1283 clock-names = "ipg", "per";
1284 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1285 dma-names = "rx", "tx";
1286 status = "disabled";
1287 };
1288
1289 uart5: serial@21f4000 {
1290 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1291 reg = <0x021f4000 0x4000>;
1292 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1293 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1294 <&clks IMX6QDL_CLK_UART_SERIAL>;
1295 clock-names = "ipg", "per";
1296 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1297 dma-names = "rx", "tx";
1298 status = "disabled";
1299 };
1300 };
1301
1302 ipu1: ipu@2400000 {
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1305 compatible = "fsl,imx6q-ipu";
1306 reg = <0x02400000 0x400000>;
1307 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1308 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1309 clocks = <&clks IMX6QDL_CLK_IPU1>,
1310 <&clks IMX6QDL_CLK_IPU1_DI0>,
1311 <&clks IMX6QDL_CLK_IPU1_DI1>;
1312 clock-names = "bus", "di0", "di1";
1313 resets = <&src 2>;
1314
1315 ipu1_csi0: port@0 {
1316 reg = <0>;
1317
1318 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1319 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1320 };
1321 };
1322
1323 ipu1_csi1: port@1 {
1324 reg = <1>;
1325 };
1326
1327 ipu1_di0: port@2 {
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1330 reg = <2>;
1331
1332 ipu1_di0_disp0: endpoint@0 {
1333 reg = <0>;
1334 };
1335
1336 ipu1_di0_hdmi: endpoint@1 {
1337 reg = <1>;
1338 remote-endpoint = <&hdmi_mux_0>;
1339 };
1340
1341 ipu1_di0_mipi: endpoint@2 {
1342 reg = <2>;
1343 remote-endpoint = <&mipi_mux_0>;
1344 };
1345
1346 ipu1_di0_lvds0: endpoint@3 {
1347 reg = <3>;
1348 remote-endpoint = <&lvds0_mux_0>;
1349 };
1350
1351 ipu1_di0_lvds1: endpoint@4 {
1352 reg = <4>;
1353 remote-endpoint = <&lvds1_mux_0>;
1354 };
1355 };
1356
1357 ipu1_di1: port@3 {
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1360 reg = <3>;
1361
1362 ipu1_di1_disp1: endpoint@0 {
1363 reg = <0>;
1364 };
1365
1366 ipu1_di1_hdmi: endpoint@1 {
1367 reg = <1>;
1368 remote-endpoint = <&hdmi_mux_1>;
1369 };
1370
1371 ipu1_di1_mipi: endpoint@2 {
1372 reg = <2>;
1373 remote-endpoint = <&mipi_mux_1>;
1374 };
1375
1376 ipu1_di1_lvds0: endpoint@3 {
1377 reg = <3>;
1378 remote-endpoint = <&lvds0_mux_1>;
1379 };
1380
1381 ipu1_di1_lvds1: endpoint@4 {
1382 reg = <4>;
1383 remote-endpoint = <&lvds1_mux_1>;
1384 };
1385 };
1386 };
1387 };
1388};
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <dt-bindings/clock/imx6qdl-clock.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15
16/ {
17 #address-cells = <1>;
18 #size-cells = <1>;
19 /*
20 * The decompressor and also some bootloaders rely on a
21 * pre-existing /chosen node to be available to insert the
22 * command line and merge other ATAGS info.
23 * Also for U-Boot there must be a pre-existing /memory node.
24 */
25 chosen {};
26 memory { device_type = "memory"; reg = <0 0>; };
27
28 aliases {
29 ethernet0 = &fec;
30 can0 = &can1;
31 can1 = &can2;
32 gpio0 = &gpio1;
33 gpio1 = &gpio2;
34 gpio2 = &gpio3;
35 gpio3 = &gpio4;
36 gpio4 = &gpio5;
37 gpio5 = &gpio6;
38 gpio6 = &gpio7;
39 i2c0 = &i2c1;
40 i2c1 = &i2c2;
41 i2c2 = &i2c3;
42 ipu0 = &ipu1;
43 mmc0 = &usdhc1;
44 mmc1 = &usdhc2;
45 mmc2 = &usdhc3;
46 mmc3 = &usdhc4;
47 serial0 = &uart1;
48 serial1 = &uart2;
49 serial2 = &uart3;
50 serial3 = &uart4;
51 serial4 = &uart5;
52 spi0 = &ecspi1;
53 spi1 = &ecspi2;
54 spi2 = &ecspi3;
55 spi3 = &ecspi4;
56 usbphy0 = &usbphy1;
57 usbphy1 = &usbphy2;
58 };
59
60 clocks {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 ckil {
65 compatible = "fsl,imx-ckil", "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <32768>;
68 };
69
70 ckih1 {
71 compatible = "fsl,imx-ckih1", "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <0>;
74 };
75
76 osc {
77 compatible = "fsl,imx-osc", "fixed-clock";
78 #clock-cells = <0>;
79 clock-frequency = <24000000>;
80 };
81 };
82
83 soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 interrupt-parent = <&gpc>;
88 ranges;
89
90 dma_apbh: dma-apbh@00110000 {
91 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
92 reg = <0x00110000 0x2000>;
93 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
94 <0 13 IRQ_TYPE_LEVEL_HIGH>,
95 <0 13 IRQ_TYPE_LEVEL_HIGH>,
96 <0 13 IRQ_TYPE_LEVEL_HIGH>;
97 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
98 #dma-cells = <1>;
99 dma-channels = <4>;
100 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
101 };
102
103 gpmi: gpmi-nand@00112000 {
104 compatible = "fsl,imx6q-gpmi-nand";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
108 reg-names = "gpmi-nand", "bch";
109 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
110 interrupt-names = "bch";
111 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
112 <&clks IMX6QDL_CLK_GPMI_APB>,
113 <&clks IMX6QDL_CLK_GPMI_BCH>,
114 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
115 <&clks IMX6QDL_CLK_PER1_BCH>;
116 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
117 "gpmi_bch_apb", "per1_bch";
118 dmas = <&dma_apbh 0>;
119 dma-names = "rx-tx";
120 status = "disabled";
121 };
122
123 hdmi: hdmi@0120000 {
124 #address-cells = <1>;
125 #size-cells = <0>;
126 reg = <0x00120000 0x9000>;
127 interrupts = <0 115 0x04>;
128 gpr = <&gpr>;
129 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
130 <&clks IMX6QDL_CLK_HDMI_ISFR>;
131 clock-names = "iahb", "isfr";
132 status = "disabled";
133
134 port@0 {
135 reg = <0>;
136
137 hdmi_mux_0: endpoint {
138 remote-endpoint = <&ipu1_di0_hdmi>;
139 };
140 };
141
142 port@1 {
143 reg = <1>;
144
145 hdmi_mux_1: endpoint {
146 remote-endpoint = <&ipu1_di1_hdmi>;
147 };
148 };
149 };
150
151 gpu_3d: gpu@00130000 {
152 compatible = "vivante,gc";
153 reg = <0x00130000 0x4000>;
154 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
156 <&clks IMX6QDL_CLK_GPU3D_CORE>,
157 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
158 clock-names = "bus", "core", "shader";
159 power-domains = <&gpc 1>;
160 };
161
162 gpu_2d: gpu@00134000 {
163 compatible = "vivante,gc";
164 reg = <0x00134000 0x4000>;
165 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
167 <&clks IMX6QDL_CLK_GPU2D_CORE>;
168 clock-names = "bus", "core";
169 power-domains = <&gpc 1>;
170 };
171
172 timer@00a00600 {
173 compatible = "arm,cortex-a9-twd-timer";
174 reg = <0x00a00600 0x20>;
175 interrupts = <1 13 0xf01>;
176 interrupt-parent = <&intc>;
177 clocks = <&clks IMX6QDL_CLK_TWD>;
178 };
179
180 intc: interrupt-controller@00a01000 {
181 compatible = "arm,cortex-a9-gic";
182 #interrupt-cells = <3>;
183 interrupt-controller;
184 reg = <0x00a01000 0x1000>,
185 <0x00a00100 0x100>;
186 interrupt-parent = <&intc>;
187 };
188
189 L2: l2-cache@00a02000 {
190 compatible = "arm,pl310-cache";
191 reg = <0x00a02000 0x1000>;
192 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
193 cache-unified;
194 cache-level = <2>;
195 arm,tag-latency = <4 2 3>;
196 arm,data-latency = <4 2 3>;
197 arm,shared-override;
198 };
199
200 pcie: pcie@0x01000000 {
201 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
202 reg = <0x01ffc000 0x04000>,
203 <0x01f00000 0x80000>;
204 reg-names = "dbi", "config";
205 #address-cells = <3>;
206 #size-cells = <2>;
207 device_type = "pci";
208 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
209 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
210 num-lanes = <1>;
211 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
212 interrupt-names = "msi";
213 #interrupt-cells = <1>;
214 interrupt-map-mask = <0 0 0 0x7>;
215 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
216 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
217 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
218 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
220 <&clks IMX6QDL_CLK_LVDS1_GATE>,
221 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
222 clock-names = "pcie", "pcie_bus", "pcie_phy";
223 status = "disabled";
224 };
225
226 pmu {
227 compatible = "arm,cortex-a9-pmu";
228 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
229 };
230
231 aips-bus@02000000 { /* AIPS1 */
232 compatible = "fsl,aips-bus", "simple-bus";
233 #address-cells = <1>;
234 #size-cells = <1>;
235 reg = <0x02000000 0x100000>;
236 ranges;
237
238 spba-bus@02000000 {
239 compatible = "fsl,spba-bus", "simple-bus";
240 #address-cells = <1>;
241 #size-cells = <1>;
242 reg = <0x02000000 0x40000>;
243 ranges;
244
245 spdif: spdif@02004000 {
246 compatible = "fsl,imx35-spdif";
247 reg = <0x02004000 0x4000>;
248 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
249 dmas = <&sdma 14 18 0>,
250 <&sdma 15 18 0>;
251 dma-names = "rx", "tx";
252 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
253 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
254 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
255 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
256 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
257 clock-names = "core", "rxtx0",
258 "rxtx1", "rxtx2",
259 "rxtx3", "rxtx4",
260 "rxtx5", "rxtx6",
261 "rxtx7", "spba";
262 status = "disabled";
263 };
264
265 ecspi1: ecspi@02008000 {
266 #address-cells = <1>;
267 #size-cells = <0>;
268 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
269 reg = <0x02008000 0x4000>;
270 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
272 <&clks IMX6QDL_CLK_ECSPI1>;
273 clock-names = "ipg", "per";
274 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
275 dma-names = "rx", "tx";
276 status = "disabled";
277 };
278
279 ecspi2: ecspi@0200c000 {
280 #address-cells = <1>;
281 #size-cells = <0>;
282 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
283 reg = <0x0200c000 0x4000>;
284 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
286 <&clks IMX6QDL_CLK_ECSPI2>;
287 clock-names = "ipg", "per";
288 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
289 dma-names = "rx", "tx";
290 status = "disabled";
291 };
292
293 ecspi3: ecspi@02010000 {
294 #address-cells = <1>;
295 #size-cells = <0>;
296 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
297 reg = <0x02010000 0x4000>;
298 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
300 <&clks IMX6QDL_CLK_ECSPI3>;
301 clock-names = "ipg", "per";
302 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
303 dma-names = "rx", "tx";
304 status = "disabled";
305 };
306
307 ecspi4: ecspi@02014000 {
308 #address-cells = <1>;
309 #size-cells = <0>;
310 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
311 reg = <0x02014000 0x4000>;
312 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
314 <&clks IMX6QDL_CLK_ECSPI4>;
315 clock-names = "ipg", "per";
316 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
317 dma-names = "rx", "tx";
318 status = "disabled";
319 };
320
321 uart1: serial@02020000 {
322 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
323 reg = <0x02020000 0x4000>;
324 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
326 <&clks IMX6QDL_CLK_UART_SERIAL>;
327 clock-names = "ipg", "per";
328 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
329 dma-names = "rx", "tx";
330 status = "disabled";
331 };
332
333 esai: esai@02024000 {
334 #sound-dai-cells = <0>;
335 compatible = "fsl,imx35-esai";
336 reg = <0x02024000 0x4000>;
337 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
339 <&clks IMX6QDL_CLK_ESAI_MEM>,
340 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
341 <&clks IMX6QDL_CLK_ESAI_IPG>,
342 <&clks IMX6QDL_CLK_SPBA>;
343 clock-names = "core", "mem", "extal", "fsys", "spba";
344 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
345 dma-names = "rx", "tx";
346 status = "disabled";
347 };
348
349 ssi1: ssi@02028000 {
350 #sound-dai-cells = <0>;
351 compatible = "fsl,imx6q-ssi",
352 "fsl,imx51-ssi";
353 reg = <0x02028000 0x4000>;
354 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
356 <&clks IMX6QDL_CLK_SSI1>;
357 clock-names = "ipg", "baud";
358 dmas = <&sdma 37 1 0>,
359 <&sdma 38 1 0>;
360 dma-names = "rx", "tx";
361 fsl,fifo-depth = <15>;
362 status = "disabled";
363 };
364
365 ssi2: ssi@0202c000 {
366 #sound-dai-cells = <0>;
367 compatible = "fsl,imx6q-ssi",
368 "fsl,imx51-ssi";
369 reg = <0x0202c000 0x4000>;
370 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
372 <&clks IMX6QDL_CLK_SSI2>;
373 clock-names = "ipg", "baud";
374 dmas = <&sdma 41 1 0>,
375 <&sdma 42 1 0>;
376 dma-names = "rx", "tx";
377 fsl,fifo-depth = <15>;
378 status = "disabled";
379 };
380
381 ssi3: ssi@02030000 {
382 #sound-dai-cells = <0>;
383 compatible = "fsl,imx6q-ssi",
384 "fsl,imx51-ssi";
385 reg = <0x02030000 0x4000>;
386 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
388 <&clks IMX6QDL_CLK_SSI3>;
389 clock-names = "ipg", "baud";
390 dmas = <&sdma 45 1 0>,
391 <&sdma 46 1 0>;
392 dma-names = "rx", "tx";
393 fsl,fifo-depth = <15>;
394 status = "disabled";
395 };
396
397 asrc: asrc@02034000 {
398 compatible = "fsl,imx53-asrc";
399 reg = <0x02034000 0x4000>;
400 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
402 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
403 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
404 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
405 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
406 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
407 <&clks IMX6QDL_CLK_SPBA>;
408 clock-names = "mem", "ipg", "asrck_0",
409 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
410 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
411 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
412 "asrck_d", "asrck_e", "asrck_f", "spba";
413 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
414 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
415 dma-names = "rxa", "rxb", "rxc",
416 "txa", "txb", "txc";
417 fsl,asrc-rate = <48000>;
418 fsl,asrc-width = <16>;
419 status = "okay";
420 };
421
422 spba@0203c000 {
423 reg = <0x0203c000 0x4000>;
424 };
425 };
426
427 vpu: vpu@02040000 {
428 compatible = "cnm,coda960";
429 reg = <0x02040000 0x3c000>;
430 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
431 <0 3 IRQ_TYPE_LEVEL_HIGH>;
432 interrupt-names = "bit", "jpeg";
433 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
434 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
435 clock-names = "per", "ahb";
436 power-domains = <&gpc 1>;
437 resets = <&src 1>;
438 iram = <&ocram>;
439 };
440
441 aipstz@0207c000 { /* AIPSTZ1 */
442 reg = <0x0207c000 0x4000>;
443 };
444
445 pwm1: pwm@02080000 {
446 #pwm-cells = <2>;
447 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
448 reg = <0x02080000 0x4000>;
449 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clks IMX6QDL_CLK_IPG>,
451 <&clks IMX6QDL_CLK_PWM1>;
452 clock-names = "ipg", "per";
453 status = "disabled";
454 };
455
456 pwm2: pwm@02084000 {
457 #pwm-cells = <2>;
458 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
459 reg = <0x02084000 0x4000>;
460 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clks IMX6QDL_CLK_IPG>,
462 <&clks IMX6QDL_CLK_PWM2>;
463 clock-names = "ipg", "per";
464 status = "disabled";
465 };
466
467 pwm3: pwm@02088000 {
468 #pwm-cells = <2>;
469 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
470 reg = <0x02088000 0x4000>;
471 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&clks IMX6QDL_CLK_IPG>,
473 <&clks IMX6QDL_CLK_PWM3>;
474 clock-names = "ipg", "per";
475 status = "disabled";
476 };
477
478 pwm4: pwm@0208c000 {
479 #pwm-cells = <2>;
480 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
481 reg = <0x0208c000 0x4000>;
482 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&clks IMX6QDL_CLK_IPG>,
484 <&clks IMX6QDL_CLK_PWM4>;
485 clock-names = "ipg", "per";
486 status = "disabled";
487 };
488
489 can1: flexcan@02090000 {
490 compatible = "fsl,imx6q-flexcan";
491 reg = <0x02090000 0x4000>;
492 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
494 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
495 clock-names = "ipg", "per";
496 status = "disabled";
497 };
498
499 can2: flexcan@02094000 {
500 compatible = "fsl,imx6q-flexcan";
501 reg = <0x02094000 0x4000>;
502 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
504 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
505 clock-names = "ipg", "per";
506 status = "disabled";
507 };
508
509 gpt: gpt@02098000 {
510 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
511 reg = <0x02098000 0x4000>;
512 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
514 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
515 <&clks IMX6QDL_CLK_GPT_3M>;
516 clock-names = "ipg", "per", "osc_per";
517 };
518
519 gpio1: gpio@0209c000 {
520 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
521 reg = <0x0209c000 0x4000>;
522 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
523 <0 67 IRQ_TYPE_LEVEL_HIGH>;
524 gpio-controller;
525 #gpio-cells = <2>;
526 interrupt-controller;
527 #interrupt-cells = <2>;
528 };
529
530 gpio2: gpio@020a0000 {
531 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
532 reg = <0x020a0000 0x4000>;
533 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
534 <0 69 IRQ_TYPE_LEVEL_HIGH>;
535 gpio-controller;
536 #gpio-cells = <2>;
537 interrupt-controller;
538 #interrupt-cells = <2>;
539 };
540
541 gpio3: gpio@020a4000 {
542 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
543 reg = <0x020a4000 0x4000>;
544 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
545 <0 71 IRQ_TYPE_LEVEL_HIGH>;
546 gpio-controller;
547 #gpio-cells = <2>;
548 interrupt-controller;
549 #interrupt-cells = <2>;
550 };
551
552 gpio4: gpio@020a8000 {
553 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
554 reg = <0x020a8000 0x4000>;
555 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
556 <0 73 IRQ_TYPE_LEVEL_HIGH>;
557 gpio-controller;
558 #gpio-cells = <2>;
559 interrupt-controller;
560 #interrupt-cells = <2>;
561 };
562
563 gpio5: gpio@020ac000 {
564 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
565 reg = <0x020ac000 0x4000>;
566 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
567 <0 75 IRQ_TYPE_LEVEL_HIGH>;
568 gpio-controller;
569 #gpio-cells = <2>;
570 interrupt-controller;
571 #interrupt-cells = <2>;
572 };
573
574 gpio6: gpio@020b0000 {
575 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
576 reg = <0x020b0000 0x4000>;
577 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
578 <0 77 IRQ_TYPE_LEVEL_HIGH>;
579 gpio-controller;
580 #gpio-cells = <2>;
581 interrupt-controller;
582 #interrupt-cells = <2>;
583 };
584
585 gpio7: gpio@020b4000 {
586 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
587 reg = <0x020b4000 0x4000>;
588 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
589 <0 79 IRQ_TYPE_LEVEL_HIGH>;
590 gpio-controller;
591 #gpio-cells = <2>;
592 interrupt-controller;
593 #interrupt-cells = <2>;
594 };
595
596 kpp: kpp@020b8000 {
597 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
598 reg = <0x020b8000 0x4000>;
599 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&clks IMX6QDL_CLK_IPG>;
601 status = "disabled";
602 };
603
604 wdog1: wdog@020bc000 {
605 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
606 reg = <0x020bc000 0x4000>;
607 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&clks IMX6QDL_CLK_DUMMY>;
609 };
610
611 wdog2: wdog@020c0000 {
612 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
613 reg = <0x020c0000 0x4000>;
614 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&clks IMX6QDL_CLK_DUMMY>;
616 status = "disabled";
617 };
618
619 clks: ccm@020c4000 {
620 compatible = "fsl,imx6q-ccm";
621 reg = <0x020c4000 0x4000>;
622 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
623 <0 88 IRQ_TYPE_LEVEL_HIGH>;
624 #clock-cells = <1>;
625 };
626
627 anatop: anatop@020c8000 {
628 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
629 reg = <0x020c8000 0x1000>;
630 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
631 <0 54 IRQ_TYPE_LEVEL_HIGH>,
632 <0 127 IRQ_TYPE_LEVEL_HIGH>;
633
634 regulator-1p1 {
635 compatible = "fsl,anatop-regulator";
636 regulator-name = "vdd1p1";
637 regulator-min-microvolt = <800000>;
638 regulator-max-microvolt = <1375000>;
639 regulator-always-on;
640 anatop-reg-offset = <0x110>;
641 anatop-vol-bit-shift = <8>;
642 anatop-vol-bit-width = <5>;
643 anatop-min-bit-val = <4>;
644 anatop-min-voltage = <800000>;
645 anatop-max-voltage = <1375000>;
646 };
647
648 regulator-3p0 {
649 compatible = "fsl,anatop-regulator";
650 regulator-name = "vdd3p0";
651 regulator-min-microvolt = <2800000>;
652 regulator-max-microvolt = <3150000>;
653 regulator-always-on;
654 anatop-reg-offset = <0x120>;
655 anatop-vol-bit-shift = <8>;
656 anatop-vol-bit-width = <5>;
657 anatop-min-bit-val = <0>;
658 anatop-min-voltage = <2625000>;
659 anatop-max-voltage = <3400000>;
660 };
661
662 regulator-2p5 {
663 compatible = "fsl,anatop-regulator";
664 regulator-name = "vdd2p5";
665 regulator-min-microvolt = <2000000>;
666 regulator-max-microvolt = <2750000>;
667 regulator-always-on;
668 anatop-reg-offset = <0x130>;
669 anatop-vol-bit-shift = <8>;
670 anatop-vol-bit-width = <5>;
671 anatop-min-bit-val = <0>;
672 anatop-min-voltage = <2000000>;
673 anatop-max-voltage = <2750000>;
674 };
675
676 reg_arm: regulator-vddcore {
677 compatible = "fsl,anatop-regulator";
678 regulator-name = "vddarm";
679 regulator-min-microvolt = <725000>;
680 regulator-max-microvolt = <1450000>;
681 regulator-always-on;
682 anatop-reg-offset = <0x140>;
683 anatop-vol-bit-shift = <0>;
684 anatop-vol-bit-width = <5>;
685 anatop-delay-reg-offset = <0x170>;
686 anatop-delay-bit-shift = <24>;
687 anatop-delay-bit-width = <2>;
688 anatop-min-bit-val = <1>;
689 anatop-min-voltage = <725000>;
690 anatop-max-voltage = <1450000>;
691 };
692
693 reg_pu: regulator-vddpu {
694 compatible = "fsl,anatop-regulator";
695 regulator-name = "vddpu";
696 regulator-min-microvolt = <725000>;
697 regulator-max-microvolt = <1450000>;
698 regulator-enable-ramp-delay = <150>;
699 anatop-reg-offset = <0x140>;
700 anatop-vol-bit-shift = <9>;
701 anatop-vol-bit-width = <5>;
702 anatop-delay-reg-offset = <0x170>;
703 anatop-delay-bit-shift = <26>;
704 anatop-delay-bit-width = <2>;
705 anatop-min-bit-val = <1>;
706 anatop-min-voltage = <725000>;
707 anatop-max-voltage = <1450000>;
708 };
709
710 reg_soc: regulator-vddsoc {
711 compatible = "fsl,anatop-regulator";
712 regulator-name = "vddsoc";
713 regulator-min-microvolt = <725000>;
714 regulator-max-microvolt = <1450000>;
715 regulator-always-on;
716 anatop-reg-offset = <0x140>;
717 anatop-vol-bit-shift = <18>;
718 anatop-vol-bit-width = <5>;
719 anatop-delay-reg-offset = <0x170>;
720 anatop-delay-bit-shift = <28>;
721 anatop-delay-bit-width = <2>;
722 anatop-min-bit-val = <1>;
723 anatop-min-voltage = <725000>;
724 anatop-max-voltage = <1450000>;
725 };
726 };
727
728 tempmon: tempmon {
729 compatible = "fsl,imx6q-tempmon";
730 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
731 fsl,tempmon = <&anatop>;
732 fsl,tempmon-data = <&ocotp>;
733 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
734 };
735
736 usbphy1: usbphy@020c9000 {
737 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
738 reg = <0x020c9000 0x1000>;
739 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
741 fsl,anatop = <&anatop>;
742 };
743
744 usbphy2: usbphy@020ca000 {
745 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
746 reg = <0x020ca000 0x1000>;
747 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
749 fsl,anatop = <&anatop>;
750 };
751
752 snvs: snvs@020cc000 {
753 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
754 reg = <0x020cc000 0x4000>;
755
756 snvs_rtc: snvs-rtc-lp {
757 compatible = "fsl,sec-v4.0-mon-rtc-lp";
758 regmap = <&snvs>;
759 offset = <0x34>;
760 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
761 <0 20 IRQ_TYPE_LEVEL_HIGH>;
762 };
763
764 snvs_poweroff: snvs-poweroff {
765 compatible = "syscon-poweroff";
766 regmap = <&snvs>;
767 offset = <0x38>;
768 mask = <0x60>;
769 status = "disabled";
770 };
771 };
772
773 epit1: epit@020d0000 { /* EPIT1 */
774 reg = <0x020d0000 0x4000>;
775 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
776 };
777
778 epit2: epit@020d4000 { /* EPIT2 */
779 reg = <0x020d4000 0x4000>;
780 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
781 };
782
783 src: src@020d8000 {
784 compatible = "fsl,imx6q-src", "fsl,imx51-src";
785 reg = <0x020d8000 0x4000>;
786 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
787 <0 96 IRQ_TYPE_LEVEL_HIGH>;
788 #reset-cells = <1>;
789 };
790
791 gpc: gpc@020dc000 {
792 compatible = "fsl,imx6q-gpc";
793 reg = <0x020dc000 0x4000>;
794 interrupt-controller;
795 #interrupt-cells = <3>;
796 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
797 <0 90 IRQ_TYPE_LEVEL_HIGH>;
798 interrupt-parent = <&intc>;
799 pu-supply = <®_pu>;
800 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
801 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
802 <&clks IMX6QDL_CLK_GPU2D_CORE>,
803 <&clks IMX6QDL_CLK_GPU2D_AXI>,
804 <&clks IMX6QDL_CLK_OPENVG_AXI>,
805 <&clks IMX6QDL_CLK_VPU_AXI>;
806 #power-domain-cells = <1>;
807 };
808
809 gpr: iomuxc-gpr@020e0000 {
810 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
811 reg = <0x020e0000 0x38>;
812 };
813
814 iomuxc: iomuxc@020e0000 {
815 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
816 reg = <0x020e0000 0x4000>;
817 };
818
819 ldb: ldb@020e0008 {
820 #address-cells = <1>;
821 #size-cells = <0>;
822 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
823 gpr = <&gpr>;
824 status = "disabled";
825
826 lvds-channel@0 {
827 #address-cells = <1>;
828 #size-cells = <0>;
829 reg = <0>;
830 status = "disabled";
831
832 port@0 {
833 reg = <0>;
834
835 lvds0_mux_0: endpoint {
836 remote-endpoint = <&ipu1_di0_lvds0>;
837 };
838 };
839
840 port@1 {
841 reg = <1>;
842
843 lvds0_mux_1: endpoint {
844 remote-endpoint = <&ipu1_di1_lvds0>;
845 };
846 };
847 };
848
849 lvds-channel@1 {
850 #address-cells = <1>;
851 #size-cells = <0>;
852 reg = <1>;
853 status = "disabled";
854
855 port@0 {
856 reg = <0>;
857
858 lvds1_mux_0: endpoint {
859 remote-endpoint = <&ipu1_di0_lvds1>;
860 };
861 };
862
863 port@1 {
864 reg = <1>;
865
866 lvds1_mux_1: endpoint {
867 remote-endpoint = <&ipu1_di1_lvds1>;
868 };
869 };
870 };
871 };
872
873 dcic1: dcic@020e4000 {
874 reg = <0x020e4000 0x4000>;
875 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
876 };
877
878 dcic2: dcic@020e8000 {
879 reg = <0x020e8000 0x4000>;
880 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
881 };
882
883 sdma: sdma@020ec000 {
884 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
885 reg = <0x020ec000 0x4000>;
886 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&clks IMX6QDL_CLK_SDMA>,
888 <&clks IMX6QDL_CLK_SDMA>;
889 clock-names = "ipg", "ahb";
890 #dma-cells = <3>;
891 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
892 };
893 };
894
895 aips-bus@02100000 { /* AIPS2 */
896 compatible = "fsl,aips-bus", "simple-bus";
897 #address-cells = <1>;
898 #size-cells = <1>;
899 reg = <0x02100000 0x100000>;
900 ranges;
901
902 crypto: caam@2100000 {
903 compatible = "fsl,sec-v4.0";
904 fsl,sec-era = <4>;
905 #address-cells = <1>;
906 #size-cells = <1>;
907 reg = <0x2100000 0x10000>;
908 ranges = <0 0x2100000 0x10000>;
909 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
910 <&clks IMX6QDL_CLK_CAAM_ACLK>,
911 <&clks IMX6QDL_CLK_CAAM_IPG>,
912 <&clks IMX6QDL_CLK_EIM_SLOW>;
913 clock-names = "mem", "aclk", "ipg", "emi_slow";
914
915 sec_jr0: jr0@1000 {
916 compatible = "fsl,sec-v4.0-job-ring";
917 reg = <0x1000 0x1000>;
918 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
919 };
920
921 sec_jr1: jr1@2000 {
922 compatible = "fsl,sec-v4.0-job-ring";
923 reg = <0x2000 0x1000>;
924 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
925 };
926 };
927
928 aipstz@0217c000 { /* AIPSTZ2 */
929 reg = <0x0217c000 0x4000>;
930 };
931
932 usbotg: usb@02184000 {
933 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
934 reg = <0x02184000 0x200>;
935 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clks IMX6QDL_CLK_USBOH3>;
937 fsl,usbphy = <&usbphy1>;
938 fsl,usbmisc = <&usbmisc 0>;
939 ahb-burst-config = <0x0>;
940 tx-burst-size-dword = <0x10>;
941 rx-burst-size-dword = <0x10>;
942 status = "disabled";
943 };
944
945 usbh1: usb@02184200 {
946 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
947 reg = <0x02184200 0x200>;
948 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&clks IMX6QDL_CLK_USBOH3>;
950 fsl,usbphy = <&usbphy2>;
951 fsl,usbmisc = <&usbmisc 1>;
952 dr_mode = "host";
953 ahb-burst-config = <0x0>;
954 tx-burst-size-dword = <0x10>;
955 rx-burst-size-dword = <0x10>;
956 status = "disabled";
957 };
958
959 usbh2: usb@02184400 {
960 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
961 reg = <0x02184400 0x200>;
962 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&clks IMX6QDL_CLK_USBOH3>;
964 fsl,usbmisc = <&usbmisc 2>;
965 dr_mode = "host";
966 ahb-burst-config = <0x0>;
967 tx-burst-size-dword = <0x10>;
968 rx-burst-size-dword = <0x10>;
969 status = "disabled";
970 };
971
972 usbh3: usb@02184600 {
973 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
974 reg = <0x02184600 0x200>;
975 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&clks IMX6QDL_CLK_USBOH3>;
977 fsl,usbmisc = <&usbmisc 3>;
978 dr_mode = "host";
979 ahb-burst-config = <0x0>;
980 tx-burst-size-dword = <0x10>;
981 rx-burst-size-dword = <0x10>;
982 status = "disabled";
983 };
984
985 usbmisc: usbmisc@02184800 {
986 #index-cells = <1>;
987 compatible = "fsl,imx6q-usbmisc";
988 reg = <0x02184800 0x200>;
989 clocks = <&clks IMX6QDL_CLK_USBOH3>;
990 };
991
992 fec: ethernet@02188000 {
993 compatible = "fsl,imx6q-fec";
994 reg = <0x02188000 0x4000>;
995 interrupts-extended =
996 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
997 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&clks IMX6QDL_CLK_ENET>,
999 <&clks IMX6QDL_CLK_ENET>,
1000 <&clks IMX6QDL_CLK_ENET_REF>;
1001 clock-names = "ipg", "ahb", "ptp";
1002 status = "disabled";
1003 };
1004
1005 mlb@0218c000 {
1006 reg = <0x0218c000 0x4000>;
1007 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1008 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1009 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1010 };
1011
1012 usdhc1: usdhc@02190000 {
1013 compatible = "fsl,imx6q-usdhc";
1014 reg = <0x02190000 0x4000>;
1015 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1016 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1017 <&clks IMX6QDL_CLK_USDHC1>,
1018 <&clks IMX6QDL_CLK_USDHC1>;
1019 clock-names = "ipg", "ahb", "per";
1020 bus-width = <4>;
1021 status = "disabled";
1022 };
1023
1024 usdhc2: usdhc@02194000 {
1025 compatible = "fsl,imx6q-usdhc";
1026 reg = <0x02194000 0x4000>;
1027 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1028 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1029 <&clks IMX6QDL_CLK_USDHC2>,
1030 <&clks IMX6QDL_CLK_USDHC2>;
1031 clock-names = "ipg", "ahb", "per";
1032 bus-width = <4>;
1033 status = "disabled";
1034 };
1035
1036 usdhc3: usdhc@02198000 {
1037 compatible = "fsl,imx6q-usdhc";
1038 reg = <0x02198000 0x4000>;
1039 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1040 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1041 <&clks IMX6QDL_CLK_USDHC3>,
1042 <&clks IMX6QDL_CLK_USDHC3>;
1043 clock-names = "ipg", "ahb", "per";
1044 bus-width = <4>;
1045 status = "disabled";
1046 };
1047
1048 usdhc4: usdhc@0219c000 {
1049 compatible = "fsl,imx6q-usdhc";
1050 reg = <0x0219c000 0x4000>;
1051 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1053 <&clks IMX6QDL_CLK_USDHC4>,
1054 <&clks IMX6QDL_CLK_USDHC4>;
1055 clock-names = "ipg", "ahb", "per";
1056 bus-width = <4>;
1057 status = "disabled";
1058 };
1059
1060 i2c1: i2c@021a0000 {
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1063 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1064 reg = <0x021a0000 0x4000>;
1065 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&clks IMX6QDL_CLK_I2C1>;
1067 status = "disabled";
1068 };
1069
1070 i2c2: i2c@021a4000 {
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1073 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1074 reg = <0x021a4000 0x4000>;
1075 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&clks IMX6QDL_CLK_I2C2>;
1077 status = "disabled";
1078 };
1079
1080 i2c3: i2c@021a8000 {
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1083 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1084 reg = <0x021a8000 0x4000>;
1085 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1086 clocks = <&clks IMX6QDL_CLK_I2C3>;
1087 status = "disabled";
1088 };
1089
1090 romcp@021ac000 {
1091 reg = <0x021ac000 0x4000>;
1092 };
1093
1094 mmdc0: mmdc@021b0000 { /* MMDC0 */
1095 compatible = "fsl,imx6q-mmdc";
1096 reg = <0x021b0000 0x4000>;
1097 };
1098
1099 mmdc1: mmdc@021b4000 { /* MMDC1 */
1100 reg = <0x021b4000 0x4000>;
1101 };
1102
1103 weim: weim@021b8000 {
1104 #address-cells = <2>;
1105 #size-cells = <1>;
1106 compatible = "fsl,imx6q-weim";
1107 reg = <0x021b8000 0x4000>;
1108 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1109 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1110 fsl,weim-cs-gpr = <&gpr>;
1111 status = "disabled";
1112 };
1113
1114 ocotp: ocotp@021bc000 {
1115 compatible = "fsl,imx6q-ocotp", "syscon";
1116 reg = <0x021bc000 0x4000>;
1117 clocks = <&clks IMX6QDL_CLK_IIM>;
1118 };
1119
1120 tzasc@021d0000 { /* TZASC1 */
1121 reg = <0x021d0000 0x4000>;
1122 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1123 };
1124
1125 tzasc@021d4000 { /* TZASC2 */
1126 reg = <0x021d4000 0x4000>;
1127 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1128 };
1129
1130 audmux: audmux@021d8000 {
1131 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1132 reg = <0x021d8000 0x4000>;
1133 status = "disabled";
1134 };
1135
1136 mipi_csi: mipi@021dc000 {
1137 reg = <0x021dc000 0x4000>;
1138 };
1139
1140 mipi_dsi: mipi@021e0000 {
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1143 reg = <0x021e0000 0x4000>;
1144 status = "disabled";
1145
1146 ports {
1147 #address-cells = <1>;
1148 #size-cells = <0>;
1149
1150 port@0 {
1151 reg = <0>;
1152
1153 mipi_mux_0: endpoint {
1154 remote-endpoint = <&ipu1_di0_mipi>;
1155 };
1156 };
1157
1158 port@1 {
1159 reg = <1>;
1160
1161 mipi_mux_1: endpoint {
1162 remote-endpoint = <&ipu1_di1_mipi>;
1163 };
1164 };
1165 };
1166 };
1167
1168 vdoa@021e4000 {
1169 reg = <0x021e4000 0x4000>;
1170 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1171 };
1172
1173 uart2: serial@021e8000 {
1174 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1175 reg = <0x021e8000 0x4000>;
1176 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1178 <&clks IMX6QDL_CLK_UART_SERIAL>;
1179 clock-names = "ipg", "per";
1180 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1181 dma-names = "rx", "tx";
1182 status = "disabled";
1183 };
1184
1185 uart3: serial@021ec000 {
1186 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1187 reg = <0x021ec000 0x4000>;
1188 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1189 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1190 <&clks IMX6QDL_CLK_UART_SERIAL>;
1191 clock-names = "ipg", "per";
1192 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1193 dma-names = "rx", "tx";
1194 status = "disabled";
1195 };
1196
1197 uart4: serial@021f0000 {
1198 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1199 reg = <0x021f0000 0x4000>;
1200 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1201 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1202 <&clks IMX6QDL_CLK_UART_SERIAL>;
1203 clock-names = "ipg", "per";
1204 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1205 dma-names = "rx", "tx";
1206 status = "disabled";
1207 };
1208
1209 uart5: serial@021f4000 {
1210 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1211 reg = <0x021f4000 0x4000>;
1212 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1213 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1214 <&clks IMX6QDL_CLK_UART_SERIAL>;
1215 clock-names = "ipg", "per";
1216 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1217 dma-names = "rx", "tx";
1218 status = "disabled";
1219 };
1220 };
1221
1222 ipu1: ipu@02400000 {
1223 #address-cells = <1>;
1224 #size-cells = <0>;
1225 compatible = "fsl,imx6q-ipu";
1226 reg = <0x02400000 0x400000>;
1227 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1228 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1229 clocks = <&clks IMX6QDL_CLK_IPU1>,
1230 <&clks IMX6QDL_CLK_IPU1_DI0>,
1231 <&clks IMX6QDL_CLK_IPU1_DI1>;
1232 clock-names = "bus", "di0", "di1";
1233 resets = <&src 2>;
1234
1235 ipu1_csi0: port@0 {
1236 reg = <0>;
1237 };
1238
1239 ipu1_csi1: port@1 {
1240 reg = <1>;
1241 };
1242
1243 ipu1_di0: port@2 {
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1246 reg = <2>;
1247
1248 ipu1_di0_disp0: disp0-endpoint {
1249 };
1250
1251 ipu1_di0_hdmi: hdmi-endpoint {
1252 remote-endpoint = <&hdmi_mux_0>;
1253 };
1254
1255 ipu1_di0_mipi: mipi-endpoint {
1256 remote-endpoint = <&mipi_mux_0>;
1257 };
1258
1259 ipu1_di0_lvds0: lvds0-endpoint {
1260 remote-endpoint = <&lvds0_mux_0>;
1261 };
1262
1263 ipu1_di0_lvds1: lvds1-endpoint {
1264 remote-endpoint = <&lvds1_mux_0>;
1265 };
1266 };
1267
1268 ipu1_di1: port@3 {
1269 #address-cells = <1>;
1270 #size-cells = <0>;
1271 reg = <3>;
1272
1273 ipu1_di1_disp1: disp1-endpoint {
1274 };
1275
1276 ipu1_di1_hdmi: hdmi-endpoint {
1277 remote-endpoint = <&hdmi_mux_1>;
1278 };
1279
1280 ipu1_di1_mipi: mipi-endpoint {
1281 remote-endpoint = <&mipi_mux_1>;
1282 };
1283
1284 ipu1_di1_lvds0: lvds0-endpoint {
1285 remote-endpoint = <&lvds0_mux_1>;
1286 };
1287
1288 ipu1_di1_lvds1: lvds1-endpoint {
1289 remote-endpoint = <&lvds1_mux_1>;
1290 };
1291 };
1292 };
1293 };
1294};