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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11 chosen {
12 stdout-path = &uart1;
13 };
14
15 sound {
16 compatible = "fsl,imx6-wandboard-sgtl5000",
17 "fsl,imx-audio-sgtl5000";
18 model = "imx6-wandboard-sgtl5000";
19 ssi-controller = <&ssi1>;
20 audio-codec = <&codec>;
21 audio-routing =
22 "MIC_IN", "Mic Jack",
23 "Mic Jack", "Mic Bias",
24 "Headphone Jack", "HP_OUT";
25 mux-int-port = <1>;
26 mux-ext-port = <3>;
27 };
28
29 sound-spdif {
30 compatible = "fsl,imx-audio-spdif";
31 model = "imx-spdif";
32 spdif-controller = <&spdif>;
33 spdif-out;
34 };
35
36 reg_1p5v: regulator-1p5v {
37 compatible = "regulator-fixed";
38 regulator-name = "1P5V";
39 regulator-min-microvolt = <1500000>;
40 regulator-max-microvolt = <1500000>;
41 regulator-always-on;
42 };
43
44 reg_1p8v: regulator-1p8v {
45 compatible = "regulator-fixed";
46 regulator-name = "1P8V";
47 regulator-min-microvolt = <1800000>;
48 regulator-max-microvolt = <1800000>;
49 regulator-always-on;
50 };
51
52 reg_2p8v: regulator-2p8v {
53 compatible = "regulator-fixed";
54 regulator-name = "2P8V";
55 regulator-min-microvolt = <2800000>;
56 regulator-max-microvolt = <2800000>;
57 regulator-always-on;
58 };
59
60 reg_2p5v: regulator-2p5v {
61 compatible = "regulator-fixed";
62 regulator-name = "2P5V";
63 regulator-min-microvolt = <2500000>;
64 regulator-max-microvolt = <2500000>;
65 regulator-always-on;
66 };
67
68 reg_3p3v: regulator-3p3v {
69 compatible = "regulator-fixed";
70 regulator-name = "3P3V";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 regulator-always-on;
74 };
75
76 reg_usb_otg_vbus: regulator-usbotgvbus {
77 compatible = "regulator-fixed";
78 regulator-name = "usb_otg_vbus";
79 regulator-min-microvolt = <5000000>;
80 regulator-max-microvolt = <5000000>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_usbotgvbus>;
83 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
84 };
85};
86
87&audmux {
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_audmux>;
90 status = "okay";
91};
92
93&hdmi {
94 ddc-i2c-bus = <&i2c1>;
95 status = "okay";
96};
97
98&i2c1 {
99 clock-frequency = <100000>;
100 pinctrl-names = "default", "gpio";
101 pinctrl-0 = <&pinctrl_i2c1>;
102 pinctrl-1 = <&pinctrl_i2c1_gpio>;
103 scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
104 sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
105 status = "okay";
106};
107
108&i2c2 {
109 clock-frequency = <100000>;
110 pinctrl-names = "default", "gpio";
111 pinctrl-0 = <&pinctrl_i2c2>;
112 pinctrl-1 = <&pinctrl_i2c2_gpio>;
113 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
114 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
115 status = "okay";
116
117 codec: sgtl5000@a {
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_mclk>;
120 compatible = "fsl,sgtl5000";
121 reg = <0x0a>;
122 clocks = <&clks IMX6QDL_CLK_CKO>;
123 VDDA-supply = <®_2p5v>;
124 VDDIO-supply = <®_3p3v>;
125 lrclk-strength = <3>;
126 };
127
128 camera@3c {
129 compatible = "ovti,ov5645";
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_ov5645>;
132 reg = <0x3c>;
133 clocks = <&clks IMX6QDL_CLK_CKO2>;
134 clock-frequency = <24000000>;
135 vdddo-supply = <®_1p8v>;
136 vdda-supply = <®_2p8v>;
137 vddd-supply = <®_1p5v>;
138 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
139 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
140
141 port {
142 ov5645_to_mipi_csi2: endpoint {
143 remote-endpoint = <&mipi_csi2_in>;
144 clock-lanes = <0>;
145 data-lanes = <1 2>;
146 };
147 };
148 };
149};
150
151&iomuxc {
152 pinctrl-names = "default";
153
154 imx6qdl-wandboard {
155
156 pinctrl_audmux: audmuxgrp {
157 fsl,pins = <
158 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
159 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
160 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
161 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
162 >;
163 };
164
165 pinctrl_enet: enetgrp {
166 fsl,pins = <
167 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
168 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
169 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
170 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
171 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
172 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
173 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
174 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
175 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
176 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
177 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
178 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
179 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
180 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
181 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
182 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
183 >;
184 };
185
186 pinctrl_i2c1: i2c1grp {
187 fsl,pins = <
188 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
189 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
190 >;
191 };
192
193 pinctrl_i2c1_gpio: i2c1gpiogrp {
194 fsl,pins = <
195 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b0
196 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b0
197 >;
198 };
199
200 pinctrl_i2c2: i2c2grp {
201 fsl,pins = <
202 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
203 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
204 >;
205 };
206
207 pinctrl_i2c2_gpio: i2c2gpiogrp {
208 fsl,pins = <
209 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b0
210 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b0
211 >;
212 };
213
214 pinctrl_mclk: mclkgrp {
215 fsl,pins = <
216 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
217 >;
218 };
219
220 pinctrl_ov5645: ov5645grp {
221 fsl,pins = <
222 MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
223 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
224 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
225 >;
226 };
227
228 pinctrl_spdif: spdifgrp {
229 fsl,pins = <
230 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
231 >;
232 };
233
234 pinctrl_uart1: uart1grp {
235 fsl,pins = <
236 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
237 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
238 >;
239 };
240
241 pinctrl_uart3: uart3grp {
242 fsl,pins = <
243 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
244 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
245 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
246 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
247 >;
248 };
249
250 pinctrl_usbotg: usbotggrp {
251 fsl,pins = <
252 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
253 >;
254 };
255
256 pinctrl_usbotgvbus: usbotgvbusgrp {
257 fsl,pins = <
258 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
259 >;
260 };
261
262 pinctrl_usdhc1: usdhc1grp {
263 fsl,pins = <
264 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
265 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
266 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
267 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
268 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
269 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
270 >;
271 };
272
273 pinctrl_usdhc2: usdhc2grp {
274 fsl,pins = <
275 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
276 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
277 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
278 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
279 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
280 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
281 >;
282 };
283
284 pinctrl_usdhc3: usdhc3grp {
285 fsl,pins = <
286 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
287 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
288 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
289 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
290 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
291 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
292 >;
293 };
294 };
295};
296
297&fec {
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_enet>;
300 phy-mode = "rgmii-id";
301 phy-handle = <ðphy>;
302 phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
303 status = "okay";
304
305 mdio {
306 #address-cells = <1>;
307 #size-cells = <0>;
308
309 ethphy: ethernet-phy@1 {
310 reg = <1>;
311 qca,clk-out-frequency = <125000000>;
312 };
313 };
314};
315
316&mipi_csi {
317 status = "okay";
318
319 port@0 {
320 reg = <0>;
321
322 mipi_csi2_in: endpoint {
323 remote-endpoint = <&ov5645_to_mipi_csi2>;
324 clock-lanes = <0>;
325 data-lanes = <1 2>;
326 };
327 };
328};
329
330&spdif {
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_spdif>;
333 status = "okay";
334};
335
336&ssi1 {
337 status = "okay";
338};
339
340&uart1 {
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_uart1>;
343 status = "okay";
344};
345
346&uart3 {
347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_uart3>;
349 uart-has-rtscts;
350 status = "okay";
351};
352
353&usbh1 {
354 status = "okay";
355};
356
357&usbotg {
358 vbus-supply = <®_usb_otg_vbus>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_usbotg>;
361 disable-over-current;
362 dr_mode = "otg";
363 status = "okay";
364};
365
366&usdhc1 {
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_usdhc1>;
369 cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
370 status = "okay";
371};
372
373&usdhc3 {
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_usdhc3>;
376 cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
377 status = "okay";
378};
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15 regulators {
16 compatible = "simple-bus";
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 reg_2p5v: regulator@0 {
21 compatible = "regulator-fixed";
22 reg = <0>;
23 regulator-name = "2P5V";
24 regulator-min-microvolt = <2500000>;
25 regulator-max-microvolt = <2500000>;
26 regulator-always-on;
27 };
28
29 reg_3p3v: regulator@1 {
30 compatible = "regulator-fixed";
31 reg = <1>;
32 regulator-name = "3P3V";
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 regulator-always-on;
36 };
37 };
38
39 sound {
40 compatible = "fsl,imx6-wandboard-sgtl5000",
41 "fsl,imx-audio-sgtl5000";
42 model = "imx6-wandboard-sgtl5000";
43 ssi-controller = <&ssi1>;
44 audio-codec = <&codec>;
45 audio-routing =
46 "MIC_IN", "Mic Jack",
47 "Mic Jack", "Mic Bias",
48 "Headphone Jack", "HP_OUT";
49 mux-int-port = <1>;
50 mux-ext-port = <3>;
51 };
52
53 sound-spdif {
54 compatible = "fsl,imx-audio-spdif";
55 model = "imx-spdif";
56 spdif-controller = <&spdif>;
57 spdif-out;
58 };
59};
60
61&audmux {
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_audmux>;
64 status = "okay";
65};
66
67&hdmi {
68 ddc-i2c-bus = <&i2c1>;
69 status = "okay";
70};
71
72&i2c1 {
73 clock-frequency = <100000>;
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_i2c1>;
76 status = "okay";
77};
78
79&i2c2 {
80 clock-frequency = <100000>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_i2c2>;
83 status = "okay";
84
85 codec: sgtl5000@0a {
86 compatible = "fsl,sgtl5000";
87 reg = <0x0a>;
88 clocks = <&clks IMX6QDL_CLK_CKO>;
89 VDDA-supply = <®_2p5v>;
90 VDDIO-supply = <®_3p3v>;
91 };
92};
93
94&iomuxc {
95 pinctrl-names = "default";
96
97 imx6qdl-wandboard {
98
99 pinctrl_audmux: audmuxgrp {
100 fsl,pins = <
101 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
102 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
103 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
104 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
105 >;
106 };
107
108 pinctrl_enet: enetgrp {
109 fsl,pins = <
110 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
111 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
112 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
113 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
114 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
115 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
116 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
117 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
118 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
119 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
120 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
121 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
122 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
123 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
124 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
125 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
126 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
127 >;
128 };
129
130 pinctrl_i2c1: i2c1grp {
131 fsl,pins = <
132 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
133 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
134 >;
135 };
136
137 pinctrl_i2c2: i2c2grp {
138 fsl,pins = <
139 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
140 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
141 >;
142 };
143
144 pinctrl_spdif: spdifgrp {
145 fsl,pins = <
146 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
147 >;
148 };
149
150 pinctrl_uart1: uart1grp {
151 fsl,pins = <
152 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
153 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
154 >;
155 };
156
157 pinctrl_uart3: uart3grp {
158 fsl,pins = <
159 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
160 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
161 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
162 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
163 >;
164 };
165
166 pinctrl_usbotg: usbotggrp {
167 fsl,pins = <
168 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
169 >;
170 };
171
172 pinctrl_usdhc1: usdhc1grp {
173 fsl,pins = <
174 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
175 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
176 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
177 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
178 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
179 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
180 >;
181 };
182
183 pinctrl_usdhc2: usdhc2grp {
184 fsl,pins = <
185 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
186 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
187 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
188 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
189 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
190 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
191 >;
192 };
193
194 pinctrl_usdhc3: usdhc3grp {
195 fsl,pins = <
196 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
197 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
198 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
199 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
200 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
201 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
202 >;
203 };
204 };
205};
206
207&fec {
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_enet>;
210 phy-mode = "rgmii";
211 phy-reset-gpios = <&gpio3 29 0>;
212 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
213 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
214 fsl,err006687-workaround-present;
215 status = "okay";
216};
217
218&spdif {
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_spdif>;
221 status = "okay";
222};
223
224&ssi1 {
225 status = "okay";
226};
227
228&uart1 {
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_uart1>;
231 status = "okay";
232};
233
234&uart3 {
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_uart3>;
237 uart-has-rtscts;
238 status = "okay";
239};
240
241&usbh1 {
242 status = "okay";
243};
244
245&usbotg {
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_usbotg>;
248 disable-over-current;
249 dr_mode = "peripheral";
250 status = "okay";
251};
252
253&usdhc1 {
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_usdhc1>;
256 cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
257 status = "okay";
258};
259
260&usdhc3 {
261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_usdhc3>;
263 cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
264 status = "okay";
265};