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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 led2 = &led2;
16 nand = &gpmi;
17 ssi0 = &ssi1;
18 usb0 = &usbh1;
19 usb1 = &usbotg;
20 };
21
22 chosen {
23 bootargs = "console=ttymxc1,115200";
24 };
25
26 backlight {
27 compatible = "pwm-backlight";
28 pwms = <&pwm4 0 5000000>;
29 brightness-levels = <0 4 8 16 32 64 128 255>;
30 default-brightness-level = <7>;
31 };
32
33 gpio-keys {
34 compatible = "gpio-keys";
35
36 user-pb {
37 label = "user_pb";
38 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
39 linux,code = <BTN_0>;
40 };
41
42 user-pb1x {
43 label = "user_pb1x";
44 linux,code = <BTN_1>;
45 interrupt-parent = <&gsc>;
46 interrupts = <0>;
47 };
48
49 key-erased {
50 label = "key-erased";
51 linux,code = <BTN_2>;
52 interrupt-parent = <&gsc>;
53 interrupts = <1>;
54 };
55
56 eeprom-wp {
57 label = "eeprom_wp";
58 linux,code = <BTN_3>;
59 interrupt-parent = <&gsc>;
60 interrupts = <2>;
61 };
62
63 tamper {
64 label = "tamper";
65 linux,code = <BTN_4>;
66 interrupt-parent = <&gsc>;
67 interrupts = <5>;
68 };
69
70 switch-hold {
71 label = "switch_hold";
72 linux,code = <BTN_5>;
73 interrupt-parent = <&gsc>;
74 interrupts = <7>;
75 };
76 };
77
78 leds {
79 compatible = "gpio-leds";
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_gpio_leds>;
82
83 led0: user1 {
84 label = "user1";
85 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
86 default-state = "on";
87 linux,default-trigger = "heartbeat";
88 };
89
90 led1: user2 {
91 label = "user2";
92 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
93 default-state = "off";
94 };
95
96 led2: user3 {
97 label = "user3";
98 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
99 default-state = "off";
100 };
101 };
102
103 memory@10000000 {
104 device_type = "memory";
105 reg = <0x10000000 0x40000000>;
106 };
107
108 pps {
109 compatible = "pps-gpio";
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_pps>;
112 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
113 status = "okay";
114 };
115
116 reg_1p0v: regulator-1p0v {
117 compatible = "regulator-fixed";
118 regulator-name = "1P0V";
119 regulator-min-microvolt = <1000000>;
120 regulator-max-microvolt = <1000000>;
121 regulator-always-on;
122 };
123
124 reg_3p3v: regulator-3p3v {
125 compatible = "regulator-fixed";
126 regulator-name = "3P3V";
127 regulator-min-microvolt = <3300000>;
128 regulator-max-microvolt = <3300000>;
129 regulator-always-on;
130 };
131
132 reg_can1_stby: regulator-can1-stby {
133 compatible = "regulator-fixed";
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_reg_can1>;
136 regulator-name = "can1_stby";
137 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
138 regulator-min-microvolt = <3300000>;
139 regulator-max-microvolt = <3300000>;
140 };
141
142 reg_usb_h1_vbus: regulator-usb-h1-vbus {
143 compatible = "regulator-fixed";
144 regulator-name = "usb_h1_vbus";
145 regulator-min-microvolt = <5000000>;
146 regulator-max-microvolt = <5000000>;
147 regulator-always-on;
148 };
149
150 reg_usb_otg_vbus: regulator-usb-otg-vbus {
151 compatible = "regulator-fixed";
152 regulator-name = "usb_otg_vbus";
153 regulator-min-microvolt = <5000000>;
154 regulator-max-microvolt = <5000000>;
155 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
156 enable-active-high;
157 };
158
159 sound {
160 compatible = "fsl,imx6q-ventana-sgtl5000",
161 "fsl,imx-audio-sgtl5000";
162 model = "sgtl5000-audio";
163 ssi-controller = <&ssi1>;
164 audio-codec = <&codec>;
165 audio-routing =
166 "MIC_IN", "Mic Jack",
167 "Mic Jack", "Mic Bias",
168 "Headphone Jack", "HP_OUT";
169 mux-int-port = <1>;
170 mux-ext-port = <4>;
171 };
172};
173
174&audmux {
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_audmux>;
177 status = "okay";
178};
179
180&can1 {
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_flexcan1>;
183 xceiver-supply = <®_can1_stby>;
184 status = "okay";
185};
186
187&clks {
188 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
189 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
190 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
191 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
192};
193
194&fec {
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_enet>;
197 phy-mode = "rgmii-id";
198 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
199 status = "okay";
200};
201
202&gpmi {
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_gpmi_nand>;
205 status = "okay";
206};
207
208&hdmi {
209 ddc-i2c-bus = <&i2c3>;
210 status = "okay";
211};
212
213&i2c1 {
214 clock-frequency = <100000>;
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_i2c1>;
217 status = "okay";
218
219 gsc: gsc@20 {
220 compatible = "gw,gsc";
221 reg = <0x20>;
222 interrupt-parent = <&gpio1>;
223 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
224 interrupt-controller;
225 #interrupt-cells = <1>;
226 #size-cells = <0>;
227
228 adc {
229 compatible = "gw,gsc-adc";
230 #address-cells = <1>;
231 #size-cells = <0>;
232
233 channel@0 {
234 gw,mode = <0>;
235 reg = <0x00>;
236 label = "temp";
237 };
238
239 channel@2 {
240 gw,mode = <1>;
241 reg = <0x02>;
242 label = "vdd_vin";
243 };
244
245 channel@5 {
246 gw,mode = <1>;
247 reg = <0x05>;
248 label = "vdd_3p3";
249 };
250
251 channel@8 {
252 gw,mode = <1>;
253 reg = <0x08>;
254 label = "vdd_bat";
255 };
256
257 channel@b {
258 gw,mode = <1>;
259 reg = <0x0b>;
260 label = "vdd_5p0";
261 };
262
263 channel@e {
264 gw,mode = <1>;
265 reg = <0xe>;
266 label = "vdd_arm";
267 };
268
269 channel@11 {
270 gw,mode = <1>;
271 reg = <0x11>;
272 label = "vdd_soc";
273 };
274
275 channel@14 {
276 gw,mode = <1>;
277 reg = <0x14>;
278 label = "vdd_3p0";
279 };
280
281 channel@17 {
282 gw,mode = <1>;
283 reg = <0x17>;
284 label = "vdd_1p5";
285 };
286
287 channel@1d {
288 gw,mode = <1>;
289 reg = <0x1d>;
290 label = "vdd_1p8";
291 };
292
293 channel@20 {
294 gw,mode = <1>;
295 reg = <0x20>;
296 label = "vdd_1p0";
297 };
298
299 channel@23 {
300 gw,mode = <1>;
301 reg = <0x23>;
302 label = "vdd_2p5";
303 };
304
305 channel@26 {
306 gw,mode = <1>;
307 reg = <0x26>;
308 label = "vdd_gps";
309 };
310
311 channel@29 {
312 gw,mode = <1>;
313 reg = <0x29>;
314 label = "vdd_an1";
315 };
316 };
317 };
318
319 gsc_gpio: gpio@23 {
320 compatible = "nxp,pca9555";
321 reg = <0x23>;
322 gpio-controller;
323 #gpio-cells = <2>;
324 interrupt-parent = <&gsc>;
325 interrupts = <4>;
326 };
327
328 eeprom1: eeprom@50 {
329 compatible = "atmel,24c02";
330 reg = <0x50>;
331 pagesize = <16>;
332 };
333
334 eeprom2: eeprom@51 {
335 compatible = "atmel,24c02";
336 reg = <0x51>;
337 pagesize = <16>;
338 };
339
340 eeprom3: eeprom@52 {
341 compatible = "atmel,24c02";
342 reg = <0x52>;
343 pagesize = <16>;
344 };
345
346 eeprom4: eeprom@53 {
347 compatible = "atmel,24c02";
348 reg = <0x53>;
349 pagesize = <16>;
350 };
351
352 rtc: ds1672@68 {
353 compatible = "dallas,ds1672";
354 reg = <0x68>;
355 };
356};
357
358&i2c2 {
359 clock-frequency = <100000>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_i2c2>;
362 status = "okay";
363
364 ltc3676: pmic@3c {
365 compatible = "lltc,ltc3676";
366 reg = <0x3c>;
367 interrupt-parent = <&gpio1>;
368 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
369
370 regulators {
371 /* VDD_SOC (1+R1/R2 = 1.635) */
372 reg_vdd_soc: sw1 {
373 regulator-name = "vddsoc";
374 regulator-min-microvolt = <674400>;
375 regulator-max-microvolt = <1308000>;
376 lltc,fb-voltage-divider = <127000 200000>;
377 regulator-ramp-delay = <7000>;
378 regulator-boot-on;
379 regulator-always-on;
380 };
381
382 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
383 reg_1p8v: sw2 {
384 regulator-name = "vdd1p8";
385 regulator-min-microvolt = <1033310>;
386 regulator-max-microvolt = <2004000>;
387 lltc,fb-voltage-divider = <301000 200000>;
388 regulator-ramp-delay = <7000>;
389 regulator-boot-on;
390 regulator-always-on;
391 };
392
393 /* VDD_ARM (1+R1/R2 = 1.635) */
394 reg_vdd_arm: sw3 {
395 regulator-name = "vddarm";
396 regulator-min-microvolt = <674400>;
397 regulator-max-microvolt = <1308000>;
398 lltc,fb-voltage-divider = <127000 200000>;
399 regulator-ramp-delay = <7000>;
400 regulator-boot-on;
401 regulator-always-on;
402 };
403
404 /* VDD_DDR (1+R1/R2 = 2.105) */
405 reg_vdd_ddr: sw4 {
406 regulator-name = "vddddr";
407 regulator-min-microvolt = <868310>;
408 regulator-max-microvolt = <1684000>;
409 lltc,fb-voltage-divider = <221000 200000>;
410 regulator-ramp-delay = <7000>;
411 regulator-boot-on;
412 regulator-always-on;
413 };
414
415 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
416 reg_2p5v: ldo2 {
417 regulator-name = "vdd2p5";
418 regulator-min-microvolt = <2490375>;
419 regulator-max-microvolt = <2490375>;
420 lltc,fb-voltage-divider = <487000 200000>;
421 regulator-boot-on;
422 regulator-always-on;
423 };
424
425 /* VDD_AUD_1P8: Audio codec */
426 reg_aud_1p8v: ldo3 {
427 regulator-name = "vdd1p8a";
428 regulator-min-microvolt = <1800000>;
429 regulator-max-microvolt = <1800000>;
430 regulator-boot-on;
431 };
432
433 /* VDD_HIGH (1+R1/R2 = 4.17) */
434 reg_3p0v: ldo4 {
435 regulator-name = "vdd3p0";
436 regulator-min-microvolt = <3023250>;
437 regulator-max-microvolt = <3023250>;
438 lltc,fb-voltage-divider = <634000 200000>;
439 regulator-boot-on;
440 regulator-always-on;
441 };
442 };
443 };
444};
445
446&i2c3 {
447 clock-frequency = <100000>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_i2c3>;
450 status = "okay";
451
452 codec: sgtl5000@a {
453 compatible = "fsl,sgtl5000";
454 reg = <0x0a>;
455 clocks = <&clks IMX6QDL_CLK_CKO>;
456 VDDA-supply = <®_1p8v>;
457 VDDIO-supply = <®_3p3v>;
458 };
459
460 touchscreen: egalax_ts@4 {
461 compatible = "eeti,egalax_ts";
462 reg = <0x04>;
463 interrupt-parent = <&gpio1>;
464 interrupts = <11 2>;
465 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
466 };
467
468 accel@1e {
469 compatible = "nxp,fxos8700";
470 reg = <0x1e>;
471 };
472};
473
474&ldb {
475 status = "okay";
476
477 lvds-channel@0 {
478 fsl,data-mapping = "spwg";
479 fsl,data-width = <18>;
480 status = "okay";
481
482 display-timings {
483 native-mode = <&timing0>;
484 timing0: hsd100pxn1 {
485 clock-frequency = <65000000>;
486 hactive = <1024>;
487 vactive = <768>;
488 hback-porch = <220>;
489 hfront-porch = <40>;
490 vback-porch = <21>;
491 vfront-porch = <7>;
492 hsync-len = <60>;
493 vsync-len = <10>;
494 };
495 };
496 };
497};
498
499&pcie {
500 pinctrl-names = "default";
501 pinctrl-0 = <&pinctrl_pcie>;
502 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
503 status = "okay";
504};
505
506&pwm2 {
507 pinctrl-names = "default";
508 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
509 status = "disabled";
510};
511
512&pwm3 {
513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
515 status = "disabled";
516};
517
518&pwm4 {
519 #pwm-cells = <2>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&pinctrl_pwm4>;
522 status = "okay";
523};
524
525&ssi1 {
526 status = "okay";
527};
528
529&uart1 {
530 pinctrl-names = "default";
531 pinctrl-0 = <&pinctrl_uart1>;
532 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
533 status = "okay";
534};
535
536&uart2 {
537 pinctrl-names = "default";
538 pinctrl-0 = <&pinctrl_uart2>;
539 status = "okay";
540};
541
542&uart5 {
543 pinctrl-names = "default";
544 pinctrl-0 = <&pinctrl_uart5>;
545 status = "okay";
546};
547
548&usbotg {
549 vbus-supply = <®_usb_otg_vbus>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&pinctrl_usbotg>;
552 disable-over-current;
553 status = "okay";
554};
555
556&usbh1 {
557 vbus-supply = <®_usb_h1_vbus>;
558 status = "okay";
559};
560
561&usdhc3 {
562 pinctrl-names = "default", "state_100mhz", "state_200mhz";
563 pinctrl-0 = <&pinctrl_usdhc3>;
564 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
565 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
566 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
567 vmmc-supply = <®_3p3v>;
568 no-1-8-v; /* firmware will remove if board revision supports */
569 status = "okay";
570};
571
572&wdog1 {
573 pinctrl-names = "default";
574 pinctrl-0 = <&pinctrl_wdog>;
575 fsl,ext-reset-output;
576};
577
578&iomuxc {
579 pinctrl_audmux: audmuxgrp {
580 fsl,pins = <
581 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
582 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
583 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
584 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
585 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
586 >;
587 };
588
589 pinctrl_enet: enetgrp {
590 fsl,pins = <
591 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
592 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
593 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
594 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
595 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
596 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
597 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
598 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
599 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
600 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
601 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
602 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
603 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
604 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
605 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
606 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
607 >;
608 };
609
610 pinctrl_flexcan1: flexcan1grp {
611 fsl,pins = <
612 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
613 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
614 >;
615 };
616
617 pinctrl_gpio_leds: gpioledsgrp {
618 fsl,pins = <
619 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
620 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
621 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
622 >;
623 };
624
625 pinctrl_gpmi_nand: gpminandgrp {
626 fsl,pins = <
627 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
628 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
629 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
630 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
631 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
632 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
633 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
634 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
635 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
636 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
637 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
638 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
639 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
640 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
641 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
642 >;
643 };
644
645 pinctrl_i2c1: i2c1grp {
646 fsl,pins = <
647 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
648 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
649 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
650 >;
651 };
652
653 pinctrl_i2c2: i2c2grp {
654 fsl,pins = <
655 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
656 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
657 >;
658 };
659
660 pinctrl_i2c3: i2c3grp {
661 fsl,pins = <
662 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
663 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
664 >;
665 };
666
667 pinctrl_pcie: pciegrp {
668 fsl,pins = <
669 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
670 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
671 >;
672 };
673
674 pinctrl_pmic: pmicgrp {
675 fsl,pins = <
676 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
677 >;
678 };
679
680 pinctrl_pps: ppsgrp {
681 fsl,pins = <
682 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
683 >;
684 };
685
686 pinctrl_pwm2: pwm2grp {
687 fsl,pins = <
688 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
689 >;
690 };
691
692 pinctrl_pwm3: pwm3grp {
693 fsl,pins = <
694 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
695 >;
696 };
697
698 pinctrl_pwm4: pwm4grp {
699 fsl,pins = <
700 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
701 >;
702 };
703
704 pinctrl_reg_can1: regcan1grp {
705 fsl,pins = <
706 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
707 >;
708 };
709
710 pinctrl_uart1: uart1grp {
711 fsl,pins = <
712 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
713 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
714 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
715 >;
716 };
717
718 pinctrl_uart2: uart2grp {
719 fsl,pins = <
720 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
721 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
722 >;
723 };
724
725 pinctrl_uart5: uart5grp {
726 fsl,pins = <
727 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
728 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
729 >;
730 };
731
732 pinctrl_usbotg: usbotggrp {
733 fsl,pins = <
734 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
735 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
736 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
737 >;
738 };
739
740 pinctrl_usdhc3: usdhc3grp {
741 fsl,pins = <
742 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
743 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
744 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
745 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
746 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
747 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
748 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
749 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
750 >;
751 };
752
753 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
754 fsl,pins = <
755 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
756 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
757 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
758 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
759 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
760 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
761 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
762 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
763 >;
764 };
765
766 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
767 fsl,pins = <
768 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
769 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
770 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
771 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
772 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
773 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
774 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
775 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
776 >;
777 };
778
779 pinctrl_wdog: wdoggrp {
780 fsl,pins = <
781 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
782 >;
783 };
784};
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15 /* these are used by bootloader for disabling nodes */
16 aliases {
17 ethernet1 = ð1;
18 led0 = &led0;
19 led1 = &led1;
20 led2 = &led2;
21 nand = &gpmi;
22 ssi0 = &ssi1;
23 usb0 = &usbh1;
24 usb1 = &usbotg;
25 };
26
27 chosen {
28 bootargs = "console=ttymxc1,115200";
29 };
30
31 backlight {
32 compatible = "pwm-backlight";
33 pwms = <&pwm4 0 5000000>;
34 brightness-levels = <0 4 8 16 32 64 128 255>;
35 default-brightness-level = <7>;
36 };
37
38 leds {
39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_gpio_leds>;
42
43 led0: user1 {
44 label = "user1";
45 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
46 default-state = "on";
47 linux,default-trigger = "heartbeat";
48 };
49
50 led1: user2 {
51 label = "user2";
52 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
53 default-state = "off";
54 };
55
56 led2: user3 {
57 label = "user3";
58 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
59 default-state = "off";
60 };
61 };
62
63 memory {
64 reg = <0x10000000 0x40000000>;
65 };
66
67 pps {
68 compatible = "pps-gpio";
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_pps>;
71 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
72 status = "okay";
73 };
74
75 regulators {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 reg_1p0v: regulator@0 {
81 compatible = "regulator-fixed";
82 reg = <0>;
83 regulator-name = "1P0V";
84 regulator-min-microvolt = <1000000>;
85 regulator-max-microvolt = <1000000>;
86 regulator-always-on;
87 };
88
89 /* remove when pmic 1p8 regulator available */
90 reg_1p8v: regulator@1 {
91 compatible = "regulator-fixed";
92 reg = <1>;
93 regulator-name = "1P8V";
94 regulator-min-microvolt = <1800000>;
95 regulator-max-microvolt = <1800000>;
96 regulator-always-on;
97 };
98
99 reg_3p3v: regulator@2 {
100 compatible = "regulator-fixed";
101 reg = <2>;
102 regulator-name = "3P3V";
103 regulator-min-microvolt = <3300000>;
104 regulator-max-microvolt = <3300000>;
105 regulator-always-on;
106 };
107
108 reg_usb_h1_vbus: regulator@3 {
109 compatible = "regulator-fixed";
110 reg = <3>;
111 regulator-name = "usb_h1_vbus";
112 regulator-min-microvolt = <5000000>;
113 regulator-max-microvolt = <5000000>;
114 regulator-always-on;
115 };
116
117 reg_usb_otg_vbus: regulator@4 {
118 compatible = "regulator-fixed";
119 reg = <4>;
120 regulator-name = "usb_otg_vbus";
121 regulator-min-microvolt = <5000000>;
122 regulator-max-microvolt = <5000000>;
123 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
124 enable-active-high;
125 };
126 };
127
128 sound {
129 compatible = "fsl,imx6q-ventana-sgtl5000",
130 "fsl,imx-audio-sgtl5000";
131 model = "sgtl5000-audio";
132 ssi-controller = <&ssi1>;
133 audio-codec = <&codec>;
134 audio-routing =
135 "MIC_IN", "Mic Jack",
136 "Mic Jack", "Mic Bias",
137 "Headphone Jack", "HP_OUT";
138 mux-int-port = <1>;
139 mux-ext-port = <4>;
140 };
141};
142
143&audmux {
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_audmux>;
146 status = "okay";
147};
148
149&can1 {
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_flexcan1>;
152 status = "okay";
153};
154
155&clks {
156 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
157 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
158 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
159 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
160};
161
162&fec {
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_enet>;
165 phy-mode = "rgmii-id";
166 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
167 status = "okay";
168};
169
170&gpmi {
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_gpmi_nand>;
173 status = "okay";
174};
175
176&hdmi {
177 ddc-i2c-bus = <&i2c3>;
178 status = "okay";
179};
180
181&i2c1 {
182 clock-frequency = <100000>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_i2c1>;
185 status = "okay";
186
187 eeprom1: eeprom@50 {
188 compatible = "atmel,24c02";
189 reg = <0x50>;
190 pagesize = <16>;
191 };
192
193 eeprom2: eeprom@51 {
194 compatible = "atmel,24c02";
195 reg = <0x51>;
196 pagesize = <16>;
197 };
198
199 eeprom3: eeprom@52 {
200 compatible = "atmel,24c02";
201 reg = <0x52>;
202 pagesize = <16>;
203 };
204
205 eeprom4: eeprom@53 {
206 compatible = "atmel,24c02";
207 reg = <0x53>;
208 pagesize = <16>;
209 };
210
211 gpio: pca9555@23 {
212 compatible = "nxp,pca9555";
213 reg = <0x23>;
214 gpio-controller;
215 #gpio-cells = <2>;
216 };
217
218 rtc: ds1672@68 {
219 compatible = "dallas,ds1672";
220 reg = <0x68>;
221 };
222};
223
224&i2c2 {
225 clock-frequency = <100000>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_i2c2>;
228 status = "okay";
229};
230
231&i2c3 {
232 clock-frequency = <100000>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_i2c3>;
235 status = "okay";
236
237 codec: sgtl5000@0a {
238 compatible = "fsl,sgtl5000";
239 reg = <0x0a>;
240 clocks = <&clks IMX6QDL_CLK_CKO>;
241 VDDA-supply = <®_1p8v>;
242 VDDIO-supply = <®_3p3v>;
243 };
244
245 touchscreen: egalax_ts@04 {
246 compatible = "eeti,egalax_ts";
247 reg = <0x04>;
248 interrupt-parent = <&gpio1>;
249 interrupts = <11 2>;
250 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
251 };
252};
253
254&ldb {
255 status = "okay";
256
257 lvds-channel@0 {
258 fsl,data-mapping = "spwg";
259 fsl,data-width = <18>;
260 status = "okay";
261
262 display-timings {
263 native-mode = <&timing0>;
264 timing0: hsd100pxn1 {
265 clock-frequency = <65000000>;
266 hactive = <1024>;
267 vactive = <768>;
268 hback-porch = <220>;
269 hfront-porch = <40>;
270 vback-porch = <21>;
271 vfront-porch = <7>;
272 hsync-len = <60>;
273 vsync-len = <10>;
274 };
275 };
276 };
277};
278
279&pcie {
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_pcie>;
282 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
283 status = "okay";
284
285 eth1: sky2@8 { /* MAC/PHY on bus 8 */
286 compatible = "marvell,sky2";
287 };
288};
289
290&pwm2 {
291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
293 status = "disabled";
294};
295
296&pwm3 {
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
299 status = "disabled";
300};
301
302&pwm4 {
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_pwm4>;
305 status = "okay";
306};
307
308&ssi1 {
309 status = "okay";
310};
311
312&uart1 {
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_uart1>;
315 uart-has-rtscts;
316 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
317 status = "okay";
318};
319
320&uart2 {
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_uart2>;
323 status = "okay";
324};
325
326&uart5 {
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_uart5>;
329 status = "okay";
330};
331
332&usbotg {
333 vbus-supply = <®_usb_otg_vbus>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&pinctrl_usbotg>;
336 disable-over-current;
337 status = "okay";
338};
339
340&usbh1 {
341 vbus-supply = <®_usb_h1_vbus>;
342 status = "okay";
343};
344
345&usdhc3 {
346 pinctrl-names = "default", "state_100mhz", "state_200mhz";
347 pinctrl-0 = <&pinctrl_usdhc3>;
348 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
349 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
350 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
351 vmmc-supply = <®_3p3v>;
352 no-1-8-v; /* firmware will remove if board revision supports */
353 status = "okay";
354};
355
356&wdog1 {
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_wdog>;
359 fsl,ext-reset-output;
360};
361
362&iomuxc {
363 imx6qdl-gw53xx {
364 pinctrl_audmux: audmuxgrp {
365 fsl,pins = <
366 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
367 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
368 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
369 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
370 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
371 >;
372 };
373
374 pinctrl_enet: enetgrp {
375 fsl,pins = <
376 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
377 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
378 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
379 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
380 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
381 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
382 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
383 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
384 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
385 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
386 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
387 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
388 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
389 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
390 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
391 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
392 >;
393 };
394
395 pinctrl_flexcan1: flexcan1grp {
396 fsl,pins = <
397 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
398 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
399 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
400 >;
401 };
402
403 pinctrl_gpio_leds: gpioledsgrp {
404 fsl,pins = <
405 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
406 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
407 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
408 >;
409 };
410
411 pinctrl_gpmi_nand: gpminandgrp {
412 fsl,pins = <
413 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
414 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
415 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
416 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
417 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
418 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
419 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
420 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
421 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
422 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
423 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
424 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
425 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
426 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
427 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
428 >;
429 };
430
431 pinctrl_i2c1: i2c1grp {
432 fsl,pins = <
433 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
434 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
435 >;
436 };
437
438 pinctrl_i2c2: i2c2grp {
439 fsl,pins = <
440 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
441 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
442 >;
443 };
444
445 pinctrl_i2c3: i2c3grp {
446 fsl,pins = <
447 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
448 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
449 >;
450 };
451
452 pinctrl_pcie: pciegrp {
453 fsl,pins = <
454 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
455 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
456 >;
457 };
458
459 pinctrl_pps: ppsgrp {
460 fsl,pins = <
461 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
462 >;
463 };
464
465 pinctrl_pwm2: pwm2grp {
466 fsl,pins = <
467 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
468 >;
469 };
470
471 pinctrl_pwm3: pwm3grp {
472 fsl,pins = <
473 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
474 >;
475 };
476
477 pinctrl_pwm4: pwm4grp {
478 fsl,pins = <
479 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
480 >;
481 };
482
483 pinctrl_uart1: uart1grp {
484 fsl,pins = <
485 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
486 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
487 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
488 >;
489 };
490
491 pinctrl_uart2: uart2grp {
492 fsl,pins = <
493 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
494 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
495 >;
496 };
497
498 pinctrl_uart5: uart5grp {
499 fsl,pins = <
500 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
501 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
502 >;
503 };
504
505 pinctrl_usbotg: usbotggrp {
506 fsl,pins = <
507 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
508 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
509 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
510 >;
511 };
512
513 pinctrl_usdhc3: usdhc3grp {
514 fsl,pins = <
515 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
516 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
517 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
518 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
519 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
520 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
521 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
522 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
523 >;
524 };
525
526 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
527 fsl,pins = <
528 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
529 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
530 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
531 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
532 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
533 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
534 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
535 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
536 >;
537 };
538
539 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
540 fsl,pins = <
541 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
542 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
543 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
544 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
545 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
546 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
547 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
548 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
549 >;
550 };
551
552 pinctrl_wdog: wdoggrp {
553 fsl,pins = <
554 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
555 >;
556 };
557 };
558};