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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4 SoC series common device tree source
4 *
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
8 * www.linaro.org
9 *
10 * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
11 * SoCs from Exynos4 series can include this file and provide values for SoCs
12 * specfic bindings.
13 *
14 * Note: This file does not include device nodes for all the controllers in
15 * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
16 * nodes can be added to this file.
17 */
18
19#include <dt-bindings/clock/exynos4.h>
20#include <dt-bindings/clock/exynos-audss-clk.h>
21#include <dt-bindings/interrupt-controller/arm-gic.h>
22#include <dt-bindings/interrupt-controller/irq.h>
23
24/ {
25 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 aliases {
30 spi0 = &spi_0;
31 spi1 = &spi_1;
32 spi2 = &spi_2;
33 i2c0 = &i2c_0;
34 i2c1 = &i2c_1;
35 i2c2 = &i2c_2;
36 i2c3 = &i2c_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 i2c8 = &i2c_8;
42 csis0 = &csis_0;
43 csis1 = &csis_1;
44 fimc0 = &fimc_0;
45 fimc1 = &fimc_1;
46 fimc2 = &fimc_2;
47 fimc3 = &fimc_3;
48 serial0 = &serial_0;
49 serial1 = &serial_1;
50 serial2 = &serial_2;
51 serial3 = &serial_3;
52 };
53
54 pmu: pmu {
55 compatible = "arm,cortex-a9-pmu";
56 interrupt-parent = <&combiner>;
57 status = "disabled";
58 };
59
60 soc: soc {
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges;
65
66 clock_audss: clock-controller@3810000 {
67 compatible = "samsung,exynos4210-audss-clock";
68 reg = <0x03810000 0x0C>;
69 #clock-cells = <1>;
70 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
71 <&clock CLK_SCLK_AUDIO0>,
72 <&clock CLK_SCLK_AUDIO0>;
73 clock-names = "pll_ref", "pll_in", "sclk_audio",
74 "sclk_pcm_in";
75 };
76
77 i2s0: i2s@3830000 {
78 compatible = "samsung,s5pv210-i2s";
79 reg = <0x03830000 0x100>;
80 clocks = <&clock_audss EXYNOS_I2S_BUS>,
81 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
82 <&clock_audss EXYNOS_SCLK_I2S>;
83 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
84 #clock-cells = <1>;
85 clock-output-names = "i2s_cdclk0";
86 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
87 dma-names = "tx", "rx", "tx-sec";
88 samsung,idma-addr = <0x03000000>;
89 #sound-dai-cells = <1>;
90 status = "disabled";
91 };
92
93 chipid@10000000 {
94 compatible = "samsung,exynos4210-chipid";
95 reg = <0x10000000 0x100>;
96 };
97
98 scu: snoop-control-unit@10500000 {
99 compatible = "arm,cortex-a9-scu";
100 reg = <0x10500000 0x2000>;
101 };
102
103 memory-controller@12570000 {
104 compatible = "samsung,exynos4210-srom";
105 reg = <0x12570000 0x14>;
106 };
107
108 mipi_phy: video-phy {
109 compatible = "samsung,s5pv210-mipi-video-phy";
110 #phy-cells = <1>;
111 syscon = <&pmu_system_controller>;
112 };
113
114 pd_mfc: power-domain@10023c40 {
115 compatible = "samsung,exynos4210-pd";
116 reg = <0x10023C40 0x20>;
117 #power-domain-cells = <0>;
118 label = "MFC";
119 };
120
121 pd_g3d: power-domain@10023c60 {
122 compatible = "samsung,exynos4210-pd";
123 reg = <0x10023C60 0x20>;
124 #power-domain-cells = <0>;
125 label = "G3D";
126 };
127
128 pd_lcd0: power-domain@10023c80 {
129 compatible = "samsung,exynos4210-pd";
130 reg = <0x10023C80 0x20>;
131 #power-domain-cells = <0>;
132 label = "LCD0";
133 };
134
135 pd_tv: power-domain@10023c20 {
136 compatible = "samsung,exynos4210-pd";
137 reg = <0x10023C20 0x20>;
138 #power-domain-cells = <0>;
139 power-domains = <&pd_lcd0>;
140 label = "TV";
141 };
142
143 pd_cam: power-domain@10023c00 {
144 compatible = "samsung,exynos4210-pd";
145 reg = <0x10023C00 0x20>;
146 #power-domain-cells = <0>;
147 label = "CAM";
148 };
149
150 pd_gps: power-domain@10023ce0 {
151 compatible = "samsung,exynos4210-pd";
152 reg = <0x10023CE0 0x20>;
153 #power-domain-cells = <0>;
154 label = "GPS";
155 };
156
157 pd_gps_alive: power-domain@10023d00 {
158 compatible = "samsung,exynos4210-pd";
159 reg = <0x10023D00 0x20>;
160 #power-domain-cells = <0>;
161 label = "GPS alive";
162 };
163
164 gic: interrupt-controller@10490000 {
165 compatible = "arm,cortex-a9-gic";
166 #interrupt-cells = <3>;
167 interrupt-controller;
168 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
169 };
170
171 combiner: interrupt-controller@10440000 {
172 compatible = "samsung,exynos4210-combiner";
173 #interrupt-cells = <2>;
174 interrupt-controller;
175 reg = <0x10440000 0x1000>;
176 };
177
178 sys_reg: syscon@10010000 {
179 compatible = "samsung,exynos4-sysreg", "syscon";
180 reg = <0x10010000 0x400>;
181 };
182
183 pmu_system_controller: system-controller@10020000 {
184 compatible = "samsung,exynos4210-pmu", "syscon";
185 reg = <0x10020000 0x4000>;
186 interrupt-controller;
187 #interrupt-cells = <3>;
188 interrupt-parent = <&gic>;
189 };
190
191 dsi_0: dsi@11c80000 {
192 compatible = "samsung,exynos4210-mipi-dsi";
193 reg = <0x11C80000 0x10000>;
194 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
195 power-domains = <&pd_lcd0>;
196 phys = <&mipi_phy 1>;
197 phy-names = "dsim";
198 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
199 clock-names = "bus_clk", "sclk_mipi";
200 status = "disabled";
201 #address-cells = <1>;
202 #size-cells = <0>;
203 };
204
205 camera: camera {
206 compatible = "samsung,fimc", "simple-bus";
207 status = "disabled";
208 #address-cells = <1>;
209 #size-cells = <1>;
210 #clock-cells = <1>;
211 clock-output-names = "cam_a_clkout", "cam_b_clkout";
212 ranges;
213
214 fimc_0: fimc@11800000 {
215 compatible = "samsung,exynos4210-fimc";
216 reg = <0x11800000 0x1000>;
217 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&clock CLK_FIMC0>,
219 <&clock CLK_SCLK_FIMC0>;
220 clock-names = "fimc", "sclk_fimc";
221 power-domains = <&pd_cam>;
222 samsung,sysreg = <&sys_reg>;
223 iommus = <&sysmmu_fimc0>;
224 status = "disabled";
225 };
226
227 fimc_1: fimc@11810000 {
228 compatible = "samsung,exynos4210-fimc";
229 reg = <0x11810000 0x1000>;
230 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&clock CLK_FIMC1>,
232 <&clock CLK_SCLK_FIMC1>;
233 clock-names = "fimc", "sclk_fimc";
234 power-domains = <&pd_cam>;
235 samsung,sysreg = <&sys_reg>;
236 iommus = <&sysmmu_fimc1>;
237 status = "disabled";
238 };
239
240 fimc_2: fimc@11820000 {
241 compatible = "samsung,exynos4210-fimc";
242 reg = <0x11820000 0x1000>;
243 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&clock CLK_FIMC2>,
245 <&clock CLK_SCLK_FIMC2>;
246 clock-names = "fimc", "sclk_fimc";
247 power-domains = <&pd_cam>;
248 samsung,sysreg = <&sys_reg>;
249 iommus = <&sysmmu_fimc2>;
250 status = "disabled";
251 };
252
253 fimc_3: fimc@11830000 {
254 compatible = "samsung,exynos4210-fimc";
255 reg = <0x11830000 0x1000>;
256 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clock CLK_FIMC3>,
258 <&clock CLK_SCLK_FIMC3>;
259 clock-names = "fimc", "sclk_fimc";
260 power-domains = <&pd_cam>;
261 samsung,sysreg = <&sys_reg>;
262 iommus = <&sysmmu_fimc3>;
263 status = "disabled";
264 };
265
266 csis_0: csis@11880000 {
267 compatible = "samsung,exynos4210-csis";
268 reg = <0x11880000 0x4000>;
269 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clock CLK_CSIS0>,
271 <&clock CLK_SCLK_CSIS0>;
272 clock-names = "csis", "sclk_csis";
273 bus-width = <4>;
274 power-domains = <&pd_cam>;
275 phys = <&mipi_phy 0>;
276 phy-names = "csis";
277 status = "disabled";
278 #address-cells = <1>;
279 #size-cells = <0>;
280 };
281
282 csis_1: csis@11890000 {
283 compatible = "samsung,exynos4210-csis";
284 reg = <0x11890000 0x4000>;
285 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clock CLK_CSIS1>,
287 <&clock CLK_SCLK_CSIS1>;
288 clock-names = "csis", "sclk_csis";
289 bus-width = <2>;
290 power-domains = <&pd_cam>;
291 phys = <&mipi_phy 2>;
292 phy-names = "csis";
293 status = "disabled";
294 #address-cells = <1>;
295 #size-cells = <0>;
296 };
297 };
298
299 rtc: rtc@10070000 {
300 compatible = "samsung,s3c6410-rtc";
301 reg = <0x10070000 0x100>;
302 interrupt-parent = <&pmu_system_controller>;
303 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&clock CLK_RTC>;
306 clock-names = "rtc";
307 status = "disabled";
308 };
309
310 keypad: keypad@100a0000 {
311 compatible = "samsung,s5pv210-keypad";
312 reg = <0x100A0000 0x100>;
313 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&clock CLK_KEYIF>;
315 clock-names = "keypad";
316 status = "disabled";
317 };
318
319 sdhci_0: mmc@12510000 {
320 compatible = "samsung,exynos4210-sdhci";
321 reg = <0x12510000 0x100>;
322 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
324 clock-names = "hsmmc", "mmc_busclk.2";
325 status = "disabled";
326 };
327
328 sdhci_1: mmc@12520000 {
329 compatible = "samsung,exynos4210-sdhci";
330 reg = <0x12520000 0x100>;
331 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
333 clock-names = "hsmmc", "mmc_busclk.2";
334 status = "disabled";
335 };
336
337 sdhci_2: mmc@12530000 {
338 compatible = "samsung,exynos4210-sdhci";
339 reg = <0x12530000 0x100>;
340 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
342 clock-names = "hsmmc", "mmc_busclk.2";
343 status = "disabled";
344 };
345
346 sdhci_3: mmc@12540000 {
347 compatible = "samsung,exynos4210-sdhci";
348 reg = <0x12540000 0x100>;
349 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
351 clock-names = "hsmmc", "mmc_busclk.2";
352 status = "disabled";
353 };
354
355 exynos_usbphy: exynos-usbphy@125b0000 {
356 compatible = "samsung,exynos4210-usb2-phy";
357 reg = <0x125B0000 0x100>;
358 samsung,pmureg-phandle = <&pmu_system_controller>;
359 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
360 clock-names = "phy", "ref";
361 #phy-cells = <1>;
362 status = "disabled";
363 };
364
365 hsotg: hsotg@12480000 {
366 compatible = "samsung,s3c6400-hsotg";
367 reg = <0x12480000 0x20000>;
368 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clock CLK_USB_DEVICE>;
370 clock-names = "otg";
371 phys = <&exynos_usbphy 0>;
372 phy-names = "usb2-phy";
373 status = "disabled";
374 };
375
376 ehci: usb@12580000 {
377 compatible = "samsung,exynos4210-ehci";
378 reg = <0x12580000 0x100>;
379 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&clock CLK_USB_HOST>;
381 clock-names = "usbhost";
382 status = "disabled";
383 phys = <&exynos_usbphy 1>, <&exynos_usbphy 2>, <&exynos_usbphy 3>;
384 phy-names = "host", "hsic0", "hsic1";
385 };
386
387 ohci: usb@12590000 {
388 compatible = "samsung,exynos4210-ohci";
389 reg = <0x12590000 0x100>;
390 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&clock CLK_USB_HOST>;
392 clock-names = "usbhost";
393 status = "disabled";
394 phys = <&exynos_usbphy 1>;
395 phy-names = "host";
396 };
397
398 gpu: gpu@13000000 {
399 compatible = "samsung,exynos4210-mali", "arm,mali-400";
400 reg = <0x13000000 0x10000>;
401 /*
402 * CLK_G3D is not actually bus clock but a IP-level clock.
403 * The bus clock is not described in hardware manual.
404 */
405 clocks = <&clock CLK_G3D>,
406 <&clock CLK_SCLK_G3D>;
407 clock-names = "bus", "core";
408 power-domains = <&pd_g3d>;
409 status = "disabled";
410 };
411
412 i2s1: i2s@13960000 {
413 compatible = "samsung,s3c6410-i2s";
414 reg = <0x13960000 0x100>;
415 clocks = <&clock CLK_I2S1>;
416 clock-names = "iis";
417 #clock-cells = <1>;
418 clock-output-names = "i2s_cdclk1";
419 dmas = <&pdma1 12>, <&pdma1 11>;
420 dma-names = "tx", "rx";
421 #sound-dai-cells = <1>;
422 status = "disabled";
423 };
424
425 i2s2: i2s@13970000 {
426 compatible = "samsung,s3c6410-i2s";
427 reg = <0x13970000 0x100>;
428 clocks = <&clock CLK_I2S2>;
429 clock-names = "iis";
430 #clock-cells = <1>;
431 clock-output-names = "i2s_cdclk2";
432 dmas = <&pdma0 14>, <&pdma0 13>;
433 dma-names = "tx", "rx";
434 #sound-dai-cells = <1>;
435 status = "disabled";
436 };
437
438 mfc: codec@13400000 {
439 compatible = "samsung,mfc-v5";
440 reg = <0x13400000 0x10000>;
441 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
442 power-domains = <&pd_mfc>;
443 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
444 clock-names = "mfc", "sclk_mfc";
445 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
446 iommu-names = "left", "right";
447 };
448
449 serial_0: serial@13800000 {
450 compatible = "samsung,exynos4210-uart";
451 reg = <0x13800000 0x100>;
452 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
454 clock-names = "uart", "clk_uart_baud0";
455 dmas = <&pdma0 15>, <&pdma0 16>;
456 dma-names = "rx", "tx";
457 status = "disabled";
458 };
459
460 serial_1: serial@13810000 {
461 compatible = "samsung,exynos4210-uart";
462 reg = <0x13810000 0x100>;
463 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
465 clock-names = "uart", "clk_uart_baud0";
466 dmas = <&pdma1 15>, <&pdma1 16>;
467 dma-names = "rx", "tx";
468 status = "disabled";
469 };
470
471 serial_2: serial@13820000 {
472 compatible = "samsung,exynos4210-uart";
473 reg = <0x13820000 0x100>;
474 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
476 clock-names = "uart", "clk_uart_baud0";
477 dmas = <&pdma0 17>, <&pdma0 18>;
478 dma-names = "rx", "tx";
479 status = "disabled";
480 };
481
482 serial_3: serial@13830000 {
483 compatible = "samsung,exynos4210-uart";
484 reg = <0x13830000 0x100>;
485 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
487 clock-names = "uart", "clk_uart_baud0";
488 dmas = <&pdma1 17>, <&pdma1 18>;
489 dma-names = "rx", "tx";
490 status = "disabled";
491 };
492
493 i2c_0: i2c@13860000 {
494 #address-cells = <1>;
495 #size-cells = <0>;
496 compatible = "samsung,s3c2440-i2c";
497 reg = <0x13860000 0x100>;
498 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&clock CLK_I2C0>;
500 clock-names = "i2c";
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2c0_bus>;
503 status = "disabled";
504 };
505
506 i2c_1: i2c@13870000 {
507 #address-cells = <1>;
508 #size-cells = <0>;
509 compatible = "samsung,s3c2440-i2c";
510 reg = <0x13870000 0x100>;
511 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clock CLK_I2C1>;
513 clock-names = "i2c";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2c1_bus>;
516 status = "disabled";
517 };
518
519 i2c_2: i2c@13880000 {
520 #address-cells = <1>;
521 #size-cells = <0>;
522 compatible = "samsung,s3c2440-i2c";
523 reg = <0x13880000 0x100>;
524 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&clock CLK_I2C2>;
526 clock-names = "i2c";
527 pinctrl-names = "default";
528 pinctrl-0 = <&i2c2_bus>;
529 status = "disabled";
530 };
531
532 i2c_3: i2c@13890000 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "samsung,s3c2440-i2c";
536 reg = <0x13890000 0x100>;
537 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&clock CLK_I2C3>;
539 clock-names = "i2c";
540 pinctrl-names = "default";
541 pinctrl-0 = <&i2c3_bus>;
542 status = "disabled";
543 };
544
545 i2c_4: i2c@138a0000 {
546 #address-cells = <1>;
547 #size-cells = <0>;
548 compatible = "samsung,s3c2440-i2c";
549 reg = <0x138A0000 0x100>;
550 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&clock CLK_I2C4>;
552 clock-names = "i2c";
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c4_bus>;
555 status = "disabled";
556 };
557
558 i2c_5: i2c@138b0000 {
559 #address-cells = <1>;
560 #size-cells = <0>;
561 compatible = "samsung,s3c2440-i2c";
562 reg = <0x138B0000 0x100>;
563 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&clock CLK_I2C5>;
565 clock-names = "i2c";
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c5_bus>;
568 status = "disabled";
569 };
570
571 i2c_6: i2c@138c0000 {
572 #address-cells = <1>;
573 #size-cells = <0>;
574 compatible = "samsung,s3c2440-i2c";
575 reg = <0x138C0000 0x100>;
576 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&clock CLK_I2C6>;
578 clock-names = "i2c";
579 pinctrl-names = "default";
580 pinctrl-0 = <&i2c6_bus>;
581 status = "disabled";
582 };
583
584 i2c_7: i2c@138d0000 {
585 #address-cells = <1>;
586 #size-cells = <0>;
587 compatible = "samsung,s3c2440-i2c";
588 reg = <0x138D0000 0x100>;
589 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&clock CLK_I2C7>;
591 clock-names = "i2c";
592 pinctrl-names = "default";
593 pinctrl-0 = <&i2c7_bus>;
594 status = "disabled";
595 };
596
597 i2c_8: i2c@138e0000 {
598 #address-cells = <1>;
599 #size-cells = <0>;
600 compatible = "samsung,s3c2440-hdmiphy-i2c";
601 reg = <0x138E0000 0x100>;
602 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&clock CLK_I2C_HDMI>;
604 clock-names = "i2c";
605 status = "disabled";
606
607 hdmi_i2c_phy: hdmiphy@38 {
608 compatible = "exynos4210-hdmiphy";
609 reg = <0x38>;
610 };
611 };
612
613 spi_0: spi@13920000 {
614 compatible = "samsung,exynos4210-spi";
615 reg = <0x13920000 0x100>;
616 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
617 dmas = <&pdma0 7>, <&pdma0 6>;
618 dma-names = "tx", "rx";
619 #address-cells = <1>;
620 #size-cells = <0>;
621 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
622 clock-names = "spi", "spi_busclk0";
623 pinctrl-names = "default";
624 pinctrl-0 = <&spi0_bus>;
625 status = "disabled";
626 };
627
628 spi_1: spi@13930000 {
629 compatible = "samsung,exynos4210-spi";
630 reg = <0x13930000 0x100>;
631 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
632 dmas = <&pdma1 7>, <&pdma1 6>;
633 dma-names = "tx", "rx";
634 #address-cells = <1>;
635 #size-cells = <0>;
636 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
637 clock-names = "spi", "spi_busclk0";
638 pinctrl-names = "default";
639 pinctrl-0 = <&spi1_bus>;
640 status = "disabled";
641 };
642
643 spi_2: spi@13940000 {
644 compatible = "samsung,exynos4210-spi";
645 reg = <0x13940000 0x100>;
646 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
647 dmas = <&pdma0 9>, <&pdma0 8>;
648 dma-names = "tx", "rx";
649 #address-cells = <1>;
650 #size-cells = <0>;
651 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
652 clock-names = "spi", "spi_busclk0";
653 pinctrl-names = "default";
654 pinctrl-0 = <&spi2_bus>;
655 status = "disabled";
656 };
657
658 pwm: pwm@139d0000 {
659 compatible = "samsung,exynos4210-pwm";
660 reg = <0x139D0000 0x1000>;
661 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&clock CLK_PWM>;
667 clock-names = "timers";
668 #pwm-cells = <3>;
669 status = "disabled";
670 };
671
672 pdma0: dma-controller@12680000 {
673 compatible = "arm,pl330", "arm,primecell";
674 reg = <0x12680000 0x1000>;
675 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&clock CLK_PDMA0>;
677 clock-names = "apb_pclk";
678 #dma-cells = <1>;
679 };
680
681 pdma1: dma-controller@12690000 {
682 compatible = "arm,pl330", "arm,primecell";
683 reg = <0x12690000 0x1000>;
684 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&clock CLK_PDMA1>;
686 clock-names = "apb_pclk";
687 #dma-cells = <1>;
688 };
689
690 mdma1: dma-controller@12850000 {
691 compatible = "arm,pl330", "arm,primecell";
692 reg = <0x12850000 0x1000>;
693 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&clock CLK_MDMA>;
695 clock-names = "apb_pclk";
696 #dma-cells = <1>;
697 };
698
699 fimd: fimd@11c00000 {
700 compatible = "samsung,exynos4210-fimd";
701 interrupt-parent = <&combiner>;
702 reg = <0x11c00000 0x20000>;
703 interrupt-names = "fifo", "vsync", "lcd_sys";
704 interrupts = <11 0>, <11 1>, <11 2>;
705 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
706 clock-names = "sclk_fimd", "fimd";
707 power-domains = <&pd_lcd0>;
708 iommus = <&sysmmu_fimd0>;
709 samsung,sysreg = <&sys_reg>;
710 status = "disabled";
711 };
712
713 tmu: tmu@100c0000 {
714 interrupt-parent = <&combiner>;
715 reg = <0x100C0000 0x100>;
716 interrupts = <2 4>;
717 status = "disabled";
718 #thermal-sensor-cells = <0>;
719 };
720
721 jpeg_codec: jpeg-codec@11840000 {
722 compatible = "samsung,exynos4210-jpeg";
723 reg = <0x11840000 0x1000>;
724 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&clock CLK_JPEG>;
726 clock-names = "jpeg";
727 power-domains = <&pd_cam>;
728 iommus = <&sysmmu_jpeg>;
729 };
730
731 rotator: rotator@12810000 {
732 compatible = "samsung,exynos4210-rotator";
733 reg = <0x12810000 0x64>;
734 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&clock CLK_ROTATOR>;
736 clock-names = "rotator";
737 iommus = <&sysmmu_rotator>;
738 };
739
740 hdmi: hdmi@12d00000 {
741 compatible = "samsung,exynos4210-hdmi";
742 reg = <0x12D00000 0x70000>;
743 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
744 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
745 "sclk_hdmiphy", "mout_hdmi";
746 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
747 <&clock CLK_SCLK_PIXEL>,
748 <&clock CLK_SCLK_HDMIPHY>,
749 <&clock CLK_MOUT_HDMI>;
750 phy = <&hdmi_i2c_phy>;
751 power-domains = <&pd_tv>;
752 samsung,syscon-phandle = <&pmu_system_controller>;
753 #sound-dai-cells = <0>;
754 status = "disabled";
755 };
756
757 hdmicec: cec@100b0000 {
758 compatible = "samsung,s5p-cec";
759 reg = <0x100B0000 0x200>;
760 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&clock CLK_HDMI_CEC>;
762 clock-names = "hdmicec";
763 samsung,syscon-phandle = <&pmu_system_controller>;
764 hdmi-phandle = <&hdmi>;
765 pinctrl-names = "default";
766 pinctrl-0 = <&hdmi_cec>;
767 status = "disabled";
768 };
769
770 mixer: mixer@12c10000 {
771 compatible = "samsung,exynos4210-mixer";
772 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
773 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
774 power-domains = <&pd_tv>;
775 iommus = <&sysmmu_tv>;
776 status = "disabled";
777 };
778
779 ppmu_dmc0: ppmu@106a0000 {
780 compatible = "samsung,exynos-ppmu";
781 reg = <0x106a0000 0x2000>;
782 clocks = <&clock CLK_PPMUDMC0>;
783 clock-names = "ppmu";
784 status = "disabled";
785 };
786
787 ppmu_dmc1: ppmu@106b0000 {
788 compatible = "samsung,exynos-ppmu";
789 reg = <0x106b0000 0x2000>;
790 clocks = <&clock CLK_PPMUDMC1>;
791 clock-names = "ppmu";
792 status = "disabled";
793 };
794
795 ppmu_cpu: ppmu@106c0000 {
796 compatible = "samsung,exynos-ppmu";
797 reg = <0x106c0000 0x2000>;
798 clocks = <&clock CLK_PPMUCPU>;
799 clock-names = "ppmu";
800 status = "disabled";
801 };
802
803 ppmu_rightbus: ppmu@112a0000 {
804 compatible = "samsung,exynos-ppmu";
805 reg = <0x112a0000 0x2000>;
806 clocks = <&clock CLK_PPMURIGHT>;
807 clock-names = "ppmu";
808 status = "disabled";
809 };
810
811 ppmu_leftbus: ppmu@116a0000 {
812 compatible = "samsung,exynos-ppmu";
813 reg = <0x116a0000 0x2000>;
814 clocks = <&clock CLK_PPMULEFT>;
815 clock-names = "ppmu";
816 status = "disabled";
817 };
818
819 ppmu_camif: ppmu@11ac0000 {
820 compatible = "samsung,exynos-ppmu";
821 reg = <0x11ac0000 0x2000>;
822 clocks = <&clock CLK_PPMUCAMIF>;
823 clock-names = "ppmu";
824 status = "disabled";
825 };
826
827 ppmu_lcd0: ppmu@11e40000 {
828 compatible = "samsung,exynos-ppmu";
829 reg = <0x11e40000 0x2000>;
830 clocks = <&clock CLK_PPMULCD0>;
831 clock-names = "ppmu";
832 status = "disabled";
833 };
834
835 ppmu_fsys: ppmu@12630000 {
836 compatible = "samsung,exynos-ppmu";
837 reg = <0x12630000 0x2000>;
838 status = "disabled";
839 };
840
841 ppmu_image: ppmu@12aa0000 {
842 compatible = "samsung,exynos-ppmu";
843 reg = <0x12aa0000 0x2000>;
844 clocks = <&clock CLK_PPMUIMAGE>;
845 clock-names = "ppmu";
846 status = "disabled";
847 };
848
849 ppmu_tv: ppmu@12e40000 {
850 compatible = "samsung,exynos-ppmu";
851 reg = <0x12e40000 0x2000>;
852 clocks = <&clock CLK_PPMUTV>;
853 clock-names = "ppmu";
854 status = "disabled";
855 };
856
857 ppmu_g3d: ppmu@13220000 {
858 compatible = "samsung,exynos-ppmu";
859 reg = <0x13220000 0x2000>;
860 clocks = <&clock CLK_PPMUG3D>;
861 clock-names = "ppmu";
862 status = "disabled";
863 };
864
865 ppmu_mfc_left: ppmu@13660000 {
866 compatible = "samsung,exynos-ppmu";
867 reg = <0x13660000 0x2000>;
868 clocks = <&clock CLK_PPMUMFC_L>;
869 clock-names = "ppmu";
870 status = "disabled";
871 };
872
873 ppmu_mfc_right: ppmu@13670000 {
874 compatible = "samsung,exynos-ppmu";
875 reg = <0x13670000 0x2000>;
876 clocks = <&clock CLK_PPMUMFC_R>;
877 clock-names = "ppmu";
878 status = "disabled";
879 };
880
881 sysmmu_mfc_l: sysmmu@13620000 {
882 compatible = "samsung,exynos-sysmmu";
883 reg = <0x13620000 0x1000>;
884 interrupt-parent = <&combiner>;
885 interrupts = <5 5>;
886 clock-names = "sysmmu", "master";
887 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
888 power-domains = <&pd_mfc>;
889 #iommu-cells = <0>;
890 };
891
892 sysmmu_mfc_r: sysmmu@13630000 {
893 compatible = "samsung,exynos-sysmmu";
894 reg = <0x13630000 0x1000>;
895 interrupt-parent = <&combiner>;
896 interrupts = <5 6>;
897 clock-names = "sysmmu", "master";
898 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
899 power-domains = <&pd_mfc>;
900 #iommu-cells = <0>;
901 };
902
903 sysmmu_tv: sysmmu@12e20000 {
904 compatible = "samsung,exynos-sysmmu";
905 reg = <0x12E20000 0x1000>;
906 interrupt-parent = <&combiner>;
907 interrupts = <5 4>;
908 clock-names = "sysmmu", "master";
909 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
910 power-domains = <&pd_tv>;
911 #iommu-cells = <0>;
912 };
913
914 sysmmu_fimc0: sysmmu@11a20000 {
915 compatible = "samsung,exynos-sysmmu";
916 reg = <0x11A20000 0x1000>;
917 interrupt-parent = <&combiner>;
918 interrupts = <4 2>;
919 clock-names = "sysmmu", "master";
920 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
921 power-domains = <&pd_cam>;
922 #iommu-cells = <0>;
923 };
924
925 sysmmu_fimc1: sysmmu@11a30000 {
926 compatible = "samsung,exynos-sysmmu";
927 reg = <0x11A30000 0x1000>;
928 interrupt-parent = <&combiner>;
929 interrupts = <4 3>;
930 clock-names = "sysmmu", "master";
931 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
932 power-domains = <&pd_cam>;
933 #iommu-cells = <0>;
934 };
935
936 sysmmu_fimc2: sysmmu@11a40000 {
937 compatible = "samsung,exynos-sysmmu";
938 reg = <0x11A40000 0x1000>;
939 interrupt-parent = <&combiner>;
940 interrupts = <4 4>;
941 clock-names = "sysmmu", "master";
942 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
943 power-domains = <&pd_cam>;
944 #iommu-cells = <0>;
945 };
946
947 sysmmu_fimc3: sysmmu@11a50000 {
948 compatible = "samsung,exynos-sysmmu";
949 reg = <0x11A50000 0x1000>;
950 interrupt-parent = <&combiner>;
951 interrupts = <4 5>;
952 clock-names = "sysmmu", "master";
953 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
954 power-domains = <&pd_cam>;
955 #iommu-cells = <0>;
956 };
957
958 sysmmu_jpeg: sysmmu@11a60000 {
959 compatible = "samsung,exynos-sysmmu";
960 reg = <0x11A60000 0x1000>;
961 interrupt-parent = <&combiner>;
962 interrupts = <4 6>;
963 clock-names = "sysmmu", "master";
964 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
965 power-domains = <&pd_cam>;
966 #iommu-cells = <0>;
967 };
968
969 sysmmu_rotator: sysmmu@12a30000 {
970 compatible = "samsung,exynos-sysmmu";
971 reg = <0x12A30000 0x1000>;
972 interrupt-parent = <&combiner>;
973 interrupts = <5 0>;
974 clock-names = "sysmmu", "master";
975 clocks = <&clock CLK_SMMU_ROTATOR>,
976 <&clock CLK_ROTATOR>;
977 #iommu-cells = <0>;
978 };
979
980 sysmmu_fimd0: sysmmu@11e20000 {
981 compatible = "samsung,exynos-sysmmu";
982 reg = <0x11E20000 0x1000>;
983 interrupt-parent = <&combiner>;
984 interrupts = <5 2>;
985 clock-names = "sysmmu", "master";
986 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
987 power-domains = <&pd_lcd0>;
988 #iommu-cells = <0>;
989 };
990
991 sss: sss@10830000 {
992 compatible = "samsung,exynos4210-secss";
993 reg = <0x10830000 0x300>;
994 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&clock CLK_SSS>;
996 clock-names = "secss";
997 };
998
999 prng: rng@10830400 {
1000 compatible = "samsung,exynos4-rng";
1001 reg = <0x10830400 0x200>;
1002 clocks = <&clock CLK_SSS>;
1003 clock-names = "secss";
1004 };
1005 };
1006};
1007
1008#include "exynos-syscon-restart.dtsi"
1/*
2 * Samsung's Exynos4 SoC series common device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
10 * SoCs from Exynos4 series can include this file and provide values for SoCs
11 * specfic bindings.
12 *
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
15 * nodes can be added to this file.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#include <dt-bindings/clock/exynos4.h>
23#include <dt-bindings/clock/exynos-audss-clk.h>
24#include <dt-bindings/interrupt-controller/arm-gic.h>
25#include <dt-bindings/interrupt-controller/irq.h>
26#include "exynos-syscon-restart.dtsi"
27
28/ {
29 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <1>;
32
33 aliases {
34 spi0 = &spi_0;
35 spi1 = &spi_1;
36 spi2 = &spi_2;
37 i2c0 = &i2c_0;
38 i2c1 = &i2c_1;
39 i2c2 = &i2c_2;
40 i2c3 = &i2c_3;
41 i2c4 = &i2c_4;
42 i2c5 = &i2c_5;
43 i2c6 = &i2c_6;
44 i2c7 = &i2c_7;
45 i2c8 = &i2c_8;
46 csis0 = &csis_0;
47 csis1 = &csis_1;
48 fimc0 = &fimc_0;
49 fimc1 = &fimc_1;
50 fimc2 = &fimc_2;
51 fimc3 = &fimc_3;
52 serial0 = &serial_0;
53 serial1 = &serial_1;
54 serial2 = &serial_2;
55 serial3 = &serial_3;
56 };
57
58 clock_audss: clock-controller@03810000 {
59 compatible = "samsung,exynos4210-audss-clock";
60 reg = <0x03810000 0x0C>;
61 #clock-cells = <1>;
62 };
63
64 i2s0: i2s@03830000 {
65 compatible = "samsung,s5pv210-i2s";
66 reg = <0x03830000 0x100>;
67 clocks = <&clock_audss EXYNOS_I2S_BUS>;
68 clock-names = "iis";
69 #clock-cells = <1>;
70 clock-output-names = "i2s_cdclk0";
71 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
72 dma-names = "tx", "rx", "tx-sec";
73 samsung,idma-addr = <0x03000000>;
74 #sound-dai-cells = <1>;
75 status = "disabled";
76 };
77
78 chipid@10000000 {
79 compatible = "samsung,exynos4210-chipid";
80 reg = <0x10000000 0x100>;
81 };
82
83 scu: snoop-control-unit@10500000 {
84 compatible = "arm,cortex-a9-scu";
85 reg = <0x10500000 0x2000>;
86 };
87
88 memory-controller@12570000 {
89 compatible = "samsung,exynos4210-srom";
90 reg = <0x12570000 0x14>;
91 };
92
93 mipi_phy: video-phy {
94 compatible = "samsung,s5pv210-mipi-video-phy";
95 #phy-cells = <1>;
96 syscon = <&pmu_system_controller>;
97 };
98
99 pd_mfc: mfc-power-domain@10023C40 {
100 compatible = "samsung,exynos4210-pd";
101 reg = <0x10023C40 0x20>;
102 #power-domain-cells = <0>;
103 };
104
105 pd_g3d: g3d-power-domain@10023C60 {
106 compatible = "samsung,exynos4210-pd";
107 reg = <0x10023C60 0x20>;
108 #power-domain-cells = <0>;
109 };
110
111 pd_lcd0: lcd0-power-domain@10023C80 {
112 compatible = "samsung,exynos4210-pd";
113 reg = <0x10023C80 0x20>;
114 #power-domain-cells = <0>;
115 };
116
117 pd_tv: tv-power-domain@10023C20 {
118 compatible = "samsung,exynos4210-pd";
119 reg = <0x10023C20 0x20>;
120 #power-domain-cells = <0>;
121 power-domains = <&pd_lcd0>;
122 };
123
124 pd_cam: cam-power-domain@10023C00 {
125 compatible = "samsung,exynos4210-pd";
126 reg = <0x10023C00 0x20>;
127 #power-domain-cells = <0>;
128 };
129
130 pd_gps: gps-power-domain@10023CE0 {
131 compatible = "samsung,exynos4210-pd";
132 reg = <0x10023CE0 0x20>;
133 #power-domain-cells = <0>;
134 };
135
136 pd_gps_alive: gps-alive-power-domain@10023D00 {
137 compatible = "samsung,exynos4210-pd";
138 reg = <0x10023D00 0x20>;
139 #power-domain-cells = <0>;
140 };
141
142 gic: interrupt-controller@10490000 {
143 compatible = "arm,cortex-a9-gic";
144 #interrupt-cells = <3>;
145 interrupt-controller;
146 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
147 };
148
149 combiner: interrupt-controller@10440000 {
150 compatible = "samsung,exynos4210-combiner";
151 #interrupt-cells = <2>;
152 interrupt-controller;
153 reg = <0x10440000 0x1000>;
154 };
155
156 pmu {
157 compatible = "arm,cortex-a9-pmu";
158 interrupt-parent = <&combiner>;
159 interrupts = <2 2>, <3 2>;
160 };
161
162 sys_reg: syscon@10010000 {
163 compatible = "samsung,exynos4-sysreg", "syscon";
164 reg = <0x10010000 0x400>;
165 };
166
167 pmu_system_controller: system-controller@10020000 {
168 compatible = "samsung,exynos4210-pmu", "syscon";
169 reg = <0x10020000 0x4000>;
170 interrupt-controller;
171 #interrupt-cells = <3>;
172 interrupt-parent = <&gic>;
173 };
174
175 dsi_0: dsi@11C80000 {
176 compatible = "samsung,exynos4210-mipi-dsi";
177 reg = <0x11C80000 0x10000>;
178 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
179 power-domains = <&pd_lcd0>;
180 phys = <&mipi_phy 1>;
181 phy-names = "dsim";
182 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
183 clock-names = "bus_clk", "sclk_mipi";
184 status = "disabled";
185 #address-cells = <1>;
186 #size-cells = <0>;
187 };
188
189 camera {
190 compatible = "samsung,fimc", "simple-bus";
191 status = "disabled";
192 #address-cells = <1>;
193 #size-cells = <1>;
194 #clock-cells = <1>;
195 clock-output-names = "cam_a_clkout", "cam_b_clkout";
196 ranges;
197
198 fimc_0: fimc@11800000 {
199 compatible = "samsung,exynos4210-fimc";
200 reg = <0x11800000 0x1000>;
201 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
203 clock-names = "fimc", "sclk_fimc";
204 power-domains = <&pd_cam>;
205 samsung,sysreg = <&sys_reg>;
206 iommus = <&sysmmu_fimc0>;
207 status = "disabled";
208 };
209
210 fimc_1: fimc@11810000 {
211 compatible = "samsung,exynos4210-fimc";
212 reg = <0x11810000 0x1000>;
213 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
215 clock-names = "fimc", "sclk_fimc";
216 power-domains = <&pd_cam>;
217 samsung,sysreg = <&sys_reg>;
218 iommus = <&sysmmu_fimc1>;
219 status = "disabled";
220 };
221
222 fimc_2: fimc@11820000 {
223 compatible = "samsung,exynos4210-fimc";
224 reg = <0x11820000 0x1000>;
225 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
227 clock-names = "fimc", "sclk_fimc";
228 power-domains = <&pd_cam>;
229 samsung,sysreg = <&sys_reg>;
230 iommus = <&sysmmu_fimc2>;
231 status = "disabled";
232 };
233
234 fimc_3: fimc@11830000 {
235 compatible = "samsung,exynos4210-fimc";
236 reg = <0x11830000 0x1000>;
237 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
239 clock-names = "fimc", "sclk_fimc";
240 power-domains = <&pd_cam>;
241 samsung,sysreg = <&sys_reg>;
242 iommus = <&sysmmu_fimc3>;
243 status = "disabled";
244 };
245
246 csis_0: csis@11880000 {
247 compatible = "samsung,exynos4210-csis";
248 reg = <0x11880000 0x4000>;
249 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
251 clock-names = "csis", "sclk_csis";
252 bus-width = <4>;
253 power-domains = <&pd_cam>;
254 phys = <&mipi_phy 0>;
255 phy-names = "csis";
256 status = "disabled";
257 #address-cells = <1>;
258 #size-cells = <0>;
259 };
260
261 csis_1: csis@11890000 {
262 compatible = "samsung,exynos4210-csis";
263 reg = <0x11890000 0x4000>;
264 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
266 clock-names = "csis", "sclk_csis";
267 bus-width = <2>;
268 power-domains = <&pd_cam>;
269 phys = <&mipi_phy 2>;
270 phy-names = "csis";
271 status = "disabled";
272 #address-cells = <1>;
273 #size-cells = <0>;
274 };
275 };
276
277 watchdog: watchdog@10060000 {
278 compatible = "samsung,s3c2410-wdt";
279 reg = <0x10060000 0x100>;
280 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clock CLK_WDT>;
282 clock-names = "watchdog";
283 status = "disabled";
284 };
285
286 rtc: rtc@10070000 {
287 compatible = "samsung,s3c6410-rtc";
288 reg = <0x10070000 0x100>;
289 interrupt-parent = <&pmu_system_controller>;
290 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&clock CLK_RTC>;
293 clock-names = "rtc";
294 status = "disabled";
295 };
296
297 keypad: keypad@100A0000 {
298 compatible = "samsung,s5pv210-keypad";
299 reg = <0x100A0000 0x100>;
300 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&clock CLK_KEYIF>;
302 clock-names = "keypad";
303 status = "disabled";
304 };
305
306 sdhci_0: sdhci@12510000 {
307 compatible = "samsung,exynos4210-sdhci";
308 reg = <0x12510000 0x100>;
309 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
311 clock-names = "hsmmc", "mmc_busclk.2";
312 status = "disabled";
313 };
314
315 sdhci_1: sdhci@12520000 {
316 compatible = "samsung,exynos4210-sdhci";
317 reg = <0x12520000 0x100>;
318 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
320 clock-names = "hsmmc", "mmc_busclk.2";
321 status = "disabled";
322 };
323
324 sdhci_2: sdhci@12530000 {
325 compatible = "samsung,exynos4210-sdhci";
326 reg = <0x12530000 0x100>;
327 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
329 clock-names = "hsmmc", "mmc_busclk.2";
330 status = "disabled";
331 };
332
333 sdhci_3: sdhci@12540000 {
334 compatible = "samsung,exynos4210-sdhci";
335 reg = <0x12540000 0x100>;
336 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
338 clock-names = "hsmmc", "mmc_busclk.2";
339 status = "disabled";
340 };
341
342 exynos_usbphy: exynos-usbphy@125B0000 {
343 compatible = "samsung,exynos4210-usb2-phy";
344 reg = <0x125B0000 0x100>;
345 samsung,pmureg-phandle = <&pmu_system_controller>;
346 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
347 clock-names = "phy", "ref";
348 #phy-cells = <1>;
349 status = "disabled";
350 };
351
352 hsotg: hsotg@12480000 {
353 compatible = "samsung,s3c6400-hsotg";
354 reg = <0x12480000 0x20000>;
355 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clock CLK_USB_DEVICE>;
357 clock-names = "otg";
358 phys = <&exynos_usbphy 0>;
359 phy-names = "usb2-phy";
360 status = "disabled";
361 };
362
363 ehci: ehci@12580000 {
364 compatible = "samsung,exynos4210-ehci";
365 reg = <0x12580000 0x100>;
366 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&clock CLK_USB_HOST>;
368 clock-names = "usbhost";
369 status = "disabled";
370 #address-cells = <1>;
371 #size-cells = <0>;
372 port@0 {
373 reg = <0>;
374 phys = <&exynos_usbphy 1>;
375 status = "disabled";
376 };
377 port@1 {
378 reg = <1>;
379 phys = <&exynos_usbphy 2>;
380 status = "disabled";
381 };
382 port@2 {
383 reg = <2>;
384 phys = <&exynos_usbphy 3>;
385 status = "disabled";
386 };
387 };
388
389 ohci: ohci@12590000 {
390 compatible = "samsung,exynos4210-ohci";
391 reg = <0x12590000 0x100>;
392 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&clock CLK_USB_HOST>;
394 clock-names = "usbhost";
395 status = "disabled";
396 #address-cells = <1>;
397 #size-cells = <0>;
398 port@0 {
399 reg = <0>;
400 phys = <&exynos_usbphy 1>;
401 status = "disabled";
402 };
403 };
404
405 i2s1: i2s@13960000 {
406 compatible = "samsung,s3c6410-i2s";
407 reg = <0x13960000 0x100>;
408 clocks = <&clock CLK_I2S1>;
409 clock-names = "iis";
410 #clock-cells = <1>;
411 clock-output-names = "i2s_cdclk1";
412 dmas = <&pdma1 12>, <&pdma1 11>;
413 dma-names = "tx", "rx";
414 #sound-dai-cells = <1>;
415 status = "disabled";
416 };
417
418 i2s2: i2s@13970000 {
419 compatible = "samsung,s3c6410-i2s";
420 reg = <0x13970000 0x100>;
421 clocks = <&clock CLK_I2S2>;
422 clock-names = "iis";
423 #clock-cells = <1>;
424 clock-output-names = "i2s_cdclk2";
425 dmas = <&pdma0 14>, <&pdma0 13>;
426 dma-names = "tx", "rx";
427 #sound-dai-cells = <1>;
428 status = "disabled";
429 };
430
431 mfc: codec@13400000 {
432 compatible = "samsung,mfc-v5";
433 reg = <0x13400000 0x10000>;
434 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
435 power-domains = <&pd_mfc>;
436 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
437 clock-names = "mfc", "sclk_mfc";
438 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
439 iommu-names = "left", "right";
440 };
441
442 serial_0: serial@13800000 {
443 compatible = "samsung,exynos4210-uart";
444 reg = <0x13800000 0x100>;
445 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
447 clock-names = "uart", "clk_uart_baud0";
448 dmas = <&pdma0 15>, <&pdma0 16>;
449 dma-names = "rx", "tx";
450 status = "disabled";
451 };
452
453 serial_1: serial@13810000 {
454 compatible = "samsung,exynos4210-uart";
455 reg = <0x13810000 0x100>;
456 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
458 clock-names = "uart", "clk_uart_baud0";
459 dmas = <&pdma1 15>, <&pdma1 16>;
460 dma-names = "rx", "tx";
461 status = "disabled";
462 };
463
464 serial_2: serial@13820000 {
465 compatible = "samsung,exynos4210-uart";
466 reg = <0x13820000 0x100>;
467 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
469 clock-names = "uart", "clk_uart_baud0";
470 dmas = <&pdma0 17>, <&pdma0 18>;
471 dma-names = "rx", "tx";
472 status = "disabled";
473 };
474
475 serial_3: serial@13830000 {
476 compatible = "samsung,exynos4210-uart";
477 reg = <0x13830000 0x100>;
478 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
480 clock-names = "uart", "clk_uart_baud0";
481 dmas = <&pdma1 17>, <&pdma1 18>;
482 dma-names = "rx", "tx";
483 status = "disabled";
484 };
485
486 i2c_0: i2c@13860000 {
487 #address-cells = <1>;
488 #size-cells = <0>;
489 compatible = "samsung,s3c2440-i2c";
490 reg = <0x13860000 0x100>;
491 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&clock CLK_I2C0>;
493 clock-names = "i2c";
494 pinctrl-names = "default";
495 pinctrl-0 = <&i2c0_bus>;
496 status = "disabled";
497 };
498
499 i2c_1: i2c@13870000 {
500 #address-cells = <1>;
501 #size-cells = <0>;
502 compatible = "samsung,s3c2440-i2c";
503 reg = <0x13870000 0x100>;
504 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&clock CLK_I2C1>;
506 clock-names = "i2c";
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2c1_bus>;
509 status = "disabled";
510 };
511
512 i2c_2: i2c@13880000 {
513 #address-cells = <1>;
514 #size-cells = <0>;
515 compatible = "samsung,s3c2440-i2c";
516 reg = <0x13880000 0x100>;
517 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clock CLK_I2C2>;
519 clock-names = "i2c";
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c2_bus>;
522 status = "disabled";
523 };
524
525 i2c_3: i2c@13890000 {
526 #address-cells = <1>;
527 #size-cells = <0>;
528 compatible = "samsung,s3c2440-i2c";
529 reg = <0x13890000 0x100>;
530 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&clock CLK_I2C3>;
532 clock-names = "i2c";
533 pinctrl-names = "default";
534 pinctrl-0 = <&i2c3_bus>;
535 status = "disabled";
536 };
537
538 i2c_4: i2c@138A0000 {
539 #address-cells = <1>;
540 #size-cells = <0>;
541 compatible = "samsung,s3c2440-i2c";
542 reg = <0x138A0000 0x100>;
543 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&clock CLK_I2C4>;
545 clock-names = "i2c";
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c4_bus>;
548 status = "disabled";
549 };
550
551 i2c_5: i2c@138B0000 {
552 #address-cells = <1>;
553 #size-cells = <0>;
554 compatible = "samsung,s3c2440-i2c";
555 reg = <0x138B0000 0x100>;
556 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&clock CLK_I2C5>;
558 clock-names = "i2c";
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c5_bus>;
561 status = "disabled";
562 };
563
564 i2c_6: i2c@138C0000 {
565 #address-cells = <1>;
566 #size-cells = <0>;
567 compatible = "samsung,s3c2440-i2c";
568 reg = <0x138C0000 0x100>;
569 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&clock CLK_I2C6>;
571 clock-names = "i2c";
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c6_bus>;
574 status = "disabled";
575 };
576
577 i2c_7: i2c@138D0000 {
578 #address-cells = <1>;
579 #size-cells = <0>;
580 compatible = "samsung,s3c2440-i2c";
581 reg = <0x138D0000 0x100>;
582 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&clock CLK_I2C7>;
584 clock-names = "i2c";
585 pinctrl-names = "default";
586 pinctrl-0 = <&i2c7_bus>;
587 status = "disabled";
588 };
589
590 i2c_8: i2c@138E0000 {
591 #address-cells = <1>;
592 #size-cells = <0>;
593 compatible = "samsung,s3c2440-hdmiphy-i2c";
594 reg = <0x138E0000 0x100>;
595 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&clock CLK_I2C_HDMI>;
597 clock-names = "i2c";
598 status = "disabled";
599
600 hdmi_i2c_phy: hdmiphy@38 {
601 compatible = "exynos4210-hdmiphy";
602 reg = <0x38>;
603 };
604 };
605
606 spi_0: spi@13920000 {
607 compatible = "samsung,exynos4210-spi";
608 reg = <0x13920000 0x100>;
609 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
610 dmas = <&pdma0 7>, <&pdma0 6>;
611 dma-names = "tx", "rx";
612 #address-cells = <1>;
613 #size-cells = <0>;
614 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
615 clock-names = "spi", "spi_busclk0";
616 pinctrl-names = "default";
617 pinctrl-0 = <&spi0_bus>;
618 status = "disabled";
619 };
620
621 spi_1: spi@13930000 {
622 compatible = "samsung,exynos4210-spi";
623 reg = <0x13930000 0x100>;
624 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
625 dmas = <&pdma1 7>, <&pdma1 6>;
626 dma-names = "tx", "rx";
627 #address-cells = <1>;
628 #size-cells = <0>;
629 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
630 clock-names = "spi", "spi_busclk0";
631 pinctrl-names = "default";
632 pinctrl-0 = <&spi1_bus>;
633 status = "disabled";
634 };
635
636 spi_2: spi@13940000 {
637 compatible = "samsung,exynos4210-spi";
638 reg = <0x13940000 0x100>;
639 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
640 dmas = <&pdma0 9>, <&pdma0 8>;
641 dma-names = "tx", "rx";
642 #address-cells = <1>;
643 #size-cells = <0>;
644 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
645 clock-names = "spi", "spi_busclk0";
646 pinctrl-names = "default";
647 pinctrl-0 = <&spi2_bus>;
648 status = "disabled";
649 };
650
651 pwm: pwm@139D0000 {
652 compatible = "samsung,exynos4210-pwm";
653 reg = <0x139D0000 0x1000>;
654 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&clock CLK_PWM>;
660 clock-names = "timers";
661 #pwm-cells = <3>;
662 status = "disabled";
663 };
664
665 amba {
666 #address-cells = <1>;
667 #size-cells = <1>;
668 compatible = "simple-bus";
669 interrupt-parent = <&gic>;
670 ranges;
671
672 pdma0: pdma@12680000 {
673 compatible = "arm,pl330", "arm,primecell";
674 reg = <0x12680000 0x1000>;
675 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&clock CLK_PDMA0>;
677 clock-names = "apb_pclk";
678 #dma-cells = <1>;
679 #dma-channels = <8>;
680 #dma-requests = <32>;
681 };
682
683 pdma1: pdma@12690000 {
684 compatible = "arm,pl330", "arm,primecell";
685 reg = <0x12690000 0x1000>;
686 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&clock CLK_PDMA1>;
688 clock-names = "apb_pclk";
689 #dma-cells = <1>;
690 #dma-channels = <8>;
691 #dma-requests = <32>;
692 };
693
694 mdma1: mdma@12850000 {
695 compatible = "arm,pl330", "arm,primecell";
696 reg = <0x12850000 0x1000>;
697 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&clock CLK_MDMA>;
699 clock-names = "apb_pclk";
700 #dma-cells = <1>;
701 #dma-channels = <8>;
702 #dma-requests = <1>;
703 };
704 };
705
706 fimd: fimd@11c00000 {
707 compatible = "samsung,exynos4210-fimd";
708 interrupt-parent = <&combiner>;
709 reg = <0x11c00000 0x20000>;
710 interrupt-names = "fifo", "vsync", "lcd_sys";
711 interrupts = <11 0>, <11 1>, <11 2>;
712 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
713 clock-names = "sclk_fimd", "fimd";
714 power-domains = <&pd_lcd0>;
715 iommus = <&sysmmu_fimd0>;
716 samsung,sysreg = <&sys_reg>;
717 status = "disabled";
718 };
719
720 tmu: tmu@100C0000 {
721 #include "exynos4412-tmu-sensor-conf.dtsi"
722 };
723
724 jpeg_codec: jpeg-codec@11840000 {
725 compatible = "samsung,exynos4210-jpeg";
726 reg = <0x11840000 0x1000>;
727 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&clock CLK_JPEG>;
729 clock-names = "jpeg";
730 power-domains = <&pd_cam>;
731 iommus = <&sysmmu_jpeg>;
732 };
733
734 rotator: rotator@12810000 {
735 compatible = "samsung,exynos4210-rotator";
736 reg = <0x12810000 0x64>;
737 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&clock CLK_ROTATOR>;
739 clock-names = "rotator";
740 iommus = <&sysmmu_rotator>;
741 };
742
743 hdmi: hdmi@12D00000 {
744 compatible = "samsung,exynos4210-hdmi";
745 reg = <0x12D00000 0x70000>;
746 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
747 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
748 "mout_hdmi";
749 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
750 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
751 <&clock CLK_MOUT_HDMI>;
752 phy = <&hdmi_i2c_phy>;
753 power-domains = <&pd_tv>;
754 samsung,syscon-phandle = <&pmu_system_controller>;
755 status = "disabled";
756 };
757
758 hdmicec: cec@100B0000 {
759 compatible = "samsung,s5p-cec";
760 reg = <0x100B0000 0x200>;
761 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&clock CLK_HDMI_CEC>;
763 clock-names = "hdmicec";
764 samsung,syscon-phandle = <&pmu_system_controller>;
765 pinctrl-names = "default";
766 pinctrl-0 = <&hdmi_cec>;
767 status = "disabled";
768 };
769
770 mixer: mixer@12C10000 {
771 compatible = "samsung,exynos4210-mixer";
772 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
773 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
774 power-domains = <&pd_tv>;
775 iommus = <&sysmmu_tv>;
776 status = "disabled";
777 };
778
779 ppmu_dmc0: ppmu_dmc0@106a0000 {
780 compatible = "samsung,exynos-ppmu";
781 reg = <0x106a0000 0x2000>;
782 clocks = <&clock CLK_PPMUDMC0>;
783 clock-names = "ppmu";
784 status = "disabled";
785 };
786
787 ppmu_dmc1: ppmu_dmc1@106b0000 {
788 compatible = "samsung,exynos-ppmu";
789 reg = <0x106b0000 0x2000>;
790 clocks = <&clock CLK_PPMUDMC1>;
791 clock-names = "ppmu";
792 status = "disabled";
793 };
794
795 ppmu_cpu: ppmu_cpu@106c0000 {
796 compatible = "samsung,exynos-ppmu";
797 reg = <0x106c0000 0x2000>;
798 clocks = <&clock CLK_PPMUCPU>;
799 clock-names = "ppmu";
800 status = "disabled";
801 };
802
803 ppmu_acp: ppmu_acp@10ae0000 {
804 compatible = "samsung,exynos-ppmu";
805 reg = <0x106e0000 0x2000>;
806 status = "disabled";
807 };
808
809 ppmu_rightbus: ppmu_rightbus@112a0000 {
810 compatible = "samsung,exynos-ppmu";
811 reg = <0x112a0000 0x2000>;
812 clocks = <&clock CLK_PPMURIGHT>;
813 clock-names = "ppmu";
814 status = "disabled";
815 };
816
817 ppmu_leftbus: ppmu_leftbus0@116a0000 {
818 compatible = "samsung,exynos-ppmu";
819 reg = <0x116a0000 0x2000>;
820 clocks = <&clock CLK_PPMULEFT>;
821 clock-names = "ppmu";
822 status = "disabled";
823 };
824
825 ppmu_camif: ppmu_camif@11ac0000 {
826 compatible = "samsung,exynos-ppmu";
827 reg = <0x11ac0000 0x2000>;
828 clocks = <&clock CLK_PPMUCAMIF>;
829 clock-names = "ppmu";
830 status = "disabled";
831 };
832
833 ppmu_lcd0: ppmu_lcd0@11e40000 {
834 compatible = "samsung,exynos-ppmu";
835 reg = <0x11e40000 0x2000>;
836 clocks = <&clock CLK_PPMULCD0>;
837 clock-names = "ppmu";
838 status = "disabled";
839 };
840
841 ppmu_fsys: ppmu_g3d@12630000 {
842 compatible = "samsung,exynos-ppmu";
843 reg = <0x12630000 0x2000>;
844 status = "disabled";
845 };
846
847 ppmu_image: ppmu_image@12aa0000 {
848 compatible = "samsung,exynos-ppmu";
849 reg = <0x12aa0000 0x2000>;
850 clocks = <&clock CLK_PPMUIMAGE>;
851 clock-names = "ppmu";
852 status = "disabled";
853 };
854
855 ppmu_tv: ppmu_tv@12e40000 {
856 compatible = "samsung,exynos-ppmu";
857 reg = <0x12e40000 0x2000>;
858 clocks = <&clock CLK_PPMUTV>;
859 clock-names = "ppmu";
860 status = "disabled";
861 };
862
863 ppmu_g3d: ppmu_g3d@13220000 {
864 compatible = "samsung,exynos-ppmu";
865 reg = <0x13220000 0x2000>;
866 clocks = <&clock CLK_PPMUG3D>;
867 clock-names = "ppmu";
868 status = "disabled";
869 };
870
871 ppmu_mfc_left: ppmu_mfc_left@13660000 {
872 compatible = "samsung,exynos-ppmu";
873 reg = <0x13660000 0x2000>;
874 clocks = <&clock CLK_PPMUMFC_L>;
875 clock-names = "ppmu";
876 status = "disabled";
877 };
878
879 ppmu_mfc_right: ppmu_mfc_right@13670000 {
880 compatible = "samsung,exynos-ppmu";
881 reg = <0x13670000 0x2000>;
882 clocks = <&clock CLK_PPMUMFC_R>;
883 clock-names = "ppmu";
884 status = "disabled";
885 };
886
887 sysmmu_mfc_l: sysmmu@13620000 {
888 compatible = "samsung,exynos-sysmmu";
889 reg = <0x13620000 0x1000>;
890 interrupt-parent = <&combiner>;
891 interrupts = <5 5>;
892 clock-names = "sysmmu", "master";
893 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
894 power-domains = <&pd_mfc>;
895 #iommu-cells = <0>;
896 };
897
898 sysmmu_mfc_r: sysmmu@13630000 {
899 compatible = "samsung,exynos-sysmmu";
900 reg = <0x13630000 0x1000>;
901 interrupt-parent = <&combiner>;
902 interrupts = <5 6>;
903 clock-names = "sysmmu", "master";
904 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
905 power-domains = <&pd_mfc>;
906 #iommu-cells = <0>;
907 };
908
909 sysmmu_tv: sysmmu@12E20000 {
910 compatible = "samsung,exynos-sysmmu";
911 reg = <0x12E20000 0x1000>;
912 interrupt-parent = <&combiner>;
913 interrupts = <5 4>;
914 clock-names = "sysmmu", "master";
915 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
916 power-domains = <&pd_tv>;
917 #iommu-cells = <0>;
918 };
919
920 sysmmu_fimc0: sysmmu@11A20000 {
921 compatible = "samsung,exynos-sysmmu";
922 reg = <0x11A20000 0x1000>;
923 interrupt-parent = <&combiner>;
924 interrupts = <4 2>;
925 clock-names = "sysmmu", "master";
926 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
927 power-domains = <&pd_cam>;
928 #iommu-cells = <0>;
929 };
930
931 sysmmu_fimc1: sysmmu@11A30000 {
932 compatible = "samsung,exynos-sysmmu";
933 reg = <0x11A30000 0x1000>;
934 interrupt-parent = <&combiner>;
935 interrupts = <4 3>;
936 clock-names = "sysmmu", "master";
937 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
938 power-domains = <&pd_cam>;
939 #iommu-cells = <0>;
940 };
941
942 sysmmu_fimc2: sysmmu@11A40000 {
943 compatible = "samsung,exynos-sysmmu";
944 reg = <0x11A40000 0x1000>;
945 interrupt-parent = <&combiner>;
946 interrupts = <4 4>;
947 clock-names = "sysmmu", "master";
948 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
949 power-domains = <&pd_cam>;
950 #iommu-cells = <0>;
951 };
952
953 sysmmu_fimc3: sysmmu@11A50000 {
954 compatible = "samsung,exynos-sysmmu";
955 reg = <0x11A50000 0x1000>;
956 interrupt-parent = <&combiner>;
957 interrupts = <4 5>;
958 clock-names = "sysmmu", "master";
959 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
960 power-domains = <&pd_cam>;
961 #iommu-cells = <0>;
962 };
963
964 sysmmu_jpeg: sysmmu@11A60000 {
965 compatible = "samsung,exynos-sysmmu";
966 reg = <0x11A60000 0x1000>;
967 interrupt-parent = <&combiner>;
968 interrupts = <4 6>;
969 clock-names = "sysmmu", "master";
970 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
971 power-domains = <&pd_cam>;
972 #iommu-cells = <0>;
973 };
974
975 sysmmu_rotator: sysmmu@12A30000 {
976 compatible = "samsung,exynos-sysmmu";
977 reg = <0x12A30000 0x1000>;
978 interrupt-parent = <&combiner>;
979 interrupts = <5 0>;
980 clock-names = "sysmmu", "master";
981 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
982 #iommu-cells = <0>;
983 };
984
985 sysmmu_fimd0: sysmmu@11E20000 {
986 compatible = "samsung,exynos-sysmmu";
987 reg = <0x11E20000 0x1000>;
988 interrupt-parent = <&combiner>;
989 interrupts = <5 2>;
990 clock-names = "sysmmu", "master";
991 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
992 power-domains = <&pd_lcd0>;
993 #iommu-cells = <0>;
994 };
995
996 sss: sss@10830000 {
997 compatible = "samsung,exynos4210-secss";
998 reg = <0x10830000 0x300>;
999 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1000 clocks = <&clock CLK_SSS>;
1001 clock-names = "secss";
1002 };
1003
1004 prng: rng@10830400 {
1005 compatible = "samsung,exynos4-rng";
1006 reg = <0x10830400 0x200>;
1007 clocks = <&clock CLK_SSS>;
1008 clock-names = "secss";
1009 };
1010};