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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada XP family SoC
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * Ben Dooks <ben.dooks@codethink.co.uk>
11 *
12 * Contains definitions specific to the Armada XP SoC that are not
13 * common to all Armada SoCs.
14 */
15
16#include "armada-370-xp.dtsi"
17
18/ {
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24
25 aliases {
26 serial2 = &uart2;
27 serial3 = &uart3;
28 };
29
30 soc {
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
32
33 bootrom {
34 compatible = "marvell,bootrom";
35 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
36 };
37
38 internal-regs {
39 sdramc: sdramc@1400 {
40 compatible = "marvell,armada-xp-sdram-controller";
41 reg = <0x1400 0x500>;
42 };
43
44 L2: l2-cache@8000 {
45 compatible = "marvell,aurora-system-cache";
46 reg = <0x08000 0x1000>;
47 cache-id-part = <0x100>;
48 cache-level = <2>;
49 cache-unified;
50 wt-override;
51 };
52
53 uart2: serial@12200 {
54 compatible = "snps,dw-apb-uart";
55 pinctrl-0 = <&uart2_pins>;
56 pinctrl-names = "default";
57 reg = <0x12200 0x100>;
58 reg-shift = <2>;
59 interrupts = <43>;
60 reg-io-width = <1>;
61 clocks = <&coreclk 0>;
62 status = "disabled";
63 };
64
65 uart3: serial@12300 {
66 compatible = "snps,dw-apb-uart";
67 pinctrl-0 = <&uart3_pins>;
68 pinctrl-names = "default";
69 reg = <0x12300 0x100>;
70 reg-shift = <2>;
71 interrupts = <44>;
72 reg-io-width = <1>;
73 clocks = <&coreclk 0>;
74 status = "disabled";
75 };
76
77 systemc: system-controller@18200 {
78 compatible = "marvell,armada-370-xp-system-controller";
79 reg = <0x18200 0x500>;
80 };
81
82 gateclk: clock-gating-control@18220 {
83 compatible = "marvell,armada-xp-gating-clock";
84 reg = <0x18220 0x4>;
85 clocks = <&coreclk 0>;
86 #clock-cells = <1>;
87 };
88
89 coreclk: mvebu-sar@18230 {
90 compatible = "marvell,armada-xp-core-clock";
91 reg = <0x18230 0x08>;
92 #clock-cells = <1>;
93 };
94
95 thermal: thermal@182b0 {
96 compatible = "marvell,armadaxp-thermal";
97 reg = <0x182b0 0x4
98 0x184d0 0x4>;
99 status = "okay";
100 };
101
102 cpuclk: clock-complex@18700 {
103 #clock-cells = <1>;
104 compatible = "marvell,armada-xp-cpu-clock";
105 reg = <0x18700 0x24>, <0x1c054 0x10>;
106 clocks = <&coreclk 1>;
107 };
108
109 cpu-config@21000 {
110 compatible = "marvell,armada-xp-cpu-config";
111 reg = <0x21000 0x8>;
112 };
113
114 eth2: ethernet@30000 {
115 compatible = "marvell,armada-xp-neta";
116 reg = <0x30000 0x4000>;
117 interrupts = <12>;
118 clocks = <&gateclk 2>;
119 status = "disabled";
120 };
121
122 usb2: usb@52000 {
123 compatible = "marvell,orion-ehci";
124 reg = <0x52000 0x500>;
125 interrupts = <47>;
126 clocks = <&gateclk 20>;
127 status = "disabled";
128 };
129
130 xor1: xor@60900 {
131 compatible = "marvell,orion-xor";
132 reg = <0x60900 0x100
133 0x60b00 0x100>;
134 clocks = <&gateclk 22>;
135 status = "okay";
136
137 xor10 {
138 interrupts = <51>;
139 dmacap,memcpy;
140 dmacap,xor;
141 };
142 xor11 {
143 interrupts = <52>;
144 dmacap,memcpy;
145 dmacap,xor;
146 dmacap,memset;
147 };
148 };
149
150 ethernet@70000 {
151 compatible = "marvell,armada-xp-neta";
152 };
153
154 ethernet@74000 {
155 compatible = "marvell,armada-xp-neta";
156 };
157
158 cesa: crypto@90000 {
159 compatible = "marvell,armada-xp-crypto";
160 reg = <0x90000 0x10000>;
161 reg-names = "regs";
162 interrupts = <48>, <49>;
163 clocks = <&gateclk 23>, <&gateclk 23>;
164 clock-names = "cesa0", "cesa1";
165 marvell,crypto-srams = <&crypto_sram0>,
166 <&crypto_sram1>;
167 marvell,crypto-sram-size = <0x800>;
168 };
169
170 bm: bm@c0000 {
171 compatible = "marvell,armada-380-neta-bm";
172 reg = <0xc0000 0xac>;
173 clocks = <&gateclk 13>;
174 internal-mem = <&bm_bppi>;
175 status = "disabled";
176 };
177
178 xor0: xor@f0900 {
179 compatible = "marvell,orion-xor";
180 reg = <0xF0900 0x100
181 0xF0B00 0x100>;
182 clocks = <&gateclk 28>;
183 status = "okay";
184
185 xor00 {
186 interrupts = <94>;
187 dmacap,memcpy;
188 dmacap,xor;
189 };
190 xor01 {
191 interrupts = <95>;
192 dmacap,memcpy;
193 dmacap,xor;
194 dmacap,memset;
195 };
196 };
197 };
198
199 crypto_sram0: sa-sram0 {
200 compatible = "mmio-sram";
201 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
202 clocks = <&gateclk 23>;
203 #address-cells = <1>;
204 #size-cells = <1>;
205 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
206 };
207
208 crypto_sram1: sa-sram1 {
209 compatible = "mmio-sram";
210 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
211 clocks = <&gateclk 23>;
212 #address-cells = <1>;
213 #size-cells = <1>;
214 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
215 };
216
217 bm_bppi: bm-bppi {
218 compatible = "mmio-sram";
219 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
220 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
221 #address-cells = <1>;
222 #size-cells = <1>;
223 clocks = <&gateclk 13>;
224 no-memory-wc;
225 status = "disabled";
226 };
227 };
228
229 clocks {
230 /* 25 MHz reference crystal */
231 refclk: oscillator {
232 compatible = "fixed-clock";
233 #clock-cells = <0>;
234 clock-frequency = <25000000>;
235 };
236 };
237};
238
239&i2c0 {
240 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
241 reg = <0x11000 0x100>;
242};
243
244&i2c1 {
245 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
246 reg = <0x11100 0x100>;
247};
248
249&mpic {
250 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
251};
252
253&timer {
254 compatible = "marvell,armada-xp-timer";
255 clocks = <&coreclk 2>, <&refclk>;
256 clock-names = "nbclk", "fixed";
257};
258
259&watchdog {
260 compatible = "marvell,armada-xp-wdt";
261 clocks = <&coreclk 2>, <&refclk>;
262 clock-names = "nbclk", "fixed";
263 interrupts = <93>, <38>;
264};
265
266&cpurst {
267 reg = <0x20800 0x20>;
268};
269
270&usb0 {
271 clocks = <&gateclk 18>;
272};
273
274&usb1 {
275 clocks = <&gateclk 19>;
276};
277
278&pinctrl {
279 ge0_gmii_pins: ge0-gmii-pins {
280 marvell,pins =
281 "mpp0", "mpp1", "mpp2", "mpp3",
282 "mpp4", "mpp5", "mpp6", "mpp7",
283 "mpp8", "mpp9", "mpp10", "mpp11",
284 "mpp12", "mpp13", "mpp14", "mpp15",
285 "mpp16", "mpp17", "mpp18", "mpp19",
286 "mpp20", "mpp21", "mpp22", "mpp23";
287 marvell,function = "ge0";
288 };
289
290 ge0_rgmii_pins: ge0-rgmii-pins {
291 marvell,pins =
292 "mpp0", "mpp1", "mpp2", "mpp3",
293 "mpp4", "mpp5", "mpp6", "mpp7",
294 "mpp8", "mpp9", "mpp10", "mpp11";
295 marvell,function = "ge0";
296 };
297
298 ge1_rgmii_pins: ge1-rgmii-pins {
299 marvell,pins =
300 "mpp12", "mpp13", "mpp14", "mpp15",
301 "mpp16", "mpp17", "mpp18", "mpp19",
302 "mpp20", "mpp21", "mpp22", "mpp23";
303 marvell,function = "ge1";
304 };
305
306 sdio_pins: sdio-pins {
307 marvell,pins = "mpp30", "mpp31", "mpp32",
308 "mpp33", "mpp34", "mpp35";
309 marvell,function = "sd0";
310 };
311
312 spi0_pins: spi0-pins {
313 marvell,pins = "mpp36", "mpp37",
314 "mpp38", "mpp39";
315 marvell,function = "spi0";
316 };
317
318 spi1_pins: spi1-pins {
319 marvell,pins = "mpp13", "mpp14",
320 "mpp16", "mpp17";
321 marvell,function = "spi1";
322 };
323
324 uart2_pins: uart2-pins {
325 marvell,pins = "mpp42", "mpp43";
326 marvell,function = "uart2";
327 };
328
329 uart3_pins: uart3-pins {
330 marvell,pins = "mpp44", "mpp45";
331 marvell,function = "uart3";
332 };
333};
334
335&spi0 {
336 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
337 pinctrl-0 = <&spi0_pins>;
338 pinctrl-names = "default";
339};
340
341&spi1 {
342 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
343 pinctrl-0 = <&spi1_pins>;
344 pinctrl-names = "default";
345};
1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of the
19 * License, or (at your option) any later version.
20 *
21 * This file is distributed in the hope that it will be useful
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * Or, alternatively
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 *
49 * Contains definitions specific to the Armada XP SoC that are not
50 * common to all Armada SoCs.
51 */
52
53#include "armada-370-xp.dtsi"
54
55/ {
56 #address-cells = <2>;
57 #size-cells = <2>;
58
59 model = "Marvell Armada XP family SoC";
60 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
61
62 aliases {
63 serial2 = &uart2;
64 serial3 = &uart3;
65 };
66
67 soc {
68 compatible = "marvell,armadaxp-mbus", "simple-bus";
69
70 bootrom {
71 compatible = "marvell,bootrom";
72 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
73 };
74
75 internal-regs {
76 sdramc@1400 {
77 compatible = "marvell,armada-xp-sdram-controller";
78 reg = <0x1400 0x500>;
79 };
80
81 L2: l2-cache@8000 {
82 compatible = "marvell,aurora-system-cache";
83 reg = <0x08000 0x1000>;
84 cache-id-part = <0x100>;
85 cache-level = <2>;
86 cache-unified;
87 wt-override;
88 };
89
90 uart2: serial@12200 {
91 compatible = "snps,dw-apb-uart";
92 pinctrl-0 = <&uart2_pins>;
93 pinctrl-names = "default";
94 reg = <0x12200 0x100>;
95 reg-shift = <2>;
96 interrupts = <43>;
97 reg-io-width = <1>;
98 clocks = <&coreclk 0>;
99 status = "disabled";
100 };
101
102 uart3: serial@12300 {
103 compatible = "snps,dw-apb-uart";
104 pinctrl-0 = <&uart3_pins>;
105 pinctrl-names = "default";
106 reg = <0x12300 0x100>;
107 reg-shift = <2>;
108 interrupts = <44>;
109 reg-io-width = <1>;
110 clocks = <&coreclk 0>;
111 status = "disabled";
112 };
113
114 systemc: system-controller@18200 {
115 compatible = "marvell,armada-370-xp-system-controller";
116 reg = <0x18200 0x500>;
117 };
118
119 gateclk: clock-gating-control@18220 {
120 compatible = "marvell,armada-xp-gating-clock";
121 reg = <0x18220 0x4>;
122 clocks = <&coreclk 0>;
123 #clock-cells = <1>;
124 };
125
126 coreclk: mvebu-sar@18230 {
127 compatible = "marvell,armada-xp-core-clock";
128 reg = <0x18230 0x08>;
129 #clock-cells = <1>;
130 };
131
132 thermal: thermal@182b0 {
133 compatible = "marvell,armadaxp-thermal";
134 reg = <0x182b0 0x4
135 0x184d0 0x4>;
136 status = "okay";
137 };
138
139 cpuclk: clock-complex@18700 {
140 #clock-cells = <1>;
141 compatible = "marvell,armada-xp-cpu-clock";
142 reg = <0x18700 0x24>, <0x1c054 0x10>;
143 clocks = <&coreclk 1>;
144 };
145
146 cpu-config@21000 {
147 compatible = "marvell,armada-xp-cpu-config";
148 reg = <0x21000 0x8>;
149 };
150
151 eth2: ethernet@30000 {
152 compatible = "marvell,armada-xp-neta";
153 reg = <0x30000 0x4000>;
154 interrupts = <12>;
155 clocks = <&gateclk 2>;
156 status = "disabled";
157 };
158
159 usb2: usb@52000 {
160 compatible = "marvell,orion-ehci";
161 reg = <0x52000 0x500>;
162 interrupts = <47>;
163 clocks = <&gateclk 20>;
164 status = "disabled";
165 };
166
167 xor1: xor@60900 {
168 compatible = "marvell,orion-xor";
169 reg = <0x60900 0x100
170 0x60b00 0x100>;
171 clocks = <&gateclk 22>;
172 status = "okay";
173
174 xor10 {
175 interrupts = <51>;
176 dmacap,memcpy;
177 dmacap,xor;
178 };
179 xor11 {
180 interrupts = <52>;
181 dmacap,memcpy;
182 dmacap,xor;
183 dmacap,memset;
184 };
185 };
186
187 ethernet@70000 {
188 compatible = "marvell,armada-xp-neta";
189 };
190
191 ethernet@74000 {
192 compatible = "marvell,armada-xp-neta";
193 };
194
195 cesa: crypto@90000 {
196 compatible = "marvell,armada-xp-crypto";
197 reg = <0x90000 0x10000>;
198 reg-names = "regs";
199 interrupts = <48>, <49>;
200 clocks = <&gateclk 23>, <&gateclk 23>;
201 clock-names = "cesa0", "cesa1";
202 marvell,crypto-srams = <&crypto_sram0>,
203 <&crypto_sram1>;
204 marvell,crypto-sram-size = <0x800>;
205 };
206
207 bm: bm@c0000 {
208 compatible = "marvell,armada-380-neta-bm";
209 reg = <0xc0000 0xac>;
210 clocks = <&gateclk 13>;
211 internal-mem = <&bm_bppi>;
212 status = "disabled";
213 };
214
215 xor0: xor@f0900 {
216 compatible = "marvell,orion-xor";
217 reg = <0xF0900 0x100
218 0xF0B00 0x100>;
219 clocks = <&gateclk 28>;
220 status = "okay";
221
222 xor00 {
223 interrupts = <94>;
224 dmacap,memcpy;
225 dmacap,xor;
226 };
227 xor01 {
228 interrupts = <95>;
229 dmacap,memcpy;
230 dmacap,xor;
231 dmacap,memset;
232 };
233 };
234 };
235
236 crypto_sram0: sa-sram0 {
237 compatible = "mmio-sram";
238 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
239 clocks = <&gateclk 23>;
240 #address-cells = <1>;
241 #size-cells = <1>;
242 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
243 };
244
245 crypto_sram1: sa-sram1 {
246 compatible = "mmio-sram";
247 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
248 clocks = <&gateclk 23>;
249 #address-cells = <1>;
250 #size-cells = <1>;
251 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
252 };
253
254 bm_bppi: bm-bppi {
255 compatible = "mmio-sram";
256 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
257 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
258 #address-cells = <1>;
259 #size-cells = <1>;
260 clocks = <&gateclk 13>;
261 no-memory-wc;
262 status = "disabled";
263 };
264 };
265
266 clocks {
267 /* 25 MHz reference crystal */
268 refclk: oscillator {
269 compatible = "fixed-clock";
270 #clock-cells = <0>;
271 clock-frequency = <25000000>;
272 };
273 };
274};
275
276&i2c0 {
277 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
278 reg = <0x11000 0x100>;
279};
280
281&i2c1 {
282 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
283 reg = <0x11100 0x100>;
284};
285
286&mpic {
287 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
288};
289
290&timer {
291 compatible = "marvell,armada-xp-timer";
292 clocks = <&coreclk 2>, <&refclk>;
293 clock-names = "nbclk", "fixed";
294};
295
296&watchdog {
297 compatible = "marvell,armada-xp-wdt";
298 clocks = <&coreclk 2>, <&refclk>;
299 clock-names = "nbclk", "fixed";
300};
301
302&cpurst {
303 reg = <0x20800 0x20>;
304};
305
306&usb0 {
307 clocks = <&gateclk 18>;
308};
309
310&usb1 {
311 clocks = <&gateclk 19>;
312};
313
314&pinctrl {
315 ge0_gmii_pins: ge0-gmii-pins {
316 marvell,pins =
317 "mpp0", "mpp1", "mpp2", "mpp3",
318 "mpp4", "mpp5", "mpp6", "mpp7",
319 "mpp8", "mpp9", "mpp10", "mpp11",
320 "mpp12", "mpp13", "mpp14", "mpp15",
321 "mpp16", "mpp17", "mpp18", "mpp19",
322 "mpp20", "mpp21", "mpp22", "mpp23";
323 marvell,function = "ge0";
324 };
325
326 ge0_rgmii_pins: ge0-rgmii-pins {
327 marvell,pins =
328 "mpp0", "mpp1", "mpp2", "mpp3",
329 "mpp4", "mpp5", "mpp6", "mpp7",
330 "mpp8", "mpp9", "mpp10", "mpp11";
331 marvell,function = "ge0";
332 };
333
334 ge1_rgmii_pins: ge1-rgmii-pins {
335 marvell,pins =
336 "mpp12", "mpp13", "mpp14", "mpp15",
337 "mpp16", "mpp17", "mpp18", "mpp19",
338 "mpp20", "mpp21", "mpp22", "mpp23";
339 marvell,function = "ge1";
340 };
341
342 sdio_pins: sdio-pins {
343 marvell,pins = "mpp30", "mpp31", "mpp32",
344 "mpp33", "mpp34", "mpp35";
345 marvell,function = "sd0";
346 };
347
348 spi0_pins: spi0-pins {
349 marvell,pins = "mpp36", "mpp37",
350 "mpp38", "mpp39";
351 marvell,function = "spi0";
352 };
353
354 spi1_pins: spi1-pins {
355 marvell,pins = "mpp13", "mpp14",
356 "mpp16", "mpp17";
357 marvell,function = "spi1";
358 };
359
360 uart2_pins: uart2-pins {
361 marvell,pins = "mpp42", "mpp43";
362 marvell,function = "uart2";
363 };
364
365 uart3_pins: uart3-pins {
366 marvell,pins = "mpp44", "mpp45";
367 marvell,function = "uart3";
368 };
369};
370
371&spi0 {
372 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
373 pinctrl-0 = <&spi0_pins>;
374 pinctrl-names = "default";
375};
376
377&spi1 {
378 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
379 pinctrl-0 = <&spi1_pins>;
380 pinctrl-names = "default";
381};