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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree file for Marvell Armada 395 GP board
4 *
5 * Copyright (C) 2016 Marvell
6 *
7 * Grzegorz Jaszczyk <jaz@semihalf.com>
8 */
9
10/dts-v1/;
11#include "armada-395.dtsi"
12
13/ {
14 model = "Marvell Armada 395 GP Board";
15 compatible = "marvell,a395-gp", "marvell,armada395",
16 "marvell,armada390";
17
18 chosen {
19 stdout-path = "serial0:115200n8";
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x00000000 0x40000000>; /* 1 GB */
25 };
26
27 soc {
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
29 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
30
31 internal-regs {
32 i2c@11000 {
33 status = "okay";
34 clock-frequency = <100000>;
35
36 eeprom@57 {
37 compatible = "atmel,24c64";
38 reg = <0x57>;
39 };
40 };
41
42 serial@12000 {
43 /*
44 * Exported on the micro USB connector CON17
45 * through an FTDI
46 */
47 status = "okay";
48 };
49
50 /* CON1 */
51 usb@58000 {
52 status = "okay";
53 };
54
55 /* CON2 */
56 sata@a8000 {
57 status = "okay";
58 };
59
60 /* CON18 */
61 sdhci@d8000 {
62 clock-frequency = <200000000>;
63 broken-cd;
64 wp-inverted;
65 bus-width = <8>;
66 status = "okay";
67 no-1-8-v;
68 };
69
70 /* CON4 */
71 usb3@f0000 {
72 status = "okay";
73 };
74 };
75
76 pcie {
77 status = "okay";
78
79 /*
80 * The two PCIe units are accessible through
81 * mini PCIe slot on the board.
82 */
83
84 /* CON7 */
85 pcie@2,0 {
86 /* Port 1, Lane 0 */
87 status = "okay";
88 };
89
90 /* CON8 */
91 pcie@4,0 {
92 /* Port 3, Lane 0 */
93 status = "okay";
94 };
95 };
96 };
97};
98
99&nand_controller {
100 status = "okay";
101 pinctrl-0 = <&nand_pins>;
102 pinctrl-names = "default";
103
104 nand@0 {
105 reg = <0>;
106 label = "pxa3xx_nand-0";
107 nand-rb = <0>;
108 marvell,nand-keep-config;
109 nand-on-flash-bbt;
110 nand-ecc-strength = <4>;
111 nand-ecc-step-size = <512>;
112
113 partitions {
114 compatible = "fixed-partitions";
115 #address-cells = <1>;
116 #size-cells = <1>;
117
118 partition@0 {
119 label = "U-Boot";
120 reg = <0x00000000 0x00600000>;
121 read-only;
122 };
123
124 partition@800000 {
125 label = "uImage";
126 reg = <0x00600000 0x00400000>;
127 read-only;
128 };
129
130 partition@1000000 {
131 label = "Root";
132 reg = <0x00a00000 0x3f600000>;
133 };
134 };
135 };
136};
1/*
2 * Device Tree file for Marvell Armada 395 GP board
3 *
4 * Copyright (C) 2016 Marvell
5 *
6 * Grzegorz Jaszczyk <jaz@semihalf.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without
15 * any warranty of any kind, whether express or implied.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41/dts-v1/;
42#include "armada-395.dtsi"
43
44/ {
45 model = "Marvell Armada 395 GP Board";
46 compatible = "marvell,a395-gp", "marvell,armada395",
47 "marvell,armada390";
48
49 chosen {
50 stdout-path = "serial0:115200n8";
51 };
52
53 memory {
54 device_type = "memory";
55 reg = <0x00000000 0x40000000>; /* 1 GB */
56 };
57
58 soc {
59 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
60 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
61
62 internal-regs {
63 i2c@11000 {
64 status = "okay";
65 clock-frequency = <100000>;
66
67 eeprom@57 {
68 compatible = "atmel,24c64";
69 reg = <0x57>;
70 };
71 };
72
73 serial@12000 {
74 /*
75 * Exported on the micro USB connector CON17
76 * through an FTDI
77 */
78 status = "okay";
79 };
80
81 /* CON1 */
82 usb@58000 {
83 status = "okay";
84 };
85
86 /* CON2 */
87 sata@a8000 {
88 status = "okay";
89 };
90
91 flash@d0000 {
92 status = "okay";
93 pinctrl-0 = <&nand_pins>;
94 pinctrl-names = "default";
95 num-cs = <1>;
96 marvell,nand-keep-config;
97 marvell,nand-enable-arbiter;
98 nand-on-flash-bbt;
99 nand-ecc-strength = <4>;
100 nand-ecc-step-size = <512>;
101
102 partitions {
103 compatible = "fixed-partitions";
104 #address-cells = <1>;
105 #size-cells = <1>;
106
107 partition@0 {
108 label = "U-Boot";
109 reg = <0x00000000 0x00600000>;
110 read-only;
111 };
112
113 partition@800000 {
114 label = "uImage";
115 reg = <0x00600000 0x00400000>;
116 read-only;
117 };
118
119 partition@1000000 {
120 label = "Root";
121 reg = <0x00a00000 0x3f600000>;
122 };
123 };
124 };
125
126 /* CON18 */
127 sdhci@d8000 {
128 clock-frequency = <200000000>;
129 broken-cd;
130 wp-inverted;
131 bus-width = <8>;
132 status = "okay";
133 no-1-8-v;
134 };
135
136 /* CON4 */
137 usb3@f0000 {
138 status = "okay";
139 };
140 };
141
142 pcie-controller {
143 status = "okay";
144
145 /*
146 * The two PCIe units are accessible through
147 * mini PCIe slot on the board.
148 */
149
150 /* CON7 */
151 pcie@2,0 {
152 /* Port 1, Lane 0 */
153 status = "okay";
154 };
155
156 /* CON8 */
157 pcie@4,0 {
158 /* Port 3, Lane 0 */
159 status = "okay";
160 };
161 };
162 };
163};