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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
4 *
5 * Copyright (C) 2015 Russell King
6 */
7
8/dts-v1/;
9#include "armada-388-clearfog.dtsi"
10
11/ {
12 model = "SolidRun Clearfog A1";
13 compatible = "solidrun,clearfog-a1", "marvell,armada388",
14 "marvell,armada385", "marvell,armada380";
15
16 soc {
17 internal-regs {
18 usb3@f0000 {
19 /* CON2, nearest CPU, USB2 only. */
20 status = "okay";
21 };
22 };
23
24 pcie {
25 pcie@3,0 {
26 /* Port 2, Lane 0. CON2, nearest CPU. */
27 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
28 status = "okay";
29 };
30 };
31 };
32
33 gpio-keys {
34 compatible = "gpio-keys";
35 pinctrl-0 = <&rear_button_pins>;
36 pinctrl-names = "default";
37
38 button-0 {
39 /* The rear SW3 button */
40 label = "Rear Button";
41 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
42 linux,can-disable;
43 linux,code = <BTN_0>;
44 };
45 };
46};
47
48ð1 {
49 /* ethernet@30000 */
50 fixed-link {
51 speed = <1000>;
52 full-duplex;
53 };
54};
55
56&expander0 {
57 /*
58 * PCA9655 GPIO expander:
59 * 0-CON3 CLKREQ#
60 * 1-CON3 PERST#
61 * 2-CON2 PERST#
62 * 3-CON3 W_DISABLE
63 * 4-CON2 CLKREQ#
64 * 5-USB3 overcurrent
65 * 6-USB3 power
66 * 7-CON2 W_DISABLE
67 * 8-JP4 P1
68 * 9-JP4 P4
69 * 10-JP4 P5
70 * 11-m.2 DEVSLP
71 * 12-SFP_LOS
72 * 13-SFP_TX_FAULT
73 * 14-SFP_TX_DISABLE
74 * 15-SFP_MOD_DEF0
75 */
76 pcie2-0-clkreq-hog {
77 gpio-hog;
78 gpios = <4 GPIO_ACTIVE_LOW>;
79 input;
80 line-name = "pcie2.0-clkreq";
81 };
82 pcie2-0-w-disable-hog {
83 gpio-hog;
84 gpios = <7 GPIO_ACTIVE_LOW>;
85 output-low;
86 line-name = "pcie2.0-w-disable";
87 };
88};
89
90&mdio {
91 status = "okay";
92
93 switch@4 {
94 compatible = "marvell,mv88e6085";
95 #address-cells = <1>;
96 #size-cells = <0>;
97 reg = <4>;
98 pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
99 pinctrl-names = "default";
100
101 ports {
102 #address-cells = <1>;
103 #size-cells = <0>;
104
105 port@0 {
106 reg = <0>;
107 label = "lan5";
108 };
109
110 port@1 {
111 reg = <1>;
112 label = "lan4";
113 };
114
115 port@2 {
116 reg = <2>;
117 label = "lan3";
118 };
119
120 port@3 {
121 reg = <3>;
122 label = "lan2";
123 };
124
125 port@4 {
126 reg = <4>;
127 label = "lan1";
128 };
129
130 port@5 {
131 reg = <5>;
132 label = "cpu";
133 ethernet = <ð1>;
134 fixed-link {
135 speed = <1000>;
136 full-duplex;
137 };
138 };
139
140 port@6 {
141 /* 88E1512 external phy */
142 reg = <6>;
143 label = "lan6";
144 fixed-link {
145 speed = <1000>;
146 full-duplex;
147 };
148 };
149 };
150 };
151};
152
153&pinctrl {
154 clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
155 marvell,pins = "mpp46";
156 marvell,function = "ref";
157 };
158 clearfog_dsa0_pins: clearfog-dsa0-pins {
159 marvell,pins = "mpp23", "mpp41";
160 marvell,function = "gpio";
161 };
162 clearfog_spi1_cs_pins: spi1-cs-pins {
163 marvell,pins = "mpp55";
164 marvell,function = "spi1";
165 };
166 rear_button_pins: rear-button-pins {
167 marvell,pins = "mpp34";
168 marvell,function = "gpio";
169 };
170};
171
172&spi1 {
173 /*
174 * Add SPI CS pins for clearfog:
175 * CS0: W25Q32
176 * CS1:
177 * CS2: mikrobus
178 */
179 pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
180};
1/*
2 * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
3 *
4 * Copyright (C) 2015 Russell King
5 *
6 * This board is in development; the contents of this file work with
7 * the A1 rev 2.0 of the board, which does not represent final
8 * production board. Things will change, don't expect this file to
9 * remain compatible info the future.
10 *
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * version 2 as published by the Free Software Foundation.
19 *
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49/dts-v1/;
50#include "armada-388.dtsi"
51#include "armada-38x-solidrun-microsom.dtsi"
52
53/ {
54 model = "SolidRun Clearfog A1";
55 compatible = "solidrun,clearfog-a1", "marvell,armada388",
56 "marvell,armada385", "marvell,armada380";
57
58 aliases {
59 /* So that mvebu u-boot can update the MAC addresses */
60 ethernet1 = ð0;
61 ethernet2 = ð1;
62 ethernet3 = ð2;
63 };
64
65 chosen {
66 stdout-path = "serial0:115200n8";
67 };
68
69 reg_3p3v: regulator-3p3v {
70 compatible = "regulator-fixed";
71 regulator-name = "3P3V";
72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>;
74 regulator-always-on;
75 };
76
77 soc {
78 internal-regs {
79 ethernet@30000 {
80 phy-mode = "sgmii";
81 buffer-manager = <&bm>;
82 bm,pool-long = <2>;
83 bm,pool-short = <1>;
84 status = "okay";
85
86 fixed-link {
87 speed = <1000>;
88 full-duplex;
89 };
90 };
91
92 ethernet@34000 {
93 phy-mode = "sgmii";
94 buffer-manager = <&bm>;
95 bm,pool-long = <3>;
96 bm,pool-short = <1>;
97 status = "okay";
98
99 fixed-link {
100 speed = <1000>;
101 full-duplex;
102 };
103 };
104
105 i2c@11000 {
106 /* Is there anything on this? */
107 clock-frequency = <100000>;
108 pinctrl-0 = <&i2c0_pins>;
109 pinctrl-names = "default";
110 status = "okay";
111
112 /*
113 * PCA9655 GPIO expander, up to 1MHz clock.
114 * 0-CON3 CLKREQ#
115 * 1-CON3 PERST#
116 * 2-CON2 PERST#
117 * 3-CON3 W_DISABLE
118 * 4-CON2 CLKREQ#
119 * 5-USB3 overcurrent
120 * 6-USB3 power
121 * 7-CON2 W_DISABLE
122 * 8-JP4 P1
123 * 9-JP4 P4
124 * 10-JP4 P5
125 * 11-m.2 DEVSLP
126 * 12-SFP_LOS
127 * 13-SFP_TX_FAULT
128 * 14-SFP_TX_DISABLE
129 * 15-SFP_MOD_DEF0
130 */
131 expander0: gpio-expander@20 {
132 /*
133 * This is how it should be:
134 * compatible = "onnn,pca9655",
135 * "nxp,pca9555";
136 * but you can't do this because of
137 * the way I2C works.
138 */
139 compatible = "nxp,pca9555";
140 gpio-controller;
141 #gpio-cells = <2>;
142 reg = <0x20>;
143
144 pcie1_0_clkreq {
145 gpio-hog;
146 gpios = <0 GPIO_ACTIVE_LOW>;
147 input;
148 line-name = "pcie1.0-clkreq";
149 };
150 pcie1_0_w_disable {
151 gpio-hog;
152 gpios = <3 GPIO_ACTIVE_LOW>;
153 output-low;
154 line-name = "pcie1.0-w-disable";
155 };
156 pcie2_0_clkreq {
157 gpio-hog;
158 gpios = <4 GPIO_ACTIVE_LOW>;
159 input;
160 line-name = "pcie2.0-clkreq";
161 };
162 pcie2_0_w_disable {
163 gpio-hog;
164 gpios = <7 GPIO_ACTIVE_LOW>;
165 output-low;
166 line-name = "pcie2.0-w-disable";
167 };
168 usb3_ilimit {
169 gpio-hog;
170 gpios = <5 GPIO_ACTIVE_LOW>;
171 input;
172 line-name = "usb3-current-limit";
173 };
174 usb3_power {
175 gpio-hog;
176 gpios = <6 GPIO_ACTIVE_HIGH>;
177 output-high;
178 line-name = "usb3-power";
179 };
180 m2_devslp {
181 gpio-hog;
182 gpios = <11 GPIO_ACTIVE_HIGH>;
183 output-low;
184 line-name = "m.2 devslp";
185 };
186 sfp_los {
187 /* SFP loss of signal */
188 gpio-hog;
189 gpios = <12 GPIO_ACTIVE_HIGH>;
190 input;
191 line-name = "sfp-los";
192 };
193 sfp_tx_fault {
194 /* SFP laser fault */
195 gpio-hog;
196 gpios = <13 GPIO_ACTIVE_HIGH>;
197 input;
198 line-name = "sfp-tx-fault";
199 };
200 sfp_tx_disable {
201 /* SFP transmit disable */
202 gpio-hog;
203 gpios = <14 GPIO_ACTIVE_HIGH>;
204 output-low;
205 line-name = "sfp-tx-disable";
206 };
207 sfp_mod_def0 {
208 /* SFP module present */
209 gpio-hog;
210 gpios = <15 GPIO_ACTIVE_LOW>;
211 input;
212 line-name = "sfp-mod-def0";
213 };
214 };
215
216 /* The MCP3021 is 100kHz clock only */
217 mikrobus_adc: mcp3021@4c {
218 compatible = "microchip,mcp3021";
219 reg = <0x4c>;
220 };
221
222 /* Also something at 0x64 */
223 };
224
225 i2c@11100 {
226 /*
227 * Routed to SFP, mikrobus, and PCIe.
228 * SFP limits this to 100kHz, and requires
229 * an AT24C01A/02/04 with address pins tied
230 * low, which takes addresses 0x50 and 0x51.
231 * Mikrobus doesn't specify beyond an I2C
232 * bus being present.
233 * PCIe uses ARP to assign addresses, or
234 * 0x63-0x64.
235 */
236 clock-frequency = <100000>;
237 pinctrl-0 = <&clearfog_i2c1_pins>;
238 pinctrl-names = "default";
239 status = "okay";
240 };
241
242 pinctrl@18000 {
243 clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
244 marvell,pins = "mpp46";
245 marvell,function = "ref";
246 };
247 clearfog_dsa0_pins: clearfog-dsa0-pins {
248 marvell,pins = "mpp23", "mpp41";
249 marvell,function = "gpio";
250 };
251 clearfog_i2c1_pins: i2c1-pins {
252 /* SFP, PCIe, mSATA, mikrobus */
253 marvell,pins = "mpp26", "mpp27";
254 marvell,function = "i2c1";
255 };
256 clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
257 marvell,pins = "mpp20";
258 marvell,function = "gpio";
259 };
260 clearfog_sdhci_pins: clearfog-sdhci-pins {
261 marvell,pins = "mpp21", "mpp28",
262 "mpp37", "mpp38",
263 "mpp39", "mpp40";
264 marvell,function = "sd0";
265 };
266 clearfog_spi1_cs_pins: spi1-cs-pins {
267 marvell,pins = "mpp55";
268 marvell,function = "spi1";
269 };
270 mikro_pins: mikro-pins {
271 /* int: mpp22 rst: mpp29 */
272 marvell,pins = "mpp22", "mpp29";
273 marvell,function = "gpio";
274 };
275 mikro_spi_pins: mikro-spi-pins {
276 marvell,pins = "mpp43";
277 marvell,function = "spi1";
278 };
279 mikro_uart_pins: mikro-uart-pins {
280 marvell,pins = "mpp24", "mpp25";
281 marvell,function = "ua1";
282 };
283 rear_button_pins: rear-button-pins {
284 marvell,pins = "mpp34";
285 marvell,function = "gpio";
286 };
287 };
288
289 sata@a8000 {
290 /* pinctrl? */
291 status = "okay";
292 };
293
294 sata@e0000 {
295 /* pinctrl? */
296 status = "okay";
297 };
298
299 sdhci@d8000 {
300 bus-width = <4>;
301 cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
302 no-1-8-v;
303 pinctrl-0 = <&clearfog_sdhci_pins
304 &clearfog_sdhci_cd_pins>;
305 pinctrl-names = "default";
306 status = "okay";
307 vmmc = <®_3p3v>;
308 wp-inverted;
309 };
310
311 serial@12100 {
312 /* mikrobus uart */
313 pinctrl-0 = <&mikro_uart_pins>;
314 pinctrl-names = "default";
315 status = "okay";
316 };
317
318 usb@58000 {
319 /* CON3, nearest power. */
320 status = "okay";
321 };
322
323 usb3@f0000 {
324 /* CON2, nearest CPU, USB2 only. */
325 status = "okay";
326 };
327
328 usb3@f8000 {
329 /* CON7 */
330 status = "okay";
331 };
332 };
333
334 pcie-controller {
335 status = "okay";
336 /*
337 * The two PCIe units are accessible through
338 * the mini-PCIe connectors on the board.
339 */
340 pcie@2,0 {
341 /* Port 1, Lane 0. CON3, nearest power. */
342 reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
343 status = "okay";
344 };
345 pcie@3,0 {
346 /* Port 2, Lane 0. CON2, nearest CPU. */
347 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
348 status = "okay";
349 };
350 };
351 };
352
353 dsa@0 {
354 compatible = "marvell,dsa";
355 dsa,ethernet = <ð1>;
356 dsa,mii-bus = <&mdio>;
357 pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
358 pinctrl-names = "default";
359 #address-cells = <2>;
360 #size-cells = <0>;
361
362 switch@0 {
363 #address-cells = <1>;
364 #size-cells = <0>;
365 reg = <4 0>;
366
367 port@0 {
368 reg = <0>;
369 label = "lan5";
370 };
371
372 port@1 {
373 reg = <1>;
374 label = "lan4";
375 };
376
377 port@2 {
378 reg = <2>;
379 label = "lan3";
380 };
381
382 port@3 {
383 reg = <3>;
384 label = "lan2";
385 };
386
387 port@4 {
388 reg = <4>;
389 label = "lan1";
390 };
391
392 port@5 {
393 reg = <5>;
394 label = "cpu";
395 };
396
397 port@6 {
398 /* 88E1512 external phy */
399 reg = <6>;
400 label = "lan6";
401 fixed-link {
402 speed = <1000>;
403 full-duplex;
404 };
405 };
406 };
407 };
408
409 gpio-keys {
410 compatible = "gpio-keys";
411 pinctrl-0 = <&rear_button_pins>;
412 pinctrl-names = "default";
413
414 button_0 {
415 /* The rear SW3 button */
416 label = "Rear Button";
417 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
418 linux,can-disable;
419 linux,code = <BTN_0>;
420 };
421 };
422};
423
424&spi1 {
425 /*
426 * We don't seem to have the W25Q32 on the
427 * A1 Rev 2.0 boards, so disable SPI.
428 * CS0: W25Q32 (doesn't appear to be present)
429 * CS1:
430 * CS2: mikrobus
431 */
432 pinctrl-0 = <&spi1_pins
433 &clearfog_spi1_cs_pins
434 &mikro_spi_pins>;
435 pinctrl-names = "default";
436 status = "okay";
437
438 spi-flash@0 {
439 #address-cells = <1>;
440 #size-cells = <0>;
441 compatible = "w25q32", "jedec,spi-nor";
442 reg = <0>; /* Chip select 0 */
443 spi-max-frequency = <3000000>;
444 status = "disabled";
445 };
446};