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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada 375 family SoC
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 */
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/phy/phy.h>
14
15#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
16
17/ {
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 model = "Marvell Armada 375 family SoC";
22 compatible = "marvell,armada375";
23
24 aliases {
25 gpio0 = &gpio0;
26 gpio1 = &gpio1;
27 gpio2 = &gpio2;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 };
31
32 clocks {
33 /* 1 GHz fixed main PLL */
34 mainpll: mainpll {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <1000000000>;
38 };
39 /* 25 MHz reference crystal */
40 refclk: oscillator {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
44 };
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 enable-method = "marvell,armada-375-smp";
51
52 cpu0: cpu@0 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a9";
55 reg = <0>;
56 };
57 cpu1: cpu@1 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a9";
60 reg = <1>;
61 };
62 };
63
64 pmu {
65 compatible = "arm,cortex-a9-pmu";
66 interrupts-extended = <&mpic 3>;
67 };
68
69 soc {
70 compatible = "marvell,armada375-mbus", "simple-bus";
71 #address-cells = <2>;
72 #size-cells = <1>;
73 controller = <&mbusc>;
74 interrupt-parent = <&gic>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
77
78 bootrom {
79 compatible = "marvell,bootrom";
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
81 };
82
83 devbus_bootcs: devbus-bootcs {
84 compatible = "marvell,mvebu-devbus";
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
87 #address-cells = <1>;
88 #size-cells = <1>;
89 clocks = <&coreclk 0>;
90 status = "disabled";
91 };
92
93 devbus_cs0: devbus-cs0 {
94 compatible = "marvell,mvebu-devbus";
95 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
96 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
97 #address-cells = <1>;
98 #size-cells = <1>;
99 clocks = <&coreclk 0>;
100 status = "disabled";
101 };
102
103 devbus_cs1: devbus-cs1 {
104 compatible = "marvell,mvebu-devbus";
105 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
106 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
107 #address-cells = <1>;
108 #size-cells = <1>;
109 clocks = <&coreclk 0>;
110 status = "disabled";
111 };
112
113 devbus_cs2: devbus-cs2 {
114 compatible = "marvell,mvebu-devbus";
115 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
116 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
117 #address-cells = <1>;
118 #size-cells = <1>;
119 clocks = <&coreclk 0>;
120 status = "disabled";
121 };
122
123 devbus_cs3: devbus-cs3 {
124 compatible = "marvell,mvebu-devbus";
125 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
126 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
127 #address-cells = <1>;
128 #size-cells = <1>;
129 clocks = <&coreclk 0>;
130 status = "disabled";
131 };
132
133 internal-regs {
134 compatible = "simple-bus";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
138
139 L2: cache-controller@8000 {
140 compatible = "arm,pl310-cache";
141 reg = <0x8000 0x1000>;
142 cache-unified;
143 cache-level = <2>;
144 arm,double-linefill-incr = <0>;
145 arm,double-linefill-wrap = <0>;
146 arm,double-linefill = <0>;
147 prefetch-data = <1>;
148 };
149
150 scu: scu@c000 {
151 compatible = "arm,cortex-a9-scu";
152 reg = <0xc000 0x58>;
153 };
154
155 timer0: timer@c600 {
156 compatible = "arm,cortex-a9-twd-timer";
157 reg = <0xc600 0x20>;
158 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
159 clocks = <&coreclk 2>;
160 };
161
162 gic: interrupt-controller@d000 {
163 compatible = "arm,cortex-a9-gic";
164 #interrupt-cells = <3>;
165 #size-cells = <0>;
166 interrupt-controller;
167 reg = <0xd000 0x1000>,
168 <0xc100 0x100>;
169 };
170
171 mdio: mdio@c0054 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "marvell,orion-mdio";
175 reg = <0xc0054 0x4>;
176 clocks = <&gateclk 19>;
177 };
178
179 /* Network controller */
180 ethernet: ethernet@f0000 {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "marvell,armada-375-pp2";
184 reg = <0xf0000 0xa000>, /* Packet Processor regs */
185 <0xc0000 0x3060>, /* LMS regs */
186 <0xc4000 0x100>, /* eth0 regs */
187 <0xc5000 0x100>; /* eth1 regs */
188 clocks = <&gateclk 3>, <&gateclk 19>;
189 clock-names = "pp_clk", "gop_clk";
190 status = "disabled";
191
192 eth0: ethernet-port@0 {
193 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
194 reg = <0>;
195 port-id = <0>; /* For backward compatibility. */
196 status = "disabled";
197 };
198
199 eth1: ethernet-port@1 {
200 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
201 reg = <1>;
202 port-id = <1>; /* For backward compatibility. */
203 status = "disabled";
204 };
205 };
206
207 rtc: rtc@10300 {
208 compatible = "marvell,orion-rtc";
209 reg = <0x10300 0x20>;
210 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
211 };
212
213 spi0: spi@10600 {
214 compatible = "marvell,armada-375-spi",
215 "marvell,orion-spi";
216 reg = <0x10600 0x50>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 cell-index = <0>;
220 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&coreclk 0>;
222 status = "disabled";
223 };
224
225 spi1: spi@10680 {
226 compatible = "marvell,armada-375-spi",
227 "marvell,orion-spi";
228 reg = <0x10680 0x50>;
229 #address-cells = <1>;
230 #size-cells = <0>;
231 cell-index = <1>;
232 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&coreclk 0>;
234 status = "disabled";
235 };
236
237 i2c0: i2c@11000 {
238 compatible = "marvell,mv64xxx-i2c";
239 reg = <0x11000 0x20>;
240 #address-cells = <1>;
241 #size-cells = <0>;
242 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&coreclk 0>;
244 status = "disabled";
245 };
246
247 i2c1: i2c@11100 {
248 compatible = "marvell,mv64xxx-i2c";
249 reg = <0x11100 0x20>;
250 #address-cells = <1>;
251 #size-cells = <0>;
252 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&coreclk 0>;
254 status = "disabled";
255 };
256
257 uart0: serial@12000 {
258 compatible = "snps,dw-apb-uart";
259 reg = <0x12000 0x100>;
260 reg-shift = <2>;
261 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
262 reg-io-width = <1>;
263 clocks = <&coreclk 0>;
264 status = "disabled";
265 };
266
267 uart1: serial@12100 {
268 compatible = "snps,dw-apb-uart";
269 reg = <0x12100 0x100>;
270 reg-shift = <2>;
271 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
272 reg-io-width = <1>;
273 clocks = <&coreclk 0>;
274 status = "disabled";
275 };
276
277 pinctrl: pinctrl@18000 {
278 compatible = "marvell,mv88f6720-pinctrl";
279 reg = <0x18000 0x24>;
280
281 i2c0_pins: i2c0-pins {
282 marvell,pins = "mpp14", "mpp15";
283 marvell,function = "i2c0";
284 };
285
286 i2c1_pins: i2c1-pins {
287 marvell,pins = "mpp61", "mpp62";
288 marvell,function = "i2c1";
289 };
290
291 nand_pins: nand-pins {
292 marvell,pins = "mpp0", "mpp1", "mpp2",
293 "mpp3", "mpp4", "mpp5",
294 "mpp6", "mpp7", "mpp8",
295 "mpp9", "mpp10", "mpp11",
296 "mpp12", "mpp13";
297 marvell,function = "nand";
298 };
299
300 sdio_pins: sdio-pins {
301 marvell,pins = "mpp24", "mpp25", "mpp26",
302 "mpp27", "mpp28", "mpp29";
303 marvell,function = "sd";
304 };
305
306 spi0_pins: spi0-pins {
307 marvell,pins = "mpp0", "mpp1", "mpp4",
308 "mpp5", "mpp8", "mpp9";
309 marvell,function = "spi0";
310 };
311 };
312
313 gpio0: gpio@18100 {
314 compatible = "marvell,orion-gpio";
315 reg = <0x18100 0x40>;
316 ngpios = <32>;
317 gpio-controller;
318 #gpio-cells = <2>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
325 };
326
327 gpio1: gpio@18140 {
328 compatible = "marvell,orion-gpio";
329 reg = <0x18140 0x40>;
330 ngpios = <32>;
331 gpio-controller;
332 #gpio-cells = <2>;
333 interrupt-controller;
334 #interrupt-cells = <2>;
335 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
339 };
340
341 gpio2: gpio@18180 {
342 compatible = "marvell,orion-gpio";
343 reg = <0x18180 0x40>;
344 ngpios = <3>;
345 gpio-controller;
346 #gpio-cells = <2>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
349 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
350 };
351
352 systemc: system-controller@18200 {
353 compatible = "marvell,armada-375-system-controller";
354 reg = <0x18200 0x100>;
355 };
356
357 gateclk: clock-gating-control@18220 {
358 compatible = "marvell,armada-375-gating-clock";
359 reg = <0x18220 0x4>;
360 clocks = <&coreclk 0>;
361 #clock-cells = <1>;
362 };
363
364 usbcluster: usb-cluster@18400 {
365 compatible = "marvell,armada-375-usb-cluster";
366 reg = <0x18400 0x4>;
367 #phy-cells = <1>;
368 };
369
370 mbusc: mbus-controller@20000 {
371 compatible = "marvell,mbus-controller";
372 reg = <0x20000 0x100>, <0x20180 0x20>;
373 };
374
375 mpic: interrupt-controller@20a00 {
376 compatible = "marvell,mpic";
377 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
378 #interrupt-cells = <1>;
379 #size-cells = <1>;
380 interrupt-controller;
381 msi-controller;
382 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
383 };
384
385 timer1: timer@20300 {
386 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
387 reg = <0x20300 0x30>, <0x21040 0x30>;
388 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
389 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
390 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
391 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
392 <&mpic 5>,
393 <&mpic 6>;
394 clocks = <&coreclk 0>, <&refclk>;
395 clock-names = "nbclk", "fixed";
396 };
397
398 watchdog: watchdog@20300 {
399 compatible = "marvell,armada-375-wdt";
400 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
401 clocks = <&coreclk 0>, <&refclk>;
402 clock-names = "nbclk", "fixed";
403 };
404
405 cpurst: cpurst@20800 {
406 compatible = "marvell,armada-370-cpu-reset";
407 reg = <0x20800 0x10>;
408 };
409
410 coherencyfab: coherency-fabric@21010 {
411 compatible = "marvell,armada-375-coherency-fabric";
412 reg = <0x21010 0x1c>;
413 };
414
415 usb0: usb@50000 {
416 compatible = "marvell,orion-ehci";
417 reg = <0x50000 0x500>;
418 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&gateclk 18>;
420 phys = <&usbcluster PHY_TYPE_USB2>;
421 phy-names = "usb";
422 status = "disabled";
423 };
424
425 usb1: usb@54000 {
426 compatible = "marvell,orion-ehci";
427 reg = <0x54000 0x500>;
428 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&gateclk 26>;
430 status = "disabled";
431 };
432
433 usb2: usb@58000 {
434 compatible = "marvell,armada-375-xhci";
435 reg = <0x58000 0x20000>,<0x5b880 0x80>;
436 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&gateclk 16>;
438 phys = <&usbcluster PHY_TYPE_USB3>;
439 phy-names = "usb";
440 status = "disabled";
441 };
442
443 xor0: xor@60800 {
444 compatible = "marvell,orion-xor";
445 reg = <0x60800 0x100
446 0x60A00 0x100>;
447 clocks = <&gateclk 22>;
448 status = "okay";
449
450 xor00 {
451 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
452 dmacap,memcpy;
453 dmacap,xor;
454 };
455 xor01 {
456 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
457 dmacap,memcpy;
458 dmacap,xor;
459 dmacap,memset;
460 };
461 };
462
463 xor1: xor@60900 {
464 compatible = "marvell,orion-xor";
465 reg = <0x60900 0x100
466 0x60b00 0x100>;
467 clocks = <&gateclk 23>;
468 status = "okay";
469
470 xor10 {
471 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
472 dmacap,memcpy;
473 dmacap,xor;
474 };
475 xor11 {
476 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
477 dmacap,memcpy;
478 dmacap,xor;
479 dmacap,memset;
480 };
481 };
482
483 cesa: crypto@90000 {
484 compatible = "marvell,armada-375-crypto";
485 reg = <0x90000 0x10000>;
486 reg-names = "regs";
487 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&gateclk 30>, <&gateclk 31>,
490 <&gateclk 28>, <&gateclk 29>;
491 clock-names = "cesa0", "cesa1",
492 "cesaz0", "cesaz1";
493 marvell,crypto-srams = <&crypto_sram0>,
494 <&crypto_sram1>;
495 marvell,crypto-sram-size = <0x800>;
496 };
497
498 sata: sata@a0000 {
499 compatible = "marvell,armada-370-sata";
500 reg = <0xa0000 0x5000>;
501 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&gateclk 14>, <&gateclk 20>;
503 clock-names = "0", "1";
504 status = "disabled";
505 };
506
507 nand_controller: nand-controller@d0000 {
508 compatible = "marvell,armada370-nand-controller";
509 reg = <0xd0000 0x54>;
510 #address-cells = <1>;
511 #size-cells = <0>;
512 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&gateclk 11>;
514 status = "disabled";
515 };
516
517 sdio: mvsdio@d4000 {
518 compatible = "marvell,orion-sdio";
519 reg = <0xd4000 0x200>;
520 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&gateclk 17>;
522 bus-width = <4>;
523 cap-sdio-irq;
524 cap-sd-highspeed;
525 cap-mmc-highspeed;
526 status = "disabled";
527 };
528
529 thermal: thermal@e8078 {
530 compatible = "marvell,armada375-thermal";
531 reg = <0xe8078 0x4>, <0xe807c 0x8>;
532 status = "okay";
533 };
534
535 coreclk: mvebu-sar@e8204 {
536 compatible = "marvell,armada-375-core-clock";
537 reg = <0xe8204 0x04>;
538 #clock-cells = <1>;
539 };
540
541 coredivclk: corediv-clock@e8250 {
542 compatible = "marvell,armada-375-corediv-clock";
543 reg = <0xe8250 0xc>;
544 #clock-cells = <1>;
545 clocks = <&mainpll>;
546 clock-output-names = "nand";
547 };
548 };
549
550 pciec: pcie@82000000 {
551 compatible = "marvell,armada-370-pcie";
552 status = "disabled";
553 device_type = "pci";
554
555 #address-cells = <3>;
556 #size-cells = <2>;
557
558 msi-parent = <&mpic>;
559 bus-range = <0x00 0xff>;
560
561 ranges =
562 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
563 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
564 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
565 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
566 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
567 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
568
569 pcie0: pcie@1,0 {
570 device_type = "pci";
571 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
572 reg = <0x0800 0 0 0 0>;
573 #address-cells = <3>;
574 #size-cells = <2>;
575 interrupt-names = "intx";
576 interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
577 #interrupt-cells = <1>;
578 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
579 0x81000000 0 0 0x81000000 0x1 0 1 0>;
580 bus-range = <0x00 0xff>;
581 interrupt-map-mask = <0 0 0 7>;
582 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
583 <0 0 0 2 &pcie0_intc 1>,
584 <0 0 0 3 &pcie0_intc 2>,
585 <0 0 0 4 &pcie0_intc 3>;
586 marvell,pcie-port = <0>;
587 marvell,pcie-lane = <0>;
588 clocks = <&gateclk 5>;
589 status = "disabled";
590
591 pcie0_intc: interrupt-controller {
592 interrupt-controller;
593 #interrupt-cells = <1>;
594 };
595 };
596
597 pcie1: pcie@2,0 {
598 device_type = "pci";
599 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
600 reg = <0x1000 0 0 0 0>;
601 #address-cells = <3>;
602 #size-cells = <2>;
603 interrupt-names = "intx";
604 interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
605 #interrupt-cells = <1>;
606 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
607 0x81000000 0 0 0x81000000 0x2 0 1 0>;
608 bus-range = <0x00 0xff>;
609 interrupt-map-mask = <0 0 0 7>;
610 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
611 <0 0 0 2 &pcie1_intc 1>,
612 <0 0 0 3 &pcie1_intc 2>,
613 <0 0 0 4 &pcie1_intc 3>;
614 marvell,pcie-port = <0>;
615 marvell,pcie-lane = <1>;
616 clocks = <&gateclk 6>;
617 status = "disabled";
618
619 pcie1_intc: interrupt-controller {
620 interrupt-controller;
621 #interrupt-cells = <1>;
622 };
623 };
624
625 };
626
627 crypto_sram0: sa-sram0 {
628 compatible = "mmio-sram";
629 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
630 clocks = <&gateclk 30>;
631 #address-cells = <1>;
632 #size-cells = <1>;
633 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
634 };
635
636 crypto_sram1: sa-sram1 {
637 compatible = "mmio-sram";
638 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
639 clocks = <&gateclk 31>;
640 #address-cells = <1>;
641 #size-cells = <1>;
642 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
643 };
644 };
645};
1/*
2 * Device Tree Include file for Marvell Armada 375 family SoC
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
18 *
19 * This file is distributed in the hope that it will be useful
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * Or, alternatively
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include <dt-bindings/interrupt-controller/arm-gic.h>
49#include <dt-bindings/interrupt-controller/irq.h>
50#include <dt-bindings/phy/phy.h>
51
52#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
53
54/ {
55 #address-cells = <1>;
56 #size-cells = <1>;
57
58 model = "Marvell Armada 375 family SoC";
59 compatible = "marvell,armada375";
60
61 aliases {
62 gpio0 = &gpio0;
63 gpio1 = &gpio1;
64 gpio2 = &gpio2;
65 serial0 = &uart0;
66 serial1 = &uart1;
67 };
68
69 clocks {
70 /* 1 GHz fixed main PLL */
71 mainpll: mainpll {
72 compatible = "fixed-clock";
73 #clock-cells = <0>;
74 clock-frequency = <1000000000>;
75 };
76 /* 25 MHz reference crystal */
77 refclk: oscillator {
78 compatible = "fixed-clock";
79 #clock-cells = <0>;
80 clock-frequency = <25000000>;
81 };
82 };
83
84 cpus {
85 #address-cells = <1>;
86 #size-cells = <0>;
87 enable-method = "marvell,armada-375-smp";
88
89 cpu0: cpu@0 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a9";
92 reg = <0>;
93 };
94 cpu1: cpu@1 {
95 device_type = "cpu";
96 compatible = "arm,cortex-a9";
97 reg = <1>;
98 };
99 };
100
101 pmu {
102 compatible = "arm,cortex-a9-pmu";
103 interrupts-extended = <&mpic 3>;
104 };
105
106 soc {
107 compatible = "marvell,armada375-mbus", "simple-bus";
108 #address-cells = <2>;
109 #size-cells = <1>;
110 controller = <&mbusc>;
111 interrupt-parent = <&gic>;
112 pcie-mem-aperture = <0xe0000000 0x8000000>;
113 pcie-io-aperture = <0xe8000000 0x100000>;
114
115 bootrom {
116 compatible = "marvell,bootrom";
117 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
118 };
119
120 devbus_bootcs: devbus-bootcs {
121 compatible = "marvell,mvebu-devbus";
122 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
123 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
124 #address-cells = <1>;
125 #size-cells = <1>;
126 clocks = <&coreclk 0>;
127 status = "disabled";
128 };
129
130 devbus_cs0: devbus-cs0 {
131 compatible = "marvell,mvebu-devbus";
132 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
133 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
134 #address-cells = <1>;
135 #size-cells = <1>;
136 clocks = <&coreclk 0>;
137 status = "disabled";
138 };
139
140 devbus_cs1: devbus-cs1 {
141 compatible = "marvell,mvebu-devbus";
142 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
143 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
144 #address-cells = <1>;
145 #size-cells = <1>;
146 clocks = <&coreclk 0>;
147 status = "disabled";
148 };
149
150 devbus_cs2: devbus-cs2 {
151 compatible = "marvell,mvebu-devbus";
152 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
153 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
154 #address-cells = <1>;
155 #size-cells = <1>;
156 clocks = <&coreclk 0>;
157 status = "disabled";
158 };
159
160 devbus_cs3: devbus-cs3 {
161 compatible = "marvell,mvebu-devbus";
162 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
163 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
164 #address-cells = <1>;
165 #size-cells = <1>;
166 clocks = <&coreclk 0>;
167 status = "disabled";
168 };
169
170 internal-regs {
171 compatible = "simple-bus";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
175
176 L2: cache-controller@8000 {
177 compatible = "arm,pl310-cache";
178 reg = <0x8000 0x1000>;
179 cache-unified;
180 cache-level = <2>;
181 arm,double-linefill-incr = <1>;
182 arm,double-linefill-wrap = <0>;
183 arm,double-linefill = <1>;
184 prefetch-data = <1>;
185 };
186
187 scu: scu@c000 {
188 compatible = "arm,cortex-a9-scu";
189 reg = <0xc000 0x58>;
190 };
191
192 timer0: timer@c600 {
193 compatible = "arm,cortex-a9-twd-timer";
194 reg = <0xc600 0x20>;
195 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
196 clocks = <&coreclk 2>;
197 };
198
199 gic: interrupt-controller@d000 {
200 compatible = "arm,cortex-a9-gic";
201 #interrupt-cells = <3>;
202 #size-cells = <0>;
203 interrupt-controller;
204 reg = <0xd000 0x1000>,
205 <0xc100 0x100>;
206 };
207
208 mdio: mdio@c0054 {
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "marvell,orion-mdio";
212 reg = <0xc0054 0x4>;
213 clocks = <&gateclk 19>;
214 };
215
216 /* Network controller */
217 ethernet: ethernet@f0000 {
218 compatible = "marvell,armada-375-pp2";
219 reg = <0xf0000 0xa000>, /* Packet Processor regs */
220 <0xc0000 0x3060>, /* LMS regs */
221 <0xc4000 0x100>, /* eth0 regs */
222 <0xc5000 0x100>; /* eth1 regs */
223 clocks = <&gateclk 3>, <&gateclk 19>;
224 clock-names = "pp_clk", "gop_clk";
225 status = "disabled";
226
227 eth0: eth0 {
228 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
229 port-id = <0>;
230 status = "disabled";
231 };
232
233 eth1: eth1 {
234 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
235 port-id = <1>;
236 status = "disabled";
237 };
238 };
239
240 rtc: rtc@10300 {
241 compatible = "marvell,orion-rtc";
242 reg = <0x10300 0x20>;
243 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
244 };
245
246 spi0: spi@10600 {
247 compatible = "marvell,armada-375-spi",
248 "marvell,orion-spi";
249 reg = <0x10600 0x50>;
250 #address-cells = <1>;
251 #size-cells = <0>;
252 cell-index = <0>;
253 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&coreclk 0>;
255 status = "disabled";
256 };
257
258 spi1: spi@10680 {
259 compatible = "marvell,armada-375-spi",
260 "marvell,orion-spi";
261 reg = <0x10680 0x50>;
262 #address-cells = <1>;
263 #size-cells = <0>;
264 cell-index = <1>;
265 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&coreclk 0>;
267 status = "disabled";
268 };
269
270 i2c0: i2c@11000 {
271 compatible = "marvell,mv64xxx-i2c";
272 reg = <0x11000 0x20>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
276 timeout-ms = <1000>;
277 clocks = <&coreclk 0>;
278 status = "disabled";
279 };
280
281 i2c1: i2c@11100 {
282 compatible = "marvell,mv64xxx-i2c";
283 reg = <0x11100 0x20>;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
287 timeout-ms = <1000>;
288 clocks = <&coreclk 0>;
289 status = "disabled";
290 };
291
292 uart0: serial@12000 {
293 compatible = "snps,dw-apb-uart";
294 reg = <0x12000 0x100>;
295 reg-shift = <2>;
296 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
297 reg-io-width = <1>;
298 clocks = <&coreclk 0>;
299 status = "disabled";
300 };
301
302 uart1: serial@12100 {
303 compatible = "snps,dw-apb-uart";
304 reg = <0x12100 0x100>;
305 reg-shift = <2>;
306 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
307 reg-io-width = <1>;
308 clocks = <&coreclk 0>;
309 status = "disabled";
310 };
311
312 pinctrl: pinctrl@18000 {
313 compatible = "marvell,mv88f6720-pinctrl";
314 reg = <0x18000 0x24>;
315
316 i2c0_pins: i2c0-pins {
317 marvell,pins = "mpp14", "mpp15";
318 marvell,function = "i2c0";
319 };
320
321 i2c1_pins: i2c1-pins {
322 marvell,pins = "mpp61", "mpp62";
323 marvell,function = "i2c1";
324 };
325
326 nand_pins: nand-pins {
327 marvell,pins = "mpp0", "mpp1", "mpp2",
328 "mpp3", "mpp4", "mpp5",
329 "mpp6", "mpp7", "mpp8",
330 "mpp9", "mpp10", "mpp11",
331 "mpp12", "mpp13";
332 marvell,function = "nand";
333 };
334
335 sdio_pins: sdio-pins {
336 marvell,pins = "mpp24", "mpp25", "mpp26",
337 "mpp27", "mpp28", "mpp29";
338 marvell,function = "sd";
339 };
340
341 spi0_pins: spi0-pins {
342 marvell,pins = "mpp0", "mpp1", "mpp4",
343 "mpp5", "mpp8", "mpp9";
344 marvell,function = "spi0";
345 };
346 };
347
348 gpio0: gpio@18100 {
349 compatible = "marvell,orion-gpio";
350 reg = <0x18100 0x40>;
351 ngpios = <32>;
352 gpio-controller;
353 #gpio-cells = <2>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
360 };
361
362 gpio1: gpio@18140 {
363 compatible = "marvell,orion-gpio";
364 reg = <0x18140 0x40>;
365 ngpios = <32>;
366 gpio-controller;
367 #gpio-cells = <2>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
370 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
374 };
375
376 gpio2: gpio@18180 {
377 compatible = "marvell,orion-gpio";
378 reg = <0x18180 0x40>;
379 ngpios = <3>;
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
385 };
386
387 systemc: system-controller@18200 {
388 compatible = "marvell,armada-375-system-controller";
389 reg = <0x18200 0x100>;
390 };
391
392 gateclk: clock-gating-control@18220 {
393 compatible = "marvell,armada-375-gating-clock";
394 reg = <0x18220 0x4>;
395 clocks = <&coreclk 0>;
396 #clock-cells = <1>;
397 };
398
399 usbcluster: usb-cluster@18400 {
400 compatible = "marvell,armada-375-usb-cluster";
401 reg = <0x18400 0x4>;
402 #phy-cells = <1>;
403 };
404
405 mbusc: mbus-controller@20000 {
406 compatible = "marvell,mbus-controller";
407 reg = <0x20000 0x100>, <0x20180 0x20>;
408 };
409
410 mpic: interrupt-controller@20a00 {
411 compatible = "marvell,mpic";
412 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
413 #interrupt-cells = <1>;
414 #size-cells = <1>;
415 interrupt-controller;
416 msi-controller;
417 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
418 };
419
420 timer1: timer@20300 {
421 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
422 reg = <0x20300 0x30>, <0x21040 0x30>;
423 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
424 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
425 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
426 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
427 <&mpic 5>,
428 <&mpic 6>;
429 clocks = <&coreclk 0>, <&refclk>;
430 clock-names = "nbclk", "fixed";
431 };
432
433 watchdog: watchdog@20300 {
434 compatible = "marvell,armada-375-wdt";
435 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
436 clocks = <&coreclk 0>, <&refclk>;
437 clock-names = "nbclk", "fixed";
438 };
439
440 cpurst: cpurst@20800 {
441 compatible = "marvell,armada-370-cpu-reset";
442 reg = <0x20800 0x10>;
443 };
444
445 coherencyfab: coherency-fabric@21010 {
446 compatible = "marvell,armada-375-coherency-fabric";
447 reg = <0x21010 0x1c>;
448 };
449
450 usb0: usb@50000 {
451 compatible = "marvell,orion-ehci";
452 reg = <0x50000 0x500>;
453 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&gateclk 18>;
455 phys = <&usbcluster PHY_TYPE_USB2>;
456 phy-names = "usb";
457 status = "disabled";
458 };
459
460 usb1: usb@54000 {
461 compatible = "marvell,orion-ehci";
462 reg = <0x54000 0x500>;
463 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&gateclk 26>;
465 status = "disabled";
466 };
467
468 usb2: usb3@58000 {
469 compatible = "marvell,armada-375-xhci";
470 reg = <0x58000 0x20000>,<0x5b880 0x80>;
471 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&gateclk 16>;
473 phys = <&usbcluster PHY_TYPE_USB3>;
474 phy-names = "usb";
475 status = "disabled";
476 };
477
478 xor0: xor@60800 {
479 compatible = "marvell,orion-xor";
480 reg = <0x60800 0x100
481 0x60A00 0x100>;
482 clocks = <&gateclk 22>;
483 status = "okay";
484
485 xor00 {
486 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
487 dmacap,memcpy;
488 dmacap,xor;
489 };
490 xor01 {
491 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
492 dmacap,memcpy;
493 dmacap,xor;
494 dmacap,memset;
495 };
496 };
497
498 xor1: xor@60900 {
499 compatible = "marvell,orion-xor";
500 reg = <0x60900 0x100
501 0x60b00 0x100>;
502 clocks = <&gateclk 23>;
503 status = "okay";
504
505 xor10 {
506 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
507 dmacap,memcpy;
508 dmacap,xor;
509 };
510 xor11 {
511 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
512 dmacap,memcpy;
513 dmacap,xor;
514 dmacap,memset;
515 };
516 };
517
518 cesa: crypto@90000 {
519 compatible = "marvell,armada-375-crypto";
520 reg = <0x90000 0x10000>;
521 reg-names = "regs";
522 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&gateclk 30>, <&gateclk 31>,
525 <&gateclk 28>, <&gateclk 29>;
526 clock-names = "cesa0", "cesa1",
527 "cesaz0", "cesaz1";
528 marvell,crypto-srams = <&crypto_sram0>,
529 <&crypto_sram1>;
530 marvell,crypto-sram-size = <0x800>;
531 };
532
533 sata: sata@a0000 {
534 compatible = "marvell,armada-370-sata";
535 reg = <0xa0000 0x5000>;
536 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&gateclk 14>, <&gateclk 20>;
538 clock-names = "0", "1";
539 status = "disabled";
540 };
541
542 nand: nand@d0000 {
543 compatible = "marvell,armada370-nand";
544 reg = <0xd0000 0x54>;
545 #address-cells = <1>;
546 #size-cells = <1>;
547 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&gateclk 11>;
549 status = "disabled";
550 };
551
552 sdio: mvsdio@d4000 {
553 compatible = "marvell,orion-sdio";
554 reg = <0xd4000 0x200>;
555 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&gateclk 17>;
557 bus-width = <4>;
558 cap-sdio-irq;
559 cap-sd-highspeed;
560 cap-mmc-highspeed;
561 status = "disabled";
562 };
563
564 thermal: thermal@e8078 {
565 compatible = "marvell,armada375-thermal";
566 reg = <0xe8078 0x4>, <0xe807c 0x8>;
567 status = "okay";
568 };
569
570 coreclk: mvebu-sar@e8204 {
571 compatible = "marvell,armada-375-core-clock";
572 reg = <0xe8204 0x04>;
573 #clock-cells = <1>;
574 };
575
576 coredivclk: corediv-clock@e8250 {
577 compatible = "marvell,armada-375-corediv-clock";
578 reg = <0xe8250 0xc>;
579 #clock-cells = <1>;
580 clocks = <&mainpll>;
581 clock-output-names = "nand";
582 };
583 };
584
585 pciec: pcie-controller@82000000 {
586 compatible = "marvell,armada-370-pcie";
587 status = "disabled";
588 device_type = "pci";
589
590 #address-cells = <3>;
591 #size-cells = <2>;
592
593 msi-parent = <&mpic>;
594 bus-range = <0x00 0xff>;
595
596 ranges =
597 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
598 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
599 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
600 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
601 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
602 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
603
604 pcie0: pcie@1,0 {
605 device_type = "pci";
606 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
607 reg = <0x0800 0 0 0 0>;
608 #address-cells = <3>;
609 #size-cells = <2>;
610 #interrupt-cells = <1>;
611 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
612 0x81000000 0 0 0x81000000 0x1 0 1 0>;
613 interrupt-map-mask = <0 0 0 0>;
614 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
615 marvell,pcie-port = <0>;
616 marvell,pcie-lane = <0>;
617 clocks = <&gateclk 5>;
618 status = "disabled";
619 };
620
621 pcie1: pcie@2,0 {
622 device_type = "pci";
623 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
624 reg = <0x1000 0 0 0 0>;
625 #address-cells = <3>;
626 #size-cells = <2>;
627 #interrupt-cells = <1>;
628 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
629 0x81000000 0 0 0x81000000 0x2 0 1 0>;
630 interrupt-map-mask = <0 0 0 0>;
631 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
632 marvell,pcie-port = <0>;
633 marvell,pcie-lane = <1>;
634 clocks = <&gateclk 6>;
635 status = "disabled";
636 };
637
638 };
639
640 crypto_sram0: sa-sram0 {
641 compatible = "mmio-sram";
642 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
643 clocks = <&gateclk 30>;
644 #address-cells = <1>;
645 #size-cells = <1>;
646 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
647 };
648
649 crypto_sram1: sa-sram1 {
650 compatible = "mmio-sram";
651 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
652 clocks = <&gateclk 31>;
653 #address-cells = <1>;
654 #size-cells = <1>;
655 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
656 };
657 };
658};