Loading...
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for Marvell Armada 370 Reference Design board
4 * (RD-88F6710-A1)
5 *
6 * Copied from arch/arm/boot/dts/armada-370-db.dts
7 *
8 * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
9 *
10 * Note: this Device Tree assumes that the bootloader has remapped the
11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
14 * boards were delivered with an older version of the bootloader that
15 * left internal registers mapped at 0xd0000000. If you are in this
16 * situation, you should either update your bootloader (preferred
17 * solution) or the below Device Tree should be adjusted.
18 */
19
20/dts-v1/;
21#include <dt-bindings/input/input.h>
22#include <dt-bindings/interrupt-controller/irq.h>
23#include <dt-bindings/gpio/gpio.h>
24#include "armada-370.dtsi"
25
26/ {
27 model = "Marvell Armada 370 Reference Design";
28 compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
29
30 chosen {
31 stdout-path = "serial0:115200n8";
32 };
33
34 memory@0 {
35 device_type = "memory";
36 reg = <0x00000000 0x20000000>; /* 512 MB */
37 };
38
39 soc {
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
43
44 internal-regs {
45 serial@12000 {
46 status = "okay";
47 };
48 sata@a0000 {
49 nr-ports = <2>;
50 status = "okay";
51 };
52
53 ethernet@70000 {
54 status = "okay";
55 phy = <&phy0>;
56 phy-mode = "sgmii";
57 };
58 ethernet@74000 {
59 pinctrl-0 = <&ge1_rgmii_pins>;
60 pinctrl-names = "default";
61 status = "okay";
62 phy-mode = "rgmii-id";
63 fixed-link {
64 speed = <1000>;
65 full-duplex;
66 };
67 };
68
69 mvsdio@d4000 {
70 pinctrl-0 = <&sdio_pins1>;
71 pinctrl-names = "default";
72 status = "okay";
73 /* No CD or WP GPIOs */
74 broken-cd;
75 };
76
77 usb@50000 {
78 status = "okay";
79 };
80
81 usb@51000 {
82 status = "okay";
83 };
84
85 gpio-keys {
86 compatible = "gpio-keys";
87 button {
88 label = "Software Button";
89 linux,code = <KEY_POWER>;
90 gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
91 };
92 };
93
94 gpio-fan {
95 compatible = "gpio-fan";
96 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
97 gpio-fan,speed-map = <0 0 3000 1>;
98 pinctrl-0 = <&fan_pins>;
99 pinctrl-names = "default";
100 };
101
102 gpio_leds {
103 compatible = "gpio-leds";
104 pinctrl-names = "default";
105 pinctrl-0 = <&led_pins>;
106
107 sw_led {
108 label = "370rd:green:sw";
109 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
110 default-state = "keep";
111 };
112 };
113 };
114 };
115};
116
117&pciec {
118 status = "okay";
119
120 /* Internal mini-PCIe connector */
121 pcie@1,0 {
122 /* Port 0, Lane 0 */
123 status = "okay";
124 };
125
126 /* Internal mini-PCIe connector */
127 pcie@2,0 {
128 /* Port 1, Lane 0 */
129 status = "okay";
130 };
131};
132
133&mdio {
134 pinctrl-0 = <&mdio_pins>;
135 pinctrl-names = "default";
136 phy0: ethernet-phy@0 {
137 reg = <0>;
138 };
139
140 switch: switch@10 {
141 compatible = "marvell,mv88e6085";
142 #address-cells = <1>;
143 #size-cells = <0>;
144 reg = <0x10>;
145 interrupt-controller;
146 #interrupt-cells = <2>;
147
148 ports {
149 #address-cells = <1>;
150 #size-cells = <0>;
151
152 port@0 {
153 reg = <0>;
154 label = "lan0";
155 };
156
157 port@1 {
158 reg = <1>;
159 label = "lan1";
160 };
161
162 port@2 {
163 reg = <2>;
164 label = "lan2";
165 };
166
167 port@3 {
168 reg = <3>;
169 label = "lan3";
170 };
171
172 port@5 {
173 reg = <5>;
174 label = "cpu";
175 ethernet = <ð1>;
176 fixed-link {
177 speed = <1000>;
178 full-duplex;
179 };
180 };
181 };
182
183 mdio {
184 #address-cells = <1>;
185 #size-cells = <0>;
186
187 switchphy0: switchphy@0 {
188 reg = <0>;
189 interrupt-parent = <&switch>;
190 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
191 };
192
193 switchphy1: switchphy@1 {
194 reg = <1>;
195 interrupt-parent = <&switch>;
196 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
197 };
198
199 switchphy2: switchphy@2 {
200 reg = <2>;
201 interrupt-parent = <&switch>;
202 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
203 };
204
205 switchphy3: switchphy@3 {
206 reg = <3>;
207 interrupt-parent = <&switch>;
208 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
209 };
210 };
211 };
212};
213
214
215&pinctrl {
216 fan_pins: fan-pins {
217 marvell,pins = "mpp8";
218 marvell,function = "gpio";
219 };
220
221 led_pins: led-pins {
222 marvell,pins = "mpp32";
223 marvell,function = "gpio";
224 };
225};
226
227&nand_controller {
228 status = "okay";
229
230 nand@0 {
231 reg = <0>;
232 label = "pxa3xx_nand-0";
233 nand-rb = <0>;
234 marvell,nand-keep-config;
235 nand-on-flash-bbt;
236
237 partitions {
238 compatible = "fixed-partitions";
239 #address-cells = <1>;
240 #size-cells = <1>;
241
242 partition@0 {
243 label = "U-Boot";
244 reg = <0 0x800000>;
245 };
246 partition@800000 {
247 label = "Linux";
248 reg = <0x800000 0x800000>;
249 };
250 partition@1000000 {
251 label = "Filesystem";
252 reg = <0x1000000 0x3f000000>;
253 };
254 };
255 };
256};
1/*
2 * Device Tree file for Marvell Armada 370 Reference Design board
3 * (RD-88F6710-A1)
4 *
5 * Copied from arch/arm/boot/dts/armada-370-db.dts
6 *
7 * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
18 *
19 * This file is distributed in the hope that it will be useful
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * Or, alternatively
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 *
47 * Note: this Device Tree assumes that the bootloader has remapped the
48 * internal registers to 0xf1000000 (instead of the default
49 * 0xd0000000). The 0xf1000000 is the default used by the recent,
50 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
51 * boards were delivered with an older version of the bootloader that
52 * left internal registers mapped at 0xd0000000. If you are in this
53 * situation, you should either update your bootloader (preferred
54 * solution) or the below Device Tree should be adjusted.
55 */
56
57/dts-v1/;
58#include <dt-bindings/input/input.h>
59#include <dt-bindings/gpio/gpio.h>
60#include "armada-370.dtsi"
61
62/ {
63 model = "Marvell Armada 370 Reference Design";
64 compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
65
66 chosen {
67 stdout-path = "serial0:115200n8";
68 };
69
70 memory@0 {
71 device_type = "memory";
72 reg = <0x00000000 0x20000000>; /* 512 MB */
73 };
74
75 soc {
76 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
77 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
78 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
79
80 internal-regs {
81 serial@12000 {
82 status = "okay";
83 };
84 sata@a0000 {
85 nr-ports = <2>;
86 status = "okay";
87 };
88
89 ethernet@70000 {
90 status = "okay";
91 phy = <&phy0>;
92 phy-mode = "sgmii";
93 };
94 ethernet@74000 {
95 pinctrl-0 = <&ge1_rgmii_pins>;
96 pinctrl-names = "default";
97 status = "okay";
98 phy-mode = "rgmii-id";
99 fixed-link {
100 speed = <1000>;
101 full-duplex;
102 };
103 };
104
105 mvsdio@d4000 {
106 pinctrl-0 = <&sdio_pins1>;
107 pinctrl-names = "default";
108 status = "okay";
109 /* No CD or WP GPIOs */
110 broken-cd;
111 };
112
113 usb@50000 {
114 status = "okay";
115 };
116
117 usb@51000 {
118 status = "okay";
119 };
120
121 gpio-keys {
122 compatible = "gpio-keys";
123 #address-cells = <1>;
124 #size-cells = <0>;
125 button {
126 label = "Software Button";
127 linux,code = <KEY_POWER>;
128 gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
129 };
130 };
131
132 gpio-fan {
133 compatible = "gpio-fan";
134 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
135 gpio-fan,speed-map = <0 0 3000 1>;
136 pinctrl-0 = <&fan_pins>;
137 pinctrl-names = "default";
138 };
139
140 gpio_leds {
141 compatible = "gpio-leds";
142 pinctrl-names = "default";
143 pinctrl-0 = <&led_pins>;
144
145 sw_led {
146 label = "370rd:green:sw";
147 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
148 default-state = "keep";
149 };
150 };
151
152 nand@d0000 {
153 status = "okay";
154 num-cs = <1>;
155 marvell,nand-keep-config;
156 marvell,nand-enable-arbiter;
157 nand-on-flash-bbt;
158
159 partition@0 {
160 label = "U-Boot";
161 reg = <0 0x800000>;
162 };
163 partition@800000 {
164 label = "Linux";
165 reg = <0x800000 0x800000>;
166 };
167 partition@1000000 {
168 label = "Filesystem";
169 reg = <0x1000000 0x3f000000>;
170 };
171 };
172 };
173 };
174
175 dsa {
176 compatible = "marvell,dsa";
177 #address-cells = <2>;
178 #size-cells = <0>;
179
180 dsa,ethernet = <ð1>;
181 dsa,mii-bus = <&mdio>;
182
183 switch@0 {
184 #address-cells = <1>;
185 #size-cells = <0>;
186 reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */
187
188 port@0 {
189 reg = <0>;
190 label = "lan0";
191 };
192
193 port@1 {
194 reg = <1>;
195 label = "lan1";
196 };
197
198 port@2 {
199 reg = <2>;
200 label = "lan2";
201 };
202
203 port@3 {
204 reg = <3>;
205 label = "lan3";
206 };
207
208 port@5 {
209 reg = <5>;
210 label = "cpu";
211 };
212 };
213 };
214};
215
216&pciec {
217 status = "okay";
218
219 /* Internal mini-PCIe connector */
220 pcie@1,0 {
221 /* Port 0, Lane 0 */
222 status = "okay";
223 };
224
225 /* Internal mini-PCIe connector */
226 pcie@2,0 {
227 /* Port 1, Lane 0 */
228 status = "okay";
229 };
230};
231
232&mdio {
233 pinctrl-0 = <&mdio_pins>;
234 pinctrl-names = "default";
235 phy0: ethernet-phy@0 {
236 reg = <0>;
237 };
238};
239
240
241&pinctrl {
242 fan_pins: fan-pins {
243 marvell,pins = "mpp8";
244 marvell,function = "gpio";
245 };
246
247 led_pins: led-pins {
248 marvell,pins = "mpp32";
249 marvell,function = "gpio";
250 };
251};