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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
4 */
5
6/*
7 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
8 */
9
10/include/ "skeleton_hs_idu.dtsi"
11
12/ {
13 compatible = "snps,arc";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 cpu_card {
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
23
24 input_clk: input-clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-frequency = <33333333>;
28 };
29
30 core_clk: core-clk@80 {
31 compatible = "snps,axs10x-arc-pll-clock";
32 reg = <0x80 0x10>, <0x100 0x10>;
33 #clock-cells = <0>;
34 clocks = <&input_clk>;
35
36 /*
37 * Set initial core pll output frequency to 100MHz.
38 * It will be applied at the core pll driver probing
39 * on early boot.
40 */
41 assigned-clocks = <&core_clk>;
42 assigned-clock-rates = <100000000>;
43 };
44
45 core_intc: archs-intc@cpu {
46 compatible = "snps,archs-intc";
47 interrupt-controller;
48 #interrupt-cells = <1>;
49 };
50
51 idu_intc: idu-interrupt-controller {
52 compatible = "snps,archs-idu-intc";
53 interrupt-controller;
54 interrupt-parent = <&core_intc>;
55 #interrupt-cells = <1>;
56 };
57
58 /*
59 * this GPIO block ORs all interrupts on CPU card (creg,..)
60 * to uplink only 1 IRQ to ARC core intc
61 */
62 dw-apb-gpio@2000 {
63 compatible = "snps,dw-apb-gpio";
64 reg = < 0x2000 0x80 >;
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 ictl_intc: gpio-controller@0 {
69 compatible = "snps,dw-apb-gpio-port";
70 gpio-controller;
71 #gpio-cells = <2>;
72 snps,nr-gpios = <30>;
73 reg = <0>;
74 interrupt-controller;
75 #interrupt-cells = <2>;
76 interrupt-parent = <&idu_intc>;
77 interrupts = <1>;
78 };
79 };
80
81 debug_uart: dw-apb-uart@5000 {
82 compatible = "snps,dw-apb-uart";
83 reg = <0x5000 0x100>;
84 clock-frequency = <33333000>;
85 interrupt-parent = <&ictl_intc>;
86 interrupts = <2 4>;
87 baud = <115200>;
88 reg-shift = <2>;
89 reg-io-width = <4>;
90 };
91
92 arcpct0: pct {
93 compatible = "snps,archs-pct";
94 #interrupt-cells = <1>;
95 interrupt-parent = <&core_intc>;
96 interrupts = <20>;
97 };
98 };
99
100 /*
101 * Mark DMA peripherals connected via IOC port as dma-coherent. We do
102 * it via overlay because peripherals defined in axs10x_mb.dtsi are
103 * used for both AXS101 and AXS103 boards and only AXS103 has IOC (so
104 * only AXS103 board has HW-coherent DMA peripherals)
105 * We don't need to mark pgu@17000 as dma-coherent because it uses
106 * external DMA buffer located outside of IOC aperture.
107 */
108 axs10x_mb {
109 ethernet@18000 {
110 dma-coherent;
111 };
112
113 usb@40000 {
114 dma-coherent;
115 };
116
117 usb@60000 {
118 dma-coherent;
119 };
120
121 mmc@15000 {
122 dma-coherent;
123 };
124 };
125
126 /*
127 * This INTC is actually connected to DW APB GPIO
128 * which acts as a wire between MB INTC and CPU INTC.
129 * GPIO INTC is configured in platform init code
130 * and here we mimic direct connection from MB INTC to
131 * CPU INTC, thus we set "interrupts = <0 1>" instead of
132 * "interrupts = <12>"
133 *
134 * This intc actually resides on MB, but we move it here to
135 * avoid duplicating the MB dtsi file given that IRQ from
136 * this intc to cpu intc are different for axs101 and axs103
137 */
138 mb_intc: interrupt-controller@e0012000 {
139 #interrupt-cells = <1>;
140 compatible = "snps,dw-apb-ictl";
141 reg = < 0x0 0xe0012000 0x0 0x200 >;
142 interrupt-controller;
143 interrupt-parent = <&idu_intc>;
144 interrupts = <0>;
145 };
146
147 memory {
148 device_type = "memory";
149 /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
150 reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
151 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
152 };
153
154 reserved-memory {
155 #address-cells = <2>;
156 #size-cells = <2>;
157 ranges;
158 /*
159 * Move frame buffer out of IOC aperture (0x8z-0xaz).
160 */
161 frame_buffer: frame_buffer@be000000 {
162 compatible = "shared-dma-pool";
163 reg = <0x0 0xbe000000 0x0 0x2000000>;
164 no-map;
165 };
166 };
167};
1/*
2 * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
11 */
12
13/include/ "skeleton_hs_idu.dtsi"
14
15/ {
16 compatible = "snps,arc";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpu_card {
21 compatible = "simple-bus";
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 ranges = <0x00000000 0xf0000000 0x10000000>;
26
27 core_clk: core_clk {
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
30 clock-frequency = <100000000>;
31 };
32
33 core_intc: archs-intc@cpu {
34 compatible = "snps,archs-intc";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 };
38
39 idu_intc: idu-interrupt-controller {
40 compatible = "snps,archs-idu-intc";
41 interrupt-controller;
42 interrupt-parent = <&core_intc>;
43
44 /*
45 * <hwirq distribution>
46 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
47 */
48 #interrupt-cells = <2>;
49
50 /*
51 * upstream irqs to core intc - downstream these are
52 * "COMMON" irq 0,1..
53 */
54 interrupts = <24 25>;
55 };
56
57 /*
58 * this GPIO block ORs all interrupts on CPU card (creg,..)
59 * to uplink only 1 IRQ to ARC core intc
60 */
61 dw-apb-gpio@0x2000 {
62 compatible = "snps,dw-apb-gpio";
63 reg = < 0x2000 0x80 >;
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 ictl_intc: gpio-controller@0 {
68 compatible = "snps,dw-apb-gpio-port";
69 gpio-controller;
70 #gpio-cells = <2>;
71 snps,nr-gpios = <30>;
72 reg = <0>;
73 interrupt-controller;
74 #interrupt-cells = <2>;
75 interrupt-parent = <&idu_intc>;
76
77 /*
78 * cmn irq 1 -> cpu irq 25
79 * Distribute to cpu0 only
80 */
81 interrupts = <1 1>;
82 };
83 };
84
85 debug_uart: dw-apb-uart@0x5000 {
86 compatible = "snps,dw-apb-uart";
87 reg = <0x5000 0x100>;
88 clock-frequency = <33333000>;
89 interrupt-parent = <&ictl_intc>;
90 interrupts = <2 4>;
91 baud = <115200>;
92 reg-shift = <2>;
93 reg-io-width = <4>;
94 };
95
96 arcpct0: pct {
97 compatible = "snps,archs-pct";
98 #interrupt-cells = <1>;
99 interrupt-parent = <&core_intc>;
100 interrupts = <20>;
101 };
102 };
103
104 /*
105 * This INTC is actually connected to DW APB GPIO
106 * which acts as a wire between MB INTC and CPU INTC.
107 * GPIO INTC is configured in platform init code
108 * and here we mimic direct connection from MB INTC to
109 * CPU INTC, thus we set "interrupts = <0 1>" instead of
110 * "interrupts = <12>"
111 *
112 * This intc actually resides on MB, but we move it here to
113 * avoid duplicating the MB dtsi file given that IRQ from
114 * this intc to cpu intc are different for axs101 and axs103
115 */
116 mb_intc: dw-apb-ictl@0xe0012000 {
117 #interrupt-cells = <1>;
118 compatible = "snps,dw-apb-ictl";
119 reg = < 0xe0012000 0x200 >;
120 interrupt-controller;
121 interrupt-parent = <&idu_intc>;
122 interrupts = <0 1>; /* cmn irq 0 -> cpu irq 24
123 distribute to cpu0 only */
124 };
125
126 memory {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 ranges = <0x00000000 0x80000000 0x40000000>;
130 device_type = "memory";
131 reg = <0x80000000 0x20000000>; /* 512MiB */
132 };
133
134 reserved-memory {
135 #address-cells = <1>;
136 #size-cells = <1>;
137 ranges;
138 /*
139 * Move frame buffer out of IOC aperture (0x8z-0xAz).
140 */
141 frame_buffer: frame_buffer@be000000 {
142 compatible = "shared-dma-pool";
143 reg = <0xbe000000 0x2000000>;
144 no-map;
145 };
146 };
147};