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1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#ifndef DEBUG_HTT_STATS_H
8#define DEBUG_HTT_STATS_H
9
10#define HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0)
11#define HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32)
12#define HTT_STATS_MAGIC_VALUE 0xF0F0F0F0
13
14enum htt_tlv_tag_t {
15 HTT_STATS_TX_PDEV_CMN_TAG = 0,
16 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1,
17 HTT_STATS_TX_PDEV_SIFS_TAG = 2,
18 HTT_STATS_TX_PDEV_FLUSH_TAG = 3,
19 HTT_STATS_TX_PDEV_PHY_ERR_TAG = 4,
20 HTT_STATS_STRING_TAG = 5,
21 HTT_STATS_TX_HWQ_CMN_TAG = 6,
22 HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG = 7,
23 HTT_STATS_TX_HWQ_CMD_RESULT_TAG = 8,
24 HTT_STATS_TX_HWQ_CMD_STALL_TAG = 9,
25 HTT_STATS_TX_HWQ_FES_STATUS_TAG = 10,
26 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11,
27 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12,
28 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13,
29 HTT_STATS_TX_TQM_CMN_TAG = 14,
30 HTT_STATS_TX_TQM_PDEV_TAG = 15,
31 HTT_STATS_TX_TQM_CMDQ_STATUS_TAG = 16,
32 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17,
33 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18,
34 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19,
35 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20,
36 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21,
37 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22,
38 HTT_STATS_TX_DE_CMN_TAG = 23,
39 HTT_STATS_RING_IF_TAG = 24,
40 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25,
41 HTT_STATS_SFM_CMN_TAG = 26,
42 HTT_STATS_SRING_STATS_TAG = 27,
43 HTT_STATS_RX_PDEV_FW_STATS_TAG = 28,
44 HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG = 29,
45 HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG = 30,
46 HTT_STATS_RX_SOC_FW_STATS_TAG = 31,
47 HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG = 32,
48 HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG = 33,
49 HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34,
50 HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35,
51 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36,
52 HTT_STATS_TX_SCHED_CMN_TAG = 37,
53 HTT_STATS_TX_PDEV_MUMIMO_MPDU_STATS_TAG = 38,
54 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39,
55 HTT_STATS_RING_IF_CMN_TAG = 40,
56 HTT_STATS_SFM_CLIENT_USER_TAG = 41,
57 HTT_STATS_SFM_CLIENT_TAG = 42,
58 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43,
59 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44,
60 HTT_STATS_SRING_CMN_TAG = 45,
61 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46,
62 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47,
63 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48,
64 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49,
65 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50,
66 HTT_STATS_TX_HWQ_MUMIMO_SCH_STATS_TAG = 51,
67 HTT_STATS_TX_HWQ_MUMIMO_MPDU_STATS_TAG = 52,
68 HTT_STATS_TX_HWQ_MUMIMO_CMN_STATS_TAG = 53,
69 HTT_STATS_HW_INTR_MISC_TAG = 54,
70 HTT_STATS_HW_WD_TIMEOUT_TAG = 55,
71 HTT_STATS_HW_PDEV_ERRS_TAG = 56,
72 HTT_STATS_COUNTER_NAME_TAG = 57,
73 HTT_STATS_TX_TID_DETAILS_TAG = 58,
74 HTT_STATS_RX_TID_DETAILS_TAG = 59,
75 HTT_STATS_PEER_STATS_CMN_TAG = 60,
76 HTT_STATS_PEER_DETAILS_TAG = 61,
77 HTT_STATS_PEER_TX_RATE_STATS_TAG = 62,
78 HTT_STATS_PEER_RX_RATE_STATS_TAG = 63,
79 HTT_STATS_PEER_MSDU_FLOWQ_TAG = 64,
80 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65,
81 HTT_STATS_WHAL_TX_TAG = 66,
82 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67,
83 HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_TAG = 68,
84 HTT_STATS_TX_TID_DETAILS_V1_TAG = 69,
85 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70,
86 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71,
87 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72,
88 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73,
89 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74,
90 HTT_STATS_PDEV_TWT_SESSIONS_TAG = 75,
91 HTT_STATS_PDEV_TWT_SESSION_TAG = 76,
92 HTT_STATS_RX_REFILL_RXDMA_ERR_TAG = 77,
93 HTT_STATS_RX_REFILL_REO_ERR_TAG = 78,
94 HTT_STATS_RX_REO_RESOURCE_STATS_TAG = 79,
95 HTT_STATS_TX_SOUNDING_STATS_TAG = 80,
96 HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG = 81,
97 HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG = 82,
98 HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG = 83,
99 HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG = 84,
100 HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG = 85,
101 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86,
102 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87,
103 HTT_STATS_PDEV_OBSS_PD_TAG = 88,
104 HTT_STATS_HW_WAR_TAG = 89,
105 HTT_STATS_RING_BACKPRESSURE_STATS_TAG = 90,
106 HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG = 101,
107 HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108,
108 HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG = 113,
109 HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG = 114,
110 HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG = 115,
111 HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG = 116,
112 HTT_STATS_PHY_COUNTERS_TAG = 121,
113 HTT_STATS_PHY_STATS_TAG = 122,
114
115 HTT_STATS_MAX_TAG,
116};
117
118#define HTT_STATS_MAX_STRING_SZ32 4
119#define HTT_STATS_MACID_INVALID 0xff
120#define HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 10
121#define HTT_TX_HWQ_MAX_CMD_RESULT_STATS 13
122#define HTT_TX_HWQ_MAX_CMD_STALL_STATS 5
123#define HTT_TX_HWQ_MAX_FES_RESULT_STATS 10
124
125enum htt_tx_pdev_underrun_enum {
126 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0,
127 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1,
128 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2,
129 HTT_TX_PDEV_MAX_URRN_STATS = 3,
130};
131
132#define HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 71
133#define HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9
134#define HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10
135#define HTT_TX_PDEV_MAX_PHY_ERR_STATS 18
136#define HTT_TX_PDEV_SCHED_TX_MODE_MAX 4
137#define HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20
138
139#define HTT_RX_STATS_REFILL_MAX_RING 4
140#define HTT_RX_STATS_RXDMA_MAX_ERR 16
141#define HTT_RX_STATS_FW_DROP_REASON_MAX 16
142
143/* Bytes stored in little endian order */
144/* Length should be multiple of DWORD */
145struct htt_stats_string_tlv {
146 u32 data[0]; /* Can be variable length */
147} __packed;
148
149#define HTT_STATS_MAC_ID GENMASK(7, 0)
150
151/* == TX PDEV STATS == */
152struct htt_tx_pdev_stats_cmn_tlv {
153 u32 mac_id__word;
154 u32 hw_queued;
155 u32 hw_reaped;
156 u32 underrun;
157 u32 hw_paused;
158 u32 hw_flush;
159 u32 hw_filt;
160 u32 tx_abort;
161 u32 mpdu_requeued;
162 u32 tx_xretry;
163 u32 data_rc;
164 u32 mpdu_dropped_xretry;
165 u32 illgl_rate_phy_err;
166 u32 cont_xretry;
167 u32 tx_timeout;
168 u32 pdev_resets;
169 u32 phy_underrun;
170 u32 txop_ovf;
171 u32 seq_posted;
172 u32 seq_failed_queueing;
173 u32 seq_completed;
174 u32 seq_restarted;
175 u32 mu_seq_posted;
176 u32 seq_switch_hw_paused;
177 u32 next_seq_posted_dsr;
178 u32 seq_posted_isr;
179 u32 seq_ctrl_cached;
180 u32 mpdu_count_tqm;
181 u32 msdu_count_tqm;
182 u32 mpdu_removed_tqm;
183 u32 msdu_removed_tqm;
184 u32 mpdus_sw_flush;
185 u32 mpdus_hw_filter;
186 u32 mpdus_truncated;
187 u32 mpdus_ack_failed;
188 u32 mpdus_expired;
189 u32 mpdus_seq_hw_retry;
190 u32 ack_tlv_proc;
191 u32 coex_abort_mpdu_cnt_valid;
192 u32 coex_abort_mpdu_cnt;
193 u32 num_total_ppdus_tried_ota;
194 u32 num_data_ppdus_tried_ota;
195 u32 local_ctrl_mgmt_enqued;
196 u32 local_ctrl_mgmt_freed;
197 u32 local_data_enqued;
198 u32 local_data_freed;
199 u32 mpdu_tried;
200 u32 isr_wait_seq_posted;
201
202 u32 tx_active_dur_us_low;
203 u32 tx_active_dur_us_high;
204};
205
206/* NOTE: Variable length TLV, use length spec to infer array size */
207struct htt_tx_pdev_stats_urrn_tlv_v {
208 u32 urrn_stats[0]; /* HTT_TX_PDEV_MAX_URRN_STATS */
209};
210
211/* NOTE: Variable length TLV, use length spec to infer array size */
212struct htt_tx_pdev_stats_flush_tlv_v {
213 u32 flush_errs[0]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */
214};
215
216/* NOTE: Variable length TLV, use length spec to infer array size */
217struct htt_tx_pdev_stats_sifs_tlv_v {
218 u32 sifs_status[0]; /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */
219};
220
221/* NOTE: Variable length TLV, use length spec to infer array size */
222struct htt_tx_pdev_stats_phy_err_tlv_v {
223 u32 phy_errs[0]; /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */
224};
225
226/* NOTE: Variable length TLV, use length spec to infer array size */
227struct htt_tx_pdev_stats_sifs_hist_tlv_v {
228 u32 sifs_hist_status[0]; /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */
229};
230
231struct htt_tx_pdev_stats_tx_ppdu_stats_tlv_v {
232 u32 num_data_ppdus_legacy_su;
233 u32 num_data_ppdus_ac_su;
234 u32 num_data_ppdus_ax_su;
235 u32 num_data_ppdus_ac_su_txbf;
236 u32 num_data_ppdus_ax_su_txbf;
237};
238
239/* NOTE: Variable length TLV, use length spec to infer array size .
240 *
241 * Tried_mpdu_cnt_hist is the histogram of MPDUs tries per HWQ.
242 * The tries here is the count of the MPDUS within a PPDU that the
243 * HW had attempted to transmit on air, for the HWSCH Schedule
244 * command submitted by FW.It is not the retry attempts.
245 * The histogram bins are 0-29, 30-59, 60-89 and so on. The are
246 * 10 bins in this histogram. They are defined in FW using the
247 * following macros
248 * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9
249 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30
250 */
251struct htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v {
252 u32 hist_bin_size;
253 u32 tried_mpdu_cnt_hist[]; /* HTT_TX_PDEV_TRIED_MPDU_CNT_HIST */
254};
255
256/* == SOC ERROR STATS == */
257
258/* =============== PDEV ERROR STATS ============== */
259#define HTT_STATS_MAX_HW_INTR_NAME_LEN 8
260struct htt_hw_stats_intr_misc_tlv {
261 /* Stored as little endian */
262 u8 hw_intr_name[HTT_STATS_MAX_HW_INTR_NAME_LEN];
263 u32 mask;
264 u32 count;
265};
266
267#define HTT_STATS_MAX_HW_MODULE_NAME_LEN 8
268struct htt_hw_stats_wd_timeout_tlv {
269 /* Stored as little endian */
270 u8 hw_module_name[HTT_STATS_MAX_HW_MODULE_NAME_LEN];
271 u32 count;
272};
273
274struct htt_hw_stats_pdev_errs_tlv {
275 u32 mac_id__word; /* BIT [ 7 : 0] : mac_id */
276 u32 tx_abort;
277 u32 tx_abort_fail_count;
278 u32 rx_abort;
279 u32 rx_abort_fail_count;
280 u32 warm_reset;
281 u32 cold_reset;
282 u32 tx_flush;
283 u32 tx_glb_reset;
284 u32 tx_txq_reset;
285 u32 rx_timeout_reset;
286};
287
288struct htt_hw_stats_whal_tx_tlv {
289 u32 mac_id__word;
290 u32 last_unpause_ppdu_id;
291 u32 hwsch_unpause_wait_tqm_write;
292 u32 hwsch_dummy_tlv_skipped;
293 u32 hwsch_misaligned_offset_received;
294 u32 hwsch_reset_count;
295 u32 hwsch_dev_reset_war;
296 u32 hwsch_delayed_pause;
297 u32 hwsch_long_delayed_pause;
298 u32 sch_rx_ppdu_no_response;
299 u32 sch_selfgen_response;
300 u32 sch_rx_sifs_resp_trigger;
301};
302
303/* ============ PEER STATS ============ */
304#define HTT_MSDU_FLOW_STATS_TX_FLOW_NO GENMASK(15, 0)
305#define HTT_MSDU_FLOW_STATS_TID_NUM GENMASK(19, 16)
306#define HTT_MSDU_FLOW_STATS_DROP_RULE BIT(20)
307
308struct htt_msdu_flow_stats_tlv {
309 u32 last_update_timestamp;
310 u32 last_add_timestamp;
311 u32 last_remove_timestamp;
312 u32 total_processed_msdu_count;
313 u32 cur_msdu_count_in_flowq;
314 u32 sw_peer_id;
315 u32 tx_flow_no__tid_num__drop_rule;
316 u32 last_cycle_enqueue_count;
317 u32 last_cycle_dequeue_count;
318 u32 last_cycle_drop_count;
319 u32 current_drop_th;
320};
321
322#define MAX_HTT_TID_NAME 8
323
324#define HTT_TX_TID_STATS_SW_PEER_ID GENMASK(15, 0)
325#define HTT_TX_TID_STATS_TID_NUM GENMASK(31, 16)
326#define HTT_TX_TID_STATS_NUM_SCHED_PENDING GENMASK(7, 0)
327#define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ GENMASK(15, 8)
328
329/* Tidq stats */
330struct htt_tx_tid_stats_tlv {
331 /* Stored as little endian */
332 u8 tid_name[MAX_HTT_TID_NAME];
333 u32 sw_peer_id__tid_num;
334 u32 num_sched_pending__num_ppdu_in_hwq;
335 u32 tid_flags;
336 u32 hw_queued;
337 u32 hw_reaped;
338 u32 mpdus_hw_filter;
339
340 u32 qdepth_bytes;
341 u32 qdepth_num_msdu;
342 u32 qdepth_num_mpdu;
343 u32 last_scheduled_tsmp;
344 u32 pause_module_id;
345 u32 block_module_id;
346 u32 tid_tx_airtime;
347};
348
349#define HTT_TX_TID_STATS_V1_SW_PEER_ID GENMASK(15, 0)
350#define HTT_TX_TID_STATS_V1_TID_NUM GENMASK(31, 16)
351#define HTT_TX_TID_STATS_V1_NUM_SCHED_PENDING GENMASK(7, 0)
352#define HTT_TX_TID_STATS_V1_NUM_PPDU_IN_HWQ GENMASK(15, 8)
353
354/* Tidq stats */
355struct htt_tx_tid_stats_v1_tlv {
356 /* Stored as little endian */
357 u8 tid_name[MAX_HTT_TID_NAME];
358 u32 sw_peer_id__tid_num;
359 u32 num_sched_pending__num_ppdu_in_hwq;
360 u32 tid_flags;
361 u32 max_qdepth_bytes;
362 u32 max_qdepth_n_msdus;
363 u32 rsvd;
364
365 u32 qdepth_bytes;
366 u32 qdepth_num_msdu;
367 u32 qdepth_num_mpdu;
368 u32 last_scheduled_tsmp;
369 u32 pause_module_id;
370 u32 block_module_id;
371 u32 tid_tx_airtime;
372 u32 allow_n_flags;
373 u32 sendn_frms_allowed;
374};
375
376#define HTT_RX_TID_STATS_SW_PEER_ID GENMASK(15, 0)
377#define HTT_RX_TID_STATS_TID_NUM GENMASK(31, 16)
378
379struct htt_rx_tid_stats_tlv {
380 u32 sw_peer_id__tid_num;
381 u8 tid_name[MAX_HTT_TID_NAME];
382 u32 dup_in_reorder;
383 u32 dup_past_outside_window;
384 u32 dup_past_within_window;
385 u32 rxdesc_err_decrypt;
386 u32 tid_rx_airtime;
387};
388
389#define HTT_MAX_COUNTER_NAME 8
390struct htt_counter_tlv {
391 u8 counter_name[HTT_MAX_COUNTER_NAME];
392 u32 count;
393};
394
395struct htt_peer_stats_cmn_tlv {
396 u32 ppdu_cnt;
397 u32 mpdu_cnt;
398 u32 msdu_cnt;
399 u32 pause_bitmap;
400 u32 block_bitmap;
401 u32 current_timestamp;
402 u32 peer_tx_airtime;
403 u32 peer_rx_airtime;
404 s32 rssi;
405 u32 peer_enqueued_count_low;
406 u32 peer_enqueued_count_high;
407 u32 peer_dequeued_count_low;
408 u32 peer_dequeued_count_high;
409 u32 peer_dropped_count_low;
410 u32 peer_dropped_count_high;
411 u32 ppdu_transmitted_bytes_low;
412 u32 ppdu_transmitted_bytes_high;
413 u32 peer_ttl_removed_count;
414 u32 inactive_time;
415};
416
417#define HTT_PEER_DETAILS_VDEV_ID GENMASK(7, 0)
418#define HTT_PEER_DETAILS_PDEV_ID GENMASK(15, 8)
419#define HTT_PEER_DETAILS_AST_IDX GENMASK(31, 16)
420
421struct htt_peer_details_tlv {
422 u32 peer_type;
423 u32 sw_peer_id;
424 u32 vdev_pdev_ast_idx;
425 struct htt_mac_addr mac_addr;
426 u32 peer_flags;
427 u32 qpeer_flags;
428};
429
430enum htt_stats_param_type {
431 HTT_STATS_PREAM_OFDM,
432 HTT_STATS_PREAM_CCK,
433 HTT_STATS_PREAM_HT,
434 HTT_STATS_PREAM_VHT,
435 HTT_STATS_PREAM_HE,
436 HTT_STATS_PREAM_RSVD,
437 HTT_STATS_PREAM_RSVD1,
438
439 HTT_STATS_PREAM_COUNT,
440};
441
442#define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12
443#define HTT_TX_PEER_STATS_NUM_GI_COUNTERS 4
444#define HTT_TX_PEER_STATS_NUM_DCM_COUNTERS 5
445#define HTT_TX_PEER_STATS_NUM_BW_COUNTERS 4
446#define HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS 8
447#define HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
448
449struct htt_tx_peer_rate_stats_tlv {
450 u32 tx_ldpc;
451 u32 rts_cnt;
452 u32 ack_rssi;
453
454 u32 tx_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
455 u32 tx_su_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
456 u32 tx_mu_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
457 /* element 0,1, ...7 -> NSS 1,2, ...8 */
458 u32 tx_nss[HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS];
459 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
460 u32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS];
461 u32 tx_stbc[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
462 u32 tx_pream[HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES];
463
464 /* Counters to track number of tx packets in each GI
465 * (400us, 800us, 1600us & 3200us) in each mcs (0-11)
466 */
467 u32 tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
468
469 /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */
470 u32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS];
471
472};
473
474#define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12
475#define HTT_RX_PEER_STATS_NUM_GI_COUNTERS 4
476#define HTT_RX_PEER_STATS_NUM_DCM_COUNTERS 5
477#define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4
478#define HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS 8
479#define HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
480
481struct htt_rx_peer_rate_stats_tlv {
482 u32 nsts;
483
484 /* Number of rx ldpc packets */
485 u32 rx_ldpc;
486 /* Number of rx rts packets */
487 u32 rts_cnt;
488
489 u32 rssi_mgmt; /* units = dB above noise floor */
490 u32 rssi_data; /* units = dB above noise floor */
491 u32 rssi_comb; /* units = dB above noise floor */
492 u32 rx_mcs[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS];
493 /* element 0,1, ...7 -> NSS 1,2, ...8 */
494 u32 rx_nss[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS];
495 u32 rx_dcm[HTT_RX_PEER_STATS_NUM_DCM_COUNTERS];
496 u32 rx_stbc[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS];
497 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
498 u32 rx_bw[HTT_RX_PEER_STATS_NUM_BW_COUNTERS];
499 u32 rx_pream[HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES];
500 /* units = dB above noise floor */
501 u8 rssi_chain[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]
502 [HTT_RX_PEER_STATS_NUM_BW_COUNTERS];
503
504 /* Counters to track number of rx packets in each GI in each mcs (0-11) */
505 u32 rx_gi[HTT_RX_PEER_STATS_NUM_GI_COUNTERS]
506 [HTT_RX_PEER_STATS_NUM_MCS_COUNTERS];
507};
508
509enum htt_peer_stats_req_mode {
510 HTT_PEER_STATS_REQ_MODE_NO_QUERY,
511 HTT_PEER_STATS_REQ_MODE_QUERY_TQM,
512 HTT_PEER_STATS_REQ_MODE_FLUSH_TQM,
513};
514
515enum htt_peer_stats_tlv_enum {
516 HTT_PEER_STATS_CMN_TLV = 0,
517 HTT_PEER_DETAILS_TLV = 1,
518 HTT_TX_PEER_RATE_STATS_TLV = 2,
519 HTT_RX_PEER_RATE_STATS_TLV = 3,
520 HTT_TX_TID_STATS_TLV = 4,
521 HTT_RX_TID_STATS_TLV = 5,
522 HTT_MSDU_FLOW_STATS_TLV = 6,
523
524 HTT_PEER_STATS_MAX_TLV = 31,
525};
526
527/* =========== MUMIMO HWQ stats =========== */
528/* MU MIMO stats per hwQ */
529struct htt_tx_hwq_mu_mimo_sch_stats_tlv {
530 u32 mu_mimo_sch_posted;
531 u32 mu_mimo_sch_failed;
532 u32 mu_mimo_ppdu_posted;
533};
534
535struct htt_tx_hwq_mu_mimo_mpdu_stats_tlv {
536 u32 mu_mimo_mpdus_queued_usr;
537 u32 mu_mimo_mpdus_tried_usr;
538 u32 mu_mimo_mpdus_failed_usr;
539 u32 mu_mimo_mpdus_requeued_usr;
540 u32 mu_mimo_err_no_ba_usr;
541 u32 mu_mimo_mpdu_underrun_usr;
542 u32 mu_mimo_ampdu_underrun_usr;
543};
544
545#define HTT_TX_HWQ_STATS_MAC_ID GENMASK(7, 0)
546#define HTT_TX_HWQ_STATS_HWQ_ID GENMASK(15, 8)
547
548struct htt_tx_hwq_mu_mimo_cmn_stats_tlv {
549 u32 mac_id__hwq_id__word;
550};
551
552/* == TX HWQ STATS == */
553struct htt_tx_hwq_stats_cmn_tlv {
554 u32 mac_id__hwq_id__word;
555
556 /* PPDU level stats */
557 u32 xretry;
558 u32 underrun_cnt;
559 u32 flush_cnt;
560 u32 filt_cnt;
561 u32 null_mpdu_bmap;
562 u32 user_ack_failure;
563 u32 ack_tlv_proc;
564 u32 sched_id_proc;
565 u32 null_mpdu_tx_count;
566 u32 mpdu_bmap_not_recvd;
567
568 /* Selfgen stats per hwQ */
569 u32 num_bar;
570 u32 rts;
571 u32 cts2self;
572 u32 qos_null;
573
574 /* MPDU level stats */
575 u32 mpdu_tried_cnt;
576 u32 mpdu_queued_cnt;
577 u32 mpdu_ack_fail_cnt;
578 u32 mpdu_filt_cnt;
579 u32 false_mpdu_ack_count;
580
581 u32 txq_timeout;
582};
583
584/* NOTE: Variable length TLV, use length spec to infer array size */
585struct htt_tx_hwq_difs_latency_stats_tlv_v {
586 u32 hist_intvl;
587 /* histogram of ppdu post to hwsch - > cmd status received */
588 u32 difs_latency_hist[]; /* HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS */
589};
590
591/* NOTE: Variable length TLV, use length spec to infer array size */
592struct htt_tx_hwq_cmd_result_stats_tlv_v {
593 /* Histogram of sched cmd result */
594 u32 cmd_result[0]; /* HTT_TX_HWQ_MAX_CMD_RESULT_STATS */
595};
596
597/* NOTE: Variable length TLV, use length spec to infer array size */
598struct htt_tx_hwq_cmd_stall_stats_tlv_v {
599 /* Histogram of various pause conitions */
600 u32 cmd_stall_status[0]; /* HTT_TX_HWQ_MAX_CMD_STALL_STATS */
601};
602
603/* NOTE: Variable length TLV, use length spec to infer array size */
604struct htt_tx_hwq_fes_result_stats_tlv_v {
605 /* Histogram of number of user fes result */
606 u32 fes_result[0]; /* HTT_TX_HWQ_MAX_FES_RESULT_STATS */
607};
608
609/* NOTE: Variable length TLV, use length spec to infer array size
610 *
611 * The hwq_tried_mpdu_cnt_hist is a histogram of MPDUs tries per HWQ.
612 * The tries here is the count of the MPDUS within a PPDU that the HW
613 * had attempted to transmit on air, for the HWSCH Schedule command
614 * submitted by FW in this HWQ .It is not the retry attempts. The
615 * histogram bins are 0-29, 30-59, 60-89 and so on. The are 10 bins
616 * in this histogram.
617 * they are defined in FW using the following macros
618 * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9
619 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30
620 */
621struct htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v {
622 u32 hist_bin_size;
623 /* Histogram of number of mpdus on tried mpdu */
624 u32 tried_mpdu_cnt_hist[]; /* HTT_TX_HWQ_TRIED_MPDU_CNT_HIST */
625};
626
627/* NOTE: Variable length TLV, use length spec to infer array size
628 *
629 * The txop_used_cnt_hist is the histogram of txop per burst. After
630 * completing the burst, we identify the txop used in the burst and
631 * incr the corresponding bin.
632 * Each bin represents 1ms & we have 10 bins in this histogram.
633 * they are defined in FW using the following macros
634 * #define WAL_MAX_TXOP_USED_CNT_HISTOGRAM 10
635 * #define WAL_TXOP_USED_HISTOGRAM_INTERVAL 1000 ( 1 ms )
636 */
637struct htt_tx_hwq_txop_used_cnt_hist_tlv_v {
638 /* Histogram of txop used cnt */
639 u32 txop_used_cnt_hist[0]; /* HTT_TX_HWQ_TXOP_USED_CNT_HIST */
640};
641
642/* == TX SELFGEN STATS == */
643struct htt_tx_selfgen_cmn_stats_tlv {
644 u32 mac_id__word;
645 u32 su_bar;
646 u32 rts;
647 u32 cts2self;
648 u32 qos_null;
649 u32 delayed_bar_1; /* MU user 1 */
650 u32 delayed_bar_2; /* MU user 2 */
651 u32 delayed_bar_3; /* MU user 3 */
652 u32 delayed_bar_4; /* MU user 4 */
653 u32 delayed_bar_5; /* MU user 5 */
654 u32 delayed_bar_6; /* MU user 6 */
655 u32 delayed_bar_7; /* MU user 7 */
656};
657
658struct htt_tx_selfgen_ac_stats_tlv {
659 /* 11AC */
660 u32 ac_su_ndpa;
661 u32 ac_su_ndp;
662 u32 ac_mu_mimo_ndpa;
663 u32 ac_mu_mimo_ndp;
664 u32 ac_mu_mimo_brpoll_1; /* MU user 1 */
665 u32 ac_mu_mimo_brpoll_2; /* MU user 2 */
666 u32 ac_mu_mimo_brpoll_3; /* MU user 3 */
667};
668
669struct htt_tx_selfgen_ax_stats_tlv {
670 /* 11AX */
671 u32 ax_su_ndpa;
672 u32 ax_su_ndp;
673 u32 ax_mu_mimo_ndpa;
674 u32 ax_mu_mimo_ndp;
675 u32 ax_mu_mimo_brpoll_1; /* MU user 1 */
676 u32 ax_mu_mimo_brpoll_2; /* MU user 2 */
677 u32 ax_mu_mimo_brpoll_3; /* MU user 3 */
678 u32 ax_mu_mimo_brpoll_4; /* MU user 4 */
679 u32 ax_mu_mimo_brpoll_5; /* MU user 5 */
680 u32 ax_mu_mimo_brpoll_6; /* MU user 6 */
681 u32 ax_mu_mimo_brpoll_7; /* MU user 7 */
682 u32 ax_basic_trigger;
683 u32 ax_bsr_trigger;
684 u32 ax_mu_bar_trigger;
685 u32 ax_mu_rts_trigger;
686 u32 ax_ulmumimo_trigger;
687};
688
689struct htt_tx_selfgen_ac_err_stats_tlv {
690 /* 11AC error stats */
691 u32 ac_su_ndp_err;
692 u32 ac_su_ndpa_err;
693 u32 ac_mu_mimo_ndpa_err;
694 u32 ac_mu_mimo_ndp_err;
695 u32 ac_mu_mimo_brp1_err;
696 u32 ac_mu_mimo_brp2_err;
697 u32 ac_mu_mimo_brp3_err;
698};
699
700struct htt_tx_selfgen_ax_err_stats_tlv {
701 /* 11AX error stats */
702 u32 ax_su_ndp_err;
703 u32 ax_su_ndpa_err;
704 u32 ax_mu_mimo_ndpa_err;
705 u32 ax_mu_mimo_ndp_err;
706 u32 ax_mu_mimo_brp1_err;
707 u32 ax_mu_mimo_brp2_err;
708 u32 ax_mu_mimo_brp3_err;
709 u32 ax_mu_mimo_brp4_err;
710 u32 ax_mu_mimo_brp5_err;
711 u32 ax_mu_mimo_brp6_err;
712 u32 ax_mu_mimo_brp7_err;
713 u32 ax_basic_trigger_err;
714 u32 ax_bsr_trigger_err;
715 u32 ax_mu_bar_trigger_err;
716 u32 ax_mu_rts_trigger_err;
717 u32 ax_ulmumimo_trigger_err;
718};
719
720/* == TX MU STATS == */
721#define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4
722#define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8
723#define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74
724#define HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS 8
725
726struct htt_tx_pdev_mu_mimo_sch_stats_tlv {
727 /* mu-mimo sw sched cmd stats */
728 u32 mu_mimo_sch_posted;
729 u32 mu_mimo_sch_failed;
730 /* MU PPDU stats per hwQ */
731 u32 mu_mimo_ppdu_posted;
732 /*
733 * Counts the number of users in each transmission of
734 * the given TX mode.
735 *
736 * Index is the number of users - 1.
737 */
738 u32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS];
739 u32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS];
740 u32 ax_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
741 u32 ax_ul_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
742 u32 ax_ul_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
743 u32 ax_ul_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
744 u32 ax_ul_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
745
746 /* UL MU-MIMO */
747 /* ax_ul_mumimo_basic_sch_nusers[i] is the number of basic triggers sent
748 * for (i+1) users
749 */
750 u32 ax_ul_mumimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS];
751
752 /* ax_ul_mumimo_brp_sch_nusers[i] is the number of brp triggers sent
753 * for (i+1) users
754 */
755 u32 ax_ul_mumimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS];
756
757 u32 ac_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS];
758 u32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS];
759};
760
761struct htt_tx_pdev_mu_mimo_mpdu_stats_tlv {
762 u32 mu_mimo_mpdus_queued_usr;
763 u32 mu_mimo_mpdus_tried_usr;
764 u32 mu_mimo_mpdus_failed_usr;
765 u32 mu_mimo_mpdus_requeued_usr;
766 u32 mu_mimo_err_no_ba_usr;
767 u32 mu_mimo_mpdu_underrun_usr;
768 u32 mu_mimo_ampdu_underrun_usr;
769
770 u32 ax_mu_mimo_mpdus_queued_usr;
771 u32 ax_mu_mimo_mpdus_tried_usr;
772 u32 ax_mu_mimo_mpdus_failed_usr;
773 u32 ax_mu_mimo_mpdus_requeued_usr;
774 u32 ax_mu_mimo_err_no_ba_usr;
775 u32 ax_mu_mimo_mpdu_underrun_usr;
776 u32 ax_mu_mimo_ampdu_underrun_usr;
777
778 u32 ax_ofdma_mpdus_queued_usr;
779 u32 ax_ofdma_mpdus_tried_usr;
780 u32 ax_ofdma_mpdus_failed_usr;
781 u32 ax_ofdma_mpdus_requeued_usr;
782 u32 ax_ofdma_err_no_ba_usr;
783 u32 ax_ofdma_mpdu_underrun_usr;
784 u32 ax_ofdma_ampdu_underrun_usr;
785};
786
787#define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC 1
788#define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX 2
789#define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX 3
790
791struct htt_tx_pdev_mpdu_stats_tlv {
792 /* mpdu level stats */
793 u32 mpdus_queued_usr;
794 u32 mpdus_tried_usr;
795 u32 mpdus_failed_usr;
796 u32 mpdus_requeued_usr;
797 u32 err_no_ba_usr;
798 u32 mpdu_underrun_usr;
799 u32 ampdu_underrun_usr;
800 u32 user_index;
801 u32 tx_sched_mode; /* HTT_STATS_TX_SCHED_MODE_xxx */
802};
803
804/* == TX SCHED STATS == */
805/* NOTE: Variable length TLV, use length spec to infer array size */
806struct htt_sched_txq_cmd_posted_tlv_v {
807 u32 sched_cmd_posted[0]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */
808};
809
810/* NOTE: Variable length TLV, use length spec to infer array size */
811struct htt_sched_txq_cmd_reaped_tlv_v {
812 u32 sched_cmd_reaped[0]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */
813};
814
815/* NOTE: Variable length TLV, use length spec to infer array size */
816struct htt_sched_txq_sched_order_su_tlv_v {
817 u32 sched_order_su[0]; /* HTT_TX_PDEV_NUM_SCHED_ORDER_LOG */
818};
819
820enum htt_sched_txq_sched_ineligibility_tlv_enum {
821 HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0,
822 HTT_SCHED_TID_SKIP_NOTIFY_MPDU,
823 HTT_SCHED_TID_SKIP_MPDU_STATE_INVALID,
824 HTT_SCHED_TID_SKIP_SCHED_DISABLED,
825 HTT_SCHED_TID_SKIP_TQM_BYPASS_CMD_PENDING,
826 HTT_SCHED_TID_SKIP_SECOND_SU_SCHEDULE,
827
828 HTT_SCHED_TID_SKIP_CMD_SLOT_NOT_AVAIL,
829 HTT_SCHED_TID_SKIP_NO_ENQ,
830 HTT_SCHED_TID_SKIP_LOW_ENQ,
831 HTT_SCHED_TID_SKIP_PAUSED,
832 HTT_SCHED_TID_SKIP_UL,
833 HTT_SCHED_TID_REMOVE_PAUSED,
834 HTT_SCHED_TID_REMOVE_NO_ENQ,
835 HTT_SCHED_TID_REMOVE_UL,
836 HTT_SCHED_TID_QUERY,
837 HTT_SCHED_TID_SU_ONLY,
838 HTT_SCHED_TID_ELIGIBLE,
839 HTT_SCHED_INELIGIBILITY_MAX,
840};
841
842/* NOTE: Variable length TLV, use length spec to infer array size */
843struct htt_sched_txq_sched_ineligibility_tlv_v {
844 /* indexed by htt_sched_txq_sched_ineligibility_tlv_enum */
845 u32 sched_ineligibility[0];
846};
847
848#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0)
849#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8)
850
851struct htt_tx_pdev_stats_sched_per_txq_tlv {
852 u32 mac_id__txq_id__word;
853 u32 sched_policy;
854 u32 last_sched_cmd_posted_timestamp;
855 u32 last_sched_cmd_compl_timestamp;
856 u32 sched_2_tac_lwm_count;
857 u32 sched_2_tac_ring_full;
858 u32 sched_cmd_post_failure;
859 u32 num_active_tids;
860 u32 num_ps_schedules;
861 u32 sched_cmds_pending;
862 u32 num_tid_register;
863 u32 num_tid_unregister;
864 u32 num_qstats_queried;
865 u32 qstats_update_pending;
866 u32 last_qstats_query_timestamp;
867 u32 num_tqm_cmdq_full;
868 u32 num_de_sched_algo_trigger;
869 u32 num_rt_sched_algo_trigger;
870 u32 num_tqm_sched_algo_trigger;
871 u32 notify_sched;
872 u32 dur_based_sendn_term;
873};
874
875struct htt_stats_tx_sched_cmn_tlv {
876 /* BIT [ 7 : 0] :- mac_id
877 * BIT [31 : 8] :- reserved
878 */
879 u32 mac_id__word;
880 /* Current timestamp */
881 u32 current_timestamp;
882};
883
884/* == TQM STATS == */
885#define HTT_TX_TQM_MAX_GEN_MPDU_END_REASON 16
886#define HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16
887#define HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16
888
889/* NOTE: Variable length TLV, use length spec to infer array size */
890struct htt_tx_tqm_gen_mpdu_stats_tlv_v {
891 u32 gen_mpdu_end_reason[0]; /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */
892};
893
894/* NOTE: Variable length TLV, use length spec to infer array size */
895struct htt_tx_tqm_list_mpdu_stats_tlv_v {
896 u32 list_mpdu_end_reason[0]; /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */
897};
898
899/* NOTE: Variable length TLV, use length spec to infer array size */
900struct htt_tx_tqm_list_mpdu_cnt_tlv_v {
901 u32 list_mpdu_cnt_hist[0];
902 /* HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS */
903};
904
905struct htt_tx_tqm_pdev_stats_tlv_v {
906 u32 msdu_count;
907 u32 mpdu_count;
908 u32 remove_msdu;
909 u32 remove_mpdu;
910 u32 remove_msdu_ttl;
911 u32 send_bar;
912 u32 bar_sync;
913 u32 notify_mpdu;
914 u32 sync_cmd;
915 u32 write_cmd;
916 u32 hwsch_trigger;
917 u32 ack_tlv_proc;
918 u32 gen_mpdu_cmd;
919 u32 gen_list_cmd;
920 u32 remove_mpdu_cmd;
921 u32 remove_mpdu_tried_cmd;
922 u32 mpdu_queue_stats_cmd;
923 u32 mpdu_head_info_cmd;
924 u32 msdu_flow_stats_cmd;
925 u32 remove_msdu_cmd;
926 u32 remove_msdu_ttl_cmd;
927 u32 flush_cache_cmd;
928 u32 update_mpduq_cmd;
929 u32 enqueue;
930 u32 enqueue_notify;
931 u32 notify_mpdu_at_head;
932 u32 notify_mpdu_state_valid;
933 /*
934 * On receiving TQM_FLOW_NOT_EMPTY_STATUS from TQM, (on MSDUs being enqueued
935 * the flow is non empty), if the number of MSDUs is greater than the threshold,
936 * notify is incremented. UDP_THRESH counters are for UDP MSDUs, and NONUDP are
937 * for non-UDP MSDUs.
938 * MSDUQ_SWNOTIFY_UDP_THRESH1 threshold - sched_udp_notify1 is incremented
939 * MSDUQ_SWNOTIFY_UDP_THRESH2 threshold - sched_udp_notify2 is incremented
940 * MSDUQ_SWNOTIFY_NONUDP_THRESH1 threshold - sched_nonudp_notify1 is incremented
941 * MSDUQ_SWNOTIFY_NONUDP_THRESH2 threshold - sched_nonudp_notify2 is incremented
942 *
943 * Notify signifies that we trigger the scheduler.
944 */
945 u32 sched_udp_notify1;
946 u32 sched_udp_notify2;
947 u32 sched_nonudp_notify1;
948 u32 sched_nonudp_notify2;
949};
950
951struct htt_tx_tqm_cmn_stats_tlv {
952 u32 mac_id__word;
953 u32 max_cmdq_id;
954 u32 list_mpdu_cnt_hist_intvl;
955
956 /* Global stats */
957 u32 add_msdu;
958 u32 q_empty;
959 u32 q_not_empty;
960 u32 drop_notification;
961 u32 desc_threshold;
962};
963
964struct htt_tx_tqm_error_stats_tlv {
965 /* Error stats */
966 u32 q_empty_failure;
967 u32 q_not_empty_failure;
968 u32 add_msdu_failure;
969};
970
971/* == TQM CMDQ stats == */
972#define HTT_TX_TQM_CMDQ_STATUS_MAC_ID GENMASK(7, 0)
973#define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID GENMASK(15, 8)
974
975struct htt_tx_tqm_cmdq_status_tlv {
976 u32 mac_id__cmdq_id__word;
977 u32 sync_cmd;
978 u32 write_cmd;
979 u32 gen_mpdu_cmd;
980 u32 mpdu_queue_stats_cmd;
981 u32 mpdu_head_info_cmd;
982 u32 msdu_flow_stats_cmd;
983 u32 remove_mpdu_cmd;
984 u32 remove_msdu_cmd;
985 u32 flush_cache_cmd;
986 u32 update_mpduq_cmd;
987 u32 update_msduq_cmd;
988};
989
990/* == TX-DE STATS == */
991/* Structures for tx de stats */
992struct htt_tx_de_eapol_packets_stats_tlv {
993 u32 m1_packets;
994 u32 m2_packets;
995 u32 m3_packets;
996 u32 m4_packets;
997 u32 g1_packets;
998 u32 g2_packets;
999};
1000
1001struct htt_tx_de_classify_failed_stats_tlv {
1002 u32 ap_bss_peer_not_found;
1003 u32 ap_bcast_mcast_no_peer;
1004 u32 sta_delete_in_progress;
1005 u32 ibss_no_bss_peer;
1006 u32 invalid_vdev_type;
1007 u32 invalid_ast_peer_entry;
1008 u32 peer_entry_invalid;
1009 u32 ethertype_not_ip;
1010 u32 eapol_lookup_failed;
1011 u32 qpeer_not_allow_data;
1012 u32 fse_tid_override;
1013 u32 ipv6_jumbogram_zero_length;
1014 u32 qos_to_non_qos_in_prog;
1015};
1016
1017struct htt_tx_de_classify_stats_tlv {
1018 u32 arp_packets;
1019 u32 igmp_packets;
1020 u32 dhcp_packets;
1021 u32 host_inspected;
1022 u32 htt_included;
1023 u32 htt_valid_mcs;
1024 u32 htt_valid_nss;
1025 u32 htt_valid_preamble_type;
1026 u32 htt_valid_chainmask;
1027 u32 htt_valid_guard_interval;
1028 u32 htt_valid_retries;
1029 u32 htt_valid_bw_info;
1030 u32 htt_valid_power;
1031 u32 htt_valid_key_flags;
1032 u32 htt_valid_no_encryption;
1033 u32 fse_entry_count;
1034 u32 fse_priority_be;
1035 u32 fse_priority_high;
1036 u32 fse_priority_low;
1037 u32 fse_traffic_ptrn_be;
1038 u32 fse_traffic_ptrn_over_sub;
1039 u32 fse_traffic_ptrn_bursty;
1040 u32 fse_traffic_ptrn_interactive;
1041 u32 fse_traffic_ptrn_periodic;
1042 u32 fse_hwqueue_alloc;
1043 u32 fse_hwqueue_created;
1044 u32 fse_hwqueue_send_to_host;
1045 u32 mcast_entry;
1046 u32 bcast_entry;
1047 u32 htt_update_peer_cache;
1048 u32 htt_learning_frame;
1049 u32 fse_invalid_peer;
1050 /*
1051 * mec_notify is HTT TX WBM multicast echo check notification
1052 * from firmware to host. FW sends SA addresses to host for all
1053 * multicast/broadcast packets received on STA side.
1054 */
1055 u32 mec_notify;
1056};
1057
1058struct htt_tx_de_classify_status_stats_tlv {
1059 u32 eok;
1060 u32 classify_done;
1061 u32 lookup_failed;
1062 u32 send_host_dhcp;
1063 u32 send_host_mcast;
1064 u32 send_host_unknown_dest;
1065 u32 send_host;
1066 u32 status_invalid;
1067};
1068
1069struct htt_tx_de_enqueue_packets_stats_tlv {
1070 u32 enqueued_pkts;
1071 u32 to_tqm;
1072 u32 to_tqm_bypass;
1073};
1074
1075struct htt_tx_de_enqueue_discard_stats_tlv {
1076 u32 discarded_pkts;
1077 u32 local_frames;
1078 u32 is_ext_msdu;
1079};
1080
1081struct htt_tx_de_compl_stats_tlv {
1082 u32 tcl_dummy_frame;
1083 u32 tqm_dummy_frame;
1084 u32 tqm_notify_frame;
1085 u32 fw2wbm_enq;
1086 u32 tqm_bypass_frame;
1087};
1088
1089/*
1090 * The htt_tx_de_fw2wbm_ring_full_hist_tlv is a histogram of time we waited
1091 * for the fw2wbm ring buffer. we are requesting a buffer in FW2WBM release
1092 * ring,which may fail, due to non availability of buffer. Hence we sleep for
1093 * 200us & again request for it. This is a histogram of time we wait, with
1094 * bin of 200ms & there are 10 bin (2 seconds max)
1095 * They are defined by the following macros in FW
1096 * #define ENTRIES_PER_BIN_COUNT 1000 // per bin 1000 * 200us = 200ms
1097 * #define RING_FULL_BIN_ENTRIES (WAL_TX_DE_FW2WBM_ALLOC_TIMEOUT_COUNT /
1098 * ENTRIES_PER_BIN_COUNT)
1099 */
1100struct htt_tx_de_fw2wbm_ring_full_hist_tlv {
1101 u32 fw2wbm_ring_full_hist[0];
1102};
1103
1104struct htt_tx_de_cmn_stats_tlv {
1105 u32 mac_id__word;
1106
1107 /* Global Stats */
1108 u32 tcl2fw_entry_count;
1109 u32 not_to_fw;
1110 u32 invalid_pdev_vdev_peer;
1111 u32 tcl_res_invalid_addrx;
1112 u32 wbm2fw_entry_count;
1113 u32 invalid_pdev;
1114};
1115
1116/* == RING-IF STATS == */
1117#define HTT_STATS_LOW_WM_BINS 5
1118#define HTT_STATS_HIGH_WM_BINS 5
1119
1120#define HTT_RING_IF_STATS_NUM_ELEMS GENMASK(15, 0)
1121#define HTT_RING_IF_STATS_PREFETCH_TAIL_INDEX GENMASK(31, 16)
1122#define HTT_RING_IF_STATS_HEAD_IDX GENMASK(15, 0)
1123#define HTT_RING_IF_STATS_TAIL_IDX GENMASK(31, 16)
1124#define HTT_RING_IF_STATS_SHADOW_HEAD_IDX GENMASK(15, 0)
1125#define HTT_RING_IF_STATS_SHADOW_TAIL_IDX GENMASK(31, 16)
1126#define HTT_RING_IF_STATS_LWM_THRESH GENMASK(15, 0)
1127#define HTT_RING_IF_STATS_HWM_THRESH GENMASK(31, 16)
1128
1129struct htt_ring_if_stats_tlv {
1130 u32 base_addr; /* DWORD aligned base memory address of the ring */
1131 u32 elem_size;
1132 u32 num_elems__prefetch_tail_idx;
1133 u32 head_idx__tail_idx;
1134 u32 shadow_head_idx__shadow_tail_idx;
1135 u32 num_tail_incr;
1136 u32 lwm_thresh__hwm_thresh;
1137 u32 overrun_hit_count;
1138 u32 underrun_hit_count;
1139 u32 prod_blockwait_count;
1140 u32 cons_blockwait_count;
1141 u32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS];
1142 u32 high_wm_hit_count[HTT_STATS_HIGH_WM_BINS];
1143};
1144
1145struct htt_ring_if_cmn_tlv {
1146 u32 mac_id__word;
1147 u32 num_records;
1148};
1149
1150/* == SFM STATS == */
1151/* NOTE: Variable length TLV, use length spec to infer array size */
1152struct htt_sfm_client_user_tlv_v {
1153 /* Number of DWORDS used per user and per client */
1154 u32 dwords_used_by_user_n[0];
1155};
1156
1157struct htt_sfm_client_tlv {
1158 /* Client ID */
1159 u32 client_id;
1160 /* Minimum number of buffers */
1161 u32 buf_min;
1162 /* Maximum number of buffers */
1163 u32 buf_max;
1164 /* Number of Busy buffers */
1165 u32 buf_busy;
1166 /* Number of Allocated buffers */
1167 u32 buf_alloc;
1168 /* Number of Available/Usable buffers */
1169 u32 buf_avail;
1170 /* Number of users */
1171 u32 num_users;
1172};
1173
1174struct htt_sfm_cmn_tlv {
1175 u32 mac_id__word;
1176 /* Indicates the total number of 128 byte buffers
1177 * in the CMEM that are available for buffer sharing
1178 */
1179 u32 buf_total;
1180 /* Indicates for certain client or all the clients
1181 * there is no dowrd saved in SFM, refer to SFM_R1_MEM_EMPTY
1182 */
1183 u32 mem_empty;
1184 /* DEALLOCATE_BUFFERS, refer to register SFM_R0_DEALLOCATE_BUFFERS */
1185 u32 deallocate_bufs;
1186 /* Number of Records */
1187 u32 num_records;
1188};
1189
1190/* == SRNG STATS == */
1191#define HTT_SRING_STATS_MAC_ID GENMASK(7, 0)
1192#define HTT_SRING_STATS_RING_ID GENMASK(15, 8)
1193#define HTT_SRING_STATS_ARENA GENMASK(23, 16)
1194#define HTT_SRING_STATS_EP BIT(24)
1195#define HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0)
1196#define HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16)
1197#define HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0)
1198#define HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16)
1199#define HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0)
1200#define HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16)
1201#define HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0)
1202#define HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16)
1203
1204struct htt_sring_stats_tlv {
1205 u32 mac_id__ring_id__arena__ep;
1206 u32 base_addr_lsb; /* DWORD aligned base memory address of the ring */
1207 u32 base_addr_msb;
1208 u32 ring_size;
1209 u32 elem_size;
1210
1211 u32 num_avail_words__num_valid_words;
1212 u32 head_ptr__tail_ptr;
1213 u32 consumer_empty__producer_full;
1214 u32 prefetch_count__internal_tail_ptr;
1215};
1216
1217struct htt_sring_cmn_tlv {
1218 u32 num_records;
1219};
1220
1221/* == PDEV TX RATE CTRL STATS == */
1222#define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12
1223#define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4
1224#define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5
1225#define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4
1226#define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8
1227#define HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
1228#define HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4
1229#define HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8
1230#define HTT_TX_PDEV_STATS_NUM_LTF 4
1231
1232#define HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \
1233 (HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \
1234 HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS)
1235
1236struct htt_tx_pdev_rate_stats_tlv {
1237 u32 mac_id__word;
1238 u32 tx_ldpc;
1239 u32 rts_cnt;
1240 /* RSSI value of last ack packet (units = dB above noise floor) */
1241 u32 ack_rssi;
1242
1243 u32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1244
1245 u32 tx_su_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1246 u32 tx_mu_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1247
1248 /* element 0,1, ...7 -> NSS 1,2, ...8 */
1249 u32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1250 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
1251 u32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1252 u32 tx_stbc[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1253 u32 tx_pream[HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES];
1254
1255 /* Counters to track number of tx packets
1256 * in each GI (400us, 800us, 1600us & 3200us) in each mcs (0-11)
1257 */
1258 u32 tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1259
1260 /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */
1261 u32 tx_dcm[HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS];
1262 /* Number of CTS-acknowledged RTS packets */
1263 u32 rts_success;
1264
1265 /*
1266 * Counters for legacy 11a and 11b transmissions.
1267 *
1268 * The index corresponds to:
1269 *
1270 * CCK: 0: 1 Mbps, 1: 2 Mbps, 2: 5.5 Mbps, 3: 11 Mbps
1271 *
1272 * OFDM: 0: 6 Mbps, 1: 9 Mbps, 2: 12 Mbps, 3: 18 Mbps,
1273 * 4: 24 Mbps, 5: 36 Mbps, 6: 48 Mbps, 7: 54 Mbps
1274 */
1275 u32 tx_legacy_cck_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS];
1276 u32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS];
1277
1278 u32 ac_mu_mimo_tx_ldpc;
1279 u32 ax_mu_mimo_tx_ldpc;
1280 u32 ofdma_tx_ldpc;
1281
1282 /*
1283 * Counters for 11ax HE LTF selection during TX.
1284 *
1285 * The index corresponds to:
1286 *
1287 * 0: unused, 1: 1x LTF, 2: 2x LTF, 3: 4x LTF
1288 */
1289 u32 tx_he_ltf[HTT_TX_PDEV_STATS_NUM_LTF];
1290
1291 u32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1292 u32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1293 u32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1294
1295 u32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1296 u32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1297 u32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1298
1299 u32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1300 u32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1301 u32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1302
1303 u32 ac_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1304 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1305 u32 ax_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1306 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1307 u32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1308 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1309};
1310
1311/* == PDEV RX RATE CTRL STATS == */
1312#define HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4
1313#define HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8
1314#define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12
1315#define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4
1316#define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5
1317#define HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4
1318#define HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8
1319#define HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
1320#define HTT_RX_PDEV_MAX_OFDMA_NUM_USER 8
1321#define HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS 16
1322#define HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS 6
1323#define HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER 8
1324
1325struct htt_rx_pdev_rate_stats_tlv {
1326 u32 mac_id__word;
1327 u32 nsts;
1328
1329 u32 rx_ldpc;
1330 u32 rts_cnt;
1331
1332 u32 rssi_mgmt; /* units = dB above noise floor */
1333 u32 rssi_data; /* units = dB above noise floor */
1334 u32 rssi_comb; /* units = dB above noise floor */
1335 u32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1336 /* element 0,1, ...7 -> NSS 1,2, ...8 */
1337 u32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1338 u32 rx_dcm[HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS];
1339 u32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1340 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
1341 u32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
1342 u32 rx_pream[HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES];
1343 u8 rssi_chain[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]
1344 [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
1345 /* units = dB above noise floor */
1346
1347 /* Counters to track number of rx packets
1348 * in each GI in each mcs (0-11)
1349 */
1350 u32 rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1351 s32 rssi_in_dbm; /* rx Signal Strength value in dBm unit */
1352
1353 u32 rx_11ax_su_ext;
1354 u32 rx_11ac_mumimo;
1355 u32 rx_11ax_mumimo;
1356 u32 rx_11ax_ofdma;
1357 u32 txbf;
1358 u32 rx_legacy_cck_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS];
1359 u32 rx_legacy_ofdm_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS];
1360 u32 rx_active_dur_us_low;
1361 u32 rx_active_dur_us_high;
1362
1363 u32 rx_11ax_ul_ofdma;
1364
1365 u32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1366 u32 ul_ofdma_rx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1367 [HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1368 u32 ul_ofdma_rx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1369 u32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1370 u32 ul_ofdma_rx_stbc;
1371 u32 ul_ofdma_rx_ldpc;
1372
1373 /* record the stats for each user index */
1374 u32 rx_ulofdma_non_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */
1375 u32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */
1376 u32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */
1377 u32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */
1378
1379 u32 nss_count;
1380 u32 pilot_count;
1381 /* RxEVM stats in dB */
1382 s32 rx_pilot_evm_db[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]
1383 [HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS];
1384 /* rx_pilot_evm_db_mean:
1385 * EVM mean across pilots, computed as
1386 * mean(10*log10(rx_pilot_evm_linear)) = mean(rx_pilot_evm_db)
1387 */
1388 s32 rx_pilot_evm_db_mean[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1389 s8 rx_ul_fd_rssi[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]
1390 [HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* dBm units */
1391 /* per_chain_rssi_pkt_type:
1392 * This field shows what type of rx frame the per-chain RSSI was computed
1393 * on, by recording the frame type and sub-type as bit-fields within this
1394 * field:
1395 * BIT [3 : 0] :- IEEE80211_FC0_TYPE
1396 * BIT [7 : 4] :- IEEE80211_FC0_SUBTYPE
1397 * BIT [31 : 8] :- Reserved
1398 */
1399 u32 per_chain_rssi_pkt_type;
1400 s8 rx_per_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]
1401 [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
1402
1403 u32 rx_su_ndpa;
1404 u32 rx_11ax_su_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1405 u32 rx_mu_ndpa;
1406 u32 rx_11ax_mu_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1407 u32 rx_br_poll;
1408 u32 rx_11ax_dl_ofdma_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1409 u32 rx_11ax_dl_ofdma_ru[HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS];
1410
1411 u32 rx_ulmumimo_non_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER];
1412 u32 rx_ulmumimo_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER];
1413 u32 rx_ulmumimo_mpdu_ok[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER];
1414 u32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER];
1415 u32 rx_ulofdma_non_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
1416 u32 rx_ulofdma_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
1417};
1418
1419/* == RX PDEV/SOC STATS == */
1420struct htt_rx_soc_fw_stats_tlv {
1421 u32 fw_reo_ring_data_msdu;
1422 u32 fw_to_host_data_msdu_bcmc;
1423 u32 fw_to_host_data_msdu_uc;
1424 u32 ofld_remote_data_buf_recycle_cnt;
1425 u32 ofld_remote_free_buf_indication_cnt;
1426
1427 u32 ofld_buf_to_host_data_msdu_uc;
1428 u32 reo_fw_ring_to_host_data_msdu_uc;
1429
1430 u32 wbm_sw_ring_reap;
1431 u32 wbm_forward_to_host_cnt;
1432 u32 wbm_target_recycle_cnt;
1433
1434 u32 target_refill_ring_recycle_cnt;
1435};
1436
1437/* NOTE: Variable length TLV, use length spec to infer array size */
1438struct htt_rx_soc_fw_refill_ring_empty_tlv_v {
1439 u32 refill_ring_empty_cnt[0]; /* HTT_RX_STATS_REFILL_MAX_RING */
1440};
1441
1442/* NOTE: Variable length TLV, use length spec to infer array size */
1443struct htt_rx_soc_fw_refill_ring_num_refill_tlv_v {
1444 u32 refill_ring_num_refill[0]; /* HTT_RX_STATS_REFILL_MAX_RING */
1445};
1446
1447/* RXDMA error code from WBM released packets */
1448enum htt_rx_rxdma_error_code_enum {
1449 HTT_RX_RXDMA_OVERFLOW_ERR = 0,
1450 HTT_RX_RXDMA_MPDU_LENGTH_ERR = 1,
1451 HTT_RX_RXDMA_FCS_ERR = 2,
1452 HTT_RX_RXDMA_DECRYPT_ERR = 3,
1453 HTT_RX_RXDMA_TKIP_MIC_ERR = 4,
1454 HTT_RX_RXDMA_UNECRYPTED_ERR = 5,
1455 HTT_RX_RXDMA_MSDU_LEN_ERR = 6,
1456 HTT_RX_RXDMA_MSDU_LIMIT_ERR = 7,
1457 HTT_RX_RXDMA_WIFI_PARSE_ERR = 8,
1458 HTT_RX_RXDMA_AMSDU_PARSE_ERR = 9,
1459 HTT_RX_RXDMA_SA_TIMEOUT_ERR = 10,
1460 HTT_RX_RXDMA_DA_TIMEOUT_ERR = 11,
1461 HTT_RX_RXDMA_FLOW_TIMEOUT_ERR = 12,
1462 HTT_RX_RXDMA_FLUSH_REQUEST = 13,
1463 HTT_RX_RXDMA_ERR_CODE_RVSD0 = 14,
1464 HTT_RX_RXDMA_ERR_CODE_RVSD1 = 15,
1465
1466 /* This MAX_ERR_CODE should not be used in any host/target messages,
1467 * so that even though it is defined within a host/target interface
1468 * definition header file, it isn't actually part of the host/target
1469 * interface, and thus can be modified.
1470 */
1471 HTT_RX_RXDMA_MAX_ERR_CODE
1472};
1473
1474/* NOTE: Variable length TLV, use length spec to infer array size */
1475struct htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v {
1476 u32 rxdma_err[0]; /* HTT_RX_RXDMA_MAX_ERR_CODE */
1477};
1478
1479/* REO error code from WBM released packets */
1480enum htt_rx_reo_error_code_enum {
1481 HTT_RX_REO_QUEUE_DESC_ADDR_ZERO = 0,
1482 HTT_RX_REO_QUEUE_DESC_NOT_VALID = 1,
1483 HTT_RX_AMPDU_IN_NON_BA = 2,
1484 HTT_RX_NON_BA_DUPLICATE = 3,
1485 HTT_RX_BA_DUPLICATE = 4,
1486 HTT_RX_REGULAR_FRAME_2K_JUMP = 5,
1487 HTT_RX_BAR_FRAME_2K_JUMP = 6,
1488 HTT_RX_REGULAR_FRAME_OOR = 7,
1489 HTT_RX_BAR_FRAME_OOR = 8,
1490 HTT_RX_BAR_FRAME_NO_BA_SESSION = 9,
1491 HTT_RX_BAR_FRAME_SN_EQUALS_SSN = 10,
1492 HTT_RX_PN_CHECK_FAILED = 11,
1493 HTT_RX_2K_ERROR_HANDLING_FLAG_SET = 12,
1494 HTT_RX_PN_ERROR_HANDLING_FLAG_SET = 13,
1495 HTT_RX_QUEUE_DESCRIPTOR_BLOCKED_SET = 14,
1496 HTT_RX_REO_ERR_CODE_RVSD = 15,
1497
1498 /* This MAX_ERR_CODE should not be used in any host/target messages,
1499 * so that even though it is defined within a host/target interface
1500 * definition header file, it isn't actually part of the host/target
1501 * interface, and thus can be modified.
1502 */
1503 HTT_RX_REO_MAX_ERR_CODE
1504};
1505
1506/* NOTE: Variable length TLV, use length spec to infer array size */
1507struct htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v {
1508 u32 reo_err[0]; /* HTT_RX_REO_MAX_ERR_CODE */
1509};
1510
1511/* == RX PDEV STATS == */
1512#define HTT_STATS_SUBTYPE_MAX 16
1513
1514struct htt_rx_pdev_fw_stats_tlv {
1515 u32 mac_id__word;
1516 u32 ppdu_recvd;
1517 u32 mpdu_cnt_fcs_ok;
1518 u32 mpdu_cnt_fcs_err;
1519 u32 tcp_msdu_cnt;
1520 u32 tcp_ack_msdu_cnt;
1521 u32 udp_msdu_cnt;
1522 u32 other_msdu_cnt;
1523 u32 fw_ring_mpdu_ind;
1524 u32 fw_ring_mgmt_subtype[HTT_STATS_SUBTYPE_MAX];
1525 u32 fw_ring_ctrl_subtype[HTT_STATS_SUBTYPE_MAX];
1526 u32 fw_ring_mcast_data_msdu;
1527 u32 fw_ring_bcast_data_msdu;
1528 u32 fw_ring_ucast_data_msdu;
1529 u32 fw_ring_null_data_msdu;
1530 u32 fw_ring_mpdu_drop;
1531 u32 ofld_local_data_ind_cnt;
1532 u32 ofld_local_data_buf_recycle_cnt;
1533 u32 drx_local_data_ind_cnt;
1534 u32 drx_local_data_buf_recycle_cnt;
1535 u32 local_nondata_ind_cnt;
1536 u32 local_nondata_buf_recycle_cnt;
1537
1538 u32 fw_status_buf_ring_refill_cnt;
1539 u32 fw_status_buf_ring_empty_cnt;
1540 u32 fw_pkt_buf_ring_refill_cnt;
1541 u32 fw_pkt_buf_ring_empty_cnt;
1542 u32 fw_link_buf_ring_refill_cnt;
1543 u32 fw_link_buf_ring_empty_cnt;
1544
1545 u32 host_pkt_buf_ring_refill_cnt;
1546 u32 host_pkt_buf_ring_empty_cnt;
1547 u32 mon_pkt_buf_ring_refill_cnt;
1548 u32 mon_pkt_buf_ring_empty_cnt;
1549 u32 mon_status_buf_ring_refill_cnt;
1550 u32 mon_status_buf_ring_empty_cnt;
1551 u32 mon_desc_buf_ring_refill_cnt;
1552 u32 mon_desc_buf_ring_empty_cnt;
1553 u32 mon_dest_ring_update_cnt;
1554 u32 mon_dest_ring_full_cnt;
1555
1556 u32 rx_suspend_cnt;
1557 u32 rx_suspend_fail_cnt;
1558 u32 rx_resume_cnt;
1559 u32 rx_resume_fail_cnt;
1560 u32 rx_ring_switch_cnt;
1561 u32 rx_ring_restore_cnt;
1562 u32 rx_flush_cnt;
1563 u32 rx_recovery_reset_cnt;
1564};
1565
1566#define HTT_STATS_PHY_ERR_MAX 43
1567
1568struct htt_rx_pdev_fw_stats_phy_err_tlv {
1569 u32 mac_id__word;
1570 u32 total_phy_err_cnt;
1571 /* Counts of different types of phy errs
1572 * The mapping of PHY error types to phy_err array elements is HW dependent.
1573 * The only currently-supported mapping is shown below:
1574 *
1575 * 0 phyrx_err_phy_off Reception aborted due to receiving a PHY_OFF TLV
1576 * 1 phyrx_err_synth_off
1577 * 2 phyrx_err_ofdma_timing
1578 * 3 phyrx_err_ofdma_signal_parity
1579 * 4 phyrx_err_ofdma_rate_illegal
1580 * 5 phyrx_err_ofdma_length_illegal
1581 * 6 phyrx_err_ofdma_restart
1582 * 7 phyrx_err_ofdma_service
1583 * 8 phyrx_err_ppdu_ofdma_power_drop
1584 * 9 phyrx_err_cck_blokker
1585 * 10 phyrx_err_cck_timing
1586 * 11 phyrx_err_cck_header_crc
1587 * 12 phyrx_err_cck_rate_illegal
1588 * 13 phyrx_err_cck_length_illegal
1589 * 14 phyrx_err_cck_restart
1590 * 15 phyrx_err_cck_service
1591 * 16 phyrx_err_cck_power_drop
1592 * 17 phyrx_err_ht_crc_err
1593 * 18 phyrx_err_ht_length_illegal
1594 * 19 phyrx_err_ht_rate_illegal
1595 * 20 phyrx_err_ht_zlf
1596 * 21 phyrx_err_false_radar_ext
1597 * 22 phyrx_err_green_field
1598 * 23 phyrx_err_bw_gt_dyn_bw
1599 * 24 phyrx_err_leg_ht_mismatch
1600 * 25 phyrx_err_vht_crc_error
1601 * 26 phyrx_err_vht_siga_unsupported
1602 * 27 phyrx_err_vht_lsig_len_invalid
1603 * 28 phyrx_err_vht_ndp_or_zlf
1604 * 29 phyrx_err_vht_nsym_lt_zero
1605 * 30 phyrx_err_vht_rx_extra_symbol_mismatch
1606 * 31 phyrx_err_vht_rx_skip_group_id0
1607 * 32 phyrx_err_vht_rx_skip_group_id1to62
1608 * 33 phyrx_err_vht_rx_skip_group_id63
1609 * 34 phyrx_err_ofdm_ldpc_decoder_disabled
1610 * 35 phyrx_err_defer_nap
1611 * 36 phyrx_err_fdomain_timeout
1612 * 37 phyrx_err_lsig_rel_check
1613 * 38 phyrx_err_bt_collision
1614 * 39 phyrx_err_unsupported_mu_feedback
1615 * 40 phyrx_err_ppdu_tx_interrupt_rx
1616 * 41 phyrx_err_unsupported_cbf
1617 * 42 phyrx_err_other
1618 */
1619 u32 phy_err[HTT_STATS_PHY_ERR_MAX];
1620};
1621
1622/* NOTE: Variable length TLV, use length spec to infer array size */
1623struct htt_rx_pdev_fw_ring_mpdu_err_tlv_v {
1624 /* Num error MPDU for each RxDMA error type */
1625 u32 fw_ring_mpdu_err[0]; /* HTT_RX_STATS_RXDMA_MAX_ERR */
1626};
1627
1628/* NOTE: Variable length TLV, use length spec to infer array size */
1629struct htt_rx_pdev_fw_mpdu_drop_tlv_v {
1630 /* Num MPDU dropped */
1631 u32 fw_mpdu_drop[0]; /* HTT_RX_STATS_FW_DROP_REASON_MAX */
1632};
1633
1634#define HTT_PDEV_CCA_STATS_TX_FRAME_INFO_PRESENT (0x1)
1635#define HTT_PDEV_CCA_STATS_RX_FRAME_INFO_PRESENT (0x2)
1636#define HTT_PDEV_CCA_STATS_RX_CLEAR_INFO_PRESENT (0x4)
1637#define HTT_PDEV_CCA_STATS_MY_RX_FRAME_INFO_PRESENT (0x8)
1638#define HTT_PDEV_CCA_STATS_USEC_CNT_INFO_PRESENT (0x10)
1639#define HTT_PDEV_CCA_STATS_MED_RX_IDLE_INFO_PRESENT (0x20)
1640#define HTT_PDEV_CCA_STATS_MED_TX_IDLE_GLOBAL_INFO_PRESENT (0x40)
1641#define HTT_PDEV_CCA_STATS_CCA_OBBS_USEC_INFO_PRESENT (0x80)
1642
1643struct htt_pdev_stats_cca_counters_tlv {
1644 /* Below values are obtained from the HW Cycles counter registers */
1645 u32 tx_frame_usec;
1646 u32 rx_frame_usec;
1647 u32 rx_clear_usec;
1648 u32 my_rx_frame_usec;
1649 u32 usec_cnt;
1650 u32 med_rx_idle_usec;
1651 u32 med_tx_idle_global_usec;
1652 u32 cca_obss_usec;
1653};
1654
1655struct htt_pdev_cca_stats_hist_v1_tlv {
1656 u32 chan_num;
1657 /* num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/
1658 u32 num_records;
1659 u32 valid_cca_counters_bitmap;
1660 u32 collection_interval;
1661
1662 /* This will be followed by an array which contains the CCA stats
1663 * collected in the last N intervals,
1664 * if the indication is for last N intervals CCA stats.
1665 * Then the pdev_cca_stats[0] element contains the oldest CCA stats
1666 * and pdev_cca_stats[N-1] will have the most recent CCA stats.
1667 * htt_pdev_stats_cca_counters_tlv cca_hist_tlv[1];
1668 */
1669};
1670
1671struct htt_pdev_stats_twt_session_tlv {
1672 u32 vdev_id;
1673 struct htt_mac_addr peer_mac;
1674 u32 flow_id_flags;
1675
1676 /* TWT_DIALOG_ID_UNAVAILABLE is used
1677 * when TWT session is not initiated by host
1678 */
1679 u32 dialog_id;
1680 u32 wake_dura_us;
1681 u32 wake_intvl_us;
1682 u32 sp_offset_us;
1683};
1684
1685struct htt_pdev_stats_twt_sessions_tlv {
1686 u32 pdev_id;
1687 u32 num_sessions;
1688 struct htt_pdev_stats_twt_session_tlv twt_session[];
1689};
1690
1691enum htt_rx_reo_resource_sample_id_enum {
1692 /* Global link descriptor queued in REO */
1693 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_0 = 0,
1694 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_1 = 1,
1695 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_2 = 2,
1696 /*Number of queue descriptors of this aging group */
1697 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC0 = 3,
1698 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC1 = 4,
1699 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC2 = 5,
1700 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC3 = 6,
1701 /* Total number of MSDUs buffered in AC */
1702 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC0 = 7,
1703 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC1 = 8,
1704 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC2 = 9,
1705 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC3 = 10,
1706
1707 HTT_RX_REO_RESOURCE_STATS_MAX = 16
1708};
1709
1710struct htt_rx_reo_resource_stats_tlv_v {
1711 /* Variable based on the Number of records. HTT_RX_REO_RESOURCE_STATS_MAX */
1712 u32 sample_id;
1713 u32 total_max;
1714 u32 total_avg;
1715 u32 total_sample;
1716 u32 non_zeros_avg;
1717 u32 non_zeros_sample;
1718 u32 last_non_zeros_max;
1719 u32 last_non_zeros_min;
1720 u32 last_non_zeros_avg;
1721 u32 last_non_zeros_sample;
1722};
1723
1724/* == TX SOUNDING STATS == */
1725
1726enum htt_txbf_sound_steer_modes {
1727 HTT_IMPLICIT_TXBF_STEER_STATS = 0,
1728 HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS = 1,
1729 HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS = 2,
1730 HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS = 3,
1731 HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS = 4,
1732 HTT_TXBF_MAX_NUM_OF_MODES = 5
1733};
1734
1735enum htt_stats_sounding_tx_mode {
1736 HTT_TX_AC_SOUNDING_MODE = 0,
1737 HTT_TX_AX_SOUNDING_MODE = 1,
1738};
1739
1740struct htt_tx_sounding_stats_tlv {
1741 u32 tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */
1742 /* Counts number of soundings for all steering modes in each bw */
1743 u32 cbf_20[HTT_TXBF_MAX_NUM_OF_MODES];
1744 u32 cbf_40[HTT_TXBF_MAX_NUM_OF_MODES];
1745 u32 cbf_80[HTT_TXBF_MAX_NUM_OF_MODES];
1746 u32 cbf_160[HTT_TXBF_MAX_NUM_OF_MODES];
1747 /*
1748 * The sounding array is a 2-D array stored as an 1-D array of
1749 * u32. The stats for a particular user/bw combination is
1750 * referenced with the following:
1751 *
1752 * sounding[(user* max_bw) + bw]
1753 *
1754 * ... where max_bw == 4 for 160mhz
1755 */
1756 u32 sounding[HTT_TX_NUM_OF_SOUNDING_STATS_WORDS];
1757};
1758
1759struct htt_pdev_obss_pd_stats_tlv {
1760 u32 num_obss_tx_ppdu_success;
1761 u32 num_obss_tx_ppdu_failure;
1762 u32 num_sr_tx_transmissions;
1763 u32 num_spatial_reuse_opportunities;
1764 u32 num_non_srg_opportunities;
1765 u32 num_non_srg_ppdu_tried;
1766 u32 num_non_srg_ppdu_success;
1767 u32 num_srg_opportunities;
1768 u32 num_srg_ppdu_tried;
1769 u32 num_srg_ppdu_success;
1770 u32 num_psr_opportunities;
1771 u32 num_psr_ppdu_tried;
1772 u32 num_psr_ppdu_success;
1773};
1774
1775struct htt_ring_backpressure_stats_tlv {
1776 u32 pdev_id;
1777 u32 current_head_idx;
1778 u32 current_tail_idx;
1779 u32 num_htt_msgs_sent;
1780 /* Time in milliseconds for which the ring has been in
1781 * its current backpressure condition
1782 */
1783 u32 backpressure_time_ms;
1784 /* backpressure_hist - histogram showing how many times
1785 * different degrees of backpressure duration occurred:
1786 * Index 0 indicates the number of times ring was
1787 * continuously in backpressure state for 100 - 200ms.
1788 * Index 1 indicates the number of times ring was
1789 * continuously in backpressure state for 200 - 300ms.
1790 * Index 2 indicates the number of times ring was
1791 * continuously in backpressure state for 300 - 400ms.
1792 * Index 3 indicates the number of times ring was
1793 * continuously in backpressure state for 400 - 500ms.
1794 * Index 4 indicates the number of times ring was
1795 * continuously in backpressure state beyond 500ms.
1796 */
1797 u32 backpressure_hist[5];
1798};
1799
1800#define HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS 14
1801#define HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS 5
1802#define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8
1803
1804struct htt_pdev_txrate_txbf_stats_tlv {
1805 /* SU TxBF TX MCS stats */
1806 u32 tx_su_txbf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS];
1807 /* Implicit BF TX MCS stats */
1808 u32 tx_su_ibf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS];
1809 /* Open loop TX MCS stats */
1810 u32 tx_su_ol_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS];
1811 /* SU TxBF TX NSS stats */
1812 u32 tx_su_txbf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1813 /* Implicit BF TX NSS stats */
1814 u32 tx_su_ibf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1815 /* Open loop TX NSS stats */
1816 u32 tx_su_ol_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1817 /* SU TxBF TX BW stats */
1818 u32 tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
1819 /* Implicit BF TX BW stats */
1820 u32 tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
1821 /* Open loop TX BW stats */
1822 u32 tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
1823};
1824
1825struct htt_txbf_ofdma_ndpa_stats_tlv {
1826 /* 11AX HE OFDMA NDPA frame queued to the HW */
1827 u32 ax_ofdma_ndpa_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1828 /* 11AX HE OFDMA NDPA frame sent over the air */
1829 u32 ax_ofdma_ndpa_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1830 /* 11AX HE OFDMA NDPA frame flushed by HW */
1831 u32 ax_ofdma_ndpa_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1832 /* 11AX HE OFDMA NDPA frame completed with error(s) */
1833 u32 ax_ofdma_ndpa_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1834};
1835
1836struct htt_txbf_ofdma_ndp_stats_tlv {
1837 /* 11AX HE OFDMA NDP frame queued to the HW */
1838 u32 ax_ofdma_ndp_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1839 /* 11AX HE OFDMA NDPA frame sent over the air */
1840 u32 ax_ofdma_ndp_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1841 /* 11AX HE OFDMA NDPA frame flushed by HW */
1842 u32 ax_ofdma_ndp_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1843 /* 11AX HE OFDMA NDPA frame completed with error(s) */
1844 u32 ax_ofdma_ndp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1845};
1846
1847struct htt_txbf_ofdma_brp_stats_tlv {
1848 /* 11AX HE OFDMA MU BRPOLL frame queued to the HW */
1849 u32 ax_ofdma_brpoll_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1850 /* 11AX HE OFDMA MU BRPOLL frame sent over the air */
1851 u32 ax_ofdma_brpoll_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1852 /* 11AX HE OFDMA MU BRPOLL frame flushed by HW */
1853 u32 ax_ofdma_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1854 /* 11AX HE OFDMA MU BRPOLL frame completed with error(s) */
1855 u32 ax_ofdma_brp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1856 /* Number of CBF(s) received when 11AX HE OFDMA MU BRPOLL frame
1857 * completed with error(s).
1858 */
1859 u32 ax_ofdma_brp_err_num_cbf_rcvd[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS + 1];
1860};
1861
1862struct htt_txbf_ofdma_steer_stats_tlv {
1863 /* 11AX HE OFDMA PPDUs that were sent over the air with steering (TXBF + OFDMA) */
1864 u32 ax_ofdma_num_ppdu_steer[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1865 /* 11AX HE OFDMA PPDUs that were sent over the air in open loop */
1866 u32 ax_ofdma_num_ppdu_ol[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1867 /* 11AX HE OFDMA number of users for which CBF prefetch was
1868 * initiated to PHY HW during TX.
1869 */
1870 u32 ax_ofdma_num_usrs_prefetch[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1871 /* 11AX HE OFDMA number of users for which sounding was initiated during TX */
1872 u32 ax_ofdma_num_usrs_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1873 /* 11AX HE OFDMA number of users for which sounding was forced during TX */
1874 u32 ax_ofdma_num_usrs_force_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1875};
1876
1877#define HTT_MAX_RX_PKT_CNT 8
1878#define HTT_MAX_RX_PKT_CRC_PASS_CNT 8
1879#define HTT_MAX_PER_BLK_ERR_CNT 20
1880#define HTT_MAX_RX_OTA_ERR_CNT 14
1881#define HTT_STATS_MAX_CHAINS 8
1882#define ATH11K_STATS_MGMT_FRM_TYPE_MAX 16
1883
1884struct htt_phy_counters_tlv {
1885 /* number of RXTD OFDMA OTA error counts except power surge and drop */
1886 u32 rx_ofdma_timing_err_cnt;
1887 /* rx_cck_fail_cnt:
1888 * number of cck error counts due to rx reception failure because of
1889 * timing error in cck
1890 */
1891 u32 rx_cck_fail_cnt;
1892 /* number of times tx abort initiated by mac */
1893 u32 mactx_abort_cnt;
1894 /* number of times rx abort initiated by mac */
1895 u32 macrx_abort_cnt;
1896 /* number of times tx abort initiated by phy */
1897 u32 phytx_abort_cnt;
1898 /* number of times rx abort initiated by phy */
1899 u32 phyrx_abort_cnt;
1900 /* number of rx deferred count initiated by phy */
1901 u32 phyrx_defer_abort_cnt;
1902 /* number of sizing events generated at LSTF */
1903 u32 rx_gain_adj_lstf_event_cnt;
1904 /* number of sizing events generated at non-legacy LTF */
1905 u32 rx_gain_adj_non_legacy_cnt;
1906 /* rx_pkt_cnt -
1907 * Received EOP (end-of-packet) count per packet type;
1908 * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF
1909 * [6-7]=RSVD
1910 */
1911 u32 rx_pkt_cnt[HTT_MAX_RX_PKT_CNT];
1912 /* rx_pkt_crc_pass_cnt -
1913 * Received EOP (end-of-packet) count per packet type;
1914 * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF
1915 * [6-7]=RSVD
1916 */
1917 u32 rx_pkt_crc_pass_cnt[HTT_MAX_RX_PKT_CRC_PASS_CNT];
1918 /* per_blk_err_cnt -
1919 * Error count per error source;
1920 * [0] = unknown; [1] = LSIG; [2] = HTSIG; [3] = VHTSIG; [4] = HESIG;
1921 * [5] = RXTD_OTA; [6] = RXTD_FATAL; [7] = DEMF; [8] = ROBE;
1922 * [9] = PMI; [10] = TXFD; [11] = TXTD; [12] = PHYRF
1923 * [13-19]=RSVD
1924 */
1925 u32 per_blk_err_cnt[HTT_MAX_PER_BLK_ERR_CNT];
1926 /* rx_ota_err_cnt -
1927 * RXTD OTA (over-the-air) error count per error reason;
1928 * [0] = voting fail; [1] = weak det fail; [2] = strong sig fail;
1929 * [3] = cck fail; [4] = power surge; [5] = power drop;
1930 * [6] = btcf timing timeout error; [7] = btcf packet detect error;
1931 * [8] = coarse timing timeout error
1932 * [9-13]=RSVD
1933 */
1934 u32 rx_ota_err_cnt[HTT_MAX_RX_OTA_ERR_CNT];
1935};
1936
1937struct htt_phy_stats_tlv {
1938 /* per chain hw noise floor values in dBm */
1939 s32 nf_chain[HTT_STATS_MAX_CHAINS];
1940 /* number of false radars detected */
1941 u32 false_radar_cnt;
1942 /* number of channel switches happened due to radar detection */
1943 u32 radar_cs_cnt;
1944 /* ani_level -
1945 * ANI level (noise interference) corresponds to the channel
1946 * the desense levels range from -5 to 15 in dB units,
1947 * higher values indicating more noise interference.
1948 */
1949 s32 ani_level;
1950 /* running time in minutes since FW boot */
1951 u32 fw_run_time;
1952};
1953
1954struct htt_peer_ctrl_path_txrx_stats_tlv {
1955 /* peer mac address */
1956 u8 peer_mac_addr[ETH_ALEN];
1957 u8 rsvd[2];
1958 /* Num of tx mgmt frames with subtype on peer level */
1959 u32 peer_tx_mgmt_subtype[ATH11K_STATS_MGMT_FRM_TYPE_MAX];
1960 /* Num of rx mgmt frames with subtype on peer level */
1961 u32 peer_rx_mgmt_subtype[ATH11K_STATS_MGMT_FRM_TYPE_MAX];
1962};
1963
1964#ifdef CONFIG_ATH11K_DEBUGFS
1965
1966void ath11k_debugfs_htt_stats_init(struct ath11k *ar);
1967void ath11k_debugfs_htt_ext_stats_handler(struct ath11k_base *ab,
1968 struct sk_buff *skb);
1969int ath11k_debugfs_htt_stats_req(struct ath11k *ar);
1970
1971#else /* CONFIG_ATH11K_DEBUGFS */
1972
1973static inline void ath11k_debugfs_htt_stats_init(struct ath11k *ar)
1974{
1975}
1976
1977static inline void ath11k_debugfs_htt_ext_stats_handler(struct ath11k_base *ab,
1978 struct sk_buff *skb)
1979{
1980}
1981
1982static inline int ath11k_debugfs_htt_stats_req(struct ath11k *ar)
1983{
1984 return 0;
1985}
1986
1987#endif /* CONFIG_ATH11K_DEBUGFS */
1988
1989#endif