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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * OMAP mailbox driver
4 *
5 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
6 * Copyright (C) 2013-2021 Texas Instruments Incorporated - https://www.ti.com
7 *
8 * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
9 * Suman Anna <s-anna@ti.com>
10 */
11
12#include <linux/interrupt.h>
13#include <linux/spinlock.h>
14#include <linux/mutex.h>
15#include <linux/slab.h>
16#include <linux/kfifo.h>
17#include <linux/err.h>
18#include <linux/module.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/omap-mailbox.h>
23#include <linux/mailbox_controller.h>
24#include <linux/mailbox_client.h>
25
26#include "mailbox.h"
27
28#define MAILBOX_REVISION 0x000
29#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
30#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
31#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
32
33#define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
34#define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
35
36#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
37#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
38#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
39
40#define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \
41 OMAP2_MAILBOX_IRQSTATUS(u))
42#define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \
43 OMAP2_MAILBOX_IRQENABLE(u))
44#define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \
45 : OMAP2_MAILBOX_IRQENABLE(u))
46
47#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
48#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
49
50/* Interrupt register configuration types */
51#define MBOX_INTR_CFG_TYPE1 0
52#define MBOX_INTR_CFG_TYPE2 1
53
54struct omap_mbox_fifo {
55 unsigned long msg;
56 unsigned long fifo_stat;
57 unsigned long msg_stat;
58 unsigned long irqenable;
59 unsigned long irqstatus;
60 unsigned long irqdisable;
61 u32 intr_bit;
62};
63
64struct omap_mbox_queue {
65 spinlock_t lock;
66 struct kfifo fifo;
67 struct work_struct work;
68 struct omap_mbox *mbox;
69 bool full;
70};
71
72struct omap_mbox_match_data {
73 u32 intr_type;
74};
75
76struct omap_mbox_device {
77 struct device *dev;
78 struct mutex cfg_lock;
79 void __iomem *mbox_base;
80 u32 *irq_ctx;
81 u32 num_users;
82 u32 num_fifos;
83 u32 intr_type;
84 struct omap_mbox **mboxes;
85 struct mbox_controller controller;
86 struct list_head elem;
87};
88
89struct omap_mbox_fifo_info {
90 int tx_id;
91 int tx_usr;
92 int tx_irq;
93
94 int rx_id;
95 int rx_usr;
96 int rx_irq;
97
98 const char *name;
99 bool send_no_irq;
100};
101
102struct omap_mbox {
103 const char *name;
104 int irq;
105 struct omap_mbox_queue *rxq;
106 struct device *dev;
107 struct omap_mbox_device *parent;
108 struct omap_mbox_fifo tx_fifo;
109 struct omap_mbox_fifo rx_fifo;
110 u32 intr_type;
111 struct mbox_chan *chan;
112 bool send_no_irq;
113};
114
115/* global variables for the mailbox devices */
116static DEFINE_MUTEX(omap_mbox_devices_lock);
117static LIST_HEAD(omap_mbox_devices);
118
119static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
120module_param(mbox_kfifo_size, uint, S_IRUGO);
121MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
122
123static struct omap_mbox *mbox_chan_to_omap_mbox(struct mbox_chan *chan)
124{
125 if (!chan || !chan->con_priv)
126 return NULL;
127
128 return (struct omap_mbox *)chan->con_priv;
129}
130
131static inline
132unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs)
133{
134 return __raw_readl(mdev->mbox_base + ofs);
135}
136
137static inline
138void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs)
139{
140 __raw_writel(val, mdev->mbox_base + ofs);
141}
142
143/* Mailbox FIFO handle functions */
144static u32 mbox_fifo_read(struct omap_mbox *mbox)
145{
146 struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
147
148 return mbox_read_reg(mbox->parent, fifo->msg);
149}
150
151static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg)
152{
153 struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
154
155 mbox_write_reg(mbox->parent, msg, fifo->msg);
156}
157
158static int mbox_fifo_empty(struct omap_mbox *mbox)
159{
160 struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
161
162 return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0);
163}
164
165static int mbox_fifo_full(struct omap_mbox *mbox)
166{
167 struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
168
169 return mbox_read_reg(mbox->parent, fifo->fifo_stat);
170}
171
172/* Mailbox IRQ handle functions */
173static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
174{
175 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
176 &mbox->tx_fifo : &mbox->rx_fifo;
177 u32 bit = fifo->intr_bit;
178 u32 irqstatus = fifo->irqstatus;
179
180 mbox_write_reg(mbox->parent, bit, irqstatus);
181
182 /* Flush posted write for irq status to avoid spurious interrupts */
183 mbox_read_reg(mbox->parent, irqstatus);
184}
185
186static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
187{
188 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
189 &mbox->tx_fifo : &mbox->rx_fifo;
190 u32 bit = fifo->intr_bit;
191 u32 irqenable = fifo->irqenable;
192 u32 irqstatus = fifo->irqstatus;
193
194 u32 enable = mbox_read_reg(mbox->parent, irqenable);
195 u32 status = mbox_read_reg(mbox->parent, irqstatus);
196
197 return (int)(enable & status & bit);
198}
199
200static void _omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
201{
202 u32 l;
203 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
204 &mbox->tx_fifo : &mbox->rx_fifo;
205 u32 bit = fifo->intr_bit;
206 u32 irqenable = fifo->irqenable;
207
208 l = mbox_read_reg(mbox->parent, irqenable);
209 l |= bit;
210 mbox_write_reg(mbox->parent, l, irqenable);
211}
212
213static void _omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
214{
215 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
216 &mbox->tx_fifo : &mbox->rx_fifo;
217 u32 bit = fifo->intr_bit;
218 u32 irqdisable = fifo->irqdisable;
219
220 /*
221 * Read and update the interrupt configuration register for pre-OMAP4.
222 * OMAP4 and later SoCs have a dedicated interrupt disabling register.
223 */
224 if (!mbox->intr_type)
225 bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit;
226
227 mbox_write_reg(mbox->parent, bit, irqdisable);
228}
229
230void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
231{
232 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
233
234 if (WARN_ON(!mbox))
235 return;
236
237 _omap_mbox_enable_irq(mbox, irq);
238}
239EXPORT_SYMBOL(omap_mbox_enable_irq);
240
241void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
242{
243 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
244
245 if (WARN_ON(!mbox))
246 return;
247
248 _omap_mbox_disable_irq(mbox, irq);
249}
250EXPORT_SYMBOL(omap_mbox_disable_irq);
251
252/*
253 * Message receiver(workqueue)
254 */
255static void mbox_rx_work(struct work_struct *work)
256{
257 struct omap_mbox_queue *mq =
258 container_of(work, struct omap_mbox_queue, work);
259 mbox_msg_t data;
260 u32 msg;
261 int len;
262
263 while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
264 len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
265 WARN_ON(len != sizeof(msg));
266 data = msg;
267
268 mbox_chan_received_data(mq->mbox->chan, (void *)data);
269 spin_lock_irq(&mq->lock);
270 if (mq->full) {
271 mq->full = false;
272 _omap_mbox_enable_irq(mq->mbox, IRQ_RX);
273 }
274 spin_unlock_irq(&mq->lock);
275 }
276}
277
278/*
279 * Mailbox interrupt handler
280 */
281static void __mbox_tx_interrupt(struct omap_mbox *mbox)
282{
283 _omap_mbox_disable_irq(mbox, IRQ_TX);
284 ack_mbox_irq(mbox, IRQ_TX);
285 mbox_chan_txdone(mbox->chan, 0);
286}
287
288static void __mbox_rx_interrupt(struct omap_mbox *mbox)
289{
290 struct omap_mbox_queue *mq = mbox->rxq;
291 u32 msg;
292 int len;
293
294 while (!mbox_fifo_empty(mbox)) {
295 if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
296 _omap_mbox_disable_irq(mbox, IRQ_RX);
297 mq->full = true;
298 goto nomem;
299 }
300
301 msg = mbox_fifo_read(mbox);
302
303 len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
304 WARN_ON(len != sizeof(msg));
305 }
306
307 /* no more messages in the fifo. clear IRQ source. */
308 ack_mbox_irq(mbox, IRQ_RX);
309nomem:
310 schedule_work(&mbox->rxq->work);
311}
312
313static irqreturn_t mbox_interrupt(int irq, void *p)
314{
315 struct omap_mbox *mbox = p;
316
317 if (is_mbox_irq(mbox, IRQ_TX))
318 __mbox_tx_interrupt(mbox);
319
320 if (is_mbox_irq(mbox, IRQ_RX))
321 __mbox_rx_interrupt(mbox);
322
323 return IRQ_HANDLED;
324}
325
326static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
327 void (*work)(struct work_struct *))
328{
329 struct omap_mbox_queue *mq;
330
331 if (!work)
332 return NULL;
333
334 mq = kzalloc(sizeof(*mq), GFP_KERNEL);
335 if (!mq)
336 return NULL;
337
338 spin_lock_init(&mq->lock);
339
340 if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
341 goto error;
342
343 INIT_WORK(&mq->work, work);
344 return mq;
345
346error:
347 kfree(mq);
348 return NULL;
349}
350
351static void mbox_queue_free(struct omap_mbox_queue *q)
352{
353 kfifo_free(&q->fifo);
354 kfree(q);
355}
356
357static int omap_mbox_startup(struct omap_mbox *mbox)
358{
359 int ret = 0;
360 struct omap_mbox_queue *mq;
361
362 mq = mbox_queue_alloc(mbox, mbox_rx_work);
363 if (!mq)
364 return -ENOMEM;
365 mbox->rxq = mq;
366 mq->mbox = mbox;
367
368 ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
369 mbox->name, mbox);
370 if (unlikely(ret)) {
371 pr_err("failed to register mailbox interrupt:%d\n", ret);
372 goto fail_request_irq;
373 }
374
375 if (mbox->send_no_irq)
376 mbox->chan->txdone_method = TXDONE_BY_ACK;
377
378 _omap_mbox_enable_irq(mbox, IRQ_RX);
379
380 return 0;
381
382fail_request_irq:
383 mbox_queue_free(mbox->rxq);
384 return ret;
385}
386
387static void omap_mbox_fini(struct omap_mbox *mbox)
388{
389 _omap_mbox_disable_irq(mbox, IRQ_RX);
390 free_irq(mbox->irq, mbox);
391 flush_work(&mbox->rxq->work);
392 mbox_queue_free(mbox->rxq);
393}
394
395static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev,
396 const char *mbox_name)
397{
398 struct omap_mbox *_mbox, *mbox = NULL;
399 struct omap_mbox **mboxes = mdev->mboxes;
400 int i;
401
402 if (!mboxes)
403 return NULL;
404
405 for (i = 0; (_mbox = mboxes[i]); i++) {
406 if (!strcmp(_mbox->name, mbox_name)) {
407 mbox = _mbox;
408 break;
409 }
410 }
411 return mbox;
412}
413
414struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl,
415 const char *chan_name)
416{
417 struct device *dev = cl->dev;
418 struct omap_mbox *mbox = NULL;
419 struct omap_mbox_device *mdev;
420 struct mbox_chan *chan;
421 unsigned long flags;
422 int ret;
423
424 if (!dev)
425 return ERR_PTR(-ENODEV);
426
427 if (dev->of_node) {
428 pr_err("%s: please use mbox_request_channel(), this API is supported only for OMAP non-DT usage\n",
429 __func__);
430 return ERR_PTR(-ENODEV);
431 }
432
433 mutex_lock(&omap_mbox_devices_lock);
434 list_for_each_entry(mdev, &omap_mbox_devices, elem) {
435 mbox = omap_mbox_device_find(mdev, chan_name);
436 if (mbox)
437 break;
438 }
439 mutex_unlock(&omap_mbox_devices_lock);
440
441 if (!mbox || !mbox->chan)
442 return ERR_PTR(-ENOENT);
443
444 chan = mbox->chan;
445 spin_lock_irqsave(&chan->lock, flags);
446 chan->msg_free = 0;
447 chan->msg_count = 0;
448 chan->active_req = NULL;
449 chan->cl = cl;
450 init_completion(&chan->tx_complete);
451 spin_unlock_irqrestore(&chan->lock, flags);
452
453 ret = chan->mbox->ops->startup(chan);
454 if (ret) {
455 pr_err("Unable to startup the chan (%d)\n", ret);
456 mbox_free_channel(chan);
457 chan = ERR_PTR(ret);
458 }
459
460 return chan;
461}
462EXPORT_SYMBOL(omap_mbox_request_channel);
463
464static struct class omap_mbox_class = { .name = "mbox", };
465
466static int omap_mbox_register(struct omap_mbox_device *mdev)
467{
468 int ret;
469 int i;
470 struct omap_mbox **mboxes;
471
472 if (!mdev || !mdev->mboxes)
473 return -EINVAL;
474
475 mboxes = mdev->mboxes;
476 for (i = 0; mboxes[i]; i++) {
477 struct omap_mbox *mbox = mboxes[i];
478
479 mbox->dev = device_create(&omap_mbox_class, mdev->dev,
480 0, mbox, "%s", mbox->name);
481 if (IS_ERR(mbox->dev)) {
482 ret = PTR_ERR(mbox->dev);
483 goto err_out;
484 }
485 }
486
487 mutex_lock(&omap_mbox_devices_lock);
488 list_add(&mdev->elem, &omap_mbox_devices);
489 mutex_unlock(&omap_mbox_devices_lock);
490
491 ret = devm_mbox_controller_register(mdev->dev, &mdev->controller);
492
493err_out:
494 if (ret) {
495 while (i--)
496 device_unregister(mboxes[i]->dev);
497 }
498 return ret;
499}
500
501static int omap_mbox_unregister(struct omap_mbox_device *mdev)
502{
503 int i;
504 struct omap_mbox **mboxes;
505
506 if (!mdev || !mdev->mboxes)
507 return -EINVAL;
508
509 mutex_lock(&omap_mbox_devices_lock);
510 list_del(&mdev->elem);
511 mutex_unlock(&omap_mbox_devices_lock);
512
513 mboxes = mdev->mboxes;
514 for (i = 0; mboxes[i]; i++)
515 device_unregister(mboxes[i]->dev);
516 return 0;
517}
518
519static int omap_mbox_chan_startup(struct mbox_chan *chan)
520{
521 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
522 struct omap_mbox_device *mdev = mbox->parent;
523 int ret = 0;
524
525 mutex_lock(&mdev->cfg_lock);
526 pm_runtime_get_sync(mdev->dev);
527 ret = omap_mbox_startup(mbox);
528 if (ret)
529 pm_runtime_put_sync(mdev->dev);
530 mutex_unlock(&mdev->cfg_lock);
531 return ret;
532}
533
534static void omap_mbox_chan_shutdown(struct mbox_chan *chan)
535{
536 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
537 struct omap_mbox_device *mdev = mbox->parent;
538
539 mutex_lock(&mdev->cfg_lock);
540 omap_mbox_fini(mbox);
541 pm_runtime_put_sync(mdev->dev);
542 mutex_unlock(&mdev->cfg_lock);
543}
544
545static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, u32 msg)
546{
547 int ret = -EBUSY;
548
549 if (!mbox_fifo_full(mbox)) {
550 _omap_mbox_enable_irq(mbox, IRQ_RX);
551 mbox_fifo_write(mbox, msg);
552 ret = 0;
553 _omap_mbox_disable_irq(mbox, IRQ_RX);
554
555 /* we must read and ack the interrupt directly from here */
556 mbox_fifo_read(mbox);
557 ack_mbox_irq(mbox, IRQ_RX);
558 }
559
560 return ret;
561}
562
563static int omap_mbox_chan_send(struct omap_mbox *mbox, u32 msg)
564{
565 int ret = -EBUSY;
566
567 if (!mbox_fifo_full(mbox)) {
568 mbox_fifo_write(mbox, msg);
569 ret = 0;
570 }
571
572 /* always enable the interrupt */
573 _omap_mbox_enable_irq(mbox, IRQ_TX);
574 return ret;
575}
576
577static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data)
578{
579 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
580 int ret;
581 u32 msg = omap_mbox_message(data);
582
583 if (!mbox)
584 return -EINVAL;
585
586 if (mbox->send_no_irq)
587 ret = omap_mbox_chan_send_noirq(mbox, msg);
588 else
589 ret = omap_mbox_chan_send(mbox, msg);
590
591 return ret;
592}
593
594static const struct mbox_chan_ops omap_mbox_chan_ops = {
595 .startup = omap_mbox_chan_startup,
596 .send_data = omap_mbox_chan_send_data,
597 .shutdown = omap_mbox_chan_shutdown,
598};
599
600#ifdef CONFIG_PM_SLEEP
601static int omap_mbox_suspend(struct device *dev)
602{
603 struct omap_mbox_device *mdev = dev_get_drvdata(dev);
604 u32 usr, fifo, reg;
605
606 if (pm_runtime_status_suspended(dev))
607 return 0;
608
609 for (fifo = 0; fifo < mdev->num_fifos; fifo++) {
610 if (mbox_read_reg(mdev, MAILBOX_MSGSTATUS(fifo))) {
611 dev_err(mdev->dev, "fifo %d has unexpected unread messages\n",
612 fifo);
613 return -EBUSY;
614 }
615 }
616
617 for (usr = 0; usr < mdev->num_users; usr++) {
618 reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
619 mdev->irq_ctx[usr] = mbox_read_reg(mdev, reg);
620 }
621
622 return 0;
623}
624
625static int omap_mbox_resume(struct device *dev)
626{
627 struct omap_mbox_device *mdev = dev_get_drvdata(dev);
628 u32 usr, reg;
629
630 if (pm_runtime_status_suspended(dev))
631 return 0;
632
633 for (usr = 0; usr < mdev->num_users; usr++) {
634 reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
635 mbox_write_reg(mdev, mdev->irq_ctx[usr], reg);
636 }
637
638 return 0;
639}
640#endif
641
642static const struct dev_pm_ops omap_mbox_pm_ops = {
643 SET_SYSTEM_SLEEP_PM_OPS(omap_mbox_suspend, omap_mbox_resume)
644};
645
646static const struct omap_mbox_match_data omap2_data = { MBOX_INTR_CFG_TYPE1 };
647static const struct omap_mbox_match_data omap4_data = { MBOX_INTR_CFG_TYPE2 };
648
649static const struct of_device_id omap_mailbox_of_match[] = {
650 {
651 .compatible = "ti,omap2-mailbox",
652 .data = &omap2_data,
653 },
654 {
655 .compatible = "ti,omap3-mailbox",
656 .data = &omap2_data,
657 },
658 {
659 .compatible = "ti,omap4-mailbox",
660 .data = &omap4_data,
661 },
662 {
663 .compatible = "ti,am654-mailbox",
664 .data = &omap4_data,
665 },
666 {
667 .compatible = "ti,am64-mailbox",
668 .data = &omap4_data,
669 },
670 {
671 /* end */
672 },
673};
674MODULE_DEVICE_TABLE(of, omap_mailbox_of_match);
675
676static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller,
677 const struct of_phandle_args *sp)
678{
679 phandle phandle = sp->args[0];
680 struct device_node *node;
681 struct omap_mbox_device *mdev;
682 struct omap_mbox *mbox;
683
684 mdev = container_of(controller, struct omap_mbox_device, controller);
685 if (WARN_ON(!mdev))
686 return ERR_PTR(-EINVAL);
687
688 node = of_find_node_by_phandle(phandle);
689 if (!node) {
690 pr_err("%s: could not find node phandle 0x%x\n",
691 __func__, phandle);
692 return ERR_PTR(-ENODEV);
693 }
694
695 mbox = omap_mbox_device_find(mdev, node->name);
696 of_node_put(node);
697 return mbox ? mbox->chan : ERR_PTR(-ENOENT);
698}
699
700static int omap_mbox_probe(struct platform_device *pdev)
701{
702 int ret;
703 struct mbox_chan *chnls;
704 struct omap_mbox **list, *mbox, *mboxblk;
705 struct omap_mbox_fifo_info *finfo, *finfoblk;
706 struct omap_mbox_device *mdev;
707 struct omap_mbox_fifo *fifo;
708 struct device_node *node = pdev->dev.of_node;
709 struct device_node *child;
710 const struct omap_mbox_match_data *match_data;
711 u32 intr_type, info_count;
712 u32 num_users, num_fifos;
713 u32 tmp[3];
714 u32 l;
715 int i;
716
717 if (!node) {
718 pr_err("%s: only DT-based devices are supported\n", __func__);
719 return -ENODEV;
720 }
721
722 match_data = of_device_get_match_data(&pdev->dev);
723 if (!match_data)
724 return -ENODEV;
725 intr_type = match_data->intr_type;
726
727 if (of_property_read_u32(node, "ti,mbox-num-users", &num_users))
728 return -ENODEV;
729
730 if (of_property_read_u32(node, "ti,mbox-num-fifos", &num_fifos))
731 return -ENODEV;
732
733 info_count = of_get_available_child_count(node);
734 if (!info_count) {
735 dev_err(&pdev->dev, "no available mbox devices found\n");
736 return -ENODEV;
737 }
738
739 finfoblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*finfoblk),
740 GFP_KERNEL);
741 if (!finfoblk)
742 return -ENOMEM;
743
744 finfo = finfoblk;
745 child = NULL;
746 for (i = 0; i < info_count; i++, finfo++) {
747 child = of_get_next_available_child(node, child);
748 ret = of_property_read_u32_array(child, "ti,mbox-tx", tmp,
749 ARRAY_SIZE(tmp));
750 if (ret)
751 return ret;
752 finfo->tx_id = tmp[0];
753 finfo->tx_irq = tmp[1];
754 finfo->tx_usr = tmp[2];
755
756 ret = of_property_read_u32_array(child, "ti,mbox-rx", tmp,
757 ARRAY_SIZE(tmp));
758 if (ret)
759 return ret;
760 finfo->rx_id = tmp[0];
761 finfo->rx_irq = tmp[1];
762 finfo->rx_usr = tmp[2];
763
764 finfo->name = child->name;
765
766 if (of_find_property(child, "ti,mbox-send-noirq", NULL))
767 finfo->send_no_irq = true;
768
769 if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos ||
770 finfo->tx_usr >= num_users || finfo->rx_usr >= num_users)
771 return -EINVAL;
772 }
773
774 mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL);
775 if (!mdev)
776 return -ENOMEM;
777
778 mdev->mbox_base = devm_platform_ioremap_resource(pdev, 0);
779 if (IS_ERR(mdev->mbox_base))
780 return PTR_ERR(mdev->mbox_base);
781
782 mdev->irq_ctx = devm_kcalloc(&pdev->dev, num_users, sizeof(u32),
783 GFP_KERNEL);
784 if (!mdev->irq_ctx)
785 return -ENOMEM;
786
787 /* allocate one extra for marking end of list */
788 list = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*list),
789 GFP_KERNEL);
790 if (!list)
791 return -ENOMEM;
792
793 chnls = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*chnls),
794 GFP_KERNEL);
795 if (!chnls)
796 return -ENOMEM;
797
798 mboxblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*mbox),
799 GFP_KERNEL);
800 if (!mboxblk)
801 return -ENOMEM;
802
803 mbox = mboxblk;
804 finfo = finfoblk;
805 for (i = 0; i < info_count; i++, finfo++) {
806 fifo = &mbox->tx_fifo;
807 fifo->msg = MAILBOX_MESSAGE(finfo->tx_id);
808 fifo->fifo_stat = MAILBOX_FIFOSTATUS(finfo->tx_id);
809 fifo->intr_bit = MAILBOX_IRQ_NOTFULL(finfo->tx_id);
810 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->tx_usr);
811 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->tx_usr);
812 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->tx_usr);
813
814 fifo = &mbox->rx_fifo;
815 fifo->msg = MAILBOX_MESSAGE(finfo->rx_id);
816 fifo->msg_stat = MAILBOX_MSGSTATUS(finfo->rx_id);
817 fifo->intr_bit = MAILBOX_IRQ_NEWMSG(finfo->rx_id);
818 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->rx_usr);
819 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->rx_usr);
820 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->rx_usr);
821
822 mbox->send_no_irq = finfo->send_no_irq;
823 mbox->intr_type = intr_type;
824
825 mbox->parent = mdev;
826 mbox->name = finfo->name;
827 mbox->irq = platform_get_irq(pdev, finfo->tx_irq);
828 if (mbox->irq < 0)
829 return mbox->irq;
830 mbox->chan = &chnls[i];
831 chnls[i].con_priv = mbox;
832 list[i] = mbox++;
833 }
834
835 mutex_init(&mdev->cfg_lock);
836 mdev->dev = &pdev->dev;
837 mdev->num_users = num_users;
838 mdev->num_fifos = num_fifos;
839 mdev->intr_type = intr_type;
840 mdev->mboxes = list;
841
842 /*
843 * OMAP/K3 Mailbox IP does not have a Tx-Done IRQ, but rather a Tx-Ready
844 * IRQ and is needed to run the Tx state machine
845 */
846 mdev->controller.txdone_irq = true;
847 mdev->controller.dev = mdev->dev;
848 mdev->controller.ops = &omap_mbox_chan_ops;
849 mdev->controller.chans = chnls;
850 mdev->controller.num_chans = info_count;
851 mdev->controller.of_xlate = omap_mbox_of_xlate;
852 ret = omap_mbox_register(mdev);
853 if (ret)
854 return ret;
855
856 platform_set_drvdata(pdev, mdev);
857 pm_runtime_enable(mdev->dev);
858
859 ret = pm_runtime_resume_and_get(mdev->dev);
860 if (ret < 0)
861 goto unregister;
862
863 /*
864 * just print the raw revision register, the format is not
865 * uniform across all SoCs
866 */
867 l = mbox_read_reg(mdev, MAILBOX_REVISION);
868 dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l);
869
870 ret = pm_runtime_put_sync(mdev->dev);
871 if (ret < 0 && ret != -ENOSYS)
872 goto unregister;
873
874 devm_kfree(&pdev->dev, finfoblk);
875 return 0;
876
877unregister:
878 pm_runtime_disable(mdev->dev);
879 omap_mbox_unregister(mdev);
880 return ret;
881}
882
883static int omap_mbox_remove(struct platform_device *pdev)
884{
885 struct omap_mbox_device *mdev = platform_get_drvdata(pdev);
886
887 pm_runtime_disable(mdev->dev);
888 omap_mbox_unregister(mdev);
889
890 return 0;
891}
892
893static struct platform_driver omap_mbox_driver = {
894 .probe = omap_mbox_probe,
895 .remove = omap_mbox_remove,
896 .driver = {
897 .name = "omap-mailbox",
898 .pm = &omap_mbox_pm_ops,
899 .of_match_table = of_match_ptr(omap_mailbox_of_match),
900 },
901};
902
903static int __init omap_mbox_init(void)
904{
905 int err;
906
907 err = class_register(&omap_mbox_class);
908 if (err)
909 return err;
910
911 /* kfifo size sanity check: alignment and minimal size */
912 mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(u32));
913 mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(u32));
914
915 err = platform_driver_register(&omap_mbox_driver);
916 if (err)
917 class_unregister(&omap_mbox_class);
918
919 return err;
920}
921subsys_initcall(omap_mbox_init);
922
923static void __exit omap_mbox_exit(void)
924{
925 platform_driver_unregister(&omap_mbox_driver);
926 class_unregister(&omap_mbox_class);
927}
928module_exit(omap_mbox_exit);
929
930MODULE_LICENSE("GPL v2");
931MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
932MODULE_AUTHOR("Toshihiro Kobayashi");
933MODULE_AUTHOR("Hiroshi DOYU");
1/*
2 * OMAP mailbox driver
3 *
4 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
5 * Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8 * Suman Anna <s-anna@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 */
19
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
22#include <linux/mutex.h>
23#include <linux/slab.h>
24#include <linux/kfifo.h>
25#include <linux/err.h>
26#include <linux/module.h>
27#include <linux/of_device.h>
28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
30#include <linux/omap-mailbox.h>
31#include <linux/mailbox_controller.h>
32#include <linux/mailbox_client.h>
33
34#include "mailbox.h"
35
36#define MAILBOX_REVISION 0x000
37#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
38#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
39#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
40
41#define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
42#define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
43
44#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
45#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
46#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
47
48#define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \
49 OMAP2_MAILBOX_IRQSTATUS(u))
50#define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \
51 OMAP2_MAILBOX_IRQENABLE(u))
52#define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \
53 : OMAP2_MAILBOX_IRQENABLE(u))
54
55#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
56#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
57
58/* Interrupt register configuration types */
59#define MBOX_INTR_CFG_TYPE1 0
60#define MBOX_INTR_CFG_TYPE2 1
61
62struct omap_mbox_fifo {
63 unsigned long msg;
64 unsigned long fifo_stat;
65 unsigned long msg_stat;
66 unsigned long irqenable;
67 unsigned long irqstatus;
68 unsigned long irqdisable;
69 u32 intr_bit;
70};
71
72struct omap_mbox_queue {
73 spinlock_t lock;
74 struct kfifo fifo;
75 struct work_struct work;
76 struct omap_mbox *mbox;
77 bool full;
78};
79
80struct omap_mbox_device {
81 struct device *dev;
82 struct mutex cfg_lock;
83 void __iomem *mbox_base;
84 u32 *irq_ctx;
85 u32 num_users;
86 u32 num_fifos;
87 u32 intr_type;
88 struct omap_mbox **mboxes;
89 struct mbox_controller controller;
90 struct list_head elem;
91};
92
93struct omap_mbox_fifo_info {
94 int tx_id;
95 int tx_usr;
96 int tx_irq;
97
98 int rx_id;
99 int rx_usr;
100 int rx_irq;
101
102 const char *name;
103 bool send_no_irq;
104};
105
106struct omap_mbox {
107 const char *name;
108 int irq;
109 struct omap_mbox_queue *rxq;
110 struct device *dev;
111 struct omap_mbox_device *parent;
112 struct omap_mbox_fifo tx_fifo;
113 struct omap_mbox_fifo rx_fifo;
114 u32 intr_type;
115 struct mbox_chan *chan;
116 bool send_no_irq;
117};
118
119/* global variables for the mailbox devices */
120static DEFINE_MUTEX(omap_mbox_devices_lock);
121static LIST_HEAD(omap_mbox_devices);
122
123static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
124module_param(mbox_kfifo_size, uint, S_IRUGO);
125MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
126
127static struct omap_mbox *mbox_chan_to_omap_mbox(struct mbox_chan *chan)
128{
129 if (!chan || !chan->con_priv)
130 return NULL;
131
132 return (struct omap_mbox *)chan->con_priv;
133}
134
135static inline
136unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs)
137{
138 return __raw_readl(mdev->mbox_base + ofs);
139}
140
141static inline
142void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs)
143{
144 __raw_writel(val, mdev->mbox_base + ofs);
145}
146
147/* Mailbox FIFO handle functions */
148static mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
149{
150 struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
151
152 return (mbox_msg_t)mbox_read_reg(mbox->parent, fifo->msg);
153}
154
155static void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
156{
157 struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
158
159 mbox_write_reg(mbox->parent, msg, fifo->msg);
160}
161
162static int mbox_fifo_empty(struct omap_mbox *mbox)
163{
164 struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
165
166 return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0);
167}
168
169static int mbox_fifo_full(struct omap_mbox *mbox)
170{
171 struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
172
173 return mbox_read_reg(mbox->parent, fifo->fifo_stat);
174}
175
176/* Mailbox IRQ handle functions */
177static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
178{
179 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
180 &mbox->tx_fifo : &mbox->rx_fifo;
181 u32 bit = fifo->intr_bit;
182 u32 irqstatus = fifo->irqstatus;
183
184 mbox_write_reg(mbox->parent, bit, irqstatus);
185
186 /* Flush posted write for irq status to avoid spurious interrupts */
187 mbox_read_reg(mbox->parent, irqstatus);
188}
189
190static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
191{
192 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
193 &mbox->tx_fifo : &mbox->rx_fifo;
194 u32 bit = fifo->intr_bit;
195 u32 irqenable = fifo->irqenable;
196 u32 irqstatus = fifo->irqstatus;
197
198 u32 enable = mbox_read_reg(mbox->parent, irqenable);
199 u32 status = mbox_read_reg(mbox->parent, irqstatus);
200
201 return (int)(enable & status & bit);
202}
203
204static void _omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
205{
206 u32 l;
207 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
208 &mbox->tx_fifo : &mbox->rx_fifo;
209 u32 bit = fifo->intr_bit;
210 u32 irqenable = fifo->irqenable;
211
212 l = mbox_read_reg(mbox->parent, irqenable);
213 l |= bit;
214 mbox_write_reg(mbox->parent, l, irqenable);
215}
216
217static void _omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
218{
219 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
220 &mbox->tx_fifo : &mbox->rx_fifo;
221 u32 bit = fifo->intr_bit;
222 u32 irqdisable = fifo->irqdisable;
223
224 /*
225 * Read and update the interrupt configuration register for pre-OMAP4.
226 * OMAP4 and later SoCs have a dedicated interrupt disabling register.
227 */
228 if (!mbox->intr_type)
229 bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit;
230
231 mbox_write_reg(mbox->parent, bit, irqdisable);
232}
233
234void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
235{
236 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
237
238 if (WARN_ON(!mbox))
239 return;
240
241 _omap_mbox_enable_irq(mbox, irq);
242}
243EXPORT_SYMBOL(omap_mbox_enable_irq);
244
245void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
246{
247 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
248
249 if (WARN_ON(!mbox))
250 return;
251
252 _omap_mbox_disable_irq(mbox, irq);
253}
254EXPORT_SYMBOL(omap_mbox_disable_irq);
255
256/*
257 * Message receiver(workqueue)
258 */
259static void mbox_rx_work(struct work_struct *work)
260{
261 struct omap_mbox_queue *mq =
262 container_of(work, struct omap_mbox_queue, work);
263 mbox_msg_t msg;
264 int len;
265
266 while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
267 len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
268 WARN_ON(len != sizeof(msg));
269
270 mbox_chan_received_data(mq->mbox->chan, (void *)msg);
271 spin_lock_irq(&mq->lock);
272 if (mq->full) {
273 mq->full = false;
274 _omap_mbox_enable_irq(mq->mbox, IRQ_RX);
275 }
276 spin_unlock_irq(&mq->lock);
277 }
278}
279
280/*
281 * Mailbox interrupt handler
282 */
283static void __mbox_tx_interrupt(struct omap_mbox *mbox)
284{
285 _omap_mbox_disable_irq(mbox, IRQ_TX);
286 ack_mbox_irq(mbox, IRQ_TX);
287 mbox_chan_txdone(mbox->chan, 0);
288}
289
290static void __mbox_rx_interrupt(struct omap_mbox *mbox)
291{
292 struct omap_mbox_queue *mq = mbox->rxq;
293 mbox_msg_t msg;
294 int len;
295
296 while (!mbox_fifo_empty(mbox)) {
297 if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
298 _omap_mbox_disable_irq(mbox, IRQ_RX);
299 mq->full = true;
300 goto nomem;
301 }
302
303 msg = mbox_fifo_read(mbox);
304
305 len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
306 WARN_ON(len != sizeof(msg));
307 }
308
309 /* no more messages in the fifo. clear IRQ source. */
310 ack_mbox_irq(mbox, IRQ_RX);
311nomem:
312 schedule_work(&mbox->rxq->work);
313}
314
315static irqreturn_t mbox_interrupt(int irq, void *p)
316{
317 struct omap_mbox *mbox = p;
318
319 if (is_mbox_irq(mbox, IRQ_TX))
320 __mbox_tx_interrupt(mbox);
321
322 if (is_mbox_irq(mbox, IRQ_RX))
323 __mbox_rx_interrupt(mbox);
324
325 return IRQ_HANDLED;
326}
327
328static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
329 void (*work)(struct work_struct *))
330{
331 struct omap_mbox_queue *mq;
332
333 if (!work)
334 return NULL;
335
336 mq = kzalloc(sizeof(*mq), GFP_KERNEL);
337 if (!mq)
338 return NULL;
339
340 spin_lock_init(&mq->lock);
341
342 if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
343 goto error;
344
345 INIT_WORK(&mq->work, work);
346 return mq;
347
348error:
349 kfree(mq);
350 return NULL;
351}
352
353static void mbox_queue_free(struct omap_mbox_queue *q)
354{
355 kfifo_free(&q->fifo);
356 kfree(q);
357}
358
359static int omap_mbox_startup(struct omap_mbox *mbox)
360{
361 int ret = 0;
362 struct omap_mbox_queue *mq;
363
364 mq = mbox_queue_alloc(mbox, mbox_rx_work);
365 if (!mq)
366 return -ENOMEM;
367 mbox->rxq = mq;
368 mq->mbox = mbox;
369
370 ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
371 mbox->name, mbox);
372 if (unlikely(ret)) {
373 pr_err("failed to register mailbox interrupt:%d\n", ret);
374 goto fail_request_irq;
375 }
376
377 if (mbox->send_no_irq)
378 mbox->chan->txdone_method = TXDONE_BY_ACK;
379
380 _omap_mbox_enable_irq(mbox, IRQ_RX);
381
382 return 0;
383
384fail_request_irq:
385 mbox_queue_free(mbox->rxq);
386 return ret;
387}
388
389static void omap_mbox_fini(struct omap_mbox *mbox)
390{
391 _omap_mbox_disable_irq(mbox, IRQ_RX);
392 free_irq(mbox->irq, mbox);
393 flush_work(&mbox->rxq->work);
394 mbox_queue_free(mbox->rxq);
395}
396
397static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev,
398 const char *mbox_name)
399{
400 struct omap_mbox *_mbox, *mbox = NULL;
401 struct omap_mbox **mboxes = mdev->mboxes;
402 int i;
403
404 if (!mboxes)
405 return NULL;
406
407 for (i = 0; (_mbox = mboxes[i]); i++) {
408 if (!strcmp(_mbox->name, mbox_name)) {
409 mbox = _mbox;
410 break;
411 }
412 }
413 return mbox;
414}
415
416struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl,
417 const char *chan_name)
418{
419 struct device *dev = cl->dev;
420 struct omap_mbox *mbox = NULL;
421 struct omap_mbox_device *mdev;
422 struct mbox_chan *chan;
423 unsigned long flags;
424 int ret;
425
426 if (!dev)
427 return ERR_PTR(-ENODEV);
428
429 if (dev->of_node) {
430 pr_err("%s: please use mbox_request_channel(), this API is supported only for OMAP non-DT usage\n",
431 __func__);
432 return ERR_PTR(-ENODEV);
433 }
434
435 mutex_lock(&omap_mbox_devices_lock);
436 list_for_each_entry(mdev, &omap_mbox_devices, elem) {
437 mbox = omap_mbox_device_find(mdev, chan_name);
438 if (mbox)
439 break;
440 }
441 mutex_unlock(&omap_mbox_devices_lock);
442
443 if (!mbox || !mbox->chan)
444 return ERR_PTR(-ENOENT);
445
446 chan = mbox->chan;
447 spin_lock_irqsave(&chan->lock, flags);
448 chan->msg_free = 0;
449 chan->msg_count = 0;
450 chan->active_req = NULL;
451 chan->cl = cl;
452 init_completion(&chan->tx_complete);
453 spin_unlock_irqrestore(&chan->lock, flags);
454
455 ret = chan->mbox->ops->startup(chan);
456 if (ret) {
457 pr_err("Unable to startup the chan (%d)\n", ret);
458 mbox_free_channel(chan);
459 chan = ERR_PTR(ret);
460 }
461
462 return chan;
463}
464EXPORT_SYMBOL(omap_mbox_request_channel);
465
466static struct class omap_mbox_class = { .name = "mbox", };
467
468static int omap_mbox_register(struct omap_mbox_device *mdev)
469{
470 int ret;
471 int i;
472 struct omap_mbox **mboxes;
473
474 if (!mdev || !mdev->mboxes)
475 return -EINVAL;
476
477 mboxes = mdev->mboxes;
478 for (i = 0; mboxes[i]; i++) {
479 struct omap_mbox *mbox = mboxes[i];
480
481 mbox->dev = device_create(&omap_mbox_class, mdev->dev,
482 0, mbox, "%s", mbox->name);
483 if (IS_ERR(mbox->dev)) {
484 ret = PTR_ERR(mbox->dev);
485 goto err_out;
486 }
487 }
488
489 mutex_lock(&omap_mbox_devices_lock);
490 list_add(&mdev->elem, &omap_mbox_devices);
491 mutex_unlock(&omap_mbox_devices_lock);
492
493 ret = mbox_controller_register(&mdev->controller);
494
495err_out:
496 if (ret) {
497 while (i--)
498 device_unregister(mboxes[i]->dev);
499 }
500 return ret;
501}
502
503static int omap_mbox_unregister(struct omap_mbox_device *mdev)
504{
505 int i;
506 struct omap_mbox **mboxes;
507
508 if (!mdev || !mdev->mboxes)
509 return -EINVAL;
510
511 mutex_lock(&omap_mbox_devices_lock);
512 list_del(&mdev->elem);
513 mutex_unlock(&omap_mbox_devices_lock);
514
515 mbox_controller_unregister(&mdev->controller);
516
517 mboxes = mdev->mboxes;
518 for (i = 0; mboxes[i]; i++)
519 device_unregister(mboxes[i]->dev);
520 return 0;
521}
522
523static int omap_mbox_chan_startup(struct mbox_chan *chan)
524{
525 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
526 struct omap_mbox_device *mdev = mbox->parent;
527 int ret = 0;
528
529 mutex_lock(&mdev->cfg_lock);
530 pm_runtime_get_sync(mdev->dev);
531 ret = omap_mbox_startup(mbox);
532 if (ret)
533 pm_runtime_put_sync(mdev->dev);
534 mutex_unlock(&mdev->cfg_lock);
535 return ret;
536}
537
538static void omap_mbox_chan_shutdown(struct mbox_chan *chan)
539{
540 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
541 struct omap_mbox_device *mdev = mbox->parent;
542
543 mutex_lock(&mdev->cfg_lock);
544 omap_mbox_fini(mbox);
545 pm_runtime_put_sync(mdev->dev);
546 mutex_unlock(&mdev->cfg_lock);
547}
548
549static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data)
550{
551 int ret = -EBUSY;
552
553 if (!mbox_fifo_full(mbox)) {
554 _omap_mbox_enable_irq(mbox, IRQ_RX);
555 mbox_fifo_write(mbox, (mbox_msg_t)data);
556 ret = 0;
557 _omap_mbox_disable_irq(mbox, IRQ_RX);
558
559 /* we must read and ack the interrupt directly from here */
560 mbox_fifo_read(mbox);
561 ack_mbox_irq(mbox, IRQ_RX);
562 }
563
564 return ret;
565}
566
567static int omap_mbox_chan_send(struct omap_mbox *mbox, void *data)
568{
569 int ret = -EBUSY;
570
571 if (!mbox_fifo_full(mbox)) {
572 mbox_fifo_write(mbox, (mbox_msg_t)data);
573 ret = 0;
574 }
575
576 /* always enable the interrupt */
577 _omap_mbox_enable_irq(mbox, IRQ_TX);
578 return ret;
579}
580
581static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data)
582{
583 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
584 int ret;
585
586 if (!mbox)
587 return -EINVAL;
588
589 if (mbox->send_no_irq)
590 ret = omap_mbox_chan_send_noirq(mbox, data);
591 else
592 ret = omap_mbox_chan_send(mbox, data);
593
594 return ret;
595}
596
597static const struct mbox_chan_ops omap_mbox_chan_ops = {
598 .startup = omap_mbox_chan_startup,
599 .send_data = omap_mbox_chan_send_data,
600 .shutdown = omap_mbox_chan_shutdown,
601};
602
603#ifdef CONFIG_PM_SLEEP
604static int omap_mbox_suspend(struct device *dev)
605{
606 struct omap_mbox_device *mdev = dev_get_drvdata(dev);
607 u32 usr, fifo, reg;
608
609 if (pm_runtime_status_suspended(dev))
610 return 0;
611
612 for (fifo = 0; fifo < mdev->num_fifos; fifo++) {
613 if (mbox_read_reg(mdev, MAILBOX_MSGSTATUS(fifo))) {
614 dev_err(mdev->dev, "fifo %d has unexpected unread messages\n",
615 fifo);
616 return -EBUSY;
617 }
618 }
619
620 for (usr = 0; usr < mdev->num_users; usr++) {
621 reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
622 mdev->irq_ctx[usr] = mbox_read_reg(mdev, reg);
623 }
624
625 return 0;
626}
627
628static int omap_mbox_resume(struct device *dev)
629{
630 struct omap_mbox_device *mdev = dev_get_drvdata(dev);
631 u32 usr, reg;
632
633 if (pm_runtime_status_suspended(dev))
634 return 0;
635
636 for (usr = 0; usr < mdev->num_users; usr++) {
637 reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
638 mbox_write_reg(mdev, mdev->irq_ctx[usr], reg);
639 }
640
641 return 0;
642}
643#endif
644
645static const struct dev_pm_ops omap_mbox_pm_ops = {
646 SET_SYSTEM_SLEEP_PM_OPS(omap_mbox_suspend, omap_mbox_resume)
647};
648
649static const struct of_device_id omap_mailbox_of_match[] = {
650 {
651 .compatible = "ti,omap2-mailbox",
652 .data = (void *)MBOX_INTR_CFG_TYPE1,
653 },
654 {
655 .compatible = "ti,omap3-mailbox",
656 .data = (void *)MBOX_INTR_CFG_TYPE1,
657 },
658 {
659 .compatible = "ti,omap4-mailbox",
660 .data = (void *)MBOX_INTR_CFG_TYPE2,
661 },
662 {
663 /* end */
664 },
665};
666MODULE_DEVICE_TABLE(of, omap_mailbox_of_match);
667
668static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller,
669 const struct of_phandle_args *sp)
670{
671 phandle phandle = sp->args[0];
672 struct device_node *node;
673 struct omap_mbox_device *mdev;
674 struct omap_mbox *mbox;
675
676 mdev = container_of(controller, struct omap_mbox_device, controller);
677 if (WARN_ON(!mdev))
678 return ERR_PTR(-EINVAL);
679
680 node = of_find_node_by_phandle(phandle);
681 if (!node) {
682 pr_err("%s: could not find node phandle 0x%x\n",
683 __func__, phandle);
684 return ERR_PTR(-ENODEV);
685 }
686
687 mbox = omap_mbox_device_find(mdev, node->name);
688 of_node_put(node);
689 return mbox ? mbox->chan : ERR_PTR(-ENOENT);
690}
691
692static int omap_mbox_probe(struct platform_device *pdev)
693{
694 struct resource *mem;
695 int ret;
696 struct mbox_chan *chnls;
697 struct omap_mbox **list, *mbox, *mboxblk;
698 struct omap_mbox_fifo_info *finfo, *finfoblk;
699 struct omap_mbox_device *mdev;
700 struct omap_mbox_fifo *fifo;
701 struct device_node *node = pdev->dev.of_node;
702 struct device_node *child;
703 const struct of_device_id *match;
704 u32 intr_type, info_count;
705 u32 num_users, num_fifos;
706 u32 tmp[3];
707 u32 l;
708 int i;
709
710 if (!node) {
711 pr_err("%s: only DT-based devices are supported\n", __func__);
712 return -ENODEV;
713 }
714
715 match = of_match_device(omap_mailbox_of_match, &pdev->dev);
716 if (!match)
717 return -ENODEV;
718 intr_type = (u32)match->data;
719
720 if (of_property_read_u32(node, "ti,mbox-num-users", &num_users))
721 return -ENODEV;
722
723 if (of_property_read_u32(node, "ti,mbox-num-fifos", &num_fifos))
724 return -ENODEV;
725
726 info_count = of_get_available_child_count(node);
727 if (!info_count) {
728 dev_err(&pdev->dev, "no available mbox devices found\n");
729 return -ENODEV;
730 }
731
732 finfoblk = devm_kzalloc(&pdev->dev, info_count * sizeof(*finfoblk),
733 GFP_KERNEL);
734 if (!finfoblk)
735 return -ENOMEM;
736
737 finfo = finfoblk;
738 child = NULL;
739 for (i = 0; i < info_count; i++, finfo++) {
740 child = of_get_next_available_child(node, child);
741 ret = of_property_read_u32_array(child, "ti,mbox-tx", tmp,
742 ARRAY_SIZE(tmp));
743 if (ret)
744 return ret;
745 finfo->tx_id = tmp[0];
746 finfo->tx_irq = tmp[1];
747 finfo->tx_usr = tmp[2];
748
749 ret = of_property_read_u32_array(child, "ti,mbox-rx", tmp,
750 ARRAY_SIZE(tmp));
751 if (ret)
752 return ret;
753 finfo->rx_id = tmp[0];
754 finfo->rx_irq = tmp[1];
755 finfo->rx_usr = tmp[2];
756
757 finfo->name = child->name;
758
759 if (of_find_property(child, "ti,mbox-send-noirq", NULL))
760 finfo->send_no_irq = true;
761
762 if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos ||
763 finfo->tx_usr >= num_users || finfo->rx_usr >= num_users)
764 return -EINVAL;
765 }
766
767 mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL);
768 if (!mdev)
769 return -ENOMEM;
770
771 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
772 mdev->mbox_base = devm_ioremap_resource(&pdev->dev, mem);
773 if (IS_ERR(mdev->mbox_base))
774 return PTR_ERR(mdev->mbox_base);
775
776 mdev->irq_ctx = devm_kzalloc(&pdev->dev, num_users * sizeof(u32),
777 GFP_KERNEL);
778 if (!mdev->irq_ctx)
779 return -ENOMEM;
780
781 /* allocate one extra for marking end of list */
782 list = devm_kzalloc(&pdev->dev, (info_count + 1) * sizeof(*list),
783 GFP_KERNEL);
784 if (!list)
785 return -ENOMEM;
786
787 chnls = devm_kzalloc(&pdev->dev, (info_count + 1) * sizeof(*chnls),
788 GFP_KERNEL);
789 if (!chnls)
790 return -ENOMEM;
791
792 mboxblk = devm_kzalloc(&pdev->dev, info_count * sizeof(*mbox),
793 GFP_KERNEL);
794 if (!mboxblk)
795 return -ENOMEM;
796
797 mbox = mboxblk;
798 finfo = finfoblk;
799 for (i = 0; i < info_count; i++, finfo++) {
800 fifo = &mbox->tx_fifo;
801 fifo->msg = MAILBOX_MESSAGE(finfo->tx_id);
802 fifo->fifo_stat = MAILBOX_FIFOSTATUS(finfo->tx_id);
803 fifo->intr_bit = MAILBOX_IRQ_NOTFULL(finfo->tx_id);
804 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->tx_usr);
805 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->tx_usr);
806 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->tx_usr);
807
808 fifo = &mbox->rx_fifo;
809 fifo->msg = MAILBOX_MESSAGE(finfo->rx_id);
810 fifo->msg_stat = MAILBOX_MSGSTATUS(finfo->rx_id);
811 fifo->intr_bit = MAILBOX_IRQ_NEWMSG(finfo->rx_id);
812 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->rx_usr);
813 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->rx_usr);
814 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->rx_usr);
815
816 mbox->send_no_irq = finfo->send_no_irq;
817 mbox->intr_type = intr_type;
818
819 mbox->parent = mdev;
820 mbox->name = finfo->name;
821 mbox->irq = platform_get_irq(pdev, finfo->tx_irq);
822 if (mbox->irq < 0)
823 return mbox->irq;
824 mbox->chan = &chnls[i];
825 chnls[i].con_priv = mbox;
826 list[i] = mbox++;
827 }
828
829 mutex_init(&mdev->cfg_lock);
830 mdev->dev = &pdev->dev;
831 mdev->num_users = num_users;
832 mdev->num_fifos = num_fifos;
833 mdev->intr_type = intr_type;
834 mdev->mboxes = list;
835
836 /* OMAP does not have a Tx-Done IRQ, but rather a Tx-Ready IRQ */
837 mdev->controller.txdone_irq = true;
838 mdev->controller.dev = mdev->dev;
839 mdev->controller.ops = &omap_mbox_chan_ops;
840 mdev->controller.chans = chnls;
841 mdev->controller.num_chans = info_count;
842 mdev->controller.of_xlate = omap_mbox_of_xlate;
843 ret = omap_mbox_register(mdev);
844 if (ret)
845 return ret;
846
847 platform_set_drvdata(pdev, mdev);
848 pm_runtime_enable(mdev->dev);
849
850 ret = pm_runtime_get_sync(mdev->dev);
851 if (ret < 0) {
852 pm_runtime_put_noidle(mdev->dev);
853 goto unregister;
854 }
855
856 /*
857 * just print the raw revision register, the format is not
858 * uniform across all SoCs
859 */
860 l = mbox_read_reg(mdev, MAILBOX_REVISION);
861 dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l);
862
863 ret = pm_runtime_put_sync(mdev->dev);
864 if (ret < 0)
865 goto unregister;
866
867 devm_kfree(&pdev->dev, finfoblk);
868 return 0;
869
870unregister:
871 pm_runtime_disable(mdev->dev);
872 omap_mbox_unregister(mdev);
873 return ret;
874}
875
876static int omap_mbox_remove(struct platform_device *pdev)
877{
878 struct omap_mbox_device *mdev = platform_get_drvdata(pdev);
879
880 pm_runtime_disable(mdev->dev);
881 omap_mbox_unregister(mdev);
882
883 return 0;
884}
885
886static struct platform_driver omap_mbox_driver = {
887 .probe = omap_mbox_probe,
888 .remove = omap_mbox_remove,
889 .driver = {
890 .name = "omap-mailbox",
891 .pm = &omap_mbox_pm_ops,
892 .of_match_table = of_match_ptr(omap_mailbox_of_match),
893 },
894};
895
896static int __init omap_mbox_init(void)
897{
898 int err;
899
900 err = class_register(&omap_mbox_class);
901 if (err)
902 return err;
903
904 /* kfifo size sanity check: alignment and minimal size */
905 mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
906 mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
907 sizeof(mbox_msg_t));
908
909 return platform_driver_register(&omap_mbox_driver);
910}
911subsys_initcall(omap_mbox_init);
912
913static void __exit omap_mbox_exit(void)
914{
915 platform_driver_unregister(&omap_mbox_driver);
916 class_unregister(&omap_mbox_class);
917}
918module_exit(omap_mbox_exit);
919
920MODULE_LICENSE("GPL v2");
921MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
922MODULE_AUTHOR("Toshihiro Kobayashi");
923MODULE_AUTHOR("Hiroshi DOYU");