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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
2/*
3 * Copyright 2018-2021 Amazon.com, Inc. or its affiliates. All rights reserved.
4 */
5
6#ifndef _EFA_ADMIN_CMDS_H_
7#define _EFA_ADMIN_CMDS_H_
8
9#define EFA_ADMIN_API_VERSION_MAJOR 0
10#define EFA_ADMIN_API_VERSION_MINOR 1
11
12/* EFA admin queue opcodes */
13enum efa_admin_aq_opcode {
14 EFA_ADMIN_CREATE_QP = 1,
15 EFA_ADMIN_MODIFY_QP = 2,
16 EFA_ADMIN_QUERY_QP = 3,
17 EFA_ADMIN_DESTROY_QP = 4,
18 EFA_ADMIN_CREATE_AH = 5,
19 EFA_ADMIN_DESTROY_AH = 6,
20 EFA_ADMIN_REG_MR = 7,
21 EFA_ADMIN_DEREG_MR = 8,
22 EFA_ADMIN_CREATE_CQ = 9,
23 EFA_ADMIN_DESTROY_CQ = 10,
24 EFA_ADMIN_GET_FEATURE = 11,
25 EFA_ADMIN_SET_FEATURE = 12,
26 EFA_ADMIN_GET_STATS = 13,
27 EFA_ADMIN_ALLOC_PD = 14,
28 EFA_ADMIN_DEALLOC_PD = 15,
29 EFA_ADMIN_ALLOC_UAR = 16,
30 EFA_ADMIN_DEALLOC_UAR = 17,
31 EFA_ADMIN_CREATE_EQ = 18,
32 EFA_ADMIN_DESTROY_EQ = 19,
33 EFA_ADMIN_MAX_OPCODE = 19,
34};
35
36enum efa_admin_aq_feature_id {
37 EFA_ADMIN_DEVICE_ATTR = 1,
38 EFA_ADMIN_AENQ_CONFIG = 2,
39 EFA_ADMIN_NETWORK_ATTR = 3,
40 EFA_ADMIN_QUEUE_ATTR = 4,
41 EFA_ADMIN_HW_HINTS = 5,
42 EFA_ADMIN_HOST_INFO = 6,
43 EFA_ADMIN_EVENT_QUEUE_ATTR = 7,
44};
45
46/* QP transport type */
47enum efa_admin_qp_type {
48 /* Unreliable Datagram */
49 EFA_ADMIN_QP_TYPE_UD = 1,
50 /* Scalable Reliable Datagram */
51 EFA_ADMIN_QP_TYPE_SRD = 2,
52};
53
54/* QP state */
55enum efa_admin_qp_state {
56 EFA_ADMIN_QP_STATE_RESET = 0,
57 EFA_ADMIN_QP_STATE_INIT = 1,
58 EFA_ADMIN_QP_STATE_RTR = 2,
59 EFA_ADMIN_QP_STATE_RTS = 3,
60 EFA_ADMIN_QP_STATE_SQD = 4,
61 EFA_ADMIN_QP_STATE_SQE = 5,
62 EFA_ADMIN_QP_STATE_ERR = 6,
63};
64
65enum efa_admin_get_stats_type {
66 EFA_ADMIN_GET_STATS_TYPE_BASIC = 0,
67 EFA_ADMIN_GET_STATS_TYPE_MESSAGES = 1,
68 EFA_ADMIN_GET_STATS_TYPE_RDMA_READ = 2,
69};
70
71enum efa_admin_get_stats_scope {
72 EFA_ADMIN_GET_STATS_SCOPE_ALL = 0,
73 EFA_ADMIN_GET_STATS_SCOPE_QUEUE = 1,
74};
75
76/*
77 * QP allocation sizes, converted by fabric QueuePair (QP) create command
78 * from QP capabilities.
79 */
80struct efa_admin_qp_alloc_size {
81 /* Send descriptor ring size in bytes */
82 u32 send_queue_ring_size;
83
84 /* Max number of WQEs that can be outstanding on send queue. */
85 u32 send_queue_depth;
86
87 /*
88 * Recv descriptor ring size in bytes, sufficient for user-provided
89 * number of WQEs
90 */
91 u32 recv_queue_ring_size;
92
93 /* Max number of WQEs that can be outstanding on recv queue */
94 u32 recv_queue_depth;
95};
96
97struct efa_admin_create_qp_cmd {
98 /* Common Admin Queue descriptor */
99 struct efa_admin_aq_common_desc aq_common_desc;
100
101 /* Protection Domain associated with this QP */
102 u16 pd;
103
104 /* QP type */
105 u8 qp_type;
106
107 /*
108 * 0 : sq_virt - If set, SQ ring base address is
109 * virtual (IOVA returned by MR registration)
110 * 1 : rq_virt - If set, RQ ring base address is
111 * virtual (IOVA returned by MR registration)
112 * 7:2 : reserved - MBZ
113 */
114 u8 flags;
115
116 /*
117 * Send queue (SQ) ring base physical address. This field is not
118 * used if this is a Low Latency Queue(LLQ).
119 */
120 u64 sq_base_addr;
121
122 /* Receive queue (RQ) ring base address. */
123 u64 rq_base_addr;
124
125 /* Index of CQ to be associated with Send Queue completions */
126 u32 send_cq_idx;
127
128 /* Index of CQ to be associated with Recv Queue completions */
129 u32 recv_cq_idx;
130
131 /*
132 * Memory registration key for the SQ ring, used only when not in
133 * LLQ mode and base address is virtual
134 */
135 u32 sq_l_key;
136
137 /*
138 * Memory registration key for the RQ ring, used only when base
139 * address is virtual
140 */
141 u32 rq_l_key;
142
143 /* Requested QP allocation sizes */
144 struct efa_admin_qp_alloc_size qp_alloc_size;
145
146 /* UAR number */
147 u16 uar;
148
149 /* MBZ */
150 u16 reserved;
151
152 /* MBZ */
153 u32 reserved2;
154};
155
156struct efa_admin_create_qp_resp {
157 /* Common Admin Queue completion descriptor */
158 struct efa_admin_acq_common_desc acq_common_desc;
159
160 /*
161 * Opaque handle to be used for consequent admin operations on the
162 * QP
163 */
164 u32 qp_handle;
165
166 /*
167 * QP number in the given EFA virtual device. Least-significant bits (as
168 * needed according to max_qp) carry unique QP ID
169 */
170 u16 qp_num;
171
172 /* MBZ */
173 u16 reserved;
174
175 /* Index of sub-CQ for Send Queue completions */
176 u16 send_sub_cq_idx;
177
178 /* Index of sub-CQ for Receive Queue completions */
179 u16 recv_sub_cq_idx;
180
181 /* SQ doorbell address, as offset to PCIe DB BAR */
182 u32 sq_db_offset;
183
184 /* RQ doorbell address, as offset to PCIe DB BAR */
185 u32 rq_db_offset;
186
187 /*
188 * low latency send queue ring base address as an offset to PCIe
189 * MMIO LLQ_MEM BAR
190 */
191 u32 llq_descriptors_offset;
192};
193
194struct efa_admin_modify_qp_cmd {
195 /* Common Admin Queue descriptor */
196 struct efa_admin_aq_common_desc aq_common_desc;
197
198 /*
199 * Mask indicating which fields should be updated
200 * 0 : qp_state
201 * 1 : cur_qp_state
202 * 2 : qkey
203 * 3 : sq_psn
204 * 4 : sq_drained_async_notify
205 * 5 : rnr_retry
206 * 31:6 : reserved
207 */
208 u32 modify_mask;
209
210 /* QP handle returned by create_qp command */
211 u32 qp_handle;
212
213 /* QP state */
214 u32 qp_state;
215
216 /* Override current QP state (before applying the transition) */
217 u32 cur_qp_state;
218
219 /* QKey */
220 u32 qkey;
221
222 /* SQ PSN */
223 u32 sq_psn;
224
225 /* Enable async notification when SQ is drained */
226 u8 sq_drained_async_notify;
227
228 /* Number of RNR retries (valid only for SRD QPs) */
229 u8 rnr_retry;
230
231 /* MBZ */
232 u16 reserved2;
233};
234
235struct efa_admin_modify_qp_resp {
236 /* Common Admin Queue completion descriptor */
237 struct efa_admin_acq_common_desc acq_common_desc;
238};
239
240struct efa_admin_query_qp_cmd {
241 /* Common Admin Queue descriptor */
242 struct efa_admin_aq_common_desc aq_common_desc;
243
244 /* QP handle returned by create_qp command */
245 u32 qp_handle;
246};
247
248struct efa_admin_query_qp_resp {
249 /* Common Admin Queue completion descriptor */
250 struct efa_admin_acq_common_desc acq_common_desc;
251
252 /* QP state */
253 u32 qp_state;
254
255 /* QKey */
256 u32 qkey;
257
258 /* SQ PSN */
259 u32 sq_psn;
260
261 /* Indicates that draining is in progress */
262 u8 sq_draining;
263
264 /* Number of RNR retries (valid only for SRD QPs) */
265 u8 rnr_retry;
266
267 /* MBZ */
268 u16 reserved2;
269};
270
271struct efa_admin_destroy_qp_cmd {
272 /* Common Admin Queue descriptor */
273 struct efa_admin_aq_common_desc aq_common_desc;
274
275 /* QP handle returned by create_qp command */
276 u32 qp_handle;
277};
278
279struct efa_admin_destroy_qp_resp {
280 /* Common Admin Queue completion descriptor */
281 struct efa_admin_acq_common_desc acq_common_desc;
282};
283
284/*
285 * Create Address Handle command parameters. Must not be called more than
286 * once for the same destination
287 */
288struct efa_admin_create_ah_cmd {
289 /* Common Admin Queue descriptor */
290 struct efa_admin_aq_common_desc aq_common_desc;
291
292 /* Destination address in network byte order */
293 u8 dest_addr[16];
294
295 /* PD number */
296 u16 pd;
297
298 /* MBZ */
299 u16 reserved;
300};
301
302struct efa_admin_create_ah_resp {
303 /* Common Admin Queue completion descriptor */
304 struct efa_admin_acq_common_desc acq_common_desc;
305
306 /* Target interface address handle (opaque) */
307 u16 ah;
308
309 /* MBZ */
310 u16 reserved;
311};
312
313struct efa_admin_destroy_ah_cmd {
314 /* Common Admin Queue descriptor */
315 struct efa_admin_aq_common_desc aq_common_desc;
316
317 /* Target interface address handle (opaque) */
318 u16 ah;
319
320 /* PD number */
321 u16 pd;
322};
323
324struct efa_admin_destroy_ah_resp {
325 /* Common Admin Queue completion descriptor */
326 struct efa_admin_acq_common_desc acq_common_desc;
327};
328
329/*
330 * Registration of MemoryRegion, required for QP working with Virtual
331 * Addresses. In standard verbs semantics, region length is limited to 2GB
332 * space, but EFA offers larger MR support for large memory space, to ease
333 * on users working with very large datasets (i.e. full GPU memory mapping).
334 */
335struct efa_admin_reg_mr_cmd {
336 /* Common Admin Queue descriptor */
337 struct efa_admin_aq_common_desc aq_common_desc;
338
339 /* Protection Domain */
340 u16 pd;
341
342 /* MBZ */
343 u16 reserved16_w1;
344
345 /* Physical Buffer List, each element is page-aligned. */
346 union {
347 /*
348 * Inline array of guest-physical page addresses of user
349 * memory pages (optimization for short region
350 * registrations)
351 */
352 u64 inline_pbl_array[4];
353
354 /* points to PBL (direct or indirect, chained if needed) */
355 struct efa_admin_ctrl_buff_info pbl;
356 } pbl;
357
358 /* Memory region length, in bytes. */
359 u64 mr_length;
360
361 /*
362 * flags and page size
363 * 4:0 : phys_page_size_shift - page size is (1 <<
364 * phys_page_size_shift). Page size is used for
365 * building the Virtual to Physical address mapping
366 * 6:5 : reserved - MBZ
367 * 7 : mem_addr_phy_mode_en - Enable bit for physical
368 * memory registration (no translation), can be used
369 * only by privileged clients. If set, PBL must
370 * contain a single entry.
371 */
372 u8 flags;
373
374 /*
375 * permissions
376 * 0 : local_write_enable - Local write permissions:
377 * must be set for RQ buffers and buffers posted for
378 * RDMA Read requests
379 * 1 : reserved1 - MBZ
380 * 2 : remote_read_enable - Remote read permissions:
381 * must be set to enable RDMA read from the region
382 * 7:3 : reserved2 - MBZ
383 */
384 u8 permissions;
385
386 /* MBZ */
387 u16 reserved16_w5;
388
389 /* number of pages in PBL (redundant, could be calculated) */
390 u32 page_num;
391
392 /*
393 * IO Virtual Address associated with this MR. If
394 * mem_addr_phy_mode_en is set, contains the physical address of
395 * the region.
396 */
397 u64 iova;
398};
399
400struct efa_admin_reg_mr_resp {
401 /* Common Admin Queue completion descriptor */
402 struct efa_admin_acq_common_desc acq_common_desc;
403
404 /*
405 * L_Key, to be used in conjunction with local buffer references in
406 * SQ and RQ WQE, or with virtual RQ/CQ rings
407 */
408 u32 l_key;
409
410 /*
411 * R_Key, to be used in RDMA messages to refer to remotely accessed
412 * memory region
413 */
414 u32 r_key;
415};
416
417struct efa_admin_dereg_mr_cmd {
418 /* Common Admin Queue descriptor */
419 struct efa_admin_aq_common_desc aq_common_desc;
420
421 /* L_Key, memory region's l_key */
422 u32 l_key;
423};
424
425struct efa_admin_dereg_mr_resp {
426 /* Common Admin Queue completion descriptor */
427 struct efa_admin_acq_common_desc acq_common_desc;
428};
429
430struct efa_admin_create_cq_cmd {
431 struct efa_admin_aq_common_desc aq_common_desc;
432
433 /*
434 * 4:0 : reserved5 - MBZ
435 * 5 : interrupt_mode_enabled - if set, cq operates
436 * in interrupt mode (i.e. CQ events and EQ elements
437 * are generated), otherwise - polling
438 * 6 : virt - If set, ring base address is virtual
439 * (IOVA returned by MR registration)
440 * 7 : reserved6 - MBZ
441 */
442 u8 cq_caps_1;
443
444 /*
445 * 4:0 : cq_entry_size_words - size of CQ entry in
446 * 32-bit words, valid values: 4, 8.
447 * 5 : set_src_addr - If set, source address will be
448 * filled on RX completions from unknown senders.
449 * Requires 8 words CQ entry size.
450 * 7:6 : reserved7 - MBZ
451 */
452 u8 cq_caps_2;
453
454 /* completion queue depth in # of entries. must be power of 2 */
455 u16 cq_depth;
456
457 /* EQ number assigned to this cq */
458 u16 eqn;
459
460 /* MBZ */
461 u16 reserved;
462
463 /*
464 * CQ ring base address, virtual or physical depending on 'virt'
465 * flag
466 */
467 struct efa_common_mem_addr cq_ba;
468
469 /*
470 * Memory registration key for the ring, used only when base
471 * address is virtual
472 */
473 u32 l_key;
474
475 /*
476 * number of sub cqs - must be equal to sub_cqs_per_cq of queue
477 * attributes.
478 */
479 u16 num_sub_cqs;
480
481 /* UAR number */
482 u16 uar;
483};
484
485struct efa_admin_create_cq_resp {
486 struct efa_admin_acq_common_desc acq_common_desc;
487
488 u16 cq_idx;
489
490 /* actual cq depth in number of entries */
491 u16 cq_actual_depth;
492
493 /* CQ doorbell address, as offset to PCIe DB BAR */
494 u32 db_offset;
495
496 /*
497 * 0 : db_valid - If set, doorbell offset is valid.
498 * Always set when interrupts are requested.
499 */
500 u32 flags;
501};
502
503struct efa_admin_destroy_cq_cmd {
504 struct efa_admin_aq_common_desc aq_common_desc;
505
506 u16 cq_idx;
507
508 /* MBZ */
509 u16 reserved1;
510};
511
512struct efa_admin_destroy_cq_resp {
513 struct efa_admin_acq_common_desc acq_common_desc;
514};
515
516/*
517 * EFA AQ Get Statistics command. Extended statistics are placed in control
518 * buffer pointed by AQ entry
519 */
520struct efa_admin_aq_get_stats_cmd {
521 struct efa_admin_aq_common_desc aq_common_descriptor;
522
523 union {
524 /* command specific inline data */
525 u32 inline_data_w1[3];
526
527 struct efa_admin_ctrl_buff_info control_buffer;
528 } u;
529
530 /* stats type as defined in enum efa_admin_get_stats_type */
531 u8 type;
532
533 /* stats scope defined in enum efa_admin_get_stats_scope */
534 u8 scope;
535
536 u16 scope_modifier;
537};
538
539struct efa_admin_basic_stats {
540 u64 tx_bytes;
541
542 u64 tx_pkts;
543
544 u64 rx_bytes;
545
546 u64 rx_pkts;
547
548 u64 rx_drops;
549};
550
551struct efa_admin_messages_stats {
552 u64 send_bytes;
553
554 u64 send_wrs;
555
556 u64 recv_bytes;
557
558 u64 recv_wrs;
559};
560
561struct efa_admin_rdma_read_stats {
562 u64 read_wrs;
563
564 u64 read_bytes;
565
566 u64 read_wr_err;
567
568 u64 read_resp_bytes;
569};
570
571struct efa_admin_acq_get_stats_resp {
572 struct efa_admin_acq_common_desc acq_common_desc;
573
574 union {
575 struct efa_admin_basic_stats basic_stats;
576
577 struct efa_admin_messages_stats messages_stats;
578
579 struct efa_admin_rdma_read_stats rdma_read_stats;
580 } u;
581};
582
583struct efa_admin_get_set_feature_common_desc {
584 /* MBZ */
585 u8 reserved0;
586
587 /* as appears in efa_admin_aq_feature_id */
588 u8 feature_id;
589
590 /* MBZ */
591 u16 reserved16;
592};
593
594struct efa_admin_feature_device_attr_desc {
595 /* Bitmap of efa_admin_aq_feature_id */
596 u64 supported_features;
597
598 /* Bitmap of supported page sizes in MR registrations */
599 u64 page_size_cap;
600
601 u32 fw_version;
602
603 u32 admin_api_version;
604
605 u32 device_version;
606
607 /* Bar used for SQ and RQ doorbells */
608 u16 db_bar;
609
610 /* Indicates how many bits are used on physical address access */
611 u8 phys_addr_width;
612
613 /* Indicates how many bits are used on virtual address access */
614 u8 virt_addr_width;
615
616 /*
617 * 0 : rdma_read - If set, RDMA Read is supported on
618 * TX queues
619 * 1 : rnr_retry - If set, RNR retry is supported on
620 * modify QP command
621 * 31:2 : reserved - MBZ
622 */
623 u32 device_caps;
624
625 /* Max RDMA transfer size in bytes */
626 u32 max_rdma_size;
627};
628
629struct efa_admin_feature_queue_attr_desc {
630 /* The maximum number of queue pairs supported */
631 u32 max_qp;
632
633 /* Maximum number of WQEs per Send Queue */
634 u32 max_sq_depth;
635
636 /* Maximum size of data that can be sent inline in a Send WQE */
637 u32 inline_buf_size;
638
639 /* Maximum number of buffer descriptors per Recv Queue */
640 u32 max_rq_depth;
641
642 /* The maximum number of completion queues supported per VF */
643 u32 max_cq;
644
645 /* Maximum number of CQEs per Completion Queue */
646 u32 max_cq_depth;
647
648 /* Number of sub-CQs to be created for each CQ */
649 u16 sub_cqs_per_cq;
650
651 /* Minimum number of WQEs per SQ */
652 u16 min_sq_depth;
653
654 /* Maximum number of SGEs (buffers) allowed for a single send WQE */
655 u16 max_wr_send_sges;
656
657 /* Maximum number of SGEs allowed for a single recv WQE */
658 u16 max_wr_recv_sges;
659
660 /* The maximum number of memory regions supported */
661 u32 max_mr;
662
663 /* The maximum number of pages can be registered */
664 u32 max_mr_pages;
665
666 /* The maximum number of protection domains supported */
667 u32 max_pd;
668
669 /* The maximum number of address handles supported */
670 u32 max_ah;
671
672 /* The maximum size of LLQ in bytes */
673 u32 max_llq_size;
674
675 /* Maximum number of SGEs for a single RDMA read WQE */
676 u16 max_wr_rdma_sges;
677
678 /*
679 * Maximum number of bytes that can be written to SQ between two
680 * consecutive doorbells (in units of 64B). Driver must ensure that only
681 * complete WQEs are written to queue before issuing a doorbell.
682 * Examples: max_tx_batch=16 and WQE size = 64B, means up to 16 WQEs can
683 * be written to SQ between two consecutive doorbells. max_tx_batch=11
684 * and WQE size = 128B, means up to 5 WQEs can be written to SQ between
685 * two consecutive doorbells. Zero means unlimited.
686 */
687 u16 max_tx_batch;
688};
689
690struct efa_admin_event_queue_attr_desc {
691 /* The maximum number of event queues supported */
692 u32 max_eq;
693
694 /* Maximum number of EQEs per Event Queue */
695 u32 max_eq_depth;
696
697 /* Supported events bitmask */
698 u32 event_bitmask;
699};
700
701struct efa_admin_feature_aenq_desc {
702 /* bitmask for AENQ groups the device can report */
703 u32 supported_groups;
704
705 /* bitmask for AENQ groups to report */
706 u32 enabled_groups;
707};
708
709struct efa_admin_feature_network_attr_desc {
710 /* Raw address data in network byte order */
711 u8 addr[16];
712
713 /* max packet payload size in bytes */
714 u32 mtu;
715};
716
717/*
718 * When hint value is 0, hints capabilities are not supported or driver
719 * should use its own predefined value
720 */
721struct efa_admin_hw_hints {
722 /* value in ms */
723 u16 mmio_read_timeout;
724
725 /* value in ms */
726 u16 driver_watchdog_timeout;
727
728 /* value in ms */
729 u16 admin_completion_timeout;
730
731 /* poll interval in ms */
732 u16 poll_interval;
733};
734
735struct efa_admin_get_feature_cmd {
736 struct efa_admin_aq_common_desc aq_common_descriptor;
737
738 struct efa_admin_ctrl_buff_info control_buffer;
739
740 struct efa_admin_get_set_feature_common_desc feature_common;
741
742 u32 raw[11];
743};
744
745struct efa_admin_get_feature_resp {
746 struct efa_admin_acq_common_desc acq_common_desc;
747
748 union {
749 u32 raw[14];
750
751 struct efa_admin_feature_device_attr_desc device_attr;
752
753 struct efa_admin_feature_aenq_desc aenq;
754
755 struct efa_admin_feature_network_attr_desc network_attr;
756
757 struct efa_admin_feature_queue_attr_desc queue_attr;
758
759 struct efa_admin_event_queue_attr_desc event_queue_attr;
760
761 struct efa_admin_hw_hints hw_hints;
762 } u;
763};
764
765struct efa_admin_set_feature_cmd {
766 struct efa_admin_aq_common_desc aq_common_descriptor;
767
768 struct efa_admin_ctrl_buff_info control_buffer;
769
770 struct efa_admin_get_set_feature_common_desc feature_common;
771
772 union {
773 u32 raw[11];
774
775 /* AENQ configuration */
776 struct efa_admin_feature_aenq_desc aenq;
777 } u;
778};
779
780struct efa_admin_set_feature_resp {
781 struct efa_admin_acq_common_desc acq_common_desc;
782
783 union {
784 u32 raw[14];
785 } u;
786};
787
788struct efa_admin_alloc_pd_cmd {
789 struct efa_admin_aq_common_desc aq_common_descriptor;
790};
791
792struct efa_admin_alloc_pd_resp {
793 struct efa_admin_acq_common_desc acq_common_desc;
794
795 /* PD number */
796 u16 pd;
797
798 /* MBZ */
799 u16 reserved;
800};
801
802struct efa_admin_dealloc_pd_cmd {
803 struct efa_admin_aq_common_desc aq_common_descriptor;
804
805 /* PD number */
806 u16 pd;
807
808 /* MBZ */
809 u16 reserved;
810};
811
812struct efa_admin_dealloc_pd_resp {
813 struct efa_admin_acq_common_desc acq_common_desc;
814};
815
816struct efa_admin_alloc_uar_cmd {
817 struct efa_admin_aq_common_desc aq_common_descriptor;
818};
819
820struct efa_admin_alloc_uar_resp {
821 struct efa_admin_acq_common_desc acq_common_desc;
822
823 /* UAR number */
824 u16 uar;
825
826 /* MBZ */
827 u16 reserved;
828};
829
830struct efa_admin_dealloc_uar_cmd {
831 struct efa_admin_aq_common_desc aq_common_descriptor;
832
833 /* UAR number */
834 u16 uar;
835
836 /* MBZ */
837 u16 reserved;
838};
839
840struct efa_admin_dealloc_uar_resp {
841 struct efa_admin_acq_common_desc acq_common_desc;
842};
843
844struct efa_admin_create_eq_cmd {
845 struct efa_admin_aq_common_desc aq_common_descriptor;
846
847 /* Size of the EQ in entries, must be power of 2 */
848 u16 depth;
849
850 /* MSI-X table entry index */
851 u8 msix_vec;
852
853 /*
854 * 4:0 : entry_size_words - size of EQ entry in
855 * 32-bit words
856 * 7:5 : reserved - MBZ
857 */
858 u8 caps;
859
860 /* EQ ring base address */
861 struct efa_common_mem_addr ba;
862
863 /*
864 * Enabled events on this EQ
865 * 0 : completion_events - Enable completion events
866 * 31:1 : reserved - MBZ
867 */
868 u32 event_bitmask;
869
870 /* MBZ */
871 u32 reserved;
872};
873
874struct efa_admin_create_eq_resp {
875 struct efa_admin_acq_common_desc acq_common_desc;
876
877 /* EQ number */
878 u16 eqn;
879
880 /* MBZ */
881 u16 reserved;
882};
883
884struct efa_admin_destroy_eq_cmd {
885 struct efa_admin_aq_common_desc aq_common_descriptor;
886
887 /* EQ number */
888 u16 eqn;
889
890 /* MBZ */
891 u16 reserved;
892};
893
894struct efa_admin_destroy_eq_resp {
895 struct efa_admin_acq_common_desc acq_common_desc;
896};
897
898/* asynchronous event notification groups */
899enum efa_admin_aenq_group {
900 EFA_ADMIN_FATAL_ERROR = 1,
901 EFA_ADMIN_WARNING = 2,
902 EFA_ADMIN_NOTIFICATION = 3,
903 EFA_ADMIN_KEEP_ALIVE = 4,
904 EFA_ADMIN_AENQ_GROUPS_NUM = 5,
905};
906
907struct efa_admin_mmio_req_read_less_resp {
908 u16 req_id;
909
910 u16 reg_off;
911
912 /* value is valid when poll is cleared */
913 u32 reg_val;
914};
915
916enum efa_admin_os_type {
917 EFA_ADMIN_OS_LINUX = 0,
918};
919
920struct efa_admin_host_info {
921 /* OS distribution string format */
922 u8 os_dist_str[128];
923
924 /* Defined in enum efa_admin_os_type */
925 u32 os_type;
926
927 /* Kernel version string format */
928 u8 kernel_ver_str[32];
929
930 /* Kernel version numeric format */
931 u32 kernel_ver;
932
933 /*
934 * 7:0 : driver_module_type
935 * 15:8 : driver_sub_minor
936 * 23:16 : driver_minor
937 * 31:24 : driver_major
938 */
939 u32 driver_ver;
940
941 /*
942 * Device's Bus, Device and Function
943 * 2:0 : function
944 * 7:3 : device
945 * 15:8 : bus
946 */
947 u16 bdf;
948
949 /*
950 * Spec version
951 * 7:0 : spec_minor
952 * 15:8 : spec_major
953 */
954 u16 spec_ver;
955
956 /*
957 * 0 : intree - Intree driver
958 * 1 : gdr - GPUDirect RDMA supported
959 * 31:2 : reserved2
960 */
961 u32 flags;
962};
963
964/* create_qp_cmd */
965#define EFA_ADMIN_CREATE_QP_CMD_SQ_VIRT_MASK BIT(0)
966#define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_MASK BIT(1)
967
968/* modify_qp_cmd */
969#define EFA_ADMIN_MODIFY_QP_CMD_QP_STATE_MASK BIT(0)
970#define EFA_ADMIN_MODIFY_QP_CMD_CUR_QP_STATE_MASK BIT(1)
971#define EFA_ADMIN_MODIFY_QP_CMD_QKEY_MASK BIT(2)
972#define EFA_ADMIN_MODIFY_QP_CMD_SQ_PSN_MASK BIT(3)
973#define EFA_ADMIN_MODIFY_QP_CMD_SQ_DRAINED_ASYNC_NOTIFY_MASK BIT(4)
974#define EFA_ADMIN_MODIFY_QP_CMD_RNR_RETRY_MASK BIT(5)
975
976/* reg_mr_cmd */
977#define EFA_ADMIN_REG_MR_CMD_PHYS_PAGE_SIZE_SHIFT_MASK GENMASK(4, 0)
978#define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_MASK BIT(7)
979#define EFA_ADMIN_REG_MR_CMD_LOCAL_WRITE_ENABLE_MASK BIT(0)
980#define EFA_ADMIN_REG_MR_CMD_REMOTE_READ_ENABLE_MASK BIT(2)
981
982/* create_cq_cmd */
983#define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
984#define EFA_ADMIN_CREATE_CQ_CMD_VIRT_MASK BIT(6)
985#define EFA_ADMIN_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
986#define EFA_ADMIN_CREATE_CQ_CMD_SET_SRC_ADDR_MASK BIT(5)
987
988/* create_cq_resp */
989#define EFA_ADMIN_CREATE_CQ_RESP_DB_VALID_MASK BIT(0)
990
991/* feature_device_attr_desc */
992#define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RDMA_READ_MASK BIT(0)
993#define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RNR_RETRY_MASK BIT(1)
994
995/* create_eq_cmd */
996#define EFA_ADMIN_CREATE_EQ_CMD_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
997#define EFA_ADMIN_CREATE_EQ_CMD_VIRT_MASK BIT(6)
998#define EFA_ADMIN_CREATE_EQ_CMD_COMPLETION_EVENTS_MASK BIT(0)
999
1000/* host_info */
1001#define EFA_ADMIN_HOST_INFO_DRIVER_MODULE_TYPE_MASK GENMASK(7, 0)
1002#define EFA_ADMIN_HOST_INFO_DRIVER_SUB_MINOR_MASK GENMASK(15, 8)
1003#define EFA_ADMIN_HOST_INFO_DRIVER_MINOR_MASK GENMASK(23, 16)
1004#define EFA_ADMIN_HOST_INFO_DRIVER_MAJOR_MASK GENMASK(31, 24)
1005#define EFA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
1006#define EFA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
1007#define EFA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
1008#define EFA_ADMIN_HOST_INFO_SPEC_MINOR_MASK GENMASK(7, 0)
1009#define EFA_ADMIN_HOST_INFO_SPEC_MAJOR_MASK GENMASK(15, 8)
1010#define EFA_ADMIN_HOST_INFO_INTREE_MASK BIT(0)
1011#define EFA_ADMIN_HOST_INFO_GDR_MASK BIT(1)
1012
1013#endif /* _EFA_ADMIN_CMDS_H_ */