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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3* Copyright (C) 2012 Invensense, Inc.
4*/
5
6#ifndef INV_MPU_IIO_H_
7#define INV_MPU_IIO_H_
8
9#include <linux/i2c.h>
10#include <linux/i2c-mux.h>
11#include <linux/mutex.h>
12#include <linux/iio/iio.h>
13#include <linux/iio/buffer.h>
14#include <linux/regmap.h>
15#include <linux/iio/sysfs.h>
16#include <linux/iio/kfifo_buf.h>
17#include <linux/iio/trigger.h>
18#include <linux/iio/triggered_buffer.h>
19#include <linux/iio/trigger_consumer.h>
20#include <linux/platform_data/invensense_mpu6050.h>
21
22/**
23 * struct inv_mpu6050_reg_map - Notable registers.
24 * @sample_rate_div: Divider applied to gyro output rate.
25 * @lpf: Configures internal low pass filter.
26 * @accel_lpf: Configures accelerometer low pass filter.
27 * @user_ctrl: Enables/resets the FIFO.
28 * @fifo_en: Determines which data will appear in FIFO.
29 * @gyro_config: gyro config register.
30 * @accl_config: accel config register
31 * @fifo_count_h: Upper byte of FIFO count.
32 * @fifo_r_w: FIFO register.
33 * @raw_gyro: Address of first gyro register.
34 * @raw_accl: Address of first accel register.
35 * @temperature: temperature register
36 * @int_enable: Interrupt enable register.
37 * @int_status: Interrupt status register.
38 * @pwr_mgmt_1: Controls chip's power state and clock source.
39 * @pwr_mgmt_2: Controls power state of individual sensors.
40 * @int_pin_cfg; Controls interrupt pin configuration.
41 * @accl_offset: Controls the accelerometer calibration offset.
42 * @gyro_offset: Controls the gyroscope calibration offset.
43 * @i2c_if: Controls the i2c interface
44 */
45struct inv_mpu6050_reg_map {
46 u8 sample_rate_div;
47 u8 lpf;
48 u8 accel_lpf;
49 u8 user_ctrl;
50 u8 fifo_en;
51 u8 gyro_config;
52 u8 accl_config;
53 u8 fifo_count_h;
54 u8 fifo_r_w;
55 u8 raw_gyro;
56 u8 raw_accl;
57 u8 temperature;
58 u8 int_enable;
59 u8 int_status;
60 u8 pwr_mgmt_1;
61 u8 pwr_mgmt_2;
62 u8 int_pin_cfg;
63 u8 accl_offset;
64 u8 gyro_offset;
65 u8 i2c_if;
66};
67
68/*device enum */
69enum inv_devices {
70 INV_MPU6050,
71 INV_MPU6500,
72 INV_MPU6515,
73 INV_MPU6880,
74 INV_MPU6000,
75 INV_MPU9150,
76 INV_MPU9250,
77 INV_MPU9255,
78 INV_ICM20608,
79 INV_ICM20608D,
80 INV_ICM20609,
81 INV_ICM20689,
82 INV_ICM20602,
83 INV_ICM20690,
84 INV_IAM20680,
85 INV_NUM_PARTS
86};
87
88/* chip sensors mask: accelerometer, gyroscope, temperature, magnetometer */
89#define INV_MPU6050_SENSOR_ACCL BIT(0)
90#define INV_MPU6050_SENSOR_GYRO BIT(1)
91#define INV_MPU6050_SENSOR_TEMP BIT(2)
92#define INV_MPU6050_SENSOR_MAGN BIT(3)
93
94/**
95 * struct inv_mpu6050_chip_config - Cached chip configuration data.
96 * @clk: selected chip clock
97 * @fsr: Full scale range.
98 * @lpf: Digital low pass filter frequency.
99 * @accl_fs: accel full scale range.
100 * @accl_en: accel engine enabled
101 * @gyro_en: gyro engine enabled
102 * @temp_en: temperature sensor enabled
103 * @magn_en: magn engine (i2c master) enabled
104 * @accl_fifo_enable: enable accel data output
105 * @gyro_fifo_enable: enable gyro data output
106 * @temp_fifo_enable: enable temp data output
107 * @magn_fifo_enable: enable magn data output
108 * @divider: chip sample rate divider (sample rate divider - 1)
109 */
110struct inv_mpu6050_chip_config {
111 unsigned int clk:3;
112 unsigned int fsr:2;
113 unsigned int lpf:3;
114 unsigned int accl_fs:2;
115 unsigned int accl_en:1;
116 unsigned int gyro_en:1;
117 unsigned int temp_en:1;
118 unsigned int magn_en:1;
119 unsigned int accl_fifo_enable:1;
120 unsigned int gyro_fifo_enable:1;
121 unsigned int temp_fifo_enable:1;
122 unsigned int magn_fifo_enable:1;
123 u8 divider;
124 u8 user_ctrl;
125};
126
127/*
128 * Maximum of 6 + 6 + 2 + 7 (for MPU9x50) = 21 round up to 24 and plus 8.
129 * May be less if fewer channels are enabled, as long as the timestamp
130 * remains 8 byte aligned
131 */
132#define INV_MPU6050_OUTPUT_DATA_SIZE 32
133
134/**
135 * struct inv_mpu6050_hw - Other important hardware information.
136 * @whoami: Self identification byte from WHO_AM_I register
137 * @name: name of the chip.
138 * @reg: register map of the chip.
139 * @config: configuration of the chip.
140 * @fifo_size: size of the FIFO in bytes.
141 * @temp: offset and scale to apply to raw temperature.
142 */
143struct inv_mpu6050_hw {
144 u8 whoami;
145 u8 *name;
146 const struct inv_mpu6050_reg_map *reg;
147 const struct inv_mpu6050_chip_config *config;
148 size_t fifo_size;
149 struct {
150 int offset;
151 int scale;
152 } temp;
153 struct {
154 unsigned int accel;
155 unsigned int gyro;
156 } startup_time;
157};
158
159/*
160 * struct inv_mpu6050_state - Driver state variables.
161 * @lock: Chip access lock.
162 * @trig: IIO trigger.
163 * @chip_config: Cached attribute information.
164 * @reg: Map of important registers.
165 * @hw: Other hardware-specific information.
166 * @chip_type: chip type.
167 * @plat_data: platform data (deprecated in favor of @orientation).
168 * @orientation: sensor chip orientation relative to main hardware.
169 * @map regmap pointer.
170 * @irq interrupt number.
171 * @irq_mask the int_pin_cfg mask to configure interrupt type.
172 * @chip_period: chip internal period estimation (~1kHz).
173 * @it_timestamp: timestamp from previous interrupt.
174 * @data_timestamp: timestamp for next data sample.
175 * @vdd_supply: VDD voltage regulator for the chip.
176 * @vddio_supply I/O voltage regulator for the chip.
177 * @magn_disabled: magnetometer disabled for backward compatibility reason.
178 * @magn_raw_to_gauss: coefficient to convert mag raw value to Gauss.
179 * @magn_orient: magnetometer sensor chip orientation if available.
180 * @suspended_sensors: sensors mask of sensors turned off for suspend
181 * @data: dma safe buffer used for bulk reads.
182 */
183struct inv_mpu6050_state {
184 struct mutex lock;
185 struct iio_trigger *trig;
186 struct inv_mpu6050_chip_config chip_config;
187 const struct inv_mpu6050_reg_map *reg;
188 const struct inv_mpu6050_hw *hw;
189 enum inv_devices chip_type;
190 struct i2c_mux_core *muxc;
191 struct i2c_client *mux_client;
192 struct inv_mpu6050_platform_data plat_data;
193 struct iio_mount_matrix orientation;
194 struct regmap *map;
195 int irq;
196 u8 irq_mask;
197 unsigned skip_samples;
198 s64 chip_period;
199 s64 it_timestamp;
200 s64 data_timestamp;
201 struct regulator *vdd_supply;
202 struct regulator *vddio_supply;
203 bool magn_disabled;
204 s32 magn_raw_to_gauss[3];
205 struct iio_mount_matrix magn_orient;
206 unsigned int suspended_sensors;
207 u8 data[INV_MPU6050_OUTPUT_DATA_SIZE] __aligned(IIO_DMA_MINALIGN);
208};
209
210/*register and associated bit definition*/
211#define INV_MPU6050_REG_ACCEL_OFFSET 0x06
212#define INV_MPU6050_REG_GYRO_OFFSET 0x13
213
214#define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19
215#define INV_MPU6050_REG_CONFIG 0x1A
216#define INV_MPU6050_REG_GYRO_CONFIG 0x1B
217#define INV_MPU6050_REG_ACCEL_CONFIG 0x1C
218
219#define INV_MPU6050_REG_FIFO_EN 0x23
220#define INV_MPU6050_BIT_SLAVE_0 0x01
221#define INV_MPU6050_BIT_SLAVE_1 0x02
222#define INV_MPU6050_BIT_SLAVE_2 0x04
223#define INV_MPU6050_BIT_ACCEL_OUT 0x08
224#define INV_MPU6050_BITS_GYRO_OUT 0x70
225#define INV_MPU6050_BIT_TEMP_OUT 0x80
226
227#define INV_MPU6050_REG_I2C_MST_CTRL 0x24
228#define INV_MPU6050_BITS_I2C_MST_CLK_400KHZ 0x0D
229#define INV_MPU6050_BIT_I2C_MST_P_NSR 0x10
230#define INV_MPU6050_BIT_SLV3_FIFO_EN 0x20
231#define INV_MPU6050_BIT_WAIT_FOR_ES 0x40
232#define INV_MPU6050_BIT_MULT_MST_EN 0x80
233
234/* control I2C slaves from 0 to 3 */
235#define INV_MPU6050_REG_I2C_SLV_ADDR(_x) (0x25 + 3 * (_x))
236#define INV_MPU6050_BIT_I2C_SLV_RNW 0x80
237
238#define INV_MPU6050_REG_I2C_SLV_REG(_x) (0x26 + 3 * (_x))
239
240#define INV_MPU6050_REG_I2C_SLV_CTRL(_x) (0x27 + 3 * (_x))
241#define INV_MPU6050_BIT_SLV_GRP 0x10
242#define INV_MPU6050_BIT_SLV_REG_DIS 0x20
243#define INV_MPU6050_BIT_SLV_BYTE_SW 0x40
244#define INV_MPU6050_BIT_SLV_EN 0x80
245
246/* I2C master delay register */
247#define INV_MPU6050_REG_I2C_SLV4_CTRL 0x34
248#define INV_MPU6050_BITS_I2C_MST_DLY(_x) ((_x) & 0x1F)
249
250#define INV_MPU6050_REG_I2C_MST_STATUS 0x36
251#define INV_MPU6050_BIT_I2C_SLV0_NACK 0x01
252#define INV_MPU6050_BIT_I2C_SLV1_NACK 0x02
253#define INV_MPU6050_BIT_I2C_SLV2_NACK 0x04
254#define INV_MPU6050_BIT_I2C_SLV3_NACK 0x08
255
256#define INV_MPU6050_REG_INT_ENABLE 0x38
257#define INV_MPU6050_BIT_DATA_RDY_EN 0x01
258#define INV_MPU6050_BIT_DMP_INT_EN 0x02
259
260#define INV_MPU6050_REG_RAW_ACCEL 0x3B
261#define INV_MPU6050_REG_TEMPERATURE 0x41
262#define INV_MPU6050_REG_RAW_GYRO 0x43
263
264#define INV_MPU6050_REG_INT_STATUS 0x3A
265#define INV_MPU6050_BIT_FIFO_OVERFLOW_INT 0x10
266#define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01
267
268#define INV_MPU6050_REG_EXT_SENS_DATA 0x49
269
270/* I2C slaves data output from 0 to 3 */
271#define INV_MPU6050_REG_I2C_SLV_DO(_x) (0x63 + (_x))
272
273#define INV_MPU6050_REG_I2C_MST_DELAY_CTRL 0x67
274#define INV_MPU6050_BIT_I2C_SLV0_DLY_EN 0x01
275#define INV_MPU6050_BIT_I2C_SLV1_DLY_EN 0x02
276#define INV_MPU6050_BIT_I2C_SLV2_DLY_EN 0x04
277#define INV_MPU6050_BIT_I2C_SLV3_DLY_EN 0x08
278#define INV_MPU6050_BIT_DELAY_ES_SHADOW 0x80
279
280#define INV_MPU6050_REG_SIGNAL_PATH_RESET 0x68
281#define INV_MPU6050_BIT_TEMP_RST BIT(0)
282#define INV_MPU6050_BIT_ACCEL_RST BIT(1)
283#define INV_MPU6050_BIT_GYRO_RST BIT(2)
284
285#define INV_MPU6050_REG_USER_CTRL 0x6A
286#define INV_MPU6050_BIT_SIG_COND_RST 0x01
287#define INV_MPU6050_BIT_FIFO_RST 0x04
288#define INV_MPU6050_BIT_DMP_RST 0x08
289#define INV_MPU6050_BIT_I2C_MST_EN 0x20
290#define INV_MPU6050_BIT_FIFO_EN 0x40
291#define INV_MPU6050_BIT_DMP_EN 0x80
292#define INV_MPU6050_BIT_I2C_IF_DIS 0x10
293
294#define INV_MPU6050_REG_PWR_MGMT_1 0x6B
295#define INV_MPU6050_BIT_H_RESET 0x80
296#define INV_MPU6050_BIT_SLEEP 0x40
297#define INV_MPU6050_BIT_TEMP_DIS 0x08
298#define INV_MPU6050_BIT_CLK_MASK 0x7
299
300#define INV_MPU6050_REG_PWR_MGMT_2 0x6C
301#define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38
302#define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07
303
304/* ICM20602 register */
305#define INV_ICM20602_REG_I2C_IF 0x70
306#define INV_ICM20602_BIT_I2C_IF_DIS 0x40
307
308#define INV_MPU6050_REG_FIFO_COUNT_H 0x72
309#define INV_MPU6050_REG_FIFO_R_W 0x74
310
311#define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6
312#define INV_MPU6050_FIFO_COUNT_BYTE 2
313
314/* MPU9X50 9-axis magnetometer */
315#define INV_MPU9X50_BYTES_MAGN 7
316
317/* FIFO temperature sample size */
318#define INV_MPU6050_BYTES_PER_TEMP_SENSOR 2
319
320/* mpu6500 registers */
321#define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D
322#define INV_ICM20689_BITS_FIFO_SIZE_MAX 0xC0
323#define INV_MPU6500_REG_ACCEL_OFFSET 0x77
324
325/* delay time in milliseconds */
326#define INV_MPU6050_POWER_UP_TIME 100
327#define INV_MPU6050_TEMP_UP_TIME 100
328#define INV_MPU6050_ACCEL_STARTUP_TIME 20
329#define INV_MPU6050_GYRO_STARTUP_TIME 60
330#define INV_MPU6050_GYRO_DOWN_TIME 150
331#define INV_MPU6050_SUSPEND_DELAY_MS 2000
332
333#define INV_MPU6500_GYRO_STARTUP_TIME 70
334#define INV_MPU6500_ACCEL_STARTUP_TIME 30
335
336#define INV_ICM20602_GYRO_STARTUP_TIME 100
337#define INV_ICM20602_ACCEL_STARTUP_TIME 20
338
339#define INV_ICM20690_GYRO_STARTUP_TIME 80
340#define INV_ICM20690_ACCEL_STARTUP_TIME 10
341
342
343/* delay time in microseconds */
344#define INV_MPU6050_REG_UP_TIME_MIN 5000
345#define INV_MPU6050_REG_UP_TIME_MAX 10000
346
347#define INV_MPU6050_TEMP_OFFSET 12420
348#define INV_MPU6050_TEMP_SCALE 2941176
349#define INV_MPU6050_MAX_GYRO_FS_PARAM 3
350#define INV_MPU6050_MAX_ACCL_FS_PARAM 3
351#define INV_MPU6050_THREE_AXIS 3
352#define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3
353#define INV_ICM20690_GYRO_CONFIG_FSR_SHIFT 2
354#define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3
355
356#define INV_MPU6500_TEMP_OFFSET 7011
357#define INV_MPU6500_TEMP_SCALE 2995178
358
359#define INV_ICM20608_TEMP_OFFSET 8170
360#define INV_ICM20608_TEMP_SCALE 3059976
361
362#define INV_MPU6050_REG_INT_PIN_CFG 0x37
363#define INV_MPU6050_ACTIVE_HIGH 0x00
364#define INV_MPU6050_ACTIVE_LOW 0x80
365/* enable level triggering */
366#define INV_MPU6050_LATCH_INT_EN 0x20
367#define INV_MPU6050_BIT_BYPASS_EN 0x2
368
369/* Allowed timestamp period jitter in percent */
370#define INV_MPU6050_TS_PERIOD_JITTER 4
371
372/* init parameters */
373#define INV_MPU6050_MAX_FIFO_RATE 1000
374#define INV_MPU6050_MIN_FIFO_RATE 4
375
376/* chip internal frequency: 1KHz */
377#define INV_MPU6050_INTERNAL_FREQ_HZ 1000
378/* return the frequency divider (chip sample rate divider + 1) */
379#define INV_MPU6050_FREQ_DIVIDER(st) \
380 ((st)->chip_config.divider + 1)
381/* chip sample rate divider to fifo rate */
382#define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate) \
383 ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1)
384#define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \
385 (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))
386
387#define INV_MPU6050_REG_WHOAMI 117
388
389#define INV_MPU6000_WHOAMI_VALUE 0x68
390#define INV_MPU6050_WHOAMI_VALUE 0x68
391#define INV_MPU6500_WHOAMI_VALUE 0x70
392#define INV_MPU6880_WHOAMI_VALUE 0x78
393#define INV_MPU9150_WHOAMI_VALUE 0x68
394#define INV_MPU9250_WHOAMI_VALUE 0x71
395#define INV_MPU9255_WHOAMI_VALUE 0x73
396#define INV_MPU6515_WHOAMI_VALUE 0x74
397#define INV_ICM20608_WHOAMI_VALUE 0xAF
398#define INV_ICM20608D_WHOAMI_VALUE 0xAE
399#define INV_ICM20609_WHOAMI_VALUE 0xA6
400#define INV_ICM20689_WHOAMI_VALUE 0x98
401#define INV_ICM20602_WHOAMI_VALUE 0x12
402#define INV_ICM20690_WHOAMI_VALUE 0x20
403#define INV_IAM20680_WHOAMI_VALUE 0xA9
404
405/* scan element definition for generic MPU6xxx devices */
406enum inv_mpu6050_scan {
407 INV_MPU6050_SCAN_ACCL_X,
408 INV_MPU6050_SCAN_ACCL_Y,
409 INV_MPU6050_SCAN_ACCL_Z,
410 INV_MPU6050_SCAN_TEMP,
411 INV_MPU6050_SCAN_GYRO_X,
412 INV_MPU6050_SCAN_GYRO_Y,
413 INV_MPU6050_SCAN_GYRO_Z,
414 INV_MPU6050_SCAN_TIMESTAMP,
415
416 INV_MPU9X50_SCAN_MAGN_X = INV_MPU6050_SCAN_GYRO_Z + 1,
417 INV_MPU9X50_SCAN_MAGN_Y,
418 INV_MPU9X50_SCAN_MAGN_Z,
419 INV_MPU9X50_SCAN_TIMESTAMP,
420};
421
422enum inv_mpu6050_filter_e {
423 INV_MPU6050_FILTER_NOLPF2 = 0,
424 INV_MPU6050_FILTER_200HZ,
425 INV_MPU6050_FILTER_100HZ,
426 INV_MPU6050_FILTER_45HZ,
427 INV_MPU6050_FILTER_20HZ,
428 INV_MPU6050_FILTER_10HZ,
429 INV_MPU6050_FILTER_5HZ,
430 INV_MPU6050_FILTER_NOLPF,
431 NUM_MPU6050_FILTER
432};
433
434/* IIO attribute address */
435enum INV_MPU6050_IIO_ATTR_ADDR {
436 ATTR_GYRO_MATRIX,
437 ATTR_ACCL_MATRIX,
438};
439
440enum inv_mpu6050_accl_fs_e {
441 INV_MPU6050_FS_02G = 0,
442 INV_MPU6050_FS_04G,
443 INV_MPU6050_FS_08G,
444 INV_MPU6050_FS_16G,
445 NUM_ACCL_FSR
446};
447
448enum inv_mpu6050_fsr_e {
449 INV_MPU6050_FSR_250DPS = 0,
450 INV_MPU6050_FSR_500DPS,
451 INV_MPU6050_FSR_1000DPS,
452 INV_MPU6050_FSR_2000DPS,
453 NUM_MPU6050_FSR
454};
455
456enum inv_mpu6050_clock_sel_e {
457 INV_CLK_INTERNAL = 0,
458 INV_CLK_PLL,
459 NUM_CLK
460};
461
462irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
463int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);
464int inv_mpu6050_prepare_fifo(struct inv_mpu6050_state *st, bool enable);
465int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en,
466 unsigned int mask);
467int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
468int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
469void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
470int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
471 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
472extern const struct dev_pm_ops inv_mpu_pmops;
473
474#endif
1/*
2* Copyright (C) 2012 Invensense, Inc.
3*
4* This software is licensed under the terms of the GNU General Public
5* License version 2, as published by the Free Software Foundation, and
6* may be copied, distributed, and modified under those terms.
7*
8* This program is distributed in the hope that it will be useful,
9* but WITHOUT ANY WARRANTY; without even the implied warranty of
10* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11* GNU General Public License for more details.
12*/
13#include <linux/i2c.h>
14#include <linux/i2c-mux.h>
15#include <linux/kfifo.h>
16#include <linux/spinlock.h>
17#include <linux/iio/iio.h>
18#include <linux/iio/buffer.h>
19#include <linux/regmap.h>
20#include <linux/iio/sysfs.h>
21#include <linux/iio/kfifo_buf.h>
22#include <linux/iio/trigger.h>
23#include <linux/iio/triggered_buffer.h>
24#include <linux/iio/trigger_consumer.h>
25#include <linux/platform_data/invensense_mpu6050.h>
26
27/**
28 * struct inv_mpu6050_reg_map - Notable registers.
29 * @sample_rate_div: Divider applied to gyro output rate.
30 * @lpf: Configures internal low pass filter.
31 * @user_ctrl: Enables/resets the FIFO.
32 * @fifo_en: Determines which data will appear in FIFO.
33 * @gyro_config: gyro config register.
34 * @accl_config: accel config register
35 * @fifo_count_h: Upper byte of FIFO count.
36 * @fifo_r_w: FIFO register.
37 * @raw_gyro: Address of first gyro register.
38 * @raw_accl: Address of first accel register.
39 * @temperature: temperature register
40 * @int_enable: Interrupt enable register.
41 * @pwr_mgmt_1: Controls chip's power state and clock source.
42 * @pwr_mgmt_2: Controls power state of individual sensors.
43 * @int_pin_cfg; Controls interrupt pin configuration.
44 * @accl_offset: Controls the accelerometer calibration offset.
45 * @gyro_offset: Controls the gyroscope calibration offset.
46 */
47struct inv_mpu6050_reg_map {
48 u8 sample_rate_div;
49 u8 lpf;
50 u8 user_ctrl;
51 u8 fifo_en;
52 u8 gyro_config;
53 u8 accl_config;
54 u8 fifo_count_h;
55 u8 fifo_r_w;
56 u8 raw_gyro;
57 u8 raw_accl;
58 u8 temperature;
59 u8 int_enable;
60 u8 pwr_mgmt_1;
61 u8 pwr_mgmt_2;
62 u8 int_pin_cfg;
63 u8 accl_offset;
64 u8 gyro_offset;
65};
66
67/*device enum */
68enum inv_devices {
69 INV_MPU6050,
70 INV_MPU6500,
71 INV_MPU6000,
72 INV_MPU9150,
73 INV_ICM20608,
74 INV_NUM_PARTS
75};
76
77/**
78 * struct inv_mpu6050_chip_config - Cached chip configuration data.
79 * @fsr: Full scale range.
80 * @lpf: Digital low pass filter frequency.
81 * @accl_fs: accel full scale range.
82 * @enable: master enable state.
83 * @accl_fifo_enable: enable accel data output
84 * @gyro_fifo_enable: enable gyro data output
85 * @fifo_rate: FIFO update rate.
86 */
87struct inv_mpu6050_chip_config {
88 unsigned int fsr:2;
89 unsigned int lpf:3;
90 unsigned int accl_fs:2;
91 unsigned int enable:1;
92 unsigned int accl_fifo_enable:1;
93 unsigned int gyro_fifo_enable:1;
94 u16 fifo_rate;
95};
96
97/**
98 * struct inv_mpu6050_hw - Other important hardware information.
99 * @whoami: Self identification byte from WHO_AM_I register
100 * @name: name of the chip.
101 * @reg: register map of the chip.
102 * @config: configuration of the chip.
103 */
104struct inv_mpu6050_hw {
105 u8 whoami;
106 u8 *name;
107 const struct inv_mpu6050_reg_map *reg;
108 const struct inv_mpu6050_chip_config *config;
109};
110
111/*
112 * struct inv_mpu6050_state - Driver state variables.
113 * @TIMESTAMP_FIFO_SIZE: fifo size for timestamp.
114 * @trig: IIO trigger.
115 * @chip_config: Cached attribute information.
116 * @reg: Map of important registers.
117 * @hw: Other hardware-specific information.
118 * @chip_type: chip type.
119 * @time_stamp_lock: spin lock to time stamp.
120 * @plat_data: platform data (deprecated in favor of @orientation).
121 * @orientation: sensor chip orientation relative to main hardware.
122 * @timestamps: kfifo queue to store time stamp.
123 * @map regmap pointer.
124 * @irq interrupt number.
125 */
126struct inv_mpu6050_state {
127#define TIMESTAMP_FIFO_SIZE 16
128 struct iio_trigger *trig;
129 struct inv_mpu6050_chip_config chip_config;
130 const struct inv_mpu6050_reg_map *reg;
131 const struct inv_mpu6050_hw *hw;
132 enum inv_devices chip_type;
133 spinlock_t time_stamp_lock;
134 struct i2c_mux_core *muxc;
135 struct i2c_client *mux_client;
136 unsigned int powerup_count;
137 struct inv_mpu6050_platform_data plat_data;
138 struct iio_mount_matrix orientation;
139 DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE);
140 struct regmap *map;
141 int irq;
142};
143
144/*register and associated bit definition*/
145#define INV_MPU6050_REG_ACCEL_OFFSET 0x06
146#define INV_MPU6050_REG_GYRO_OFFSET 0x13
147
148#define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19
149#define INV_MPU6050_REG_CONFIG 0x1A
150#define INV_MPU6050_REG_GYRO_CONFIG 0x1B
151#define INV_MPU6050_REG_ACCEL_CONFIG 0x1C
152
153#define INV_MPU6050_REG_FIFO_EN 0x23
154#define INV_MPU6050_BIT_ACCEL_OUT 0x08
155#define INV_MPU6050_BITS_GYRO_OUT 0x70
156
157#define INV_MPU6050_REG_INT_ENABLE 0x38
158#define INV_MPU6050_BIT_DATA_RDY_EN 0x01
159#define INV_MPU6050_BIT_DMP_INT_EN 0x02
160
161#define INV_MPU6050_REG_RAW_ACCEL 0x3B
162#define INV_MPU6050_REG_TEMPERATURE 0x41
163#define INV_MPU6050_REG_RAW_GYRO 0x43
164
165#define INV_MPU6050_REG_USER_CTRL 0x6A
166#define INV_MPU6050_BIT_FIFO_RST 0x04
167#define INV_MPU6050_BIT_DMP_RST 0x08
168#define INV_MPU6050_BIT_I2C_MST_EN 0x20
169#define INV_MPU6050_BIT_FIFO_EN 0x40
170#define INV_MPU6050_BIT_DMP_EN 0x80
171#define INV_MPU6050_BIT_I2C_IF_DIS 0x10
172
173#define INV_MPU6050_REG_PWR_MGMT_1 0x6B
174#define INV_MPU6050_BIT_H_RESET 0x80
175#define INV_MPU6050_BIT_SLEEP 0x40
176#define INV_MPU6050_BIT_CLK_MASK 0x7
177
178#define INV_MPU6050_REG_PWR_MGMT_2 0x6C
179#define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38
180#define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07
181
182#define INV_MPU6050_REG_FIFO_COUNT_H 0x72
183#define INV_MPU6050_REG_FIFO_R_W 0x74
184
185#define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6
186#define INV_MPU6050_FIFO_COUNT_BYTE 2
187#define INV_MPU6050_FIFO_THRESHOLD 500
188
189/* mpu6500 registers */
190#define INV_MPU6500_REG_ACCEL_OFFSET 0x77
191
192/* delay time in milliseconds */
193#define INV_MPU6050_POWER_UP_TIME 100
194#define INV_MPU6050_TEMP_UP_TIME 100
195#define INV_MPU6050_SENSOR_UP_TIME 30
196
197/* delay time in microseconds */
198#define INV_MPU6050_REG_UP_TIME_MIN 5000
199#define INV_MPU6050_REG_UP_TIME_MAX 10000
200
201#define INV_MPU6050_TEMP_OFFSET 12421
202#define INV_MPU6050_TEMP_SCALE 2941
203#define INV_MPU6050_MAX_GYRO_FS_PARAM 3
204#define INV_MPU6050_MAX_ACCL_FS_PARAM 3
205#define INV_MPU6050_THREE_AXIS 3
206#define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3
207#define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3
208
209/* 6 + 6 round up and plus 8 */
210#define INV_MPU6050_OUTPUT_DATA_SIZE 24
211
212#define INV_MPU6050_REG_INT_PIN_CFG 0x37
213#define INV_MPU6050_BIT_BYPASS_EN 0x2
214#define INV_MPU6050_INT_PIN_CFG 0
215
216/* init parameters */
217#define INV_MPU6050_INIT_FIFO_RATE 50
218#define INV_MPU6050_TIME_STAMP_TOR 5
219#define INV_MPU6050_MAX_FIFO_RATE 1000
220#define INV_MPU6050_MIN_FIFO_RATE 4
221#define INV_MPU6050_ONE_K_HZ 1000
222
223#define INV_MPU6050_REG_WHOAMI 117
224
225#define INV_MPU6000_WHOAMI_VALUE 0x68
226#define INV_MPU6050_WHOAMI_VALUE 0x68
227#define INV_MPU6500_WHOAMI_VALUE 0x70
228#define INV_MPU9150_WHOAMI_VALUE 0x68
229#define INV_ICM20608_WHOAMI_VALUE 0xAF
230
231/* scan element definition */
232enum inv_mpu6050_scan {
233 INV_MPU6050_SCAN_ACCL_X,
234 INV_MPU6050_SCAN_ACCL_Y,
235 INV_MPU6050_SCAN_ACCL_Z,
236 INV_MPU6050_SCAN_GYRO_X,
237 INV_MPU6050_SCAN_GYRO_Y,
238 INV_MPU6050_SCAN_GYRO_Z,
239 INV_MPU6050_SCAN_TIMESTAMP,
240};
241
242enum inv_mpu6050_filter_e {
243 INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
244 INV_MPU6050_FILTER_188HZ,
245 INV_MPU6050_FILTER_98HZ,
246 INV_MPU6050_FILTER_42HZ,
247 INV_MPU6050_FILTER_20HZ,
248 INV_MPU6050_FILTER_10HZ,
249 INV_MPU6050_FILTER_5HZ,
250 INV_MPU6050_FILTER_2100HZ_NOLPF,
251 NUM_MPU6050_FILTER
252};
253
254/* IIO attribute address */
255enum INV_MPU6050_IIO_ATTR_ADDR {
256 ATTR_GYRO_MATRIX,
257 ATTR_ACCL_MATRIX,
258};
259
260enum inv_mpu6050_accl_fs_e {
261 INV_MPU6050_FS_02G = 0,
262 INV_MPU6050_FS_04G,
263 INV_MPU6050_FS_08G,
264 INV_MPU6050_FS_16G,
265 NUM_ACCL_FSR
266};
267
268enum inv_mpu6050_fsr_e {
269 INV_MPU6050_FSR_250DPS = 0,
270 INV_MPU6050_FSR_500DPS,
271 INV_MPU6050_FSR_1000DPS,
272 INV_MPU6050_FSR_2000DPS,
273 NUM_MPU6050_FSR
274};
275
276enum inv_mpu6050_clock_sel_e {
277 INV_CLK_INTERNAL = 0,
278 INV_CLK_PLL,
279 NUM_CLK
280};
281
282irqreturn_t inv_mpu6050_irq_handler(int irq, void *p);
283irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
284int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev);
285void inv_mpu6050_remove_trigger(struct inv_mpu6050_state *st);
286int inv_reset_fifo(struct iio_dev *indio_dev);
287int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
288int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
289int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
290int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
291void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
292int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
293 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
294int inv_mpu_core_remove(struct device *dev);
295int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
296extern const struct dev_pm_ops inv_mpu_pmops;