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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2009 Nokia Corporation
4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 */
6
7#define DSS_SUBSYS_NAME "SDI"
8
9#include <linux/delay.h>
10#include <linux/err.h>
11#include <linux/export.h>
12#include <linux/kernel.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/regulator/consumer.h>
16#include <linux/string.h>
17
18#include <drm/drm_bridge.h>
19
20#include "dss.h"
21#include "omapdss.h"
22
23struct sdi_device {
24 struct platform_device *pdev;
25 struct dss_device *dss;
26
27 bool update_enabled;
28 struct regulator *vdds_sdi_reg;
29
30 struct dss_lcd_mgr_config mgr_config;
31 unsigned long pixelclock;
32 int datapairs;
33
34 struct omap_dss_device output;
35 struct drm_bridge bridge;
36};
37
38#define drm_bridge_to_sdi(bridge) \
39 container_of(bridge, struct sdi_device, bridge)
40
41struct sdi_clk_calc_ctx {
42 struct sdi_device *sdi;
43 unsigned long pck_min, pck_max;
44
45 unsigned long fck;
46 struct dispc_clock_info dispc_cinfo;
47};
48
49static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
50 unsigned long pck, void *data)
51{
52 struct sdi_clk_calc_ctx *ctx = data;
53
54 ctx->dispc_cinfo.lck_div = lckd;
55 ctx->dispc_cinfo.pck_div = pckd;
56 ctx->dispc_cinfo.lck = lck;
57 ctx->dispc_cinfo.pck = pck;
58
59 return true;
60}
61
62static bool dpi_calc_dss_cb(unsigned long fck, void *data)
63{
64 struct sdi_clk_calc_ctx *ctx = data;
65
66 ctx->fck = fck;
67
68 return dispc_div_calc(ctx->sdi->dss->dispc, fck,
69 ctx->pck_min, ctx->pck_max,
70 dpi_calc_dispc_cb, ctx);
71}
72
73static int sdi_calc_clock_div(struct sdi_device *sdi, unsigned long pclk,
74 unsigned long *fck,
75 struct dispc_clock_info *dispc_cinfo)
76{
77 int i;
78 struct sdi_clk_calc_ctx ctx;
79
80 /*
81 * DSS fclk gives us very few possibilities, so finding a good pixel
82 * clock may not be possible. We try multiple times to find the clock,
83 * each time widening the pixel clock range we look for, up to
84 * +/- 1MHz.
85 */
86
87 for (i = 0; i < 10; ++i) {
88 bool ok;
89
90 memset(&ctx, 0, sizeof(ctx));
91
92 ctx.sdi = sdi;
93
94 if (pclk > 1000 * i * i * i)
95 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
96 else
97 ctx.pck_min = 0;
98 ctx.pck_max = pclk + 1000 * i * i * i;
99
100 ok = dss_div_calc(sdi->dss, pclk, ctx.pck_min,
101 dpi_calc_dss_cb, &ctx);
102 if (ok) {
103 *fck = ctx.fck;
104 *dispc_cinfo = ctx.dispc_cinfo;
105 return 0;
106 }
107 }
108
109 return -EINVAL;
110}
111
112static void sdi_config_lcd_manager(struct sdi_device *sdi)
113{
114 sdi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
115
116 sdi->mgr_config.stallmode = false;
117 sdi->mgr_config.fifohandcheck = false;
118
119 sdi->mgr_config.video_port_width = 24;
120 sdi->mgr_config.lcden_sig_polarity = 1;
121
122 dss_mgr_set_lcd_config(&sdi->output, &sdi->mgr_config);
123}
124
125/* -----------------------------------------------------------------------------
126 * DRM Bridge Operations
127 */
128
129static int sdi_bridge_attach(struct drm_bridge *bridge,
130 enum drm_bridge_attach_flags flags)
131{
132 struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
133
134 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
135 return -EINVAL;
136
137 return drm_bridge_attach(bridge->encoder, sdi->output.next_bridge,
138 bridge, flags);
139}
140
141static enum drm_mode_status
142sdi_bridge_mode_valid(struct drm_bridge *bridge,
143 const struct drm_display_info *info,
144 const struct drm_display_mode *mode)
145{
146 struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
147 unsigned long pixelclock = mode->clock * 1000;
148 struct dispc_clock_info dispc_cinfo;
149 unsigned long fck;
150 int ret;
151
152 if (pixelclock == 0)
153 return MODE_NOCLOCK;
154
155 ret = sdi_calc_clock_div(sdi, pixelclock, &fck, &dispc_cinfo);
156 if (ret < 0)
157 return MODE_CLOCK_RANGE;
158
159 return MODE_OK;
160}
161
162static bool sdi_bridge_mode_fixup(struct drm_bridge *bridge,
163 const struct drm_display_mode *mode,
164 struct drm_display_mode *adjusted_mode)
165{
166 struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
167 unsigned long pixelclock = mode->clock * 1000;
168 struct dispc_clock_info dispc_cinfo;
169 unsigned long fck;
170 unsigned long pck;
171 int ret;
172
173 ret = sdi_calc_clock_div(sdi, pixelclock, &fck, &dispc_cinfo);
174 if (ret < 0)
175 return false;
176
177 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
178
179 if (pck != pixelclock)
180 dev_dbg(&sdi->pdev->dev,
181 "pixel clock adjusted from %lu Hz to %lu Hz\n",
182 pixelclock, pck);
183
184 adjusted_mode->clock = pck / 1000;
185
186 return true;
187}
188
189static void sdi_bridge_mode_set(struct drm_bridge *bridge,
190 const struct drm_display_mode *mode,
191 const struct drm_display_mode *adjusted_mode)
192{
193 struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
194
195 sdi->pixelclock = adjusted_mode->clock * 1000;
196}
197
198static void sdi_bridge_enable(struct drm_bridge *bridge)
199{
200 struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
201 struct dispc_clock_info dispc_cinfo;
202 unsigned long fck;
203 int r;
204
205 r = regulator_enable(sdi->vdds_sdi_reg);
206 if (r)
207 return;
208
209 r = dispc_runtime_get(sdi->dss->dispc);
210 if (r)
211 goto err_get_dispc;
212
213 r = sdi_calc_clock_div(sdi, sdi->pixelclock, &fck, &dispc_cinfo);
214 if (r)
215 goto err_calc_clock_div;
216
217 sdi->mgr_config.clock_info = dispc_cinfo;
218
219 r = dss_set_fck_rate(sdi->dss, fck);
220 if (r)
221 goto err_set_dss_clock_div;
222
223 sdi_config_lcd_manager(sdi);
224
225 /*
226 * LCLK and PCLK divisors are located in shadow registers, and we
227 * normally write them to DISPC registers when enabling the output.
228 * However, SDI uses pck-free as source clock for its PLL, and pck-free
229 * is affected by the divisors. And as we need the PLL before enabling
230 * the output, we need to write the divisors early.
231 *
232 * It seems just writing to the DISPC register is enough, and we don't
233 * need to care about the shadow register mechanism for pck-free. The
234 * exact reason for this is unknown.
235 */
236 dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel,
237 &sdi->mgr_config.clock_info);
238
239 dss_sdi_init(sdi->dss, sdi->datapairs);
240 r = dss_sdi_enable(sdi->dss);
241 if (r)
242 goto err_sdi_enable;
243 mdelay(2);
244
245 r = dss_mgr_enable(&sdi->output);
246 if (r)
247 goto err_mgr_enable;
248
249 return;
250
251err_mgr_enable:
252 dss_sdi_disable(sdi->dss);
253err_sdi_enable:
254err_set_dss_clock_div:
255err_calc_clock_div:
256 dispc_runtime_put(sdi->dss->dispc);
257err_get_dispc:
258 regulator_disable(sdi->vdds_sdi_reg);
259}
260
261static void sdi_bridge_disable(struct drm_bridge *bridge)
262{
263 struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
264
265 dss_mgr_disable(&sdi->output);
266
267 dss_sdi_disable(sdi->dss);
268
269 dispc_runtime_put(sdi->dss->dispc);
270
271 regulator_disable(sdi->vdds_sdi_reg);
272}
273
274static const struct drm_bridge_funcs sdi_bridge_funcs = {
275 .attach = sdi_bridge_attach,
276 .mode_valid = sdi_bridge_mode_valid,
277 .mode_fixup = sdi_bridge_mode_fixup,
278 .mode_set = sdi_bridge_mode_set,
279 .enable = sdi_bridge_enable,
280 .disable = sdi_bridge_disable,
281};
282
283static void sdi_bridge_init(struct sdi_device *sdi)
284{
285 sdi->bridge.funcs = &sdi_bridge_funcs;
286 sdi->bridge.of_node = sdi->pdev->dev.of_node;
287 sdi->bridge.type = DRM_MODE_CONNECTOR_LVDS;
288
289 drm_bridge_add(&sdi->bridge);
290}
291
292static void sdi_bridge_cleanup(struct sdi_device *sdi)
293{
294 drm_bridge_remove(&sdi->bridge);
295}
296
297/* -----------------------------------------------------------------------------
298 * Initialisation and Cleanup
299 */
300
301static int sdi_init_output(struct sdi_device *sdi)
302{
303 struct omap_dss_device *out = &sdi->output;
304 int r;
305
306 sdi_bridge_init(sdi);
307
308 out->dev = &sdi->pdev->dev;
309 out->id = OMAP_DSS_OUTPUT_SDI;
310 out->type = OMAP_DISPLAY_TYPE_SDI;
311 out->name = "sdi.0";
312 out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
313 /* We have SDI only on OMAP3, where it's on port 1 */
314 out->of_port = 1;
315 out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE /* 15.5.9.1.2 */
316 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE;
317
318 r = omapdss_device_init_output(out, &sdi->bridge);
319 if (r < 0) {
320 sdi_bridge_cleanup(sdi);
321 return r;
322 }
323
324 omapdss_device_register(out);
325
326 return 0;
327}
328
329static void sdi_uninit_output(struct sdi_device *sdi)
330{
331 omapdss_device_unregister(&sdi->output);
332 omapdss_device_cleanup_output(&sdi->output);
333
334 sdi_bridge_cleanup(sdi);
335}
336
337int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
338 struct device_node *port)
339{
340 struct sdi_device *sdi;
341 struct device_node *ep;
342 u32 datapairs;
343 int r;
344
345 sdi = kzalloc(sizeof(*sdi), GFP_KERNEL);
346 if (!sdi)
347 return -ENOMEM;
348
349 ep = of_get_next_child(port, NULL);
350 if (!ep) {
351 r = 0;
352 goto err_free;
353 }
354
355 r = of_property_read_u32(ep, "datapairs", &datapairs);
356 of_node_put(ep);
357 if (r) {
358 DSSERR("failed to parse datapairs\n");
359 goto err_free;
360 }
361
362 sdi->datapairs = datapairs;
363 sdi->dss = dss;
364
365 sdi->pdev = pdev;
366 port->data = sdi;
367
368 sdi->vdds_sdi_reg = devm_regulator_get(&pdev->dev, "vdds_sdi");
369 if (IS_ERR(sdi->vdds_sdi_reg)) {
370 r = PTR_ERR(sdi->vdds_sdi_reg);
371 if (r != -EPROBE_DEFER)
372 DSSERR("can't get VDDS_SDI regulator\n");
373 goto err_free;
374 }
375
376 r = sdi_init_output(sdi);
377 if (r)
378 goto err_free;
379
380 return 0;
381
382err_free:
383 kfree(sdi);
384
385 return r;
386}
387
388void sdi_uninit_port(struct device_node *port)
389{
390 struct sdi_device *sdi = port->data;
391
392 if (!sdi)
393 return;
394
395 sdi_uninit_output(sdi);
396 kfree(sdi);
397}
1/*
2 * linux/drivers/video/omap2/dss/sdi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DSS_SUBSYS_NAME "SDI"
21
22#include <linux/kernel.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/regulator/consumer.h>
26#include <linux/export.h>
27#include <linux/platform_device.h>
28#include <linux/string.h>
29#include <linux/of.h>
30#include <linux/component.h>
31
32#include "omapdss.h"
33#include "dss.h"
34
35static struct {
36 struct platform_device *pdev;
37
38 bool update_enabled;
39 struct regulator *vdds_sdi_reg;
40
41 struct dss_lcd_mgr_config mgr_config;
42 struct videomode vm;
43 int datapairs;
44
45 struct omap_dss_device output;
46
47 bool port_initialized;
48} sdi;
49
50struct sdi_clk_calc_ctx {
51 unsigned long pck_min, pck_max;
52
53 unsigned long fck;
54 struct dispc_clock_info dispc_cinfo;
55};
56
57static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
58 unsigned long pck, void *data)
59{
60 struct sdi_clk_calc_ctx *ctx = data;
61
62 ctx->dispc_cinfo.lck_div = lckd;
63 ctx->dispc_cinfo.pck_div = pckd;
64 ctx->dispc_cinfo.lck = lck;
65 ctx->dispc_cinfo.pck = pck;
66
67 return true;
68}
69
70static bool dpi_calc_dss_cb(unsigned long fck, void *data)
71{
72 struct sdi_clk_calc_ctx *ctx = data;
73
74 ctx->fck = fck;
75
76 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
77 dpi_calc_dispc_cb, ctx);
78}
79
80static int sdi_calc_clock_div(unsigned long pclk,
81 unsigned long *fck,
82 struct dispc_clock_info *dispc_cinfo)
83{
84 int i;
85 struct sdi_clk_calc_ctx ctx;
86
87 /*
88 * DSS fclk gives us very few possibilities, so finding a good pixel
89 * clock may not be possible. We try multiple times to find the clock,
90 * each time widening the pixel clock range we look for, up to
91 * +/- 1MHz.
92 */
93
94 for (i = 0; i < 10; ++i) {
95 bool ok;
96
97 memset(&ctx, 0, sizeof(ctx));
98 if (pclk > 1000 * i * i * i)
99 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
100 else
101 ctx.pck_min = 0;
102 ctx.pck_max = pclk + 1000 * i * i * i;
103
104 ok = dss_div_calc(pclk, ctx.pck_min, dpi_calc_dss_cb, &ctx);
105 if (ok) {
106 *fck = ctx.fck;
107 *dispc_cinfo = ctx.dispc_cinfo;
108 return 0;
109 }
110 }
111
112 return -EINVAL;
113}
114
115static void sdi_config_lcd_manager(struct omap_dss_device *dssdev)
116{
117 enum omap_channel channel = dssdev->dispc_channel;
118
119 sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
120
121 sdi.mgr_config.stallmode = false;
122 sdi.mgr_config.fifohandcheck = false;
123
124 sdi.mgr_config.video_port_width = 24;
125 sdi.mgr_config.lcden_sig_polarity = 1;
126
127 dss_mgr_set_lcd_config(channel, &sdi.mgr_config);
128}
129
130static int sdi_display_enable(struct omap_dss_device *dssdev)
131{
132 struct omap_dss_device *out = &sdi.output;
133 enum omap_channel channel = dssdev->dispc_channel;
134 struct videomode *vm = &sdi.vm;
135 unsigned long fck;
136 struct dispc_clock_info dispc_cinfo;
137 unsigned long pck;
138 int r;
139
140 if (!out->dispc_channel_connected) {
141 DSSERR("failed to enable display: no output/manager\n");
142 return -ENODEV;
143 }
144
145 r = regulator_enable(sdi.vdds_sdi_reg);
146 if (r)
147 goto err_reg_enable;
148
149 r = dispc_runtime_get();
150 if (r)
151 goto err_get_dispc;
152
153 /* 15.5.9.1.2 */
154 vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE;
155
156 r = sdi_calc_clock_div(vm->pixelclock, &fck, &dispc_cinfo);
157 if (r)
158 goto err_calc_clock_div;
159
160 sdi.mgr_config.clock_info = dispc_cinfo;
161
162 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
163
164 if (pck != vm->pixelclock) {
165 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n",
166 vm->pixelclock, pck);
167
168 vm->pixelclock = pck;
169 }
170
171
172 dss_mgr_set_timings(channel, vm);
173
174 r = dss_set_fck_rate(fck);
175 if (r)
176 goto err_set_dss_clock_div;
177
178 sdi_config_lcd_manager(dssdev);
179
180 /*
181 * LCLK and PCLK divisors are located in shadow registers, and we
182 * normally write them to DISPC registers when enabling the output.
183 * However, SDI uses pck-free as source clock for its PLL, and pck-free
184 * is affected by the divisors. And as we need the PLL before enabling
185 * the output, we need to write the divisors early.
186 *
187 * It seems just writing to the DISPC register is enough, and we don't
188 * need to care about the shadow register mechanism for pck-free. The
189 * exact reason for this is unknown.
190 */
191 dispc_mgr_set_clock_div(channel, &sdi.mgr_config.clock_info);
192
193 dss_sdi_init(sdi.datapairs);
194 r = dss_sdi_enable();
195 if (r)
196 goto err_sdi_enable;
197 mdelay(2);
198
199 r = dss_mgr_enable(channel);
200 if (r)
201 goto err_mgr_enable;
202
203 return 0;
204
205err_mgr_enable:
206 dss_sdi_disable();
207err_sdi_enable:
208err_set_dss_clock_div:
209err_calc_clock_div:
210 dispc_runtime_put();
211err_get_dispc:
212 regulator_disable(sdi.vdds_sdi_reg);
213err_reg_enable:
214 return r;
215}
216
217static void sdi_display_disable(struct omap_dss_device *dssdev)
218{
219 enum omap_channel channel = dssdev->dispc_channel;
220
221 dss_mgr_disable(channel);
222
223 dss_sdi_disable();
224
225 dispc_runtime_put();
226
227 regulator_disable(sdi.vdds_sdi_reg);
228}
229
230static void sdi_set_timings(struct omap_dss_device *dssdev,
231 struct videomode *vm)
232{
233 sdi.vm = *vm;
234}
235
236static void sdi_get_timings(struct omap_dss_device *dssdev,
237 struct videomode *vm)
238{
239 *vm = sdi.vm;
240}
241
242static int sdi_check_timings(struct omap_dss_device *dssdev,
243 struct videomode *vm)
244{
245 enum omap_channel channel = dssdev->dispc_channel;
246
247 if (!dispc_mgr_timings_ok(channel, vm))
248 return -EINVAL;
249
250 if (vm->pixelclock == 0)
251 return -EINVAL;
252
253 return 0;
254}
255
256static void sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs)
257{
258 sdi.datapairs = datapairs;
259}
260
261static int sdi_init_regulator(void)
262{
263 struct regulator *vdds_sdi;
264
265 if (sdi.vdds_sdi_reg)
266 return 0;
267
268 vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi");
269 if (IS_ERR(vdds_sdi)) {
270 if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER)
271 DSSERR("can't get VDDS_SDI regulator\n");
272 return PTR_ERR(vdds_sdi);
273 }
274
275 sdi.vdds_sdi_reg = vdds_sdi;
276
277 return 0;
278}
279
280static int sdi_connect(struct omap_dss_device *dssdev,
281 struct omap_dss_device *dst)
282{
283 enum omap_channel channel = dssdev->dispc_channel;
284 int r;
285
286 r = sdi_init_regulator();
287 if (r)
288 return r;
289
290 r = dss_mgr_connect(channel, dssdev);
291 if (r)
292 return r;
293
294 r = omapdss_output_set_device(dssdev, dst);
295 if (r) {
296 DSSERR("failed to connect output to new device: %s\n",
297 dst->name);
298 dss_mgr_disconnect(channel, dssdev);
299 return r;
300 }
301
302 return 0;
303}
304
305static void sdi_disconnect(struct omap_dss_device *dssdev,
306 struct omap_dss_device *dst)
307{
308 enum omap_channel channel = dssdev->dispc_channel;
309
310 WARN_ON(dst != dssdev->dst);
311
312 if (dst != dssdev->dst)
313 return;
314
315 omapdss_output_unset_device(dssdev);
316
317 dss_mgr_disconnect(channel, dssdev);
318}
319
320static const struct omapdss_sdi_ops sdi_ops = {
321 .connect = sdi_connect,
322 .disconnect = sdi_disconnect,
323
324 .enable = sdi_display_enable,
325 .disable = sdi_display_disable,
326
327 .check_timings = sdi_check_timings,
328 .set_timings = sdi_set_timings,
329 .get_timings = sdi_get_timings,
330
331 .set_datapairs = sdi_set_datapairs,
332};
333
334static void sdi_init_output(struct platform_device *pdev)
335{
336 struct omap_dss_device *out = &sdi.output;
337
338 out->dev = &pdev->dev;
339 out->id = OMAP_DSS_OUTPUT_SDI;
340 out->output_type = OMAP_DISPLAY_TYPE_SDI;
341 out->name = "sdi.0";
342 out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
343 /* We have SDI only on OMAP3, where it's on port 1 */
344 out->port_num = 1;
345 out->ops.sdi = &sdi_ops;
346 out->owner = THIS_MODULE;
347
348 omapdss_register_output(out);
349}
350
351static void sdi_uninit_output(struct platform_device *pdev)
352{
353 struct omap_dss_device *out = &sdi.output;
354
355 omapdss_unregister_output(out);
356}
357
358static int sdi_bind(struct device *dev, struct device *master, void *data)
359{
360 struct platform_device *pdev = to_platform_device(dev);
361
362 sdi.pdev = pdev;
363
364 sdi_init_output(pdev);
365
366 return 0;
367}
368
369static void sdi_unbind(struct device *dev, struct device *master, void *data)
370{
371 struct platform_device *pdev = to_platform_device(dev);
372
373 sdi_uninit_output(pdev);
374}
375
376static const struct component_ops sdi_component_ops = {
377 .bind = sdi_bind,
378 .unbind = sdi_unbind,
379};
380
381static int sdi_probe(struct platform_device *pdev)
382{
383 return component_add(&pdev->dev, &sdi_component_ops);
384}
385
386static int sdi_remove(struct platform_device *pdev)
387{
388 component_del(&pdev->dev, &sdi_component_ops);
389 return 0;
390}
391
392static struct platform_driver omap_sdi_driver = {
393 .probe = sdi_probe,
394 .remove = sdi_remove,
395 .driver = {
396 .name = "omapdss_sdi",
397 .suppress_bind_attrs = true,
398 },
399};
400
401int __init sdi_init_platform_driver(void)
402{
403 return platform_driver_register(&omap_sdi_driver);
404}
405
406void sdi_uninit_platform_driver(void)
407{
408 platform_driver_unregister(&omap_sdi_driver);
409}
410
411int sdi_init_port(struct platform_device *pdev, struct device_node *port)
412{
413 struct device_node *ep;
414 u32 datapairs;
415 int r;
416
417 ep = omapdss_of_get_next_endpoint(port, NULL);
418 if (!ep)
419 return 0;
420
421 r = of_property_read_u32(ep, "datapairs", &datapairs);
422 if (r) {
423 DSSERR("failed to parse datapairs\n");
424 goto err_datapairs;
425 }
426
427 sdi.datapairs = datapairs;
428
429 of_node_put(ep);
430
431 sdi.pdev = pdev;
432
433 sdi_init_output(pdev);
434
435 sdi.port_initialized = true;
436
437 return 0;
438
439err_datapairs:
440 of_node_put(ep);
441
442 return r;
443}
444
445void sdi_uninit_port(struct device_node *port)
446{
447 if (!sdi.port_initialized)
448 return;
449
450 sdi_uninit_output(sdi.pdev);
451}