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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
4 * Author: Archit Taneja <archit@ti.com>
5 */
6
7#ifndef __OMAP2_DISPC_REG_H
8#define __OMAP2_DISPC_REG_H
9
10/* DISPC common registers */
11#define DISPC_REVISION 0x0000
12#define DISPC_SYSCONFIG 0x0010
13#define DISPC_SYSSTATUS 0x0014
14#define DISPC_IRQSTATUS 0x0018
15#define DISPC_IRQENABLE 0x001C
16#define DISPC_CONTROL 0x0040
17#define DISPC_CONFIG 0x0044
18#define DISPC_CAPABLE 0x0048
19#define DISPC_LINE_STATUS 0x005C
20#define DISPC_LINE_NUMBER 0x0060
21#define DISPC_GLOBAL_ALPHA 0x0074
22#define DISPC_CONTROL2 0x0238
23#define DISPC_CONFIG2 0x0620
24#define DISPC_DIVISOR 0x0804
25#define DISPC_GLOBAL_BUFFER 0x0800
26#define DISPC_CONTROL3 0x0848
27#define DISPC_CONFIG3 0x084C
28#define DISPC_MSTANDBY_CTRL 0x0858
29#define DISPC_GLOBAL_MFLAG_ATTRIBUTE 0x085C
30
31#define DISPC_GAMMA_TABLE0 0x0630
32#define DISPC_GAMMA_TABLE1 0x0634
33#define DISPC_GAMMA_TABLE2 0x0638
34#define DISPC_GAMMA_TABLE3 0x0850
35
36/* DISPC overlay registers */
37#define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
38 DISPC_BA0_OFFSET(n))
39#define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
40 DISPC_BA1_OFFSET(n))
41#define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
42 DISPC_BA0_UV_OFFSET(n))
43#define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
44 DISPC_BA1_UV_OFFSET(n))
45#define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
46 DISPC_POS_OFFSET(n))
47#define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
48 DISPC_SIZE_OFFSET(n))
49#define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
50 DISPC_ATTR_OFFSET(n))
51#define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
52 DISPC_ATTR2_OFFSET(n))
53#define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
54 DISPC_FIFO_THRESH_OFFSET(n))
55#define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
56 DISPC_FIFO_SIZE_STATUS_OFFSET(n))
57#define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
58 DISPC_ROW_INC_OFFSET(n))
59#define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
60 DISPC_PIX_INC_OFFSET(n))
61#define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
62 DISPC_WINDOW_SKIP_OFFSET(n))
63#define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
64 DISPC_TABLE_BA_OFFSET(n))
65#define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
66 DISPC_FIR_OFFSET(n))
67#define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
68 DISPC_FIR2_OFFSET(n))
69#define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
70 DISPC_PIC_SIZE_OFFSET(n))
71#define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
72 DISPC_ACCU0_OFFSET(n))
73#define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
74 DISPC_ACCU1_OFFSET(n))
75#define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
76 DISPC_ACCU2_0_OFFSET(n))
77#define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
78 DISPC_ACCU2_1_OFFSET(n))
79#define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
80 DISPC_FIR_COEF_H_OFFSET(n, i))
81#define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
82 DISPC_FIR_COEF_HV_OFFSET(n, i))
83#define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
84 DISPC_FIR_COEF_H2_OFFSET(n, i))
85#define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
86 DISPC_FIR_COEF_HV2_OFFSET(n, i))
87#define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
88 DISPC_CONV_COEF_OFFSET(n, i))
89#define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
90 DISPC_FIR_COEF_V_OFFSET(n, i))
91#define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
92 DISPC_FIR_COEF_V2_OFFSET(n, i))
93#define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
94 DISPC_PRELOAD_OFFSET(n))
95#define DISPC_OVL_MFLAG_THRESHOLD(n) DISPC_MFLAG_THRESHOLD_OFFSET(n)
96
97/* DISPC up/downsampling FIR filter coefficient structure */
98struct dispc_coef {
99 s8 hc4_vc22;
100 s8 hc3_vc2;
101 u8 hc2_vc1;
102 s8 hc1_vc0;
103 s8 hc0_vc00;
104};
105
106const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
107
108/* DISPC manager/channel specific registers */
109static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
110{
111 switch (channel) {
112 case OMAP_DSS_CHANNEL_LCD:
113 return 0x004C;
114 case OMAP_DSS_CHANNEL_DIGIT:
115 return 0x0050;
116 case OMAP_DSS_CHANNEL_LCD2:
117 return 0x03AC;
118 case OMAP_DSS_CHANNEL_LCD3:
119 return 0x0814;
120 default:
121 BUG();
122 return 0;
123 }
124}
125
126static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
127{
128 switch (channel) {
129 case OMAP_DSS_CHANNEL_LCD:
130 return 0x0054;
131 case OMAP_DSS_CHANNEL_DIGIT:
132 return 0x0058;
133 case OMAP_DSS_CHANNEL_LCD2:
134 return 0x03B0;
135 case OMAP_DSS_CHANNEL_LCD3:
136 return 0x0818;
137 default:
138 BUG();
139 return 0;
140 }
141}
142
143static inline u16 DISPC_TIMING_H(enum omap_channel channel)
144{
145 switch (channel) {
146 case OMAP_DSS_CHANNEL_LCD:
147 return 0x0064;
148 case OMAP_DSS_CHANNEL_DIGIT:
149 BUG();
150 return 0;
151 case OMAP_DSS_CHANNEL_LCD2:
152 return 0x0400;
153 case OMAP_DSS_CHANNEL_LCD3:
154 return 0x0840;
155 default:
156 BUG();
157 return 0;
158 }
159}
160
161static inline u16 DISPC_TIMING_V(enum omap_channel channel)
162{
163 switch (channel) {
164 case OMAP_DSS_CHANNEL_LCD:
165 return 0x0068;
166 case OMAP_DSS_CHANNEL_DIGIT:
167 BUG();
168 return 0;
169 case OMAP_DSS_CHANNEL_LCD2:
170 return 0x0404;
171 case OMAP_DSS_CHANNEL_LCD3:
172 return 0x0844;
173 default:
174 BUG();
175 return 0;
176 }
177}
178
179static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
180{
181 switch (channel) {
182 case OMAP_DSS_CHANNEL_LCD:
183 return 0x006C;
184 case OMAP_DSS_CHANNEL_DIGIT:
185 BUG();
186 return 0;
187 case OMAP_DSS_CHANNEL_LCD2:
188 return 0x0408;
189 case OMAP_DSS_CHANNEL_LCD3:
190 return 0x083C;
191 default:
192 BUG();
193 return 0;
194 }
195}
196
197static inline u16 DISPC_DIVISORo(enum omap_channel channel)
198{
199 switch (channel) {
200 case OMAP_DSS_CHANNEL_LCD:
201 return 0x0070;
202 case OMAP_DSS_CHANNEL_DIGIT:
203 BUG();
204 return 0;
205 case OMAP_DSS_CHANNEL_LCD2:
206 return 0x040C;
207 case OMAP_DSS_CHANNEL_LCD3:
208 return 0x0838;
209 default:
210 BUG();
211 return 0;
212 }
213}
214
215/* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
216static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
217{
218 switch (channel) {
219 case OMAP_DSS_CHANNEL_LCD:
220 return 0x007C;
221 case OMAP_DSS_CHANNEL_DIGIT:
222 return 0x0078;
223 case OMAP_DSS_CHANNEL_LCD2:
224 return 0x03CC;
225 case OMAP_DSS_CHANNEL_LCD3:
226 return 0x0834;
227 default:
228 BUG();
229 return 0;
230 }
231}
232
233static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
234{
235 switch (channel) {
236 case OMAP_DSS_CHANNEL_LCD:
237 return 0x01D4;
238 case OMAP_DSS_CHANNEL_DIGIT:
239 BUG();
240 return 0;
241 case OMAP_DSS_CHANNEL_LCD2:
242 return 0x03C0;
243 case OMAP_DSS_CHANNEL_LCD3:
244 return 0x0828;
245 default:
246 BUG();
247 return 0;
248 }
249}
250
251static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
252{
253 switch (channel) {
254 case OMAP_DSS_CHANNEL_LCD:
255 return 0x01D8;
256 case OMAP_DSS_CHANNEL_DIGIT:
257 BUG();
258 return 0;
259 case OMAP_DSS_CHANNEL_LCD2:
260 return 0x03C4;
261 case OMAP_DSS_CHANNEL_LCD3:
262 return 0x082C;
263 default:
264 BUG();
265 return 0;
266 }
267}
268
269static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
270{
271 switch (channel) {
272 case OMAP_DSS_CHANNEL_LCD:
273 return 0x01DC;
274 case OMAP_DSS_CHANNEL_DIGIT:
275 BUG();
276 return 0;
277 case OMAP_DSS_CHANNEL_LCD2:
278 return 0x03C8;
279 case OMAP_DSS_CHANNEL_LCD3:
280 return 0x0830;
281 default:
282 BUG();
283 return 0;
284 }
285}
286
287static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
288{
289 switch (channel) {
290 case OMAP_DSS_CHANNEL_LCD:
291 return 0x0220;
292 case OMAP_DSS_CHANNEL_DIGIT:
293 BUG();
294 return 0;
295 case OMAP_DSS_CHANNEL_LCD2:
296 return 0x03BC;
297 case OMAP_DSS_CHANNEL_LCD3:
298 return 0x0824;
299 default:
300 BUG();
301 return 0;
302 }
303}
304
305static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
306{
307 switch (channel) {
308 case OMAP_DSS_CHANNEL_LCD:
309 return 0x0224;
310 case OMAP_DSS_CHANNEL_DIGIT:
311 BUG();
312 return 0;
313 case OMAP_DSS_CHANNEL_LCD2:
314 return 0x03B8;
315 case OMAP_DSS_CHANNEL_LCD3:
316 return 0x0820;
317 default:
318 BUG();
319 return 0;
320 }
321}
322
323static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
324{
325 switch (channel) {
326 case OMAP_DSS_CHANNEL_LCD:
327 return 0x0228;
328 case OMAP_DSS_CHANNEL_DIGIT:
329 BUG();
330 return 0;
331 case OMAP_DSS_CHANNEL_LCD2:
332 return 0x03B4;
333 case OMAP_DSS_CHANNEL_LCD3:
334 return 0x081C;
335 default:
336 BUG();
337 return 0;
338 }
339}
340
341/* DISPC overlay register base addresses */
342static inline u16 DISPC_OVL_BASE(enum omap_plane_id plane)
343{
344 switch (plane) {
345 case OMAP_DSS_GFX:
346 return 0x0080;
347 case OMAP_DSS_VIDEO1:
348 return 0x00BC;
349 case OMAP_DSS_VIDEO2:
350 return 0x014C;
351 case OMAP_DSS_VIDEO3:
352 return 0x0300;
353 case OMAP_DSS_WB:
354 return 0x0500;
355 default:
356 BUG();
357 return 0;
358 }
359}
360
361/* DISPC overlay register offsets */
362static inline u16 DISPC_BA0_OFFSET(enum omap_plane_id plane)
363{
364 switch (plane) {
365 case OMAP_DSS_GFX:
366 case OMAP_DSS_VIDEO1:
367 case OMAP_DSS_VIDEO2:
368 return 0x0000;
369 case OMAP_DSS_VIDEO3:
370 case OMAP_DSS_WB:
371 return 0x0008;
372 default:
373 BUG();
374 return 0;
375 }
376}
377
378static inline u16 DISPC_BA1_OFFSET(enum omap_plane_id plane)
379{
380 switch (plane) {
381 case OMAP_DSS_GFX:
382 case OMAP_DSS_VIDEO1:
383 case OMAP_DSS_VIDEO2:
384 return 0x0004;
385 case OMAP_DSS_VIDEO3:
386 case OMAP_DSS_WB:
387 return 0x000C;
388 default:
389 BUG();
390 return 0;
391 }
392}
393
394static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane_id plane)
395{
396 switch (plane) {
397 case OMAP_DSS_GFX:
398 BUG();
399 return 0;
400 case OMAP_DSS_VIDEO1:
401 return 0x0544;
402 case OMAP_DSS_VIDEO2:
403 return 0x04BC;
404 case OMAP_DSS_VIDEO3:
405 return 0x0310;
406 case OMAP_DSS_WB:
407 return 0x0118;
408 default:
409 BUG();
410 return 0;
411 }
412}
413
414static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane_id plane)
415{
416 switch (plane) {
417 case OMAP_DSS_GFX:
418 BUG();
419 return 0;
420 case OMAP_DSS_VIDEO1:
421 return 0x0548;
422 case OMAP_DSS_VIDEO2:
423 return 0x04C0;
424 case OMAP_DSS_VIDEO3:
425 return 0x0314;
426 case OMAP_DSS_WB:
427 return 0x011C;
428 default:
429 BUG();
430 return 0;
431 }
432}
433
434static inline u16 DISPC_POS_OFFSET(enum omap_plane_id plane)
435{
436 switch (plane) {
437 case OMAP_DSS_GFX:
438 case OMAP_DSS_VIDEO1:
439 case OMAP_DSS_VIDEO2:
440 return 0x0008;
441 case OMAP_DSS_VIDEO3:
442 return 0x009C;
443 default:
444 BUG();
445 return 0;
446 }
447}
448
449static inline u16 DISPC_SIZE_OFFSET(enum omap_plane_id plane)
450{
451 switch (plane) {
452 case OMAP_DSS_GFX:
453 case OMAP_DSS_VIDEO1:
454 case OMAP_DSS_VIDEO2:
455 return 0x000C;
456 case OMAP_DSS_VIDEO3:
457 case OMAP_DSS_WB:
458 return 0x00A8;
459 default:
460 BUG();
461 return 0;
462 }
463}
464
465static inline u16 DISPC_ATTR_OFFSET(enum omap_plane_id plane)
466{
467 switch (plane) {
468 case OMAP_DSS_GFX:
469 return 0x0020;
470 case OMAP_DSS_VIDEO1:
471 case OMAP_DSS_VIDEO2:
472 return 0x0010;
473 case OMAP_DSS_VIDEO3:
474 case OMAP_DSS_WB:
475 return 0x0070;
476 default:
477 BUG();
478 return 0;
479 }
480}
481
482static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane_id plane)
483{
484 switch (plane) {
485 case OMAP_DSS_GFX:
486 BUG();
487 return 0;
488 case OMAP_DSS_VIDEO1:
489 return 0x0568;
490 case OMAP_DSS_VIDEO2:
491 return 0x04DC;
492 case OMAP_DSS_VIDEO3:
493 return 0x032C;
494 case OMAP_DSS_WB:
495 return 0x0310;
496 default:
497 BUG();
498 return 0;
499 }
500}
501
502static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane_id plane)
503{
504 switch (plane) {
505 case OMAP_DSS_GFX:
506 return 0x0024;
507 case OMAP_DSS_VIDEO1:
508 case OMAP_DSS_VIDEO2:
509 return 0x0014;
510 case OMAP_DSS_VIDEO3:
511 case OMAP_DSS_WB:
512 return 0x008C;
513 default:
514 BUG();
515 return 0;
516 }
517}
518
519static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane_id plane)
520{
521 switch (plane) {
522 case OMAP_DSS_GFX:
523 return 0x0028;
524 case OMAP_DSS_VIDEO1:
525 case OMAP_DSS_VIDEO2:
526 return 0x0018;
527 case OMAP_DSS_VIDEO3:
528 case OMAP_DSS_WB:
529 return 0x0088;
530 default:
531 BUG();
532 return 0;
533 }
534}
535
536static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane_id plane)
537{
538 switch (plane) {
539 case OMAP_DSS_GFX:
540 return 0x002C;
541 case OMAP_DSS_VIDEO1:
542 case OMAP_DSS_VIDEO2:
543 return 0x001C;
544 case OMAP_DSS_VIDEO3:
545 case OMAP_DSS_WB:
546 return 0x00A4;
547 default:
548 BUG();
549 return 0;
550 }
551}
552
553static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane_id plane)
554{
555 switch (plane) {
556 case OMAP_DSS_GFX:
557 return 0x0030;
558 case OMAP_DSS_VIDEO1:
559 case OMAP_DSS_VIDEO2:
560 return 0x0020;
561 case OMAP_DSS_VIDEO3:
562 case OMAP_DSS_WB:
563 return 0x0098;
564 default:
565 BUG();
566 return 0;
567 }
568}
569
570static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane_id plane)
571{
572 switch (plane) {
573 case OMAP_DSS_GFX:
574 return 0x0034;
575 case OMAP_DSS_VIDEO1:
576 case OMAP_DSS_VIDEO2:
577 case OMAP_DSS_VIDEO3:
578 BUG();
579 return 0;
580 default:
581 BUG();
582 return 0;
583 }
584}
585
586static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane_id plane)
587{
588 switch (plane) {
589 case OMAP_DSS_GFX:
590 return 0x0038;
591 case OMAP_DSS_VIDEO1:
592 case OMAP_DSS_VIDEO2:
593 case OMAP_DSS_VIDEO3:
594 BUG();
595 return 0;
596 default:
597 BUG();
598 return 0;
599 }
600}
601
602static inline u16 DISPC_FIR_OFFSET(enum omap_plane_id plane)
603{
604 switch (plane) {
605 case OMAP_DSS_GFX:
606 BUG();
607 return 0;
608 case OMAP_DSS_VIDEO1:
609 case OMAP_DSS_VIDEO2:
610 return 0x0024;
611 case OMAP_DSS_VIDEO3:
612 case OMAP_DSS_WB:
613 return 0x0090;
614 default:
615 BUG();
616 return 0;
617 }
618}
619
620static inline u16 DISPC_FIR2_OFFSET(enum omap_plane_id plane)
621{
622 switch (plane) {
623 case OMAP_DSS_GFX:
624 BUG();
625 return 0;
626 case OMAP_DSS_VIDEO1:
627 return 0x0580;
628 case OMAP_DSS_VIDEO2:
629 return 0x055C;
630 case OMAP_DSS_VIDEO3:
631 return 0x0424;
632 case OMAP_DSS_WB:
633 return 0x290;
634 default:
635 BUG();
636 return 0;
637 }
638}
639
640static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane_id plane)
641{
642 switch (plane) {
643 case OMAP_DSS_GFX:
644 BUG();
645 return 0;
646 case OMAP_DSS_VIDEO1:
647 case OMAP_DSS_VIDEO2:
648 return 0x0028;
649 case OMAP_DSS_VIDEO3:
650 case OMAP_DSS_WB:
651 return 0x0094;
652 default:
653 BUG();
654 return 0;
655 }
656}
657
658
659static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane_id plane)
660{
661 switch (plane) {
662 case OMAP_DSS_GFX:
663 BUG();
664 return 0;
665 case OMAP_DSS_VIDEO1:
666 case OMAP_DSS_VIDEO2:
667 return 0x002C;
668 case OMAP_DSS_VIDEO3:
669 case OMAP_DSS_WB:
670 return 0x0000;
671 default:
672 BUG();
673 return 0;
674 }
675}
676
677static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane_id plane)
678{
679 switch (plane) {
680 case OMAP_DSS_GFX:
681 BUG();
682 return 0;
683 case OMAP_DSS_VIDEO1:
684 return 0x0584;
685 case OMAP_DSS_VIDEO2:
686 return 0x0560;
687 case OMAP_DSS_VIDEO3:
688 return 0x0428;
689 case OMAP_DSS_WB:
690 return 0x0294;
691 default:
692 BUG();
693 return 0;
694 }
695}
696
697static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane_id plane)
698{
699 switch (plane) {
700 case OMAP_DSS_GFX:
701 BUG();
702 return 0;
703 case OMAP_DSS_VIDEO1:
704 case OMAP_DSS_VIDEO2:
705 return 0x0030;
706 case OMAP_DSS_VIDEO3:
707 case OMAP_DSS_WB:
708 return 0x0004;
709 default:
710 BUG();
711 return 0;
712 }
713}
714
715static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane_id plane)
716{
717 switch (plane) {
718 case OMAP_DSS_GFX:
719 BUG();
720 return 0;
721 case OMAP_DSS_VIDEO1:
722 return 0x0588;
723 case OMAP_DSS_VIDEO2:
724 return 0x0564;
725 case OMAP_DSS_VIDEO3:
726 return 0x042C;
727 case OMAP_DSS_WB:
728 return 0x0298;
729 default:
730 BUG();
731 return 0;
732 }
733}
734
735/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
736static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane_id plane, u16 i)
737{
738 switch (plane) {
739 case OMAP_DSS_GFX:
740 BUG();
741 return 0;
742 case OMAP_DSS_VIDEO1:
743 case OMAP_DSS_VIDEO2:
744 return 0x0034 + i * 0x8;
745 case OMAP_DSS_VIDEO3:
746 case OMAP_DSS_WB:
747 return 0x0010 + i * 0x8;
748 default:
749 BUG();
750 return 0;
751 }
752}
753
754/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
755static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane_id plane, u16 i)
756{
757 switch (plane) {
758 case OMAP_DSS_GFX:
759 BUG();
760 return 0;
761 case OMAP_DSS_VIDEO1:
762 return 0x058C + i * 0x8;
763 case OMAP_DSS_VIDEO2:
764 return 0x0568 + i * 0x8;
765 case OMAP_DSS_VIDEO3:
766 return 0x0430 + i * 0x8;
767 case OMAP_DSS_WB:
768 return 0x02A0 + i * 0x8;
769 default:
770 BUG();
771 return 0;
772 }
773}
774
775/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
776static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane_id plane, u16 i)
777{
778 switch (plane) {
779 case OMAP_DSS_GFX:
780 BUG();
781 return 0;
782 case OMAP_DSS_VIDEO1:
783 case OMAP_DSS_VIDEO2:
784 return 0x0038 + i * 0x8;
785 case OMAP_DSS_VIDEO3:
786 case OMAP_DSS_WB:
787 return 0x0014 + i * 0x8;
788 default:
789 BUG();
790 return 0;
791 }
792}
793
794/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
795static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane_id plane, u16 i)
796{
797 switch (plane) {
798 case OMAP_DSS_GFX:
799 BUG();
800 return 0;
801 case OMAP_DSS_VIDEO1:
802 return 0x0590 + i * 8;
803 case OMAP_DSS_VIDEO2:
804 return 0x056C + i * 0x8;
805 case OMAP_DSS_VIDEO3:
806 return 0x0434 + i * 0x8;
807 case OMAP_DSS_WB:
808 return 0x02A4 + i * 0x8;
809 default:
810 BUG();
811 return 0;
812 }
813}
814
815/* coef index i = {0, 1, 2, 3, 4,} */
816static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane_id plane, u16 i)
817{
818 switch (plane) {
819 case OMAP_DSS_GFX:
820 BUG();
821 return 0;
822 case OMAP_DSS_VIDEO1:
823 case OMAP_DSS_VIDEO2:
824 case OMAP_DSS_VIDEO3:
825 case OMAP_DSS_WB:
826 return 0x0074 + i * 0x4;
827 default:
828 BUG();
829 return 0;
830 }
831}
832
833/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
834static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane_id plane, u16 i)
835{
836 switch (plane) {
837 case OMAP_DSS_GFX:
838 BUG();
839 return 0;
840 case OMAP_DSS_VIDEO1:
841 return 0x0124 + i * 0x4;
842 case OMAP_DSS_VIDEO2:
843 return 0x00B4 + i * 0x4;
844 case OMAP_DSS_VIDEO3:
845 case OMAP_DSS_WB:
846 return 0x0050 + i * 0x4;
847 default:
848 BUG();
849 return 0;
850 }
851}
852
853/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
854static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane_id plane, u16 i)
855{
856 switch (plane) {
857 case OMAP_DSS_GFX:
858 BUG();
859 return 0;
860 case OMAP_DSS_VIDEO1:
861 return 0x05CC + i * 0x4;
862 case OMAP_DSS_VIDEO2:
863 return 0x05A8 + i * 0x4;
864 case OMAP_DSS_VIDEO3:
865 return 0x0470 + i * 0x4;
866 case OMAP_DSS_WB:
867 return 0x02E0 + i * 0x4;
868 default:
869 BUG();
870 return 0;
871 }
872}
873
874static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane_id plane)
875{
876 switch (plane) {
877 case OMAP_DSS_GFX:
878 return 0x01AC;
879 case OMAP_DSS_VIDEO1:
880 return 0x0174;
881 case OMAP_DSS_VIDEO2:
882 return 0x00E8;
883 case OMAP_DSS_VIDEO3:
884 return 0x00A0;
885 default:
886 BUG();
887 return 0;
888 }
889}
890
891static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane_id plane)
892{
893 switch (plane) {
894 case OMAP_DSS_GFX:
895 return 0x0860;
896 case OMAP_DSS_VIDEO1:
897 return 0x0864;
898 case OMAP_DSS_VIDEO2:
899 return 0x0868;
900 case OMAP_DSS_VIDEO3:
901 return 0x086c;
902 case OMAP_DSS_WB:
903 return 0x0870;
904 default:
905 BUG();
906 return 0;
907 }
908}
909#endif
1/*
2 * linux/drivers/video/omap2/dss/dispc.h
3 *
4 * Copyright (C) 2011 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef __OMAP2_DISPC_REG_H
22#define __OMAP2_DISPC_REG_H
23
24/* DISPC common registers */
25#define DISPC_REVISION 0x0000
26#define DISPC_SYSCONFIG 0x0010
27#define DISPC_SYSSTATUS 0x0014
28#define DISPC_IRQSTATUS 0x0018
29#define DISPC_IRQENABLE 0x001C
30#define DISPC_CONTROL 0x0040
31#define DISPC_CONFIG 0x0044
32#define DISPC_CAPABLE 0x0048
33#define DISPC_LINE_STATUS 0x005C
34#define DISPC_LINE_NUMBER 0x0060
35#define DISPC_GLOBAL_ALPHA 0x0074
36#define DISPC_CONTROL2 0x0238
37#define DISPC_CONFIG2 0x0620
38#define DISPC_DIVISOR 0x0804
39#define DISPC_GLOBAL_BUFFER 0x0800
40#define DISPC_CONTROL3 0x0848
41#define DISPC_CONFIG3 0x084C
42#define DISPC_MSTANDBY_CTRL 0x0858
43#define DISPC_GLOBAL_MFLAG_ATTRIBUTE 0x085C
44
45#define DISPC_GAMMA_TABLE0 0x0630
46#define DISPC_GAMMA_TABLE1 0x0634
47#define DISPC_GAMMA_TABLE2 0x0638
48#define DISPC_GAMMA_TABLE3 0x0850
49
50/* DISPC overlay registers */
51#define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
52 DISPC_BA0_OFFSET(n))
53#define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
54 DISPC_BA1_OFFSET(n))
55#define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
56 DISPC_BA0_UV_OFFSET(n))
57#define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
58 DISPC_BA1_UV_OFFSET(n))
59#define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
60 DISPC_POS_OFFSET(n))
61#define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
62 DISPC_SIZE_OFFSET(n))
63#define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
64 DISPC_ATTR_OFFSET(n))
65#define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
66 DISPC_ATTR2_OFFSET(n))
67#define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
68 DISPC_FIFO_THRESH_OFFSET(n))
69#define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
70 DISPC_FIFO_SIZE_STATUS_OFFSET(n))
71#define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
72 DISPC_ROW_INC_OFFSET(n))
73#define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
74 DISPC_PIX_INC_OFFSET(n))
75#define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
76 DISPC_WINDOW_SKIP_OFFSET(n))
77#define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
78 DISPC_TABLE_BA_OFFSET(n))
79#define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
80 DISPC_FIR_OFFSET(n))
81#define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
82 DISPC_FIR2_OFFSET(n))
83#define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
84 DISPC_PIC_SIZE_OFFSET(n))
85#define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
86 DISPC_ACCU0_OFFSET(n))
87#define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
88 DISPC_ACCU1_OFFSET(n))
89#define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
90 DISPC_ACCU2_0_OFFSET(n))
91#define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
92 DISPC_ACCU2_1_OFFSET(n))
93#define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
94 DISPC_FIR_COEF_H_OFFSET(n, i))
95#define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
96 DISPC_FIR_COEF_HV_OFFSET(n, i))
97#define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
98 DISPC_FIR_COEF_H2_OFFSET(n, i))
99#define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
100 DISPC_FIR_COEF_HV2_OFFSET(n, i))
101#define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
102 DISPC_CONV_COEF_OFFSET(n, i))
103#define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
104 DISPC_FIR_COEF_V_OFFSET(n, i))
105#define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
106 DISPC_FIR_COEF_V2_OFFSET(n, i))
107#define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
108 DISPC_PRELOAD_OFFSET(n))
109#define DISPC_OVL_MFLAG_THRESHOLD(n) DISPC_MFLAG_THRESHOLD_OFFSET(n)
110
111/* DISPC up/downsampling FIR filter coefficient structure */
112struct dispc_coef {
113 s8 hc4_vc22;
114 s8 hc3_vc2;
115 u8 hc2_vc1;
116 s8 hc1_vc0;
117 s8 hc0_vc00;
118};
119
120const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
121
122/* DISPC manager/channel specific registers */
123static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
124{
125 switch (channel) {
126 case OMAP_DSS_CHANNEL_LCD:
127 return 0x004C;
128 case OMAP_DSS_CHANNEL_DIGIT:
129 return 0x0050;
130 case OMAP_DSS_CHANNEL_LCD2:
131 return 0x03AC;
132 case OMAP_DSS_CHANNEL_LCD3:
133 return 0x0814;
134 default:
135 BUG();
136 return 0;
137 }
138}
139
140static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
141{
142 switch (channel) {
143 case OMAP_DSS_CHANNEL_LCD:
144 return 0x0054;
145 case OMAP_DSS_CHANNEL_DIGIT:
146 return 0x0058;
147 case OMAP_DSS_CHANNEL_LCD2:
148 return 0x03B0;
149 case OMAP_DSS_CHANNEL_LCD3:
150 return 0x0818;
151 default:
152 BUG();
153 return 0;
154 }
155}
156
157static inline u16 DISPC_TIMING_H(enum omap_channel channel)
158{
159 switch (channel) {
160 case OMAP_DSS_CHANNEL_LCD:
161 return 0x0064;
162 case OMAP_DSS_CHANNEL_DIGIT:
163 BUG();
164 return 0;
165 case OMAP_DSS_CHANNEL_LCD2:
166 return 0x0400;
167 case OMAP_DSS_CHANNEL_LCD3:
168 return 0x0840;
169 default:
170 BUG();
171 return 0;
172 }
173}
174
175static inline u16 DISPC_TIMING_V(enum omap_channel channel)
176{
177 switch (channel) {
178 case OMAP_DSS_CHANNEL_LCD:
179 return 0x0068;
180 case OMAP_DSS_CHANNEL_DIGIT:
181 BUG();
182 return 0;
183 case OMAP_DSS_CHANNEL_LCD2:
184 return 0x0404;
185 case OMAP_DSS_CHANNEL_LCD3:
186 return 0x0844;
187 default:
188 BUG();
189 return 0;
190 }
191}
192
193static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
194{
195 switch (channel) {
196 case OMAP_DSS_CHANNEL_LCD:
197 return 0x006C;
198 case OMAP_DSS_CHANNEL_DIGIT:
199 BUG();
200 return 0;
201 case OMAP_DSS_CHANNEL_LCD2:
202 return 0x0408;
203 case OMAP_DSS_CHANNEL_LCD3:
204 return 0x083C;
205 default:
206 BUG();
207 return 0;
208 }
209}
210
211static inline u16 DISPC_DIVISORo(enum omap_channel channel)
212{
213 switch (channel) {
214 case OMAP_DSS_CHANNEL_LCD:
215 return 0x0070;
216 case OMAP_DSS_CHANNEL_DIGIT:
217 BUG();
218 return 0;
219 case OMAP_DSS_CHANNEL_LCD2:
220 return 0x040C;
221 case OMAP_DSS_CHANNEL_LCD3:
222 return 0x0838;
223 default:
224 BUG();
225 return 0;
226 }
227}
228
229/* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
230static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
231{
232 switch (channel) {
233 case OMAP_DSS_CHANNEL_LCD:
234 return 0x007C;
235 case OMAP_DSS_CHANNEL_DIGIT:
236 return 0x0078;
237 case OMAP_DSS_CHANNEL_LCD2:
238 return 0x03CC;
239 case OMAP_DSS_CHANNEL_LCD3:
240 return 0x0834;
241 default:
242 BUG();
243 return 0;
244 }
245}
246
247static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
248{
249 switch (channel) {
250 case OMAP_DSS_CHANNEL_LCD:
251 return 0x01D4;
252 case OMAP_DSS_CHANNEL_DIGIT:
253 BUG();
254 return 0;
255 case OMAP_DSS_CHANNEL_LCD2:
256 return 0x03C0;
257 case OMAP_DSS_CHANNEL_LCD3:
258 return 0x0828;
259 default:
260 BUG();
261 return 0;
262 }
263}
264
265static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
266{
267 switch (channel) {
268 case OMAP_DSS_CHANNEL_LCD:
269 return 0x01D8;
270 case OMAP_DSS_CHANNEL_DIGIT:
271 BUG();
272 return 0;
273 case OMAP_DSS_CHANNEL_LCD2:
274 return 0x03C4;
275 case OMAP_DSS_CHANNEL_LCD3:
276 return 0x082C;
277 default:
278 BUG();
279 return 0;
280 }
281}
282
283static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
284{
285 switch (channel) {
286 case OMAP_DSS_CHANNEL_LCD:
287 return 0x01DC;
288 case OMAP_DSS_CHANNEL_DIGIT:
289 BUG();
290 return 0;
291 case OMAP_DSS_CHANNEL_LCD2:
292 return 0x03C8;
293 case OMAP_DSS_CHANNEL_LCD3:
294 return 0x0830;
295 default:
296 BUG();
297 return 0;
298 }
299}
300
301static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
302{
303 switch (channel) {
304 case OMAP_DSS_CHANNEL_LCD:
305 return 0x0220;
306 case OMAP_DSS_CHANNEL_DIGIT:
307 BUG();
308 return 0;
309 case OMAP_DSS_CHANNEL_LCD2:
310 return 0x03BC;
311 case OMAP_DSS_CHANNEL_LCD3:
312 return 0x0824;
313 default:
314 BUG();
315 return 0;
316 }
317}
318
319static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
320{
321 switch (channel) {
322 case OMAP_DSS_CHANNEL_LCD:
323 return 0x0224;
324 case OMAP_DSS_CHANNEL_DIGIT:
325 BUG();
326 return 0;
327 case OMAP_DSS_CHANNEL_LCD2:
328 return 0x03B8;
329 case OMAP_DSS_CHANNEL_LCD3:
330 return 0x0820;
331 default:
332 BUG();
333 return 0;
334 }
335}
336
337static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
338{
339 switch (channel) {
340 case OMAP_DSS_CHANNEL_LCD:
341 return 0x0228;
342 case OMAP_DSS_CHANNEL_DIGIT:
343 BUG();
344 return 0;
345 case OMAP_DSS_CHANNEL_LCD2:
346 return 0x03B4;
347 case OMAP_DSS_CHANNEL_LCD3:
348 return 0x081C;
349 default:
350 BUG();
351 return 0;
352 }
353}
354
355/* DISPC overlay register base addresses */
356static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
357{
358 switch (plane) {
359 case OMAP_DSS_GFX:
360 return 0x0080;
361 case OMAP_DSS_VIDEO1:
362 return 0x00BC;
363 case OMAP_DSS_VIDEO2:
364 return 0x014C;
365 case OMAP_DSS_VIDEO3:
366 return 0x0300;
367 case OMAP_DSS_WB:
368 return 0x0500;
369 default:
370 BUG();
371 return 0;
372 }
373}
374
375/* DISPC overlay register offsets */
376static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
377{
378 switch (plane) {
379 case OMAP_DSS_GFX:
380 case OMAP_DSS_VIDEO1:
381 case OMAP_DSS_VIDEO2:
382 return 0x0000;
383 case OMAP_DSS_VIDEO3:
384 case OMAP_DSS_WB:
385 return 0x0008;
386 default:
387 BUG();
388 return 0;
389 }
390}
391
392static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
393{
394 switch (plane) {
395 case OMAP_DSS_GFX:
396 case OMAP_DSS_VIDEO1:
397 case OMAP_DSS_VIDEO2:
398 return 0x0004;
399 case OMAP_DSS_VIDEO3:
400 case OMAP_DSS_WB:
401 return 0x000C;
402 default:
403 BUG();
404 return 0;
405 }
406}
407
408static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
409{
410 switch (plane) {
411 case OMAP_DSS_GFX:
412 BUG();
413 return 0;
414 case OMAP_DSS_VIDEO1:
415 return 0x0544;
416 case OMAP_DSS_VIDEO2:
417 return 0x04BC;
418 case OMAP_DSS_VIDEO3:
419 return 0x0310;
420 case OMAP_DSS_WB:
421 return 0x0118;
422 default:
423 BUG();
424 return 0;
425 }
426}
427
428static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
429{
430 switch (plane) {
431 case OMAP_DSS_GFX:
432 BUG();
433 return 0;
434 case OMAP_DSS_VIDEO1:
435 return 0x0548;
436 case OMAP_DSS_VIDEO2:
437 return 0x04C0;
438 case OMAP_DSS_VIDEO3:
439 return 0x0314;
440 case OMAP_DSS_WB:
441 return 0x011C;
442 default:
443 BUG();
444 return 0;
445 }
446}
447
448static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
449{
450 switch (plane) {
451 case OMAP_DSS_GFX:
452 case OMAP_DSS_VIDEO1:
453 case OMAP_DSS_VIDEO2:
454 return 0x0008;
455 case OMAP_DSS_VIDEO3:
456 return 0x009C;
457 default:
458 BUG();
459 return 0;
460 }
461}
462
463static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
464{
465 switch (plane) {
466 case OMAP_DSS_GFX:
467 case OMAP_DSS_VIDEO1:
468 case OMAP_DSS_VIDEO2:
469 return 0x000C;
470 case OMAP_DSS_VIDEO3:
471 case OMAP_DSS_WB:
472 return 0x00A8;
473 default:
474 BUG();
475 return 0;
476 }
477}
478
479static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
480{
481 switch (plane) {
482 case OMAP_DSS_GFX:
483 return 0x0020;
484 case OMAP_DSS_VIDEO1:
485 case OMAP_DSS_VIDEO2:
486 return 0x0010;
487 case OMAP_DSS_VIDEO3:
488 case OMAP_DSS_WB:
489 return 0x0070;
490 default:
491 BUG();
492 return 0;
493 }
494}
495
496static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
497{
498 switch (plane) {
499 case OMAP_DSS_GFX:
500 BUG();
501 return 0;
502 case OMAP_DSS_VIDEO1:
503 return 0x0568;
504 case OMAP_DSS_VIDEO2:
505 return 0x04DC;
506 case OMAP_DSS_VIDEO3:
507 return 0x032C;
508 case OMAP_DSS_WB:
509 return 0x0310;
510 default:
511 BUG();
512 return 0;
513 }
514}
515
516static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
517{
518 switch (plane) {
519 case OMAP_DSS_GFX:
520 return 0x0024;
521 case OMAP_DSS_VIDEO1:
522 case OMAP_DSS_VIDEO2:
523 return 0x0014;
524 case OMAP_DSS_VIDEO3:
525 case OMAP_DSS_WB:
526 return 0x008C;
527 default:
528 BUG();
529 return 0;
530 }
531}
532
533static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
534{
535 switch (plane) {
536 case OMAP_DSS_GFX:
537 return 0x0028;
538 case OMAP_DSS_VIDEO1:
539 case OMAP_DSS_VIDEO2:
540 return 0x0018;
541 case OMAP_DSS_VIDEO3:
542 case OMAP_DSS_WB:
543 return 0x0088;
544 default:
545 BUG();
546 return 0;
547 }
548}
549
550static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
551{
552 switch (plane) {
553 case OMAP_DSS_GFX:
554 return 0x002C;
555 case OMAP_DSS_VIDEO1:
556 case OMAP_DSS_VIDEO2:
557 return 0x001C;
558 case OMAP_DSS_VIDEO3:
559 case OMAP_DSS_WB:
560 return 0x00A4;
561 default:
562 BUG();
563 return 0;
564 }
565}
566
567static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
568{
569 switch (plane) {
570 case OMAP_DSS_GFX:
571 return 0x0030;
572 case OMAP_DSS_VIDEO1:
573 case OMAP_DSS_VIDEO2:
574 return 0x0020;
575 case OMAP_DSS_VIDEO3:
576 case OMAP_DSS_WB:
577 return 0x0098;
578 default:
579 BUG();
580 return 0;
581 }
582}
583
584static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
585{
586 switch (plane) {
587 case OMAP_DSS_GFX:
588 return 0x0034;
589 case OMAP_DSS_VIDEO1:
590 case OMAP_DSS_VIDEO2:
591 case OMAP_DSS_VIDEO3:
592 BUG();
593 return 0;
594 default:
595 BUG();
596 return 0;
597 }
598}
599
600static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
601{
602 switch (plane) {
603 case OMAP_DSS_GFX:
604 return 0x0038;
605 case OMAP_DSS_VIDEO1:
606 case OMAP_DSS_VIDEO2:
607 case OMAP_DSS_VIDEO3:
608 BUG();
609 return 0;
610 default:
611 BUG();
612 return 0;
613 }
614}
615
616static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
617{
618 switch (plane) {
619 case OMAP_DSS_GFX:
620 BUG();
621 return 0;
622 case OMAP_DSS_VIDEO1:
623 case OMAP_DSS_VIDEO2:
624 return 0x0024;
625 case OMAP_DSS_VIDEO3:
626 case OMAP_DSS_WB:
627 return 0x0090;
628 default:
629 BUG();
630 return 0;
631 }
632}
633
634static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
635{
636 switch (plane) {
637 case OMAP_DSS_GFX:
638 BUG();
639 return 0;
640 case OMAP_DSS_VIDEO1:
641 return 0x0580;
642 case OMAP_DSS_VIDEO2:
643 return 0x055C;
644 case OMAP_DSS_VIDEO3:
645 return 0x0424;
646 case OMAP_DSS_WB:
647 return 0x290;
648 default:
649 BUG();
650 return 0;
651 }
652}
653
654static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
655{
656 switch (plane) {
657 case OMAP_DSS_GFX:
658 BUG();
659 return 0;
660 case OMAP_DSS_VIDEO1:
661 case OMAP_DSS_VIDEO2:
662 return 0x0028;
663 case OMAP_DSS_VIDEO3:
664 case OMAP_DSS_WB:
665 return 0x0094;
666 default:
667 BUG();
668 return 0;
669 }
670}
671
672
673static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
674{
675 switch (plane) {
676 case OMAP_DSS_GFX:
677 BUG();
678 return 0;
679 case OMAP_DSS_VIDEO1:
680 case OMAP_DSS_VIDEO2:
681 return 0x002C;
682 case OMAP_DSS_VIDEO3:
683 case OMAP_DSS_WB:
684 return 0x0000;
685 default:
686 BUG();
687 return 0;
688 }
689}
690
691static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
692{
693 switch (plane) {
694 case OMAP_DSS_GFX:
695 BUG();
696 return 0;
697 case OMAP_DSS_VIDEO1:
698 return 0x0584;
699 case OMAP_DSS_VIDEO2:
700 return 0x0560;
701 case OMAP_DSS_VIDEO3:
702 return 0x0428;
703 case OMAP_DSS_WB:
704 return 0x0294;
705 default:
706 BUG();
707 return 0;
708 }
709}
710
711static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
712{
713 switch (plane) {
714 case OMAP_DSS_GFX:
715 BUG();
716 return 0;
717 case OMAP_DSS_VIDEO1:
718 case OMAP_DSS_VIDEO2:
719 return 0x0030;
720 case OMAP_DSS_VIDEO3:
721 case OMAP_DSS_WB:
722 return 0x0004;
723 default:
724 BUG();
725 return 0;
726 }
727}
728
729static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
730{
731 switch (plane) {
732 case OMAP_DSS_GFX:
733 BUG();
734 return 0;
735 case OMAP_DSS_VIDEO1:
736 return 0x0588;
737 case OMAP_DSS_VIDEO2:
738 return 0x0564;
739 case OMAP_DSS_VIDEO3:
740 return 0x042C;
741 case OMAP_DSS_WB:
742 return 0x0298;
743 default:
744 BUG();
745 return 0;
746 }
747}
748
749/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
750static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
751{
752 switch (plane) {
753 case OMAP_DSS_GFX:
754 BUG();
755 return 0;
756 case OMAP_DSS_VIDEO1:
757 case OMAP_DSS_VIDEO2:
758 return 0x0034 + i * 0x8;
759 case OMAP_DSS_VIDEO3:
760 case OMAP_DSS_WB:
761 return 0x0010 + i * 0x8;
762 default:
763 BUG();
764 return 0;
765 }
766}
767
768/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
769static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
770{
771 switch (plane) {
772 case OMAP_DSS_GFX:
773 BUG();
774 return 0;
775 case OMAP_DSS_VIDEO1:
776 return 0x058C + i * 0x8;
777 case OMAP_DSS_VIDEO2:
778 return 0x0568 + i * 0x8;
779 case OMAP_DSS_VIDEO3:
780 return 0x0430 + i * 0x8;
781 case OMAP_DSS_WB:
782 return 0x02A0 + i * 0x8;
783 default:
784 BUG();
785 return 0;
786 }
787}
788
789/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
790static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
791{
792 switch (plane) {
793 case OMAP_DSS_GFX:
794 BUG();
795 return 0;
796 case OMAP_DSS_VIDEO1:
797 case OMAP_DSS_VIDEO2:
798 return 0x0038 + i * 0x8;
799 case OMAP_DSS_VIDEO3:
800 case OMAP_DSS_WB:
801 return 0x0014 + i * 0x8;
802 default:
803 BUG();
804 return 0;
805 }
806}
807
808/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
809static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
810{
811 switch (plane) {
812 case OMAP_DSS_GFX:
813 BUG();
814 return 0;
815 case OMAP_DSS_VIDEO1:
816 return 0x0590 + i * 8;
817 case OMAP_DSS_VIDEO2:
818 return 0x056C + i * 0x8;
819 case OMAP_DSS_VIDEO3:
820 return 0x0434 + i * 0x8;
821 case OMAP_DSS_WB:
822 return 0x02A4 + i * 0x8;
823 default:
824 BUG();
825 return 0;
826 }
827}
828
829/* coef index i = {0, 1, 2, 3, 4,} */
830static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
831{
832 switch (plane) {
833 case OMAP_DSS_GFX:
834 BUG();
835 return 0;
836 case OMAP_DSS_VIDEO1:
837 case OMAP_DSS_VIDEO2:
838 case OMAP_DSS_VIDEO3:
839 case OMAP_DSS_WB:
840 return 0x0074 + i * 0x4;
841 default:
842 BUG();
843 return 0;
844 }
845}
846
847/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
848static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
849{
850 switch (plane) {
851 case OMAP_DSS_GFX:
852 BUG();
853 return 0;
854 case OMAP_DSS_VIDEO1:
855 return 0x0124 + i * 0x4;
856 case OMAP_DSS_VIDEO2:
857 return 0x00B4 + i * 0x4;
858 case OMAP_DSS_VIDEO3:
859 case OMAP_DSS_WB:
860 return 0x0050 + i * 0x4;
861 default:
862 BUG();
863 return 0;
864 }
865}
866
867/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
868static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
869{
870 switch (plane) {
871 case OMAP_DSS_GFX:
872 BUG();
873 return 0;
874 case OMAP_DSS_VIDEO1:
875 return 0x05CC + i * 0x4;
876 case OMAP_DSS_VIDEO2:
877 return 0x05A8 + i * 0x4;
878 case OMAP_DSS_VIDEO3:
879 return 0x0470 + i * 0x4;
880 case OMAP_DSS_WB:
881 return 0x02E0 + i * 0x4;
882 default:
883 BUG();
884 return 0;
885 }
886}
887
888static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
889{
890 switch (plane) {
891 case OMAP_DSS_GFX:
892 return 0x01AC;
893 case OMAP_DSS_VIDEO1:
894 return 0x0174;
895 case OMAP_DSS_VIDEO2:
896 return 0x00E8;
897 case OMAP_DSS_VIDEO3:
898 return 0x00A0;
899 default:
900 BUG();
901 return 0;
902 }
903}
904
905static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane plane)
906{
907 switch (plane) {
908 case OMAP_DSS_GFX:
909 return 0x0860;
910 case OMAP_DSS_VIDEO1:
911 return 0x0864;
912 case OMAP_DSS_VIDEO2:
913 return 0x0868;
914 case OMAP_DSS_VIDEO3:
915 return 0x086c;
916 case OMAP_DSS_WB:
917 return 0x0870;
918 default:
919 BUG();
920 return 0;
921 }
922}
923#endif