1/* SPDX-License-Identifier: MIT */
 2#ifndef __NVBIOS_M0203_H__
 3#define __NVBIOS_M0203_H__
 4struct nvbios_M0203T {
 5#define M0203T_TYPE_RAMCFG 0x00
 6	u8  type;
 7	u16 pointer;
 8};
 9
10u32 nvbios_M0203Te(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
11u32 nvbios_M0203Tp(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
12		   struct nvbios_M0203T *);
13
14struct nvbios_M0203E {
15#define M0203E_TYPE_DDR2   0x0
16#define M0203E_TYPE_DDR3   0x1
17#define M0203E_TYPE_GDDR3  0x2
18#define M0203E_TYPE_GDDR5  0x3
19#define M0203E_TYPE_HBM2   0x6
20#define M0203E_TYPE_GDDR5X 0x8
21#define M0203E_TYPE_GDDR6  0x9
22#define M0203E_TYPE_SKIP   0xf
23	u8 type;
24	u8 strap;
25	u8 group;
26};
27
28u32 nvbios_M0203Ee(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
29u32 nvbios_M0203Ep(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
30		   struct nvbios_M0203E *);
31u32 nvbios_M0203Em(struct nvkm_bios *, u8 ramcfg, u8 *ver, u8 *hdr,
32		   struct nvbios_M0203E *);
33#endif

 
 1#ifndef __NVBIOS_M0203_H__
 2#define __NVBIOS_M0203_H__
 3struct nvbios_M0203T {
 4#define M0203T_TYPE_RAMCFG 0x00
 5	u8  type;
 6	u16 pointer;
 7};
 8
 9u32 nvbios_M0203Te(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
10u32 nvbios_M0203Tp(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
11		   struct nvbios_M0203T *);
12
13struct nvbios_M0203E {
14#define M0203E_TYPE_DDR2  0x0
15#define M0203E_TYPE_DDR3  0x1
16#define M0203E_TYPE_GDDR3 0x2
17#define M0203E_TYPE_GDDR5 0x3
18#define M0203E_TYPE_SKIP  0xf
 
 
 
19	u8 type;
20	u8 strap;
21	u8 group;
22};
23
24u32 nvbios_M0203Ee(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
25u32 nvbios_M0203Ep(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
26		   struct nvbios_M0203E *);
27u32 nvbios_M0203Em(struct nvkm_bios *, u8 ramcfg, u8 *ver, u8 *hdr,
28		   struct nvbios_M0203E *);
29#endif