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1/*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27
28#include <linux/file.h>
29#include <linux/pagemap.h>
30#include <linux/sync_file.h>
31#include <linux/dma-buf.h>
32
33#include <drm/amdgpu_drm.h>
34#include <drm/drm_syncobj.h>
35#include "amdgpu_cs.h"
36#include "amdgpu.h"
37#include "amdgpu_trace.h"
38#include "amdgpu_gmc.h"
39#include "amdgpu_gem.h"
40#include "amdgpu_ras.h"
41
42static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p,
43 struct amdgpu_device *adev,
44 struct drm_file *filp,
45 union drm_amdgpu_cs *cs)
46{
47 struct amdgpu_fpriv *fpriv = filp->driver_priv;
48
49 if (cs->in.num_chunks == 0)
50 return -EINVAL;
51
52 memset(p, 0, sizeof(*p));
53 p->adev = adev;
54 p->filp = filp;
55
56 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
57 if (!p->ctx)
58 return -EINVAL;
59
60 if (atomic_read(&p->ctx->guilty)) {
61 amdgpu_ctx_put(p->ctx);
62 return -ECANCELED;
63 }
64
65 amdgpu_sync_create(&p->sync);
66 return 0;
67}
68
69static int amdgpu_cs_job_idx(struct amdgpu_cs_parser *p,
70 struct drm_amdgpu_cs_chunk_ib *chunk_ib)
71{
72 struct drm_sched_entity *entity;
73 unsigned int i;
74 int r;
75
76 r = amdgpu_ctx_get_entity(p->ctx, chunk_ib->ip_type,
77 chunk_ib->ip_instance,
78 chunk_ib->ring, &entity);
79 if (r)
80 return r;
81
82 /*
83 * Abort if there is no run queue associated with this entity.
84 * Possibly because of disabled HW IP.
85 */
86 if (entity->rq == NULL)
87 return -EINVAL;
88
89 /* Check if we can add this IB to some existing job */
90 for (i = 0; i < p->gang_size; ++i)
91 if (p->entities[i] == entity)
92 return i;
93
94 /* If not increase the gang size if possible */
95 if (i == AMDGPU_CS_GANG_SIZE)
96 return -EINVAL;
97
98 p->entities[i] = entity;
99 p->gang_size = i + 1;
100 return i;
101}
102
103static int amdgpu_cs_p1_ib(struct amdgpu_cs_parser *p,
104 struct drm_amdgpu_cs_chunk_ib *chunk_ib,
105 unsigned int *num_ibs)
106{
107 int r;
108
109 r = amdgpu_cs_job_idx(p, chunk_ib);
110 if (r < 0)
111 return r;
112
113 ++(num_ibs[r]);
114 p->gang_leader_idx = r;
115 return 0;
116}
117
118static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p,
119 struct drm_amdgpu_cs_chunk_fence *data,
120 uint32_t *offset)
121{
122 struct drm_gem_object *gobj;
123 struct amdgpu_bo *bo;
124 unsigned long size;
125 int r;
126
127 gobj = drm_gem_object_lookup(p->filp, data->handle);
128 if (gobj == NULL)
129 return -EINVAL;
130
131 bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
132 p->uf_entry.priority = 0;
133 p->uf_entry.tv.bo = &bo->tbo;
134 /* One for TTM and two for the CS job */
135 p->uf_entry.tv.num_shared = 3;
136
137 drm_gem_object_put(gobj);
138
139 size = amdgpu_bo_size(bo);
140 if (size != PAGE_SIZE || (data->offset + 8) > size) {
141 r = -EINVAL;
142 goto error_unref;
143 }
144
145 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
146 r = -EINVAL;
147 goto error_unref;
148 }
149
150 *offset = data->offset;
151
152 return 0;
153
154error_unref:
155 amdgpu_bo_unref(&bo);
156 return r;
157}
158
159static int amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser *p,
160 struct drm_amdgpu_bo_list_in *data)
161{
162 struct drm_amdgpu_bo_list_entry *info;
163 int r;
164
165 r = amdgpu_bo_create_list_entry_array(data, &info);
166 if (r)
167 return r;
168
169 r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
170 &p->bo_list);
171 if (r)
172 goto error_free;
173
174 kvfree(info);
175 return 0;
176
177error_free:
178 kvfree(info);
179
180 return r;
181}
182
183/* Copy the data from userspace and go over it the first time */
184static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,
185 union drm_amdgpu_cs *cs)
186{
187 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
188 unsigned int num_ibs[AMDGPU_CS_GANG_SIZE] = { };
189 struct amdgpu_vm *vm = &fpriv->vm;
190 uint64_t *chunk_array_user;
191 uint64_t *chunk_array;
192 uint32_t uf_offset = 0;
193 unsigned int size;
194 int ret;
195 int i;
196
197 chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t),
198 GFP_KERNEL);
199 if (!chunk_array)
200 return -ENOMEM;
201
202 /* get chunks */
203 chunk_array_user = u64_to_user_ptr(cs->in.chunks);
204 if (copy_from_user(chunk_array, chunk_array_user,
205 sizeof(uint64_t)*cs->in.num_chunks)) {
206 ret = -EFAULT;
207 goto free_chunk;
208 }
209
210 p->nchunks = cs->in.num_chunks;
211 p->chunks = kvmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
212 GFP_KERNEL);
213 if (!p->chunks) {
214 ret = -ENOMEM;
215 goto free_chunk;
216 }
217
218 for (i = 0; i < p->nchunks; i++) {
219 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
220 struct drm_amdgpu_cs_chunk user_chunk;
221 uint32_t __user *cdata;
222
223 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
224 if (copy_from_user(&user_chunk, chunk_ptr,
225 sizeof(struct drm_amdgpu_cs_chunk))) {
226 ret = -EFAULT;
227 i--;
228 goto free_partial_kdata;
229 }
230 p->chunks[i].chunk_id = user_chunk.chunk_id;
231 p->chunks[i].length_dw = user_chunk.length_dw;
232
233 size = p->chunks[i].length_dw;
234 cdata = u64_to_user_ptr(user_chunk.chunk_data);
235
236 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t),
237 GFP_KERNEL);
238 if (p->chunks[i].kdata == NULL) {
239 ret = -ENOMEM;
240 i--;
241 goto free_partial_kdata;
242 }
243 size *= sizeof(uint32_t);
244 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
245 ret = -EFAULT;
246 goto free_partial_kdata;
247 }
248
249 /* Assume the worst on the following checks */
250 ret = -EINVAL;
251 switch (p->chunks[i].chunk_id) {
252 case AMDGPU_CHUNK_ID_IB:
253 if (size < sizeof(struct drm_amdgpu_cs_chunk_ib))
254 goto free_partial_kdata;
255
256 ret = amdgpu_cs_p1_ib(p, p->chunks[i].kdata, num_ibs);
257 if (ret)
258 goto free_partial_kdata;
259 break;
260
261 case AMDGPU_CHUNK_ID_FENCE:
262 if (size < sizeof(struct drm_amdgpu_cs_chunk_fence))
263 goto free_partial_kdata;
264
265 ret = amdgpu_cs_p1_user_fence(p, p->chunks[i].kdata,
266 &uf_offset);
267 if (ret)
268 goto free_partial_kdata;
269 break;
270
271 case AMDGPU_CHUNK_ID_BO_HANDLES:
272 if (size < sizeof(struct drm_amdgpu_bo_list_in))
273 goto free_partial_kdata;
274
275 ret = amdgpu_cs_p1_bo_handles(p, p->chunks[i].kdata);
276 if (ret)
277 goto free_partial_kdata;
278 break;
279
280 case AMDGPU_CHUNK_ID_DEPENDENCIES:
281 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
282 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
283 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
284 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
285 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
286 break;
287
288 default:
289 goto free_partial_kdata;
290 }
291 }
292
293 if (!p->gang_size) {
294 ret = -EINVAL;
295 goto free_partial_kdata;
296 }
297
298 for (i = 0; i < p->gang_size; ++i) {
299 ret = amdgpu_job_alloc(p->adev, vm, p->entities[i], vm,
300 num_ibs[i], &p->jobs[i]);
301 if (ret)
302 goto free_all_kdata;
303 }
304 p->gang_leader = p->jobs[p->gang_leader_idx];
305
306 if (p->ctx->vram_lost_counter != p->gang_leader->vram_lost_counter) {
307 ret = -ECANCELED;
308 goto free_all_kdata;
309 }
310
311 if (p->uf_entry.tv.bo)
312 p->gang_leader->uf_addr = uf_offset;
313 kvfree(chunk_array);
314
315 /* Use this opportunity to fill in task info for the vm */
316 amdgpu_vm_set_task_info(vm);
317
318 return 0;
319
320free_all_kdata:
321 i = p->nchunks - 1;
322free_partial_kdata:
323 for (; i >= 0; i--)
324 kvfree(p->chunks[i].kdata);
325 kvfree(p->chunks);
326 p->chunks = NULL;
327 p->nchunks = 0;
328free_chunk:
329 kvfree(chunk_array);
330
331 return ret;
332}
333
334static int amdgpu_cs_p2_ib(struct amdgpu_cs_parser *p,
335 struct amdgpu_cs_chunk *chunk,
336 unsigned int *ce_preempt,
337 unsigned int *de_preempt)
338{
339 struct drm_amdgpu_cs_chunk_ib *chunk_ib = chunk->kdata;
340 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
341 struct amdgpu_vm *vm = &fpriv->vm;
342 struct amdgpu_ring *ring;
343 struct amdgpu_job *job;
344 struct amdgpu_ib *ib;
345 int r;
346
347 r = amdgpu_cs_job_idx(p, chunk_ib);
348 if (r < 0)
349 return r;
350
351 job = p->jobs[r];
352 ring = amdgpu_job_ring(job);
353 ib = &job->ibs[job->num_ibs++];
354
355 /* MM engine doesn't support user fences */
356 if (p->uf_entry.tv.bo && ring->funcs->no_user_fence)
357 return -EINVAL;
358
359 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
360 chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
361 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
362 (*ce_preempt)++;
363 else
364 (*de_preempt)++;
365
366 /* Each GFX command submit allows only 1 IB max
367 * preemptible for CE & DE */
368 if (*ce_preempt > 1 || *de_preempt > 1)
369 return -EINVAL;
370 }
371
372 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
373 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
374
375 r = amdgpu_ib_get(p->adev, vm, ring->funcs->parse_cs ?
376 chunk_ib->ib_bytes : 0,
377 AMDGPU_IB_POOL_DELAYED, ib);
378 if (r) {
379 DRM_ERROR("Failed to get ib !\n");
380 return r;
381 }
382
383 ib->gpu_addr = chunk_ib->va_start;
384 ib->length_dw = chunk_ib->ib_bytes / 4;
385 ib->flags = chunk_ib->flags;
386 return 0;
387}
388
389static int amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser *p,
390 struct amdgpu_cs_chunk *chunk)
391{
392 struct drm_amdgpu_cs_chunk_dep *deps = chunk->kdata;
393 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
394 unsigned num_deps;
395 int i, r;
396
397 num_deps = chunk->length_dw * 4 /
398 sizeof(struct drm_amdgpu_cs_chunk_dep);
399
400 for (i = 0; i < num_deps; ++i) {
401 struct amdgpu_ctx *ctx;
402 struct drm_sched_entity *entity;
403 struct dma_fence *fence;
404
405 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
406 if (ctx == NULL)
407 return -EINVAL;
408
409 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
410 deps[i].ip_instance,
411 deps[i].ring, &entity);
412 if (r) {
413 amdgpu_ctx_put(ctx);
414 return r;
415 }
416
417 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
418 amdgpu_ctx_put(ctx);
419
420 if (IS_ERR(fence))
421 return PTR_ERR(fence);
422 else if (!fence)
423 continue;
424
425 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
426 struct drm_sched_fence *s_fence;
427 struct dma_fence *old = fence;
428
429 s_fence = to_drm_sched_fence(fence);
430 fence = dma_fence_get(&s_fence->scheduled);
431 dma_fence_put(old);
432 }
433
434 r = amdgpu_sync_fence(&p->sync, fence);
435 dma_fence_put(fence);
436 if (r)
437 return r;
438 }
439 return 0;
440}
441
442static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p,
443 uint32_t handle, u64 point,
444 u64 flags)
445{
446 struct dma_fence *fence;
447 int r;
448
449 r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
450 if (r) {
451 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
452 handle, point, r);
453 return r;
454 }
455
456 r = amdgpu_sync_fence(&p->sync, fence);
457 dma_fence_put(fence);
458 return r;
459}
460
461static int amdgpu_cs_p2_syncobj_in(struct amdgpu_cs_parser *p,
462 struct amdgpu_cs_chunk *chunk)
463{
464 struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
465 unsigned num_deps;
466 int i, r;
467
468 num_deps = chunk->length_dw * 4 /
469 sizeof(struct drm_amdgpu_cs_chunk_sem);
470 for (i = 0; i < num_deps; ++i) {
471 r = amdgpu_syncobj_lookup_and_add(p, deps[i].handle, 0, 0);
472 if (r)
473 return r;
474 }
475
476 return 0;
477}
478
479static int amdgpu_cs_p2_syncobj_timeline_wait(struct amdgpu_cs_parser *p,
480 struct amdgpu_cs_chunk *chunk)
481{
482 struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
483 unsigned num_deps;
484 int i, r;
485
486 num_deps = chunk->length_dw * 4 /
487 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
488 for (i = 0; i < num_deps; ++i) {
489 r = amdgpu_syncobj_lookup_and_add(p, syncobj_deps[i].handle,
490 syncobj_deps[i].point,
491 syncobj_deps[i].flags);
492 if (r)
493 return r;
494 }
495
496 return 0;
497}
498
499static int amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser *p,
500 struct amdgpu_cs_chunk *chunk)
501{
502 struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
503 unsigned num_deps;
504 int i;
505
506 num_deps = chunk->length_dw * 4 /
507 sizeof(struct drm_amdgpu_cs_chunk_sem);
508
509 if (p->post_deps)
510 return -EINVAL;
511
512 p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
513 GFP_KERNEL);
514 p->num_post_deps = 0;
515
516 if (!p->post_deps)
517 return -ENOMEM;
518
519
520 for (i = 0; i < num_deps; ++i) {
521 p->post_deps[i].syncobj =
522 drm_syncobj_find(p->filp, deps[i].handle);
523 if (!p->post_deps[i].syncobj)
524 return -EINVAL;
525 p->post_deps[i].chain = NULL;
526 p->post_deps[i].point = 0;
527 p->num_post_deps++;
528 }
529
530 return 0;
531}
532
533static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p,
534 struct amdgpu_cs_chunk *chunk)
535{
536 struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
537 unsigned num_deps;
538 int i;
539
540 num_deps = chunk->length_dw * 4 /
541 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
542
543 if (p->post_deps)
544 return -EINVAL;
545
546 p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
547 GFP_KERNEL);
548 p->num_post_deps = 0;
549
550 if (!p->post_deps)
551 return -ENOMEM;
552
553 for (i = 0; i < num_deps; ++i) {
554 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
555
556 dep->chain = NULL;
557 if (syncobj_deps[i].point) {
558 dep->chain = dma_fence_chain_alloc();
559 if (!dep->chain)
560 return -ENOMEM;
561 }
562
563 dep->syncobj = drm_syncobj_find(p->filp,
564 syncobj_deps[i].handle);
565 if (!dep->syncobj) {
566 dma_fence_chain_free(dep->chain);
567 return -EINVAL;
568 }
569 dep->point = syncobj_deps[i].point;
570 p->num_post_deps++;
571 }
572
573 return 0;
574}
575
576static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p)
577{
578 unsigned int ce_preempt = 0, de_preempt = 0;
579 int i, r;
580
581 for (i = 0; i < p->nchunks; ++i) {
582 struct amdgpu_cs_chunk *chunk;
583
584 chunk = &p->chunks[i];
585
586 switch (chunk->chunk_id) {
587 case AMDGPU_CHUNK_ID_IB:
588 r = amdgpu_cs_p2_ib(p, chunk, &ce_preempt, &de_preempt);
589 if (r)
590 return r;
591 break;
592 case AMDGPU_CHUNK_ID_DEPENDENCIES:
593 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
594 r = amdgpu_cs_p2_dependencies(p, chunk);
595 if (r)
596 return r;
597 break;
598 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
599 r = amdgpu_cs_p2_syncobj_in(p, chunk);
600 if (r)
601 return r;
602 break;
603 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
604 r = amdgpu_cs_p2_syncobj_out(p, chunk);
605 if (r)
606 return r;
607 break;
608 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
609 r = amdgpu_cs_p2_syncobj_timeline_wait(p, chunk);
610 if (r)
611 return r;
612 break;
613 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
614 r = amdgpu_cs_p2_syncobj_timeline_signal(p, chunk);
615 if (r)
616 return r;
617 break;
618 }
619 }
620
621 return 0;
622}
623
624/* Convert microseconds to bytes. */
625static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
626{
627 if (us <= 0 || !adev->mm_stats.log2_max_MBps)
628 return 0;
629
630 /* Since accum_us is incremented by a million per second, just
631 * multiply it by the number of MB/s to get the number of bytes.
632 */
633 return us << adev->mm_stats.log2_max_MBps;
634}
635
636static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
637{
638 if (!adev->mm_stats.log2_max_MBps)
639 return 0;
640
641 return bytes >> adev->mm_stats.log2_max_MBps;
642}
643
644/* Returns how many bytes TTM can move right now. If no bytes can be moved,
645 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
646 * which means it can go over the threshold once. If that happens, the driver
647 * will be in debt and no other buffer migrations can be done until that debt
648 * is repaid.
649 *
650 * This approach allows moving a buffer of any size (it's important to allow
651 * that).
652 *
653 * The currency is simply time in microseconds and it increases as the clock
654 * ticks. The accumulated microseconds (us) are converted to bytes and
655 * returned.
656 */
657static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
658 u64 *max_bytes,
659 u64 *max_vis_bytes)
660{
661 s64 time_us, increment_us;
662 u64 free_vram, total_vram, used_vram;
663 /* Allow a maximum of 200 accumulated ms. This is basically per-IB
664 * throttling.
665 *
666 * It means that in order to get full max MBps, at least 5 IBs per
667 * second must be submitted and not more than 200ms apart from each
668 * other.
669 */
670 const s64 us_upper_bound = 200000;
671
672 if (!adev->mm_stats.log2_max_MBps) {
673 *max_bytes = 0;
674 *max_vis_bytes = 0;
675 return;
676 }
677
678 total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
679 used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
680 free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
681
682 spin_lock(&adev->mm_stats.lock);
683
684 /* Increase the amount of accumulated us. */
685 time_us = ktime_to_us(ktime_get());
686 increment_us = time_us - adev->mm_stats.last_update_us;
687 adev->mm_stats.last_update_us = time_us;
688 adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
689 us_upper_bound);
690
691 /* This prevents the short period of low performance when the VRAM
692 * usage is low and the driver is in debt or doesn't have enough
693 * accumulated us to fill VRAM quickly.
694 *
695 * The situation can occur in these cases:
696 * - a lot of VRAM is freed by userspace
697 * - the presence of a big buffer causes a lot of evictions
698 * (solution: split buffers into smaller ones)
699 *
700 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
701 * accum_us to a positive number.
702 */
703 if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
704 s64 min_us;
705
706 /* Be more aggressive on dGPUs. Try to fill a portion of free
707 * VRAM now.
708 */
709 if (!(adev->flags & AMD_IS_APU))
710 min_us = bytes_to_us(adev, free_vram / 4);
711 else
712 min_us = 0; /* Reset accum_us on APUs. */
713
714 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
715 }
716
717 /* This is set to 0 if the driver is in debt to disallow (optional)
718 * buffer moves.
719 */
720 *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
721
722 /* Do the same for visible VRAM if half of it is free */
723 if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
724 u64 total_vis_vram = adev->gmc.visible_vram_size;
725 u64 used_vis_vram =
726 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
727
728 if (used_vis_vram < total_vis_vram) {
729 u64 free_vis_vram = total_vis_vram - used_vis_vram;
730 adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
731 increment_us, us_upper_bound);
732
733 if (free_vis_vram >= total_vis_vram / 2)
734 adev->mm_stats.accum_us_vis =
735 max(bytes_to_us(adev, free_vis_vram / 2),
736 adev->mm_stats.accum_us_vis);
737 }
738
739 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
740 } else {
741 *max_vis_bytes = 0;
742 }
743
744 spin_unlock(&adev->mm_stats.lock);
745}
746
747/* Report how many bytes have really been moved for the last command
748 * submission. This can result in a debt that can stop buffer migrations
749 * temporarily.
750 */
751void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
752 u64 num_vis_bytes)
753{
754 spin_lock(&adev->mm_stats.lock);
755 adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
756 adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
757 spin_unlock(&adev->mm_stats.lock);
758}
759
760static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
761{
762 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
763 struct amdgpu_cs_parser *p = param;
764 struct ttm_operation_ctx ctx = {
765 .interruptible = true,
766 .no_wait_gpu = false,
767 .resv = bo->tbo.base.resv
768 };
769 uint32_t domain;
770 int r;
771
772 if (bo->tbo.pin_count)
773 return 0;
774
775 /* Don't move this buffer if we have depleted our allowance
776 * to move it. Don't move anything if the threshold is zero.
777 */
778 if (p->bytes_moved < p->bytes_moved_threshold &&
779 (!bo->tbo.base.dma_buf ||
780 list_empty(&bo->tbo.base.dma_buf->attachments))) {
781 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
782 (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
783 /* And don't move a CPU_ACCESS_REQUIRED BO to limited
784 * visible VRAM if we've depleted our allowance to do
785 * that.
786 */
787 if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
788 domain = bo->preferred_domains;
789 else
790 domain = bo->allowed_domains;
791 } else {
792 domain = bo->preferred_domains;
793 }
794 } else {
795 domain = bo->allowed_domains;
796 }
797
798retry:
799 amdgpu_bo_placement_from_domain(bo, domain);
800 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
801
802 p->bytes_moved += ctx.bytes_moved;
803 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
804 amdgpu_bo_in_cpu_visible_vram(bo))
805 p->bytes_moved_vis += ctx.bytes_moved;
806
807 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
808 domain = bo->allowed_domains;
809 goto retry;
810 }
811
812 return r;
813}
814
815static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
816 struct list_head *validated)
817{
818 struct ttm_operation_ctx ctx = { true, false };
819 struct amdgpu_bo_list_entry *lobj;
820 int r;
821
822 list_for_each_entry(lobj, validated, tv.head) {
823 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
824 struct mm_struct *usermm;
825
826 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
827 if (usermm && usermm != current->mm)
828 return -EPERM;
829
830 if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
831 lobj->user_invalidated && lobj->user_pages) {
832 amdgpu_bo_placement_from_domain(bo,
833 AMDGPU_GEM_DOMAIN_CPU);
834 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
835 if (r)
836 return r;
837
838 amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
839 lobj->user_pages);
840 }
841
842 r = amdgpu_cs_bo_validate(p, bo);
843 if (r)
844 return r;
845
846 kvfree(lobj->user_pages);
847 lobj->user_pages = NULL;
848 }
849 return 0;
850}
851
852static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
853 union drm_amdgpu_cs *cs)
854{
855 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
856 struct amdgpu_vm *vm = &fpriv->vm;
857 struct amdgpu_bo_list_entry *e;
858 struct list_head duplicates;
859 unsigned int i;
860 int r;
861
862 INIT_LIST_HEAD(&p->validated);
863
864 /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
865 if (cs->in.bo_list_handle) {
866 if (p->bo_list)
867 return -EINVAL;
868
869 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
870 &p->bo_list);
871 if (r)
872 return r;
873 } else if (!p->bo_list) {
874 /* Create a empty bo_list when no handle is provided */
875 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
876 &p->bo_list);
877 if (r)
878 return r;
879 }
880
881 mutex_lock(&p->bo_list->bo_list_mutex);
882
883 /* One for TTM and one for the CS job */
884 amdgpu_bo_list_for_each_entry(e, p->bo_list)
885 e->tv.num_shared = 2;
886
887 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
888
889 INIT_LIST_HEAD(&duplicates);
890 amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
891
892 if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
893 list_add(&p->uf_entry.tv.head, &p->validated);
894
895 /* Get userptr backing pages. If pages are updated after registered
896 * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
897 * amdgpu_ttm_backend_bind() to flush and invalidate new pages
898 */
899 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
900 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
901 bool userpage_invalidated = false;
902 int i;
903
904 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
905 sizeof(struct page *),
906 GFP_KERNEL | __GFP_ZERO);
907 if (!e->user_pages) {
908 DRM_ERROR("kvmalloc_array failure\n");
909 r = -ENOMEM;
910 goto out_free_user_pages;
911 }
912
913 r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages, &e->range);
914 if (r) {
915 kvfree(e->user_pages);
916 e->user_pages = NULL;
917 goto out_free_user_pages;
918 }
919
920 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
921 if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
922 userpage_invalidated = true;
923 break;
924 }
925 }
926 e->user_invalidated = userpage_invalidated;
927 }
928
929 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
930 &duplicates);
931 if (unlikely(r != 0)) {
932 if (r != -ERESTARTSYS)
933 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
934 goto out_free_user_pages;
935 }
936
937 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
938 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
939
940 e->bo_va = amdgpu_vm_bo_find(vm, bo);
941 }
942
943 amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
944 &p->bytes_moved_vis_threshold);
945 p->bytes_moved = 0;
946 p->bytes_moved_vis = 0;
947
948 r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
949 amdgpu_cs_bo_validate, p);
950 if (r) {
951 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
952 goto error_validate;
953 }
954
955 r = amdgpu_cs_list_validate(p, &duplicates);
956 if (r)
957 goto error_validate;
958
959 r = amdgpu_cs_list_validate(p, &p->validated);
960 if (r)
961 goto error_validate;
962
963 if (p->uf_entry.tv.bo) {
964 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
965
966 r = amdgpu_ttm_alloc_gart(&uf->tbo);
967 if (r)
968 goto error_validate;
969
970 p->gang_leader->uf_addr += amdgpu_bo_gpu_offset(uf);
971 }
972
973 amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
974 p->bytes_moved_vis);
975
976 for (i = 0; i < p->gang_size; ++i)
977 amdgpu_job_set_resources(p->jobs[i], p->bo_list->gds_obj,
978 p->bo_list->gws_obj,
979 p->bo_list->oa_obj);
980 return 0;
981
982error_validate:
983 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
984
985out_free_user_pages:
986 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
987 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
988
989 if (!e->user_pages)
990 continue;
991 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, e->range);
992 kvfree(e->user_pages);
993 e->user_pages = NULL;
994 e->range = NULL;
995 }
996 mutex_unlock(&p->bo_list->bo_list_mutex);
997 return r;
998}
999
1000static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *p)
1001{
1002 int i, j;
1003
1004 if (!trace_amdgpu_cs_enabled())
1005 return;
1006
1007 for (i = 0; i < p->gang_size; ++i) {
1008 struct amdgpu_job *job = p->jobs[i];
1009
1010 for (j = 0; j < job->num_ibs; ++j)
1011 trace_amdgpu_cs(p, job, &job->ibs[j]);
1012 }
1013}
1014
1015static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p,
1016 struct amdgpu_job *job)
1017{
1018 struct amdgpu_ring *ring = amdgpu_job_ring(job);
1019 unsigned int i;
1020 int r;
1021
1022 /* Only for UVD/VCE VM emulation */
1023 if (!ring->funcs->parse_cs && !ring->funcs->patch_cs_in_place)
1024 return 0;
1025
1026 for (i = 0; i < job->num_ibs; ++i) {
1027 struct amdgpu_ib *ib = &job->ibs[i];
1028 struct amdgpu_bo_va_mapping *m;
1029 struct amdgpu_bo *aobj;
1030 uint64_t va_start;
1031 uint8_t *kptr;
1032
1033 va_start = ib->gpu_addr & AMDGPU_GMC_HOLE_MASK;
1034 r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
1035 if (r) {
1036 DRM_ERROR("IB va_start is invalid\n");
1037 return r;
1038 }
1039
1040 if ((va_start + ib->length_dw * 4) >
1041 (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
1042 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
1043 return -EINVAL;
1044 }
1045
1046 /* the IB should be reserved at this point */
1047 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
1048 if (r) {
1049 return r;
1050 }
1051
1052 kptr += va_start - (m->start * AMDGPU_GPU_PAGE_SIZE);
1053
1054 if (ring->funcs->parse_cs) {
1055 memcpy(ib->ptr, kptr, ib->length_dw * 4);
1056 amdgpu_bo_kunmap(aobj);
1057
1058 r = amdgpu_ring_parse_cs(ring, p, job, ib);
1059 if (r)
1060 return r;
1061 } else {
1062 ib->ptr = (uint32_t *)kptr;
1063 r = amdgpu_ring_patch_cs_in_place(ring, p, job, ib);
1064 amdgpu_bo_kunmap(aobj);
1065 if (r)
1066 return r;
1067 }
1068 }
1069
1070 return 0;
1071}
1072
1073static int amdgpu_cs_patch_jobs(struct amdgpu_cs_parser *p)
1074{
1075 unsigned int i;
1076 int r;
1077
1078 for (i = 0; i < p->gang_size; ++i) {
1079 r = amdgpu_cs_patch_ibs(p, p->jobs[i]);
1080 if (r)
1081 return r;
1082 }
1083 return 0;
1084}
1085
1086static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
1087{
1088 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1089 struct amdgpu_job *job = p->gang_leader;
1090 struct amdgpu_device *adev = p->adev;
1091 struct amdgpu_vm *vm = &fpriv->vm;
1092 struct amdgpu_bo_list_entry *e;
1093 struct amdgpu_bo_va *bo_va;
1094 struct amdgpu_bo *bo;
1095 unsigned int i;
1096 int r;
1097
1098 r = amdgpu_vm_clear_freed(adev, vm, NULL);
1099 if (r)
1100 return r;
1101
1102 r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
1103 if (r)
1104 return r;
1105
1106 r = amdgpu_sync_fence(&p->sync, fpriv->prt_va->last_pt_update);
1107 if (r)
1108 return r;
1109
1110 if (fpriv->csa_va) {
1111 bo_va = fpriv->csa_va;
1112 BUG_ON(!bo_va);
1113 r = amdgpu_vm_bo_update(adev, bo_va, false);
1114 if (r)
1115 return r;
1116
1117 r = amdgpu_sync_fence(&p->sync, bo_va->last_pt_update);
1118 if (r)
1119 return r;
1120 }
1121
1122 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1123 /* ignore duplicates */
1124 bo = ttm_to_amdgpu_bo(e->tv.bo);
1125 if (!bo)
1126 continue;
1127
1128 bo_va = e->bo_va;
1129 if (bo_va == NULL)
1130 continue;
1131
1132 r = amdgpu_vm_bo_update(adev, bo_va, false);
1133 if (r)
1134 return r;
1135
1136 r = amdgpu_sync_fence(&p->sync, bo_va->last_pt_update);
1137 if (r)
1138 return r;
1139 }
1140
1141 r = amdgpu_vm_handle_moved(adev, vm);
1142 if (r)
1143 return r;
1144
1145 r = amdgpu_vm_update_pdes(adev, vm, false);
1146 if (r)
1147 return r;
1148
1149 r = amdgpu_sync_fence(&p->sync, vm->last_update);
1150 if (r)
1151 return r;
1152
1153 for (i = 0; i < p->gang_size; ++i) {
1154 job = p->jobs[i];
1155
1156 if (!job->vm)
1157 continue;
1158
1159 job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
1160 }
1161
1162 if (amdgpu_vm_debug) {
1163 /* Invalidate all BOs to test for userspace bugs */
1164 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1165 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1166
1167 /* ignore duplicates */
1168 if (!bo)
1169 continue;
1170
1171 amdgpu_vm_bo_invalidate(adev, bo, false);
1172 }
1173 }
1174
1175 return 0;
1176}
1177
1178static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
1179{
1180 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1181 struct drm_gpu_scheduler *sched;
1182 struct amdgpu_bo_list_entry *e;
1183 struct dma_fence *fence;
1184 unsigned int i;
1185 int r;
1186
1187 r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entities[p->gang_leader_idx]);
1188 if (r) {
1189 if (r != -ERESTARTSYS)
1190 DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n");
1191 return r;
1192 }
1193
1194 list_for_each_entry(e, &p->validated, tv.head) {
1195 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1196 struct dma_resv *resv = bo->tbo.base.resv;
1197 enum amdgpu_sync_mode sync_mode;
1198
1199 sync_mode = amdgpu_bo_explicit_sync(bo) ?
1200 AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
1201 r = amdgpu_sync_resv(p->adev, &p->sync, resv, sync_mode,
1202 &fpriv->vm);
1203 if (r)
1204 return r;
1205 }
1206
1207 for (i = 0; i < p->gang_size; ++i) {
1208 r = amdgpu_sync_push_to_job(&p->sync, p->jobs[i]);
1209 if (r)
1210 return r;
1211 }
1212
1213 sched = p->gang_leader->base.entity->rq->sched;
1214 while ((fence = amdgpu_sync_get_fence(&p->sync))) {
1215 struct drm_sched_fence *s_fence = to_drm_sched_fence(fence);
1216
1217 /*
1218 * When we have an dependency it might be necessary to insert a
1219 * pipeline sync to make sure that all caches etc are flushed and the
1220 * next job actually sees the results from the previous one
1221 * before we start executing on the same scheduler ring.
1222 */
1223 if (!s_fence || s_fence->sched != sched) {
1224 dma_fence_put(fence);
1225 continue;
1226 }
1227
1228 r = amdgpu_sync_fence(&p->gang_leader->explicit_sync, fence);
1229 dma_fence_put(fence);
1230 if (r)
1231 return r;
1232 }
1233 return 0;
1234}
1235
1236static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1237{
1238 int i;
1239
1240 for (i = 0; i < p->num_post_deps; ++i) {
1241 if (p->post_deps[i].chain && p->post_deps[i].point) {
1242 drm_syncobj_add_point(p->post_deps[i].syncobj,
1243 p->post_deps[i].chain,
1244 p->fence, p->post_deps[i].point);
1245 p->post_deps[i].chain = NULL;
1246 } else {
1247 drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1248 p->fence);
1249 }
1250 }
1251}
1252
1253static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1254 union drm_amdgpu_cs *cs)
1255{
1256 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1257 struct amdgpu_job *leader = p->gang_leader;
1258 struct amdgpu_bo_list_entry *e;
1259 unsigned int i;
1260 uint64_t seq;
1261 int r;
1262
1263 for (i = 0; i < p->gang_size; ++i)
1264 drm_sched_job_arm(&p->jobs[i]->base);
1265
1266 for (i = 0; i < p->gang_size; ++i) {
1267 struct dma_fence *fence;
1268
1269 if (p->jobs[i] == leader)
1270 continue;
1271
1272 fence = &p->jobs[i]->base.s_fence->scheduled;
1273 dma_fence_get(fence);
1274 r = drm_sched_job_add_dependency(&leader->base, fence);
1275 if (r) {
1276 dma_fence_put(fence);
1277 goto error_cleanup;
1278 }
1279 }
1280
1281 if (p->gang_size > 1) {
1282 for (i = 0; i < p->gang_size; ++i)
1283 amdgpu_job_set_gang_leader(p->jobs[i], leader);
1284 }
1285
1286 /* No memory allocation is allowed while holding the notifier lock.
1287 * The lock is held until amdgpu_cs_submit is finished and fence is
1288 * added to BOs.
1289 */
1290 mutex_lock(&p->adev->notifier_lock);
1291
1292 /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1293 * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1294 */
1295 r = 0;
1296 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1297 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1298
1299 r |= !amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, e->range);
1300 e->range = NULL;
1301 }
1302 if (r) {
1303 r = -EAGAIN;
1304 goto error_unlock;
1305 }
1306
1307 p->fence = dma_fence_get(&leader->base.s_fence->finished);
1308 list_for_each_entry(e, &p->validated, tv.head) {
1309
1310 /* Everybody except for the gang leader uses READ */
1311 for (i = 0; i < p->gang_size; ++i) {
1312 if (p->jobs[i] == leader)
1313 continue;
1314
1315 dma_resv_add_fence(e->tv.bo->base.resv,
1316 &p->jobs[i]->base.s_fence->finished,
1317 DMA_RESV_USAGE_READ);
1318 }
1319
1320 /* The gang leader is remembered as writer */
1321 e->tv.num_shared = 0;
1322 }
1323
1324 seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_leader_idx],
1325 p->fence);
1326 amdgpu_cs_post_dependencies(p);
1327
1328 if ((leader->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1329 !p->ctx->preamble_presented) {
1330 leader->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1331 p->ctx->preamble_presented = true;
1332 }
1333
1334 cs->out.handle = seq;
1335 leader->uf_sequence = seq;
1336
1337 amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1338 for (i = 0; i < p->gang_size; ++i) {
1339 amdgpu_job_free_resources(p->jobs[i]);
1340 trace_amdgpu_cs_ioctl(p->jobs[i]);
1341 drm_sched_entity_push_job(&p->jobs[i]->base);
1342 p->jobs[i] = NULL;
1343 }
1344
1345 amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1346 ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1347
1348 mutex_unlock(&p->adev->notifier_lock);
1349 mutex_unlock(&p->bo_list->bo_list_mutex);
1350 return 0;
1351
1352error_unlock:
1353 mutex_unlock(&p->adev->notifier_lock);
1354
1355error_cleanup:
1356 for (i = 0; i < p->gang_size; ++i)
1357 drm_sched_job_cleanup(&p->jobs[i]->base);
1358 return r;
1359}
1360
1361/* Cleanup the parser structure */
1362static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser)
1363{
1364 unsigned i;
1365
1366 amdgpu_sync_free(&parser->sync);
1367 for (i = 0; i < parser->num_post_deps; i++) {
1368 drm_syncobj_put(parser->post_deps[i].syncobj);
1369 kfree(parser->post_deps[i].chain);
1370 }
1371 kfree(parser->post_deps);
1372
1373 dma_fence_put(parser->fence);
1374
1375 if (parser->ctx)
1376 amdgpu_ctx_put(parser->ctx);
1377 if (parser->bo_list)
1378 amdgpu_bo_list_put(parser->bo_list);
1379
1380 for (i = 0; i < parser->nchunks; i++)
1381 kvfree(parser->chunks[i].kdata);
1382 kvfree(parser->chunks);
1383 for (i = 0; i < parser->gang_size; ++i) {
1384 if (parser->jobs[i])
1385 amdgpu_job_free(parser->jobs[i]);
1386 }
1387 if (parser->uf_entry.tv.bo) {
1388 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
1389
1390 amdgpu_bo_unref(&uf);
1391 }
1392}
1393
1394int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1395{
1396 struct amdgpu_device *adev = drm_to_adev(dev);
1397 struct amdgpu_cs_parser parser;
1398 int r;
1399
1400 if (amdgpu_ras_intr_triggered())
1401 return -EHWPOISON;
1402
1403 if (!adev->accel_working)
1404 return -EBUSY;
1405
1406 r = amdgpu_cs_parser_init(&parser, adev, filp, data);
1407 if (r) {
1408 if (printk_ratelimit())
1409 DRM_ERROR("Failed to initialize parser %d!\n", r);
1410 return r;
1411 }
1412
1413 r = amdgpu_cs_pass1(&parser, data);
1414 if (r)
1415 goto error_fini;
1416
1417 r = amdgpu_cs_pass2(&parser);
1418 if (r)
1419 goto error_fini;
1420
1421 r = amdgpu_cs_parser_bos(&parser, data);
1422 if (r) {
1423 if (r == -ENOMEM)
1424 DRM_ERROR("Not enough memory for command submission!\n");
1425 else if (r != -ERESTARTSYS && r != -EAGAIN)
1426 DRM_ERROR("Failed to process the buffer list %d!\n", r);
1427 goto error_fini;
1428 }
1429
1430 r = amdgpu_cs_patch_jobs(&parser);
1431 if (r)
1432 goto error_backoff;
1433
1434 r = amdgpu_cs_vm_handling(&parser);
1435 if (r)
1436 goto error_backoff;
1437
1438 r = amdgpu_cs_sync_rings(&parser);
1439 if (r)
1440 goto error_backoff;
1441
1442 trace_amdgpu_cs_ibs(&parser);
1443
1444 r = amdgpu_cs_submit(&parser, data);
1445 if (r)
1446 goto error_backoff;
1447
1448 amdgpu_cs_parser_fini(&parser);
1449 return 0;
1450
1451error_backoff:
1452 ttm_eu_backoff_reservation(&parser.ticket, &parser.validated);
1453 mutex_unlock(&parser.bo_list->bo_list_mutex);
1454
1455error_fini:
1456 amdgpu_cs_parser_fini(&parser);
1457 return r;
1458}
1459
1460/**
1461 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1462 *
1463 * @dev: drm device
1464 * @data: data from userspace
1465 * @filp: file private
1466 *
1467 * Wait for the command submission identified by handle to finish.
1468 */
1469int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1470 struct drm_file *filp)
1471{
1472 union drm_amdgpu_wait_cs *wait = data;
1473 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1474 struct drm_sched_entity *entity;
1475 struct amdgpu_ctx *ctx;
1476 struct dma_fence *fence;
1477 long r;
1478
1479 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1480 if (ctx == NULL)
1481 return -EINVAL;
1482
1483 r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1484 wait->in.ring, &entity);
1485 if (r) {
1486 amdgpu_ctx_put(ctx);
1487 return r;
1488 }
1489
1490 fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1491 if (IS_ERR(fence))
1492 r = PTR_ERR(fence);
1493 else if (fence) {
1494 r = dma_fence_wait_timeout(fence, true, timeout);
1495 if (r > 0 && fence->error)
1496 r = fence->error;
1497 dma_fence_put(fence);
1498 } else
1499 r = 1;
1500
1501 amdgpu_ctx_put(ctx);
1502 if (r < 0)
1503 return r;
1504
1505 memset(wait, 0, sizeof(*wait));
1506 wait->out.status = (r == 0);
1507
1508 return 0;
1509}
1510
1511/**
1512 * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1513 *
1514 * @adev: amdgpu device
1515 * @filp: file private
1516 * @user: drm_amdgpu_fence copied from user space
1517 */
1518static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1519 struct drm_file *filp,
1520 struct drm_amdgpu_fence *user)
1521{
1522 struct drm_sched_entity *entity;
1523 struct amdgpu_ctx *ctx;
1524 struct dma_fence *fence;
1525 int r;
1526
1527 ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1528 if (ctx == NULL)
1529 return ERR_PTR(-EINVAL);
1530
1531 r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1532 user->ring, &entity);
1533 if (r) {
1534 amdgpu_ctx_put(ctx);
1535 return ERR_PTR(r);
1536 }
1537
1538 fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1539 amdgpu_ctx_put(ctx);
1540
1541 return fence;
1542}
1543
1544int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1545 struct drm_file *filp)
1546{
1547 struct amdgpu_device *adev = drm_to_adev(dev);
1548 union drm_amdgpu_fence_to_handle *info = data;
1549 struct dma_fence *fence;
1550 struct drm_syncobj *syncobj;
1551 struct sync_file *sync_file;
1552 int fd, r;
1553
1554 fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1555 if (IS_ERR(fence))
1556 return PTR_ERR(fence);
1557
1558 if (!fence)
1559 fence = dma_fence_get_stub();
1560
1561 switch (info->in.what) {
1562 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1563 r = drm_syncobj_create(&syncobj, 0, fence);
1564 dma_fence_put(fence);
1565 if (r)
1566 return r;
1567 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1568 drm_syncobj_put(syncobj);
1569 return r;
1570
1571 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1572 r = drm_syncobj_create(&syncobj, 0, fence);
1573 dma_fence_put(fence);
1574 if (r)
1575 return r;
1576 r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
1577 drm_syncobj_put(syncobj);
1578 return r;
1579
1580 case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1581 fd = get_unused_fd_flags(O_CLOEXEC);
1582 if (fd < 0) {
1583 dma_fence_put(fence);
1584 return fd;
1585 }
1586
1587 sync_file = sync_file_create(fence);
1588 dma_fence_put(fence);
1589 if (!sync_file) {
1590 put_unused_fd(fd);
1591 return -ENOMEM;
1592 }
1593
1594 fd_install(fd, sync_file->file);
1595 info->out.handle = fd;
1596 return 0;
1597
1598 default:
1599 dma_fence_put(fence);
1600 return -EINVAL;
1601 }
1602}
1603
1604/**
1605 * amdgpu_cs_wait_all_fences - wait on all fences to signal
1606 *
1607 * @adev: amdgpu device
1608 * @filp: file private
1609 * @wait: wait parameters
1610 * @fences: array of drm_amdgpu_fence
1611 */
1612static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1613 struct drm_file *filp,
1614 union drm_amdgpu_wait_fences *wait,
1615 struct drm_amdgpu_fence *fences)
1616{
1617 uint32_t fence_count = wait->in.fence_count;
1618 unsigned int i;
1619 long r = 1;
1620
1621 for (i = 0; i < fence_count; i++) {
1622 struct dma_fence *fence;
1623 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1624
1625 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1626 if (IS_ERR(fence))
1627 return PTR_ERR(fence);
1628 else if (!fence)
1629 continue;
1630
1631 r = dma_fence_wait_timeout(fence, true, timeout);
1632 dma_fence_put(fence);
1633 if (r < 0)
1634 return r;
1635
1636 if (r == 0)
1637 break;
1638
1639 if (fence->error)
1640 return fence->error;
1641 }
1642
1643 memset(wait, 0, sizeof(*wait));
1644 wait->out.status = (r > 0);
1645
1646 return 0;
1647}
1648
1649/**
1650 * amdgpu_cs_wait_any_fence - wait on any fence to signal
1651 *
1652 * @adev: amdgpu device
1653 * @filp: file private
1654 * @wait: wait parameters
1655 * @fences: array of drm_amdgpu_fence
1656 */
1657static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1658 struct drm_file *filp,
1659 union drm_amdgpu_wait_fences *wait,
1660 struct drm_amdgpu_fence *fences)
1661{
1662 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1663 uint32_t fence_count = wait->in.fence_count;
1664 uint32_t first = ~0;
1665 struct dma_fence **array;
1666 unsigned int i;
1667 long r;
1668
1669 /* Prepare the fence array */
1670 array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1671
1672 if (array == NULL)
1673 return -ENOMEM;
1674
1675 for (i = 0; i < fence_count; i++) {
1676 struct dma_fence *fence;
1677
1678 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1679 if (IS_ERR(fence)) {
1680 r = PTR_ERR(fence);
1681 goto err_free_fence_array;
1682 } else if (fence) {
1683 array[i] = fence;
1684 } else { /* NULL, the fence has been already signaled */
1685 r = 1;
1686 first = i;
1687 goto out;
1688 }
1689 }
1690
1691 r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1692 &first);
1693 if (r < 0)
1694 goto err_free_fence_array;
1695
1696out:
1697 memset(wait, 0, sizeof(*wait));
1698 wait->out.status = (r > 0);
1699 wait->out.first_signaled = first;
1700
1701 if (first < fence_count && array[first])
1702 r = array[first]->error;
1703 else
1704 r = 0;
1705
1706err_free_fence_array:
1707 for (i = 0; i < fence_count; i++)
1708 dma_fence_put(array[i]);
1709 kfree(array);
1710
1711 return r;
1712}
1713
1714/**
1715 * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1716 *
1717 * @dev: drm device
1718 * @data: data from userspace
1719 * @filp: file private
1720 */
1721int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1722 struct drm_file *filp)
1723{
1724 struct amdgpu_device *adev = drm_to_adev(dev);
1725 union drm_amdgpu_wait_fences *wait = data;
1726 uint32_t fence_count = wait->in.fence_count;
1727 struct drm_amdgpu_fence *fences_user;
1728 struct drm_amdgpu_fence *fences;
1729 int r;
1730
1731 /* Get the fences from userspace */
1732 fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1733 GFP_KERNEL);
1734 if (fences == NULL)
1735 return -ENOMEM;
1736
1737 fences_user = u64_to_user_ptr(wait->in.fences);
1738 if (copy_from_user(fences, fences_user,
1739 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1740 r = -EFAULT;
1741 goto err_free_fences;
1742 }
1743
1744 if (wait->in.wait_all)
1745 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1746 else
1747 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1748
1749err_free_fences:
1750 kfree(fences);
1751
1752 return r;
1753}
1754
1755/**
1756 * amdgpu_cs_find_mapping - find bo_va for VM address
1757 *
1758 * @parser: command submission parser context
1759 * @addr: VM address
1760 * @bo: resulting BO of the mapping found
1761 * @map: Placeholder to return found BO mapping
1762 *
1763 * Search the buffer objects in the command submission context for a certain
1764 * virtual memory address. Returns allocation structure when found, NULL
1765 * otherwise.
1766 */
1767int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1768 uint64_t addr, struct amdgpu_bo **bo,
1769 struct amdgpu_bo_va_mapping **map)
1770{
1771 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1772 struct ttm_operation_ctx ctx = { false, false };
1773 struct amdgpu_vm *vm = &fpriv->vm;
1774 struct amdgpu_bo_va_mapping *mapping;
1775 int r;
1776
1777 addr /= AMDGPU_GPU_PAGE_SIZE;
1778
1779 mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1780 if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1781 return -EINVAL;
1782
1783 *bo = mapping->bo_va->base.bo;
1784 *map = mapping;
1785
1786 /* Double check that the BO is reserved by this CS */
1787 if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket)
1788 return -EINVAL;
1789
1790 if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1791 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1792 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1793 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1794 if (r)
1795 return r;
1796 }
1797
1798 return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1799}
1/*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27#include <linux/pagemap.h>
28#include <drm/drmP.h>
29#include <drm/amdgpu_drm.h>
30#include "amdgpu.h"
31#include "amdgpu_trace.h"
32
33int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
34 u32 ip_instance, u32 ring,
35 struct amdgpu_ring **out_ring)
36{
37 /* Right now all IPs have only one instance - multiple rings. */
38 if (ip_instance != 0) {
39 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
40 return -EINVAL;
41 }
42
43 switch (ip_type) {
44 default:
45 DRM_ERROR("unknown ip type: %d\n", ip_type);
46 return -EINVAL;
47 case AMDGPU_HW_IP_GFX:
48 if (ring < adev->gfx.num_gfx_rings) {
49 *out_ring = &adev->gfx.gfx_ring[ring];
50 } else {
51 DRM_ERROR("only %d gfx rings are supported now\n",
52 adev->gfx.num_gfx_rings);
53 return -EINVAL;
54 }
55 break;
56 case AMDGPU_HW_IP_COMPUTE:
57 if (ring < adev->gfx.num_compute_rings) {
58 *out_ring = &adev->gfx.compute_ring[ring];
59 } else {
60 DRM_ERROR("only %d compute rings are supported now\n",
61 adev->gfx.num_compute_rings);
62 return -EINVAL;
63 }
64 break;
65 case AMDGPU_HW_IP_DMA:
66 if (ring < adev->sdma.num_instances) {
67 *out_ring = &adev->sdma.instance[ring].ring;
68 } else {
69 DRM_ERROR("only %d SDMA rings are supported\n",
70 adev->sdma.num_instances);
71 return -EINVAL;
72 }
73 break;
74 case AMDGPU_HW_IP_UVD:
75 *out_ring = &adev->uvd.ring;
76 break;
77 case AMDGPU_HW_IP_VCE:
78 if (ring < 2){
79 *out_ring = &adev->vce.ring[ring];
80 } else {
81 DRM_ERROR("only two VCE rings are supported\n");
82 return -EINVAL;
83 }
84 break;
85 }
86
87 if (!(*out_ring && (*out_ring)->adev)) {
88 DRM_ERROR("Ring %d is not initialized on IP %d\n",
89 ring, ip_type);
90 return -EINVAL;
91 }
92
93 return 0;
94}
95
96static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
97 struct drm_amdgpu_cs_chunk_fence *data,
98 uint32_t *offset)
99{
100 struct drm_gem_object *gobj;
101 unsigned long size;
102
103 gobj = drm_gem_object_lookup(p->filp, data->handle);
104 if (gobj == NULL)
105 return -EINVAL;
106
107 p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
108 p->uf_entry.priority = 0;
109 p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
110 p->uf_entry.tv.shared = true;
111 p->uf_entry.user_pages = NULL;
112
113 size = amdgpu_bo_size(p->uf_entry.robj);
114 if (size != PAGE_SIZE || (data->offset + 8) > size)
115 return -EINVAL;
116
117 *offset = data->offset;
118
119 drm_gem_object_unreference_unlocked(gobj);
120
121 if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
122 amdgpu_bo_unref(&p->uf_entry.robj);
123 return -EINVAL;
124 }
125
126 return 0;
127}
128
129int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
130{
131 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
132 struct amdgpu_vm *vm = &fpriv->vm;
133 union drm_amdgpu_cs *cs = data;
134 uint64_t *chunk_array_user;
135 uint64_t *chunk_array;
136 unsigned size, num_ibs = 0;
137 uint32_t uf_offset = 0;
138 int i;
139 int ret;
140
141 if (cs->in.num_chunks == 0)
142 return 0;
143
144 chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
145 if (!chunk_array)
146 return -ENOMEM;
147
148 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
149 if (!p->ctx) {
150 ret = -EINVAL;
151 goto free_chunk;
152 }
153
154 /* get chunks */
155 chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);
156 if (copy_from_user(chunk_array, chunk_array_user,
157 sizeof(uint64_t)*cs->in.num_chunks)) {
158 ret = -EFAULT;
159 goto put_ctx;
160 }
161
162 p->nchunks = cs->in.num_chunks;
163 p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
164 GFP_KERNEL);
165 if (!p->chunks) {
166 ret = -ENOMEM;
167 goto put_ctx;
168 }
169
170 for (i = 0; i < p->nchunks; i++) {
171 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
172 struct drm_amdgpu_cs_chunk user_chunk;
173 uint32_t __user *cdata;
174
175 chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
176 if (copy_from_user(&user_chunk, chunk_ptr,
177 sizeof(struct drm_amdgpu_cs_chunk))) {
178 ret = -EFAULT;
179 i--;
180 goto free_partial_kdata;
181 }
182 p->chunks[i].chunk_id = user_chunk.chunk_id;
183 p->chunks[i].length_dw = user_chunk.length_dw;
184
185 size = p->chunks[i].length_dw;
186 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
187
188 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
189 if (p->chunks[i].kdata == NULL) {
190 ret = -ENOMEM;
191 i--;
192 goto free_partial_kdata;
193 }
194 size *= sizeof(uint32_t);
195 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
196 ret = -EFAULT;
197 goto free_partial_kdata;
198 }
199
200 switch (p->chunks[i].chunk_id) {
201 case AMDGPU_CHUNK_ID_IB:
202 ++num_ibs;
203 break;
204
205 case AMDGPU_CHUNK_ID_FENCE:
206 size = sizeof(struct drm_amdgpu_cs_chunk_fence);
207 if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
208 ret = -EINVAL;
209 goto free_partial_kdata;
210 }
211
212 ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
213 &uf_offset);
214 if (ret)
215 goto free_partial_kdata;
216
217 break;
218
219 case AMDGPU_CHUNK_ID_DEPENDENCIES:
220 break;
221
222 default:
223 ret = -EINVAL;
224 goto free_partial_kdata;
225 }
226 }
227
228 ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
229 if (ret)
230 goto free_all_kdata;
231
232 if (p->uf_entry.robj)
233 p->job->uf_addr = uf_offset;
234 kfree(chunk_array);
235 return 0;
236
237free_all_kdata:
238 i = p->nchunks - 1;
239free_partial_kdata:
240 for (; i >= 0; i--)
241 drm_free_large(p->chunks[i].kdata);
242 kfree(p->chunks);
243put_ctx:
244 amdgpu_ctx_put(p->ctx);
245free_chunk:
246 kfree(chunk_array);
247
248 return ret;
249}
250
251/* Convert microseconds to bytes. */
252static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
253{
254 if (us <= 0 || !adev->mm_stats.log2_max_MBps)
255 return 0;
256
257 /* Since accum_us is incremented by a million per second, just
258 * multiply it by the number of MB/s to get the number of bytes.
259 */
260 return us << adev->mm_stats.log2_max_MBps;
261}
262
263static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
264{
265 if (!adev->mm_stats.log2_max_MBps)
266 return 0;
267
268 return bytes >> adev->mm_stats.log2_max_MBps;
269}
270
271/* Returns how many bytes TTM can move right now. If no bytes can be moved,
272 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
273 * which means it can go over the threshold once. If that happens, the driver
274 * will be in debt and no other buffer migrations can be done until that debt
275 * is repaid.
276 *
277 * This approach allows moving a buffer of any size (it's important to allow
278 * that).
279 *
280 * The currency is simply time in microseconds and it increases as the clock
281 * ticks. The accumulated microseconds (us) are converted to bytes and
282 * returned.
283 */
284static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
285{
286 s64 time_us, increment_us;
287 u64 max_bytes;
288 u64 free_vram, total_vram, used_vram;
289
290 /* Allow a maximum of 200 accumulated ms. This is basically per-IB
291 * throttling.
292 *
293 * It means that in order to get full max MBps, at least 5 IBs per
294 * second must be submitted and not more than 200ms apart from each
295 * other.
296 */
297 const s64 us_upper_bound = 200000;
298
299 if (!adev->mm_stats.log2_max_MBps)
300 return 0;
301
302 total_vram = adev->mc.real_vram_size - adev->vram_pin_size;
303 used_vram = atomic64_read(&adev->vram_usage);
304 free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
305
306 spin_lock(&adev->mm_stats.lock);
307
308 /* Increase the amount of accumulated us. */
309 time_us = ktime_to_us(ktime_get());
310 increment_us = time_us - adev->mm_stats.last_update_us;
311 adev->mm_stats.last_update_us = time_us;
312 adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
313 us_upper_bound);
314
315 /* This prevents the short period of low performance when the VRAM
316 * usage is low and the driver is in debt or doesn't have enough
317 * accumulated us to fill VRAM quickly.
318 *
319 * The situation can occur in these cases:
320 * - a lot of VRAM is freed by userspace
321 * - the presence of a big buffer causes a lot of evictions
322 * (solution: split buffers into smaller ones)
323 *
324 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
325 * accum_us to a positive number.
326 */
327 if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
328 s64 min_us;
329
330 /* Be more aggresive on dGPUs. Try to fill a portion of free
331 * VRAM now.
332 */
333 if (!(adev->flags & AMD_IS_APU))
334 min_us = bytes_to_us(adev, free_vram / 4);
335 else
336 min_us = 0; /* Reset accum_us on APUs. */
337
338 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
339 }
340
341 /* This returns 0 if the driver is in debt to disallow (optional)
342 * buffer moves.
343 */
344 max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
345
346 spin_unlock(&adev->mm_stats.lock);
347 return max_bytes;
348}
349
350/* Report how many bytes have really been moved for the last command
351 * submission. This can result in a debt that can stop buffer migrations
352 * temporarily.
353 */
354static void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev,
355 u64 num_bytes)
356{
357 spin_lock(&adev->mm_stats.lock);
358 adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
359 spin_unlock(&adev->mm_stats.lock);
360}
361
362static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
363 struct amdgpu_bo *bo)
364{
365 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
366 u64 initial_bytes_moved;
367 uint32_t domain;
368 int r;
369
370 if (bo->pin_count)
371 return 0;
372
373 /* Don't move this buffer if we have depleted our allowance
374 * to move it. Don't move anything if the threshold is zero.
375 */
376 if (p->bytes_moved < p->bytes_moved_threshold)
377 domain = bo->prefered_domains;
378 else
379 domain = bo->allowed_domains;
380
381retry:
382 amdgpu_ttm_placement_from_domain(bo, domain);
383 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
384 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
385 p->bytes_moved += atomic64_read(&adev->num_bytes_moved) -
386 initial_bytes_moved;
387
388 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
389 domain = bo->allowed_domains;
390 goto retry;
391 }
392
393 return r;
394}
395
396/* Last resort, try to evict something from the current working set */
397static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
398 struct amdgpu_bo *validated)
399{
400 uint32_t domain = validated->allowed_domains;
401 int r;
402
403 if (!p->evictable)
404 return false;
405
406 for (;&p->evictable->tv.head != &p->validated;
407 p->evictable = list_prev_entry(p->evictable, tv.head)) {
408
409 struct amdgpu_bo_list_entry *candidate = p->evictable;
410 struct amdgpu_bo *bo = candidate->robj;
411 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
412 u64 initial_bytes_moved;
413 uint32_t other;
414
415 /* If we reached our current BO we can forget it */
416 if (candidate->robj == validated)
417 break;
418
419 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
420
421 /* Check if this BO is in one of the domains we need space for */
422 if (!(other & domain))
423 continue;
424
425 /* Check if we can move this BO somewhere else */
426 other = bo->allowed_domains & ~domain;
427 if (!other)
428 continue;
429
430 /* Good we can try to move this BO somewhere else */
431 amdgpu_ttm_placement_from_domain(bo, other);
432 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
433 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
434 p->bytes_moved += atomic64_read(&adev->num_bytes_moved) -
435 initial_bytes_moved;
436
437 if (unlikely(r))
438 break;
439
440 p->evictable = list_prev_entry(p->evictable, tv.head);
441 list_move(&candidate->tv.head, &p->validated);
442
443 return true;
444 }
445
446 return false;
447}
448
449static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
450{
451 struct amdgpu_cs_parser *p = param;
452 int r;
453
454 do {
455 r = amdgpu_cs_bo_validate(p, bo);
456 } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
457 if (r)
458 return r;
459
460 if (bo->shadow)
461 r = amdgpu_cs_bo_validate(p, bo->shadow);
462
463 return r;
464}
465
466static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
467 struct list_head *validated)
468{
469 struct amdgpu_bo_list_entry *lobj;
470 int r;
471
472 list_for_each_entry(lobj, validated, tv.head) {
473 struct amdgpu_bo *bo = lobj->robj;
474 bool binding_userptr = false;
475 struct mm_struct *usermm;
476
477 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
478 if (usermm && usermm != current->mm)
479 return -EPERM;
480
481 /* Check if we have user pages and nobody bound the BO already */
482 if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
483 size_t size = sizeof(struct page *);
484
485 size *= bo->tbo.ttm->num_pages;
486 memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
487 binding_userptr = true;
488 }
489
490 if (p->evictable == lobj)
491 p->evictable = NULL;
492
493 r = amdgpu_cs_validate(p, bo);
494 if (r)
495 return r;
496
497 if (binding_userptr) {
498 drm_free_large(lobj->user_pages);
499 lobj->user_pages = NULL;
500 }
501 }
502 return 0;
503}
504
505static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
506 union drm_amdgpu_cs *cs)
507{
508 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
509 struct amdgpu_bo_list_entry *e;
510 struct list_head duplicates;
511 bool need_mmap_lock = false;
512 unsigned i, tries = 10;
513 int r;
514
515 INIT_LIST_HEAD(&p->validated);
516
517 p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
518 if (p->bo_list) {
519 need_mmap_lock = p->bo_list->first_userptr !=
520 p->bo_list->num_entries;
521 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
522 }
523
524 INIT_LIST_HEAD(&duplicates);
525 amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
526
527 if (p->uf_entry.robj)
528 list_add(&p->uf_entry.tv.head, &p->validated);
529
530 if (need_mmap_lock)
531 down_read(¤t->mm->mmap_sem);
532
533 while (1) {
534 struct list_head need_pages;
535 unsigned i;
536
537 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
538 &duplicates);
539 if (unlikely(r != 0)) {
540 if (r != -ERESTARTSYS)
541 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
542 goto error_free_pages;
543 }
544
545 /* Without a BO list we don't have userptr BOs */
546 if (!p->bo_list)
547 break;
548
549 INIT_LIST_HEAD(&need_pages);
550 for (i = p->bo_list->first_userptr;
551 i < p->bo_list->num_entries; ++i) {
552
553 e = &p->bo_list->array[i];
554
555 if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
556 &e->user_invalidated) && e->user_pages) {
557
558 /* We acquired a page array, but somebody
559 * invalidated it. Free it an try again
560 */
561 release_pages(e->user_pages,
562 e->robj->tbo.ttm->num_pages,
563 false);
564 drm_free_large(e->user_pages);
565 e->user_pages = NULL;
566 }
567
568 if (e->robj->tbo.ttm->state != tt_bound &&
569 !e->user_pages) {
570 list_del(&e->tv.head);
571 list_add(&e->tv.head, &need_pages);
572
573 amdgpu_bo_unreserve(e->robj);
574 }
575 }
576
577 if (list_empty(&need_pages))
578 break;
579
580 /* Unreserve everything again. */
581 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
582
583 /* We tried too many times, just abort */
584 if (!--tries) {
585 r = -EDEADLK;
586 DRM_ERROR("deadlock in %s\n", __func__);
587 goto error_free_pages;
588 }
589
590 /* Fill the page arrays for all useptrs. */
591 list_for_each_entry(e, &need_pages, tv.head) {
592 struct ttm_tt *ttm = e->robj->tbo.ttm;
593
594 e->user_pages = drm_calloc_large(ttm->num_pages,
595 sizeof(struct page*));
596 if (!e->user_pages) {
597 r = -ENOMEM;
598 DRM_ERROR("calloc failure in %s\n", __func__);
599 goto error_free_pages;
600 }
601
602 r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
603 if (r) {
604 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
605 drm_free_large(e->user_pages);
606 e->user_pages = NULL;
607 goto error_free_pages;
608 }
609 }
610
611 /* And try again. */
612 list_splice(&need_pages, &p->validated);
613 }
614
615 p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev);
616 p->bytes_moved = 0;
617 p->evictable = list_last_entry(&p->validated,
618 struct amdgpu_bo_list_entry,
619 tv.head);
620
621 r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
622 amdgpu_cs_validate, p);
623 if (r) {
624 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
625 goto error_validate;
626 }
627
628 r = amdgpu_cs_list_validate(p, &duplicates);
629 if (r) {
630 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
631 goto error_validate;
632 }
633
634 r = amdgpu_cs_list_validate(p, &p->validated);
635 if (r) {
636 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
637 goto error_validate;
638 }
639
640 amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved);
641
642 fpriv->vm.last_eviction_counter =
643 atomic64_read(&p->adev->num_evictions);
644
645 if (p->bo_list) {
646 struct amdgpu_bo *gds = p->bo_list->gds_obj;
647 struct amdgpu_bo *gws = p->bo_list->gws_obj;
648 struct amdgpu_bo *oa = p->bo_list->oa_obj;
649 struct amdgpu_vm *vm = &fpriv->vm;
650 unsigned i;
651
652 for (i = 0; i < p->bo_list->num_entries; i++) {
653 struct amdgpu_bo *bo = p->bo_list->array[i].robj;
654
655 p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
656 }
657
658 if (gds) {
659 p->job->gds_base = amdgpu_bo_gpu_offset(gds);
660 p->job->gds_size = amdgpu_bo_size(gds);
661 }
662 if (gws) {
663 p->job->gws_base = amdgpu_bo_gpu_offset(gws);
664 p->job->gws_size = amdgpu_bo_size(gws);
665 }
666 if (oa) {
667 p->job->oa_base = amdgpu_bo_gpu_offset(oa);
668 p->job->oa_size = amdgpu_bo_size(oa);
669 }
670 }
671
672 if (!r && p->uf_entry.robj) {
673 struct amdgpu_bo *uf = p->uf_entry.robj;
674
675 r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem);
676 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
677 }
678
679error_validate:
680 if (r) {
681 amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm);
682 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
683 }
684
685error_free_pages:
686
687 if (need_mmap_lock)
688 up_read(¤t->mm->mmap_sem);
689
690 if (p->bo_list) {
691 for (i = p->bo_list->first_userptr;
692 i < p->bo_list->num_entries; ++i) {
693 e = &p->bo_list->array[i];
694
695 if (!e->user_pages)
696 continue;
697
698 release_pages(e->user_pages,
699 e->robj->tbo.ttm->num_pages,
700 false);
701 drm_free_large(e->user_pages);
702 }
703 }
704
705 return r;
706}
707
708static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
709{
710 struct amdgpu_bo_list_entry *e;
711 int r;
712
713 list_for_each_entry(e, &p->validated, tv.head) {
714 struct reservation_object *resv = e->robj->tbo.resv;
715 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
716
717 if (r)
718 return r;
719 }
720 return 0;
721}
722
723/**
724 * cs_parser_fini() - clean parser states
725 * @parser: parser structure holding parsing context.
726 * @error: error number
727 *
728 * If error is set than unvalidate buffer, otherwise just free memory
729 * used by parsing context.
730 **/
731static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
732{
733 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
734 unsigned i;
735
736 if (!error) {
737 amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);
738
739 ttm_eu_fence_buffer_objects(&parser->ticket,
740 &parser->validated,
741 parser->fence);
742 } else if (backoff) {
743 ttm_eu_backoff_reservation(&parser->ticket,
744 &parser->validated);
745 }
746 dma_fence_put(parser->fence);
747
748 if (parser->ctx)
749 amdgpu_ctx_put(parser->ctx);
750 if (parser->bo_list)
751 amdgpu_bo_list_put(parser->bo_list);
752
753 for (i = 0; i < parser->nchunks; i++)
754 drm_free_large(parser->chunks[i].kdata);
755 kfree(parser->chunks);
756 if (parser->job)
757 amdgpu_job_free(parser->job);
758 amdgpu_bo_unref(&parser->uf_entry.robj);
759}
760
761static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
762 struct amdgpu_vm *vm)
763{
764 struct amdgpu_device *adev = p->adev;
765 struct amdgpu_bo_va *bo_va;
766 struct amdgpu_bo *bo;
767 int i, r;
768
769 r = amdgpu_vm_update_page_directory(adev, vm);
770 if (r)
771 return r;
772
773 r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence);
774 if (r)
775 return r;
776
777 r = amdgpu_vm_clear_freed(adev, vm);
778 if (r)
779 return r;
780
781 if (p->bo_list) {
782 for (i = 0; i < p->bo_list->num_entries; i++) {
783 struct dma_fence *f;
784
785 /* ignore duplicates */
786 bo = p->bo_list->array[i].robj;
787 if (!bo)
788 continue;
789
790 bo_va = p->bo_list->array[i].bo_va;
791 if (bo_va == NULL)
792 continue;
793
794 r = amdgpu_vm_bo_update(adev, bo_va, false);
795 if (r)
796 return r;
797
798 f = bo_va->last_pt_update;
799 r = amdgpu_sync_fence(adev, &p->job->sync, f);
800 if (r)
801 return r;
802 }
803
804 }
805
806 r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync);
807
808 if (amdgpu_vm_debug && p->bo_list) {
809 /* Invalidate all BOs to test for userspace bugs */
810 for (i = 0; i < p->bo_list->num_entries; i++) {
811 /* ignore duplicates */
812 bo = p->bo_list->array[i].robj;
813 if (!bo)
814 continue;
815
816 amdgpu_vm_bo_invalidate(adev, bo);
817 }
818 }
819
820 return r;
821}
822
823static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
824 struct amdgpu_cs_parser *p)
825{
826 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
827 struct amdgpu_vm *vm = &fpriv->vm;
828 struct amdgpu_ring *ring = p->job->ring;
829 int i, r;
830
831 /* Only for UVD/VCE VM emulation */
832 if (ring->funcs->parse_cs) {
833 for (i = 0; i < p->job->num_ibs; i++) {
834 r = amdgpu_ring_parse_cs(ring, p, i);
835 if (r)
836 return r;
837 }
838 }
839
840 if (p->job->vm) {
841 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
842
843 r = amdgpu_bo_vm_update_pte(p, vm);
844 if (r)
845 return r;
846 }
847
848 return amdgpu_cs_sync_rings(p);
849}
850
851static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
852 struct amdgpu_cs_parser *parser)
853{
854 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
855 struct amdgpu_vm *vm = &fpriv->vm;
856 int i, j;
857 int r;
858
859 for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
860 struct amdgpu_cs_chunk *chunk;
861 struct amdgpu_ib *ib;
862 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
863 struct amdgpu_ring *ring;
864
865 chunk = &parser->chunks[i];
866 ib = &parser->job->ibs[j];
867 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
868
869 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
870 continue;
871
872 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
873 chunk_ib->ip_instance, chunk_ib->ring,
874 &ring);
875 if (r)
876 return r;
877
878 if (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
879 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
880 if (!parser->ctx->preamble_presented) {
881 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
882 parser->ctx->preamble_presented = true;
883 }
884 }
885
886 if (parser->job->ring && parser->job->ring != ring)
887 return -EINVAL;
888
889 parser->job->ring = ring;
890
891 if (ring->funcs->parse_cs) {
892 struct amdgpu_bo_va_mapping *m;
893 struct amdgpu_bo *aobj = NULL;
894 uint64_t offset;
895 uint8_t *kptr;
896
897 m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
898 &aobj);
899 if (!aobj) {
900 DRM_ERROR("IB va_start is invalid\n");
901 return -EINVAL;
902 }
903
904 if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
905 (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
906 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
907 return -EINVAL;
908 }
909
910 /* the IB should be reserved at this point */
911 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
912 if (r) {
913 return r;
914 }
915
916 offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
917 kptr += chunk_ib->va_start - offset;
918
919 r = amdgpu_ib_get(adev, vm, chunk_ib->ib_bytes, ib);
920 if (r) {
921 DRM_ERROR("Failed to get ib !\n");
922 return r;
923 }
924
925 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
926 amdgpu_bo_kunmap(aobj);
927 } else {
928 r = amdgpu_ib_get(adev, vm, 0, ib);
929 if (r) {
930 DRM_ERROR("Failed to get ib !\n");
931 return r;
932 }
933
934 }
935
936 ib->gpu_addr = chunk_ib->va_start;
937 ib->length_dw = chunk_ib->ib_bytes / 4;
938 ib->flags = chunk_ib->flags;
939 j++;
940 }
941
942 /* UVD & VCE fw doesn't support user fences */
943 if (parser->job->uf_addr && (
944 parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
945 parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
946 return -EINVAL;
947
948 return 0;
949}
950
951static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
952 struct amdgpu_cs_parser *p)
953{
954 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
955 int i, j, r;
956
957 for (i = 0; i < p->nchunks; ++i) {
958 struct drm_amdgpu_cs_chunk_dep *deps;
959 struct amdgpu_cs_chunk *chunk;
960 unsigned num_deps;
961
962 chunk = &p->chunks[i];
963
964 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
965 continue;
966
967 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
968 num_deps = chunk->length_dw * 4 /
969 sizeof(struct drm_amdgpu_cs_chunk_dep);
970
971 for (j = 0; j < num_deps; ++j) {
972 struct amdgpu_ring *ring;
973 struct amdgpu_ctx *ctx;
974 struct dma_fence *fence;
975
976 r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
977 deps[j].ip_instance,
978 deps[j].ring, &ring);
979 if (r)
980 return r;
981
982 ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
983 if (ctx == NULL)
984 return -EINVAL;
985
986 fence = amdgpu_ctx_get_fence(ctx, ring,
987 deps[j].handle);
988 if (IS_ERR(fence)) {
989 r = PTR_ERR(fence);
990 amdgpu_ctx_put(ctx);
991 return r;
992
993 } else if (fence) {
994 r = amdgpu_sync_fence(adev, &p->job->sync,
995 fence);
996 dma_fence_put(fence);
997 amdgpu_ctx_put(ctx);
998 if (r)
999 return r;
1000 }
1001 }
1002 }
1003
1004 return 0;
1005}
1006
1007static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1008 union drm_amdgpu_cs *cs)
1009{
1010 struct amdgpu_ring *ring = p->job->ring;
1011 struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
1012 struct amdgpu_job *job;
1013 int r;
1014
1015 job = p->job;
1016 p->job = NULL;
1017
1018 r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
1019 if (r) {
1020 amdgpu_job_free(job);
1021 return r;
1022 }
1023
1024 job->owner = p->filp;
1025 job->fence_ctx = entity->fence_context;
1026 p->fence = dma_fence_get(&job->base.s_fence->finished);
1027 cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
1028 job->uf_sequence = cs->out.handle;
1029 amdgpu_job_free_resources(job);
1030
1031 trace_amdgpu_cs_ioctl(job);
1032 amd_sched_entity_push_job(&job->base);
1033
1034 return 0;
1035}
1036
1037int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1038{
1039 struct amdgpu_device *adev = dev->dev_private;
1040 union drm_amdgpu_cs *cs = data;
1041 struct amdgpu_cs_parser parser = {};
1042 bool reserved_buffers = false;
1043 int i, r;
1044
1045 if (!adev->accel_working)
1046 return -EBUSY;
1047
1048 parser.adev = adev;
1049 parser.filp = filp;
1050
1051 r = amdgpu_cs_parser_init(&parser, data);
1052 if (r) {
1053 DRM_ERROR("Failed to initialize parser !\n");
1054 goto out;
1055 }
1056
1057 r = amdgpu_cs_parser_bos(&parser, data);
1058 if (r) {
1059 if (r == -ENOMEM)
1060 DRM_ERROR("Not enough memory for command submission!\n");
1061 else if (r != -ERESTARTSYS)
1062 DRM_ERROR("Failed to process the buffer list %d!\n", r);
1063 goto out;
1064 }
1065
1066 reserved_buffers = true;
1067 r = amdgpu_cs_ib_fill(adev, &parser);
1068 if (r)
1069 goto out;
1070
1071 r = amdgpu_cs_dependencies(adev, &parser);
1072 if (r) {
1073 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1074 goto out;
1075 }
1076
1077 for (i = 0; i < parser.job->num_ibs; i++)
1078 trace_amdgpu_cs(&parser, i);
1079
1080 r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1081 if (r)
1082 goto out;
1083
1084 r = amdgpu_cs_submit(&parser, cs);
1085
1086out:
1087 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1088 return r;
1089}
1090
1091/**
1092 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1093 *
1094 * @dev: drm device
1095 * @data: data from userspace
1096 * @filp: file private
1097 *
1098 * Wait for the command submission identified by handle to finish.
1099 */
1100int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1101 struct drm_file *filp)
1102{
1103 union drm_amdgpu_wait_cs *wait = data;
1104 struct amdgpu_device *adev = dev->dev_private;
1105 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1106 struct amdgpu_ring *ring = NULL;
1107 struct amdgpu_ctx *ctx;
1108 struct dma_fence *fence;
1109 long r;
1110
1111 r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
1112 wait->in.ring, &ring);
1113 if (r)
1114 return r;
1115
1116 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1117 if (ctx == NULL)
1118 return -EINVAL;
1119
1120 fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
1121 if (IS_ERR(fence))
1122 r = PTR_ERR(fence);
1123 else if (fence) {
1124 r = dma_fence_wait_timeout(fence, true, timeout);
1125 dma_fence_put(fence);
1126 } else
1127 r = 1;
1128
1129 amdgpu_ctx_put(ctx);
1130 if (r < 0)
1131 return r;
1132
1133 memset(wait, 0, sizeof(*wait));
1134 wait->out.status = (r == 0);
1135
1136 return 0;
1137}
1138
1139/**
1140 * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1141 *
1142 * @adev: amdgpu device
1143 * @filp: file private
1144 * @user: drm_amdgpu_fence copied from user space
1145 */
1146static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1147 struct drm_file *filp,
1148 struct drm_amdgpu_fence *user)
1149{
1150 struct amdgpu_ring *ring;
1151 struct amdgpu_ctx *ctx;
1152 struct dma_fence *fence;
1153 int r;
1154
1155 r = amdgpu_cs_get_ring(adev, user->ip_type, user->ip_instance,
1156 user->ring, &ring);
1157 if (r)
1158 return ERR_PTR(r);
1159
1160 ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1161 if (ctx == NULL)
1162 return ERR_PTR(-EINVAL);
1163
1164 fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no);
1165 amdgpu_ctx_put(ctx);
1166
1167 return fence;
1168}
1169
1170/**
1171 * amdgpu_cs_wait_all_fence - wait on all fences to signal
1172 *
1173 * @adev: amdgpu device
1174 * @filp: file private
1175 * @wait: wait parameters
1176 * @fences: array of drm_amdgpu_fence
1177 */
1178static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1179 struct drm_file *filp,
1180 union drm_amdgpu_wait_fences *wait,
1181 struct drm_amdgpu_fence *fences)
1182{
1183 uint32_t fence_count = wait->in.fence_count;
1184 unsigned int i;
1185 long r = 1;
1186
1187 for (i = 0; i < fence_count; i++) {
1188 struct dma_fence *fence;
1189 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1190
1191 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1192 if (IS_ERR(fence))
1193 return PTR_ERR(fence);
1194 else if (!fence)
1195 continue;
1196
1197 r = dma_fence_wait_timeout(fence, true, timeout);
1198 if (r < 0)
1199 return r;
1200
1201 if (r == 0)
1202 break;
1203 }
1204
1205 memset(wait, 0, sizeof(*wait));
1206 wait->out.status = (r > 0);
1207
1208 return 0;
1209}
1210
1211/**
1212 * amdgpu_cs_wait_any_fence - wait on any fence to signal
1213 *
1214 * @adev: amdgpu device
1215 * @filp: file private
1216 * @wait: wait parameters
1217 * @fences: array of drm_amdgpu_fence
1218 */
1219static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1220 struct drm_file *filp,
1221 union drm_amdgpu_wait_fences *wait,
1222 struct drm_amdgpu_fence *fences)
1223{
1224 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1225 uint32_t fence_count = wait->in.fence_count;
1226 uint32_t first = ~0;
1227 struct dma_fence **array;
1228 unsigned int i;
1229 long r;
1230
1231 /* Prepare the fence array */
1232 array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1233
1234 if (array == NULL)
1235 return -ENOMEM;
1236
1237 for (i = 0; i < fence_count; i++) {
1238 struct dma_fence *fence;
1239
1240 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1241 if (IS_ERR(fence)) {
1242 r = PTR_ERR(fence);
1243 goto err_free_fence_array;
1244 } else if (fence) {
1245 array[i] = fence;
1246 } else { /* NULL, the fence has been already signaled */
1247 r = 1;
1248 goto out;
1249 }
1250 }
1251
1252 r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1253 &first);
1254 if (r < 0)
1255 goto err_free_fence_array;
1256
1257out:
1258 memset(wait, 0, sizeof(*wait));
1259 wait->out.status = (r > 0);
1260 wait->out.first_signaled = first;
1261 /* set return value 0 to indicate success */
1262 r = 0;
1263
1264err_free_fence_array:
1265 for (i = 0; i < fence_count; i++)
1266 dma_fence_put(array[i]);
1267 kfree(array);
1268
1269 return r;
1270}
1271
1272/**
1273 * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1274 *
1275 * @dev: drm device
1276 * @data: data from userspace
1277 * @filp: file private
1278 */
1279int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1280 struct drm_file *filp)
1281{
1282 struct amdgpu_device *adev = dev->dev_private;
1283 union drm_amdgpu_wait_fences *wait = data;
1284 uint32_t fence_count = wait->in.fence_count;
1285 struct drm_amdgpu_fence *fences_user;
1286 struct drm_amdgpu_fence *fences;
1287 int r;
1288
1289 /* Get the fences from userspace */
1290 fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1291 GFP_KERNEL);
1292 if (fences == NULL)
1293 return -ENOMEM;
1294
1295 fences_user = (void __user *)(unsigned long)(wait->in.fences);
1296 if (copy_from_user(fences, fences_user,
1297 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1298 r = -EFAULT;
1299 goto err_free_fences;
1300 }
1301
1302 if (wait->in.wait_all)
1303 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1304 else
1305 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1306
1307err_free_fences:
1308 kfree(fences);
1309
1310 return r;
1311}
1312
1313/**
1314 * amdgpu_cs_find_bo_va - find bo_va for VM address
1315 *
1316 * @parser: command submission parser context
1317 * @addr: VM address
1318 * @bo: resulting BO of the mapping found
1319 *
1320 * Search the buffer objects in the command submission context for a certain
1321 * virtual memory address. Returns allocation structure when found, NULL
1322 * otherwise.
1323 */
1324struct amdgpu_bo_va_mapping *
1325amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1326 uint64_t addr, struct amdgpu_bo **bo)
1327{
1328 struct amdgpu_bo_va_mapping *mapping;
1329 unsigned i;
1330
1331 if (!parser->bo_list)
1332 return NULL;
1333
1334 addr /= AMDGPU_GPU_PAGE_SIZE;
1335
1336 for (i = 0; i < parser->bo_list->num_entries; i++) {
1337 struct amdgpu_bo_list_entry *lobj;
1338
1339 lobj = &parser->bo_list->array[i];
1340 if (!lobj->bo_va)
1341 continue;
1342
1343 list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
1344 if (mapping->it.start > addr ||
1345 addr > mapping->it.last)
1346 continue;
1347
1348 *bo = lobj->bo_va->bo;
1349 return mapping;
1350 }
1351
1352 list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
1353 if (mapping->it.start > addr ||
1354 addr > mapping->it.last)
1355 continue;
1356
1357 *bo = lobj->bo_va->bo;
1358 return mapping;
1359 }
1360 }
1361
1362 return NULL;
1363}
1364
1365/**
1366 * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM
1367 *
1368 * @parser: command submission parser context
1369 *
1370 * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM.
1371 */
1372int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser)
1373{
1374 unsigned i;
1375 int r;
1376
1377 if (!parser->bo_list)
1378 return 0;
1379
1380 for (i = 0; i < parser->bo_list->num_entries; i++) {
1381 struct amdgpu_bo *bo = parser->bo_list->array[i].robj;
1382
1383 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
1384 if (unlikely(r))
1385 return r;
1386
1387 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
1388 continue;
1389
1390 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1391 amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains);
1392 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
1393 if (unlikely(r))
1394 return r;
1395 }
1396
1397 return 0;
1398}