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1// SPDX-License-Identifier: GPL-2.0
2
3#include "dt-bindings/clock/bcm3368-clock.h"
4
5/ {
6 #address-cells = <1>;
7 #size-cells = <1>;
8 compatible = "brcm,bcm3368";
9
10 cpus {
11 #address-cells = <1>;
12 #size-cells = <0>;
13
14 mips-hpt-frequency = <150000000>;
15
16 cpu@0 {
17 compatible = "brcm,bmips4350";
18 device_type = "cpu";
19 reg = <0>;
20 };
21
22 cpu@1 {
23 compatible = "brcm,bmips4350";
24 device_type = "cpu";
25 reg = <1>;
26 };
27 };
28
29 clocks {
30 periph_clk: periph-clk {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <50000000>;
34 };
35 };
36
37 aliases {
38 serial0 = &uart0;
39 serial1 = &uart1;
40 };
41
42 cpu_intc: interrupt-controller {
43 #address-cells = <0>;
44 compatible = "mti,cpu-interrupt-controller";
45
46 interrupt-controller;
47 #interrupt-cells = <1>;
48 };
49
50 ubus {
51 #address-cells = <1>;
52 #size-cells = <1>;
53
54 compatible = "simple-bus";
55 ranges;
56
57 clkctl: clock-controller@fff8c004 {
58 compatible = "brcm,bcm3368-clocks";
59 reg = <0xfff8c004 0x4>;
60 #clock-cells = <1>;
61 };
62
63 periph_cntl: syscon@fff8c008 {
64 compatible = "syscon";
65 reg = <0xfff8c008 0x4>;
66 native-endian;
67 };
68
69 reboot: syscon-reboot@fff8c008 {
70 compatible = "syscon-reboot";
71 regmap = <&periph_cntl>;
72 offset = <0x0>;
73 mask = <0x1>;
74 };
75
76 periph_intc: interrupt-controller@fff8c00c {
77 compatible = "brcm,bcm6345-l1-intc";
78 reg = <0xfff8c00c 0x8>;
79
80 interrupt-controller;
81 #interrupt-cells = <1>;
82
83 interrupt-parent = <&cpu_intc>;
84 interrupts = <2>;
85 };
86
87 uart0: serial@fff8c100 {
88 compatible = "brcm,bcm6345-uart";
89 reg = <0xfff8c100 0x18>;
90
91 interrupt-parent = <&periph_intc>;
92 interrupts = <2>;
93
94 clocks = <&periph_clk>;
95 clock-names = "refclk";
96
97 status = "disabled";
98 };
99
100 uart1: serial@fff8c120 {
101 compatible = "brcm,bcm6345-uart";
102 reg = <0xfff8c120 0x18>;
103
104 interrupt-parent = <&periph_intc>;
105 interrupts = <3>;
106
107 clocks = <&periph_clk>;
108 clock-names = "refclk";
109
110 status = "disabled";
111 };
112 };
113};
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm3368";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 mips-hpt-frequency = <150000000>;
11
12 cpu@0 {
13 compatible = "brcm,bmips4350";
14 device_type = "cpu";
15 reg = <0>;
16 };
17
18 cpu@1 {
19 compatible = "brcm,bmips4350";
20 device_type = "cpu";
21 reg = <1>;
22 };
23 };
24
25 clocks {
26 periph_clk: periph-clk {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <50000000>;
30 };
31 };
32
33 aliases {
34 serial0 = &uart0;
35 serial1 = &uart1;
36 };
37
38 cpu_intc: interrupt-controller {
39 #address-cells = <0>;
40 compatible = "mti,cpu-interrupt-controller";
41
42 interrupt-controller;
43 #interrupt-cells = <1>;
44 };
45
46 ubus {
47 #address-cells = <1>;
48 #size-cells = <1>;
49
50 compatible = "simple-bus";
51 ranges;
52
53 periph_cntl: syscon@fff8c000 {
54 compatible = "syscon";
55 reg = <0xfff8c000 0xc>;
56 native-endian;
57 };
58
59 reboot: syscon-reboot@fff8c008 {
60 compatible = "syscon-reboot";
61 regmap = <&periph_cntl>;
62 offset = <0x8>;
63 mask = <0x1>;
64 };
65
66 periph_intc: interrupt-controller@fff8c00c {
67 compatible = "brcm,bcm6345-l1-intc";
68 reg = <0xfff8c00c 0x8>;
69
70 interrupt-controller;
71 #interrupt-cells = <1>;
72
73 interrupt-parent = <&cpu_intc>;
74 interrupts = <2>;
75 };
76
77 uart0: serial@fff8c100 {
78 compatible = "brcm,bcm6345-uart";
79 reg = <0xfff8c100 0x18>;
80
81 interrupt-parent = <&periph_intc>;
82 interrupts = <2>;
83
84 clocks = <&periph_clk>;
85
86 status = "disabled";
87 };
88
89 uart1: serial@fff8c120 {
90 compatible = "brcm,bcm6345-uart";
91 reg = <0xfff8c120 0x18>;
92
93 interrupt-parent = <&periph_intc>;
94 interrupts = <3>;
95
96 clocks = <&periph_clk>;
97
98 status = "disabled";
99 };
100 };
101};