Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for OMAP4 clock data
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */
7&cm1_clocks {
8 extalt_clkin_ck: extalt_clkin_ck {
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
13 };
14
15 pad_clks_src_ck: pad_clks_src_ck {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
20 };
21
22 pad_clks_ck: pad_clks_ck@108 {
23 #clock-cells = <0>;
24 compatible = "ti,gate-clock";
25 clock-output-names = "pad_clks_ck";
26 clocks = <&pad_clks_src_ck>;
27 ti,bit-shift = <8>;
28 reg = <0x0108>;
29 };
30
31 pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
32 #clock-cells = <0>;
33 compatible = "fixed-clock";
34 clock-output-names = "pad_slimbus_core_clks_ck";
35 clock-frequency = <12000000>;
36 };
37
38 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
39 #clock-cells = <0>;
40 compatible = "fixed-clock";
41 clock-output-names = "secure_32k_clk_src_ck";
42 clock-frequency = <32768>;
43 };
44
45 slimbus_src_clk: slimbus_src_clk {
46 #clock-cells = <0>;
47 compatible = "fixed-clock";
48 clock-output-names = "slimbus_src_clk";
49 clock-frequency = <12000000>;
50 };
51
52 slimbus_clk: slimbus_clk@108 {
53 #clock-cells = <0>;
54 compatible = "ti,gate-clock";
55 clock-output-names = "slimbus_clk";
56 clocks = <&slimbus_src_clk>;
57 ti,bit-shift = <10>;
58 reg = <0x0108>;
59 };
60
61 sys_32k_ck: sys_32k_ck {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 clock-output-names = "sys_32k_ck";
65 clock-frequency = <32768>;
66 };
67
68 virt_12000000_ck: virt_12000000_ck {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-output-names = "virt_12000000_ck";
72 clock-frequency = <12000000>;
73 };
74
75 virt_13000000_ck: virt_13000000_ck {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-output-names = "virt_13000000_ck";
79 clock-frequency = <13000000>;
80 };
81
82 virt_16800000_ck: virt_16800000_ck {
83 #clock-cells = <0>;
84 compatible = "fixed-clock";
85 clock-output-names = "virt_16800000_ck";
86 clock-frequency = <16800000>;
87 };
88
89 virt_19200000_ck: virt_19200000_ck {
90 #clock-cells = <0>;
91 compatible = "fixed-clock";
92 clock-output-names = "virt_19200000_ck";
93 clock-frequency = <19200000>;
94 };
95
96 virt_26000000_ck: virt_26000000_ck {
97 #clock-cells = <0>;
98 compatible = "fixed-clock";
99 clock-output-names = "virt_26000000_ck";
100 clock-frequency = <26000000>;
101 };
102
103 virt_27000000_ck: virt_27000000_ck {
104 #clock-cells = <0>;
105 compatible = "fixed-clock";
106 clock-output-names = "virt_27000000_ck";
107 clock-frequency = <27000000>;
108 };
109
110 virt_38400000_ck: virt_38400000_ck {
111 #clock-cells = <0>;
112 compatible = "fixed-clock";
113 clock-output-names = "virt_38400000_ck";
114 clock-frequency = <38400000>;
115 };
116
117 tie_low_clock_ck: tie_low_clock_ck {
118 #clock-cells = <0>;
119 compatible = "fixed-clock";
120 clock-output-names = "tie_low_clock_ck";
121 clock-frequency = <0>;
122 };
123
124 utmi_phy_clkout_ck: utmi_phy_clkout_ck {
125 #clock-cells = <0>;
126 compatible = "fixed-clock";
127 clock-output-names = "utmi_phy_clkout_ck";
128 clock-frequency = <60000000>;
129 };
130
131 xclk60mhsp1_ck: xclk60mhsp1_ck {
132 #clock-cells = <0>;
133 compatible = "fixed-clock";
134 clock-output-names = "xclk60mhsp1_ck";
135 clock-frequency = <60000000>;
136 };
137
138 xclk60mhsp2_ck: xclk60mhsp2_ck {
139 #clock-cells = <0>;
140 compatible = "fixed-clock";
141 clock-output-names = "xclk60mhsp2_ck";
142 clock-frequency = <60000000>;
143 };
144
145 xclk60motg_ck: xclk60motg_ck {
146 #clock-cells = <0>;
147 compatible = "fixed-clock";
148 clock-output-names = "xclk60motg_ck";
149 clock-frequency = <60000000>;
150 };
151
152 dpll_abe_ck: dpll_abe_ck@1e0 {
153 #clock-cells = <0>;
154 compatible = "ti,omap4-dpll-m4xen-clock";
155 clock-output-names = "dpll_abe_ck";
156 clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
157 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
158 };
159
160 dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
161 #clock-cells = <0>;
162 compatible = "ti,omap4-dpll-x2-clock";
163 clock-output-names = "dpll_abe_x2_ck";
164 clocks = <&dpll_abe_ck>;
165 reg = <0x01f0>;
166 };
167
168 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
169 #clock-cells = <0>;
170 compatible = "ti,divider-clock";
171 clock-output-names = "dpll_abe_m2x2_ck";
172 clocks = <&dpll_abe_x2_ck>;
173 ti,max-div = <31>;
174 ti,autoidle-shift = <8>;
175 reg = <0x01f0>;
176 ti,index-starts-at-one;
177 ti,invert-autoidle-bit;
178 };
179
180 abe_24m_fclk: abe_24m_fclk {
181 #clock-cells = <0>;
182 compatible = "fixed-factor-clock";
183 clock-output-names = "abe_24m_fclk";
184 clocks = <&dpll_abe_m2x2_ck>;
185 clock-mult = <1>;
186 clock-div = <8>;
187 };
188
189 abe_clk: abe_clk@108 {
190 #clock-cells = <0>;
191 compatible = "ti,divider-clock";
192 clock-output-names = "abe_clk";
193 clocks = <&dpll_abe_m2x2_ck>;
194 ti,max-div = <4>;
195 reg = <0x0108>;
196 ti,index-power-of-two;
197 };
198
199
200 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
201 #clock-cells = <0>;
202 compatible = "ti,divider-clock";
203 clock-output-names = "dpll_abe_m3x2_ck";
204 clocks = <&dpll_abe_x2_ck>;
205 ti,max-div = <31>;
206 ti,autoidle-shift = <8>;
207 reg = <0x01f4>;
208 ti,index-starts-at-one;
209 ti,invert-autoidle-bit;
210 };
211
212 core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
213 #clock-cells = <0>;
214 compatible = "ti,mux-clock";
215 clock-output-names = "core_hsd_byp_clk_mux_ck";
216 clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
217 ti,bit-shift = <23>;
218 reg = <0x012c>;
219 };
220
221 dpll_core_ck: dpll_core_ck@120 {
222 #clock-cells = <0>;
223 compatible = "ti,omap4-dpll-core-clock";
224 clock-output-names = "dpll_core_ck";
225 clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
226 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
227 };
228
229 dpll_core_x2_ck: dpll_core_x2_ck {
230 #clock-cells = <0>;
231 compatible = "ti,omap4-dpll-x2-clock";
232 clock-output-names = "dpll_core_x2_ck";
233 clocks = <&dpll_core_ck>;
234 };
235
236 dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
237 #clock-cells = <0>;
238 compatible = "ti,divider-clock";
239 clock-output-names = "dpll_core_m6x2_ck";
240 clocks = <&dpll_core_x2_ck>;
241 ti,max-div = <31>;
242 ti,autoidle-shift = <8>;
243 reg = <0x0140>;
244 ti,index-starts-at-one;
245 ti,invert-autoidle-bit;
246 };
247
248 dpll_core_m2_ck: dpll_core_m2_ck@130 {
249 #clock-cells = <0>;
250 compatible = "ti,divider-clock";
251 clock-output-names = "dpll_core_m2_ck";
252 clocks = <&dpll_core_ck>;
253 ti,max-div = <31>;
254 ti,autoidle-shift = <8>;
255 reg = <0x0130>;
256 ti,index-starts-at-one;
257 ti,invert-autoidle-bit;
258 };
259
260 ddrphy_ck: ddrphy_ck {
261 #clock-cells = <0>;
262 compatible = "fixed-factor-clock";
263 clock-output-names = "ddrphy_ck";
264 clocks = <&dpll_core_m2_ck>;
265 clock-mult = <1>;
266 clock-div = <2>;
267 };
268
269 dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
270 #clock-cells = <0>;
271 compatible = "ti,divider-clock";
272 clock-output-names = "dpll_core_m5x2_ck";
273 clocks = <&dpll_core_x2_ck>;
274 ti,max-div = <31>;
275 ti,autoidle-shift = <8>;
276 reg = <0x013c>;
277 ti,index-starts-at-one;
278 ti,invert-autoidle-bit;
279 };
280
281 div_core_ck: div_core_ck@100 {
282 #clock-cells = <0>;
283 compatible = "ti,divider-clock";
284 clock-output-names = "div_core_ck";
285 clocks = <&dpll_core_m5x2_ck>;
286 reg = <0x0100>;
287 ti,max-div = <2>;
288 };
289
290 div_iva_hs_clk: div_iva_hs_clk@1dc {
291 #clock-cells = <0>;
292 compatible = "ti,divider-clock";
293 clock-output-names = "div_iva_hs_clk";
294 clocks = <&dpll_core_m5x2_ck>;
295 ti,max-div = <4>;
296 reg = <0x01dc>;
297 ti,index-power-of-two;
298 };
299
300 div_mpu_hs_clk: div_mpu_hs_clk@19c {
301 #clock-cells = <0>;
302 compatible = "ti,divider-clock";
303 clock-output-names = "div_mpu_hs_clk";
304 clocks = <&dpll_core_m5x2_ck>;
305 ti,max-div = <4>;
306 reg = <0x019c>;
307 ti,index-power-of-two;
308 };
309
310 dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
311 #clock-cells = <0>;
312 compatible = "ti,divider-clock";
313 clock-output-names = "dpll_core_m4x2_ck";
314 clocks = <&dpll_core_x2_ck>;
315 ti,max-div = <31>;
316 ti,autoidle-shift = <8>;
317 reg = <0x0138>;
318 ti,index-starts-at-one;
319 ti,invert-autoidle-bit;
320 };
321
322 dll_clk_div_ck: dll_clk_div_ck {
323 #clock-cells = <0>;
324 compatible = "fixed-factor-clock";
325 clock-output-names = "dll_clk_div_ck";
326 clocks = <&dpll_core_m4x2_ck>;
327 clock-mult = <1>;
328 clock-div = <2>;
329 };
330
331 dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
332 #clock-cells = <0>;
333 compatible = "ti,divider-clock";
334 clock-output-names = "dpll_abe_m2_ck";
335 clocks = <&dpll_abe_ck>;
336 ti,max-div = <31>;
337 reg = <0x01f0>;
338 ti,index-starts-at-one;
339 };
340
341 dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
342 #clock-cells = <0>;
343 compatible = "ti,composite-no-wait-gate-clock";
344 clock-output-names = "dpll_core_m3x2_gate_ck";
345 clocks = <&dpll_core_x2_ck>;
346 ti,bit-shift = <8>;
347 reg = <0x0134>;
348 };
349
350 dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
351 #clock-cells = <0>;
352 compatible = "ti,composite-divider-clock";
353 clock-output-names = "dpll_core_m3x2_div_ck";
354 clocks = <&dpll_core_x2_ck>;
355 ti,max-div = <31>;
356 reg = <0x0134>;
357 ti,index-starts-at-one;
358 };
359
360 dpll_core_m3x2_ck: dpll_core_m3x2_ck {
361 #clock-cells = <0>;
362 compatible = "ti,composite-clock";
363 clock-output-names = "dpll_core_m3x2_ck";
364 clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
365 };
366
367 dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
368 #clock-cells = <0>;
369 compatible = "ti,divider-clock";
370 clock-output-names = "dpll_core_m7x2_ck";
371 clocks = <&dpll_core_x2_ck>;
372 ti,max-div = <31>;
373 ti,autoidle-shift = <8>;
374 reg = <0x0144>;
375 ti,index-starts-at-one;
376 ti,invert-autoidle-bit;
377 };
378
379 iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
380 #clock-cells = <0>;
381 compatible = "ti,mux-clock";
382 clock-output-names = "iva_hsd_byp_clk_mux_ck";
383 clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
384 ti,bit-shift = <23>;
385 reg = <0x01ac>;
386 };
387
388 dpll_iva_ck: dpll_iva_ck@1a0 {
389 #clock-cells = <0>;
390 compatible = "ti,omap4-dpll-clock";
391 clock-output-names = "dpll_iva_ck";
392 clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
393 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
394 assigned-clocks = <&dpll_iva_ck>;
395 assigned-clock-rates = <931200000>;
396 };
397
398 dpll_iva_x2_ck: dpll_iva_x2_ck {
399 #clock-cells = <0>;
400 compatible = "ti,omap4-dpll-x2-clock";
401 clock-output-names = "dpll_iva_x2_ck";
402 clocks = <&dpll_iva_ck>;
403 };
404
405 dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
406 #clock-cells = <0>;
407 compatible = "ti,divider-clock";
408 clock-output-names = "dpll_iva_m4x2_ck";
409 clocks = <&dpll_iva_x2_ck>;
410 ti,max-div = <31>;
411 ti,autoidle-shift = <8>;
412 reg = <0x01b8>;
413 ti,index-starts-at-one;
414 ti,invert-autoidle-bit;
415 assigned-clocks = <&dpll_iva_m4x2_ck>;
416 assigned-clock-rates = <465600000>;
417 };
418
419 dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
420 #clock-cells = <0>;
421 compatible = "ti,divider-clock";
422 clock-output-names = "dpll_iva_m5x2_ck";
423 clocks = <&dpll_iva_x2_ck>;
424 ti,max-div = <31>;
425 ti,autoidle-shift = <8>;
426 reg = <0x01bc>;
427 ti,index-starts-at-one;
428 ti,invert-autoidle-bit;
429 assigned-clocks = <&dpll_iva_m5x2_ck>;
430 assigned-clock-rates = <266100000>;
431 };
432
433 dpll_mpu_ck: dpll_mpu_ck@160 {
434 #clock-cells = <0>;
435 compatible = "ti,omap4-dpll-clock";
436 clock-output-names = "dpll_mpu_ck";
437 clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
438 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
439 };
440
441 dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
442 #clock-cells = <0>;
443 compatible = "ti,divider-clock";
444 clock-output-names = "dpll_mpu_m2_ck";
445 clocks = <&dpll_mpu_ck>;
446 ti,max-div = <31>;
447 ti,autoidle-shift = <8>;
448 reg = <0x0170>;
449 ti,index-starts-at-one;
450 ti,invert-autoidle-bit;
451 };
452
453 per_hs_clk_div_ck: per_hs_clk_div_ck {
454 #clock-cells = <0>;
455 compatible = "fixed-factor-clock";
456 clock-output-names = "per_hs_clk_div_ck";
457 clocks = <&dpll_abe_m3x2_ck>;
458 clock-mult = <1>;
459 clock-div = <2>;
460 };
461
462 usb_hs_clk_div_ck: usb_hs_clk_div_ck {
463 #clock-cells = <0>;
464 compatible = "fixed-factor-clock";
465 clock-output-names = "usb_hs_clk_div_ck";
466 clocks = <&dpll_abe_m3x2_ck>;
467 clock-mult = <1>;
468 clock-div = <3>;
469 };
470
471 l3_div_ck: l3_div_ck@100 {
472 #clock-cells = <0>;
473 compatible = "ti,divider-clock";
474 clock-output-names = "l3_div_ck";
475 clocks = <&div_core_ck>;
476 ti,bit-shift = <4>;
477 ti,max-div = <2>;
478 reg = <0x0100>;
479 };
480
481 l4_div_ck: l4_div_ck@100 {
482 #clock-cells = <0>;
483 compatible = "ti,divider-clock";
484 clock-output-names = "l4_div_ck";
485 clocks = <&l3_div_ck>;
486 ti,bit-shift = <8>;
487 ti,max-div = <2>;
488 reg = <0x0100>;
489 };
490
491 lp_clk_div_ck: lp_clk_div_ck {
492 #clock-cells = <0>;
493 compatible = "fixed-factor-clock";
494 clock-output-names = "lp_clk_div_ck";
495 clocks = <&dpll_abe_m2x2_ck>;
496 clock-mult = <1>;
497 clock-div = <16>;
498 };
499
500 mpu_periphclk: mpu_periphclk {
501 #clock-cells = <0>;
502 compatible = "fixed-factor-clock";
503 clock-output-names = "mpu_periphclk";
504 clocks = <&dpll_mpu_ck>;
505 clock-mult = <1>;
506 clock-div = <2>;
507 };
508
509 ocp_abe_iclk: ocp_abe_iclk@528 {
510 #clock-cells = <0>;
511 compatible = "ti,divider-clock";
512 clock-output-names = "ocp_abe_iclk";
513 clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>;
514 ti,bit-shift = <24>;
515 reg = <0x0528>;
516 ti,dividers = <2>, <1>;
517 };
518
519 per_abe_24m_fclk: per_abe_24m_fclk {
520 #clock-cells = <0>;
521 compatible = "fixed-factor-clock";
522 clock-output-names = "per_abe_24m_fclk";
523 clocks = <&dpll_abe_m2_ck>;
524 clock-mult = <1>;
525 clock-div = <4>;
526 };
527
528 dummy_ck: dummy_ck {
529 #clock-cells = <0>;
530 compatible = "fixed-clock";
531 clock-output-names = "dummy_ck";
532 clock-frequency = <0>;
533 };
534};
535
536&prm_clocks {
537 sys_clkin_ck: sys_clkin_ck@110 {
538 #clock-cells = <0>;
539 compatible = "ti,mux-clock";
540 clock-output-names = "sys_clkin_ck";
541 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
542 reg = <0x0110>;
543 ti,index-starts-at-one;
544 };
545
546 abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
547 #clock-cells = <0>;
548 compatible = "ti,mux-clock";
549 clock-output-names = "abe_dpll_bypass_clk_mux_ck";
550 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
551 ti,bit-shift = <24>;
552 reg = <0x0108>;
553 };
554
555 abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
556 #clock-cells = <0>;
557 compatible = "ti,mux-clock";
558 clock-output-names = "abe_dpll_refclk_mux_ck";
559 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
560 reg = <0x010c>;
561 };
562
563 dbgclk_mux_ck: dbgclk_mux_ck {
564 #clock-cells = <0>;
565 compatible = "fixed-factor-clock";
566 clock-output-names = "dbgclk_mux_ck";
567 clocks = <&sys_clkin_ck>;
568 clock-mult = <1>;
569 clock-div = <1>;
570 };
571
572 l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
573 #clock-cells = <0>;
574 compatible = "ti,mux-clock";
575 clock-output-names = "l4_wkup_clk_mux_ck";
576 clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
577 reg = <0x0108>;
578 };
579
580 syc_clk_div_ck: syc_clk_div_ck@100 {
581 #clock-cells = <0>;
582 compatible = "ti,divider-clock";
583 clock-output-names = "syc_clk_div_ck";
584 clocks = <&sys_clkin_ck>;
585 reg = <0x0100>;
586 ti,max-div = <2>;
587 };
588
589 usim_ck: usim_ck@1858 {
590 #clock-cells = <0>;
591 compatible = "ti,divider-clock";
592 clock-output-names = "usim_ck";
593 clocks = <&dpll_per_m4x2_ck>;
594 ti,bit-shift = <24>;
595 reg = <0x1858>;
596 ti,dividers = <14>, <18>;
597 };
598
599 usim_fclk: usim_fclk@1858 {
600 #clock-cells = <0>;
601 compatible = "ti,gate-clock";
602 clock-output-names = "usim_fclk";
603 clocks = <&usim_ck>;
604 ti,bit-shift = <8>;
605 reg = <0x1858>;
606 };
607
608 trace_clk_div_ck: trace_clk_div_ck {
609 #clock-cells = <0>;
610 compatible = "ti,clkdm-gate-clock";
611 clock-output-names = "trace_clk_div_ck";
612 clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>;
613 };
614};
615
616&prm_clockdomains {
617 emu_sys_clkdm: emu_sys_clkdm {
618 compatible = "ti,clockdomain";
619 clock-output-names = "emu_sys_clkdm";
620 clocks = <&trace_clk_div_ck>;
621 };
622};
623
624&cm2_clocks {
625 per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
626 #clock-cells = <0>;
627 compatible = "ti,mux-clock";
628 clock-output-names = "per_hsd_byp_clk_mux_ck";
629 clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
630 ti,bit-shift = <23>;
631 reg = <0x014c>;
632 };
633
634 dpll_per_ck: dpll_per_ck@140 {
635 #clock-cells = <0>;
636 compatible = "ti,omap4-dpll-clock";
637 clock-output-names = "dpll_per_ck";
638 clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
639 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
640 };
641
642 dpll_per_m2_ck: dpll_per_m2_ck@150 {
643 #clock-cells = <0>;
644 compatible = "ti,divider-clock";
645 clock-output-names = "dpll_per_m2_ck";
646 clocks = <&dpll_per_ck>;
647 ti,max-div = <31>;
648 reg = <0x0150>;
649 ti,index-starts-at-one;
650 };
651
652 dpll_per_x2_ck: dpll_per_x2_ck@150 {
653 #clock-cells = <0>;
654 compatible = "ti,omap4-dpll-x2-clock";
655 clock-output-names = "dpll_per_x2_ck";
656 clocks = <&dpll_per_ck>;
657 reg = <0x0150>;
658 };
659
660 dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
661 #clock-cells = <0>;
662 compatible = "ti,divider-clock";
663 clock-output-names = "dpll_per_m2x2_ck";
664 clocks = <&dpll_per_x2_ck>;
665 ti,max-div = <31>;
666 ti,autoidle-shift = <8>;
667 reg = <0x0150>;
668 ti,index-starts-at-one;
669 ti,invert-autoidle-bit;
670 };
671
672 dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
673 #clock-cells = <0>;
674 compatible = "ti,composite-no-wait-gate-clock";
675 clock-output-names = "dpll_per_m3x2_gate_ck";
676 clocks = <&dpll_per_x2_ck>;
677 ti,bit-shift = <8>;
678 reg = <0x0154>;
679 };
680
681 dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
682 #clock-cells = <0>;
683 compatible = "ti,composite-divider-clock";
684 clock-output-names = "dpll_per_m3x2_div_ck";
685 clocks = <&dpll_per_x2_ck>;
686 ti,max-div = <31>;
687 reg = <0x0154>;
688 ti,index-starts-at-one;
689 };
690
691 dpll_per_m3x2_ck: dpll_per_m3x2_ck {
692 #clock-cells = <0>;
693 compatible = "ti,composite-clock";
694 clock-output-names = "dpll_per_m3x2_ck";
695 clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
696 };
697
698 dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
699 #clock-cells = <0>;
700 compatible = "ti,divider-clock";
701 clock-output-names = "dpll_per_m4x2_ck";
702 clocks = <&dpll_per_x2_ck>;
703 ti,max-div = <31>;
704 ti,autoidle-shift = <8>;
705 reg = <0x0158>;
706 ti,index-starts-at-one;
707 ti,invert-autoidle-bit;
708 };
709
710 dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
711 #clock-cells = <0>;
712 compatible = "ti,divider-clock";
713 clock-output-names = "dpll_per_m5x2_ck";
714 clocks = <&dpll_per_x2_ck>;
715 ti,max-div = <31>;
716 ti,autoidle-shift = <8>;
717 reg = <0x015c>;
718 ti,index-starts-at-one;
719 ti,invert-autoidle-bit;
720 };
721
722 dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
723 #clock-cells = <0>;
724 compatible = "ti,divider-clock";
725 clock-output-names = "dpll_per_m6x2_ck";
726 clocks = <&dpll_per_x2_ck>;
727 ti,max-div = <31>;
728 ti,autoidle-shift = <8>;
729 reg = <0x0160>;
730 ti,index-starts-at-one;
731 ti,invert-autoidle-bit;
732 };
733
734 dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
735 #clock-cells = <0>;
736 compatible = "ti,divider-clock";
737 clock-output-names = "dpll_per_m7x2_ck";
738 clocks = <&dpll_per_x2_ck>;
739 ti,max-div = <31>;
740 ti,autoidle-shift = <8>;
741 reg = <0x0164>;
742 ti,index-starts-at-one;
743 ti,invert-autoidle-bit;
744 };
745
746 dpll_usb_ck: dpll_usb_ck@180 {
747 #clock-cells = <0>;
748 compatible = "ti,omap4-dpll-j-type-clock";
749 clock-output-names = "dpll_usb_ck";
750 clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
751 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
752 };
753
754 dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
755 #clock-cells = <0>;
756 compatible = "ti,fixed-factor-clock";
757 clock-output-names = "dpll_usb_clkdcoldo_ck";
758 clocks = <&dpll_usb_ck>;
759 ti,clock-div = <1>;
760 ti,autoidle-shift = <8>;
761 reg = <0x01b4>;
762 ti,clock-mult = <1>;
763 ti,invert-autoidle-bit;
764 };
765
766 dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
767 #clock-cells = <0>;
768 compatible = "ti,divider-clock";
769 clock-output-names = "dpll_usb_m2_ck";
770 clocks = <&dpll_usb_ck>;
771 ti,max-div = <127>;
772 ti,autoidle-shift = <8>;
773 reg = <0x0190>;
774 ti,index-starts-at-one;
775 ti,invert-autoidle-bit;
776 };
777
778 ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
779 #clock-cells = <0>;
780 compatible = "ti,mux-clock";
781 clock-output-names = "ducati_clk_mux_ck";
782 clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
783 reg = <0x0100>;
784 };
785
786 func_12m_fclk: func_12m_fclk {
787 #clock-cells = <0>;
788 compatible = "fixed-factor-clock";
789 clock-output-names = "func_12m_fclk";
790 clocks = <&dpll_per_m2x2_ck>;
791 clock-mult = <1>;
792 clock-div = <16>;
793 };
794
795 func_24m_clk: func_24m_clk {
796 #clock-cells = <0>;
797 compatible = "fixed-factor-clock";
798 clock-output-names = "func_24m_clk";
799 clocks = <&dpll_per_m2_ck>;
800 clock-mult = <1>;
801 clock-div = <4>;
802 };
803
804 func_24mc_fclk: func_24mc_fclk {
805 #clock-cells = <0>;
806 compatible = "fixed-factor-clock";
807 clock-output-names = "func_24mc_fclk";
808 clocks = <&dpll_per_m2x2_ck>;
809 clock-mult = <1>;
810 clock-div = <8>;
811 };
812
813 func_48m_fclk: func_48m_fclk@108 {
814 #clock-cells = <0>;
815 compatible = "ti,divider-clock";
816 clock-output-names = "func_48m_fclk";
817 clocks = <&dpll_per_m2x2_ck>;
818 reg = <0x0108>;
819 ti,dividers = <4>, <8>;
820 };
821
822 func_48mc_fclk: func_48mc_fclk {
823 #clock-cells = <0>;
824 compatible = "fixed-factor-clock";
825 clock-output-names = "func_48mc_fclk";
826 clocks = <&dpll_per_m2x2_ck>;
827 clock-mult = <1>;
828 clock-div = <4>;
829 };
830
831 func_64m_fclk: func_64m_fclk@108 {
832 #clock-cells = <0>;
833 compatible = "ti,divider-clock";
834 clock-output-names = "func_64m_fclk";
835 clocks = <&dpll_per_m4x2_ck>;
836 reg = <0x0108>;
837 ti,dividers = <2>, <4>;
838 };
839
840 func_96m_fclk: func_96m_fclk@108 {
841 #clock-cells = <0>;
842 compatible = "ti,divider-clock";
843 clock-output-names = "func_96m_fclk";
844 clocks = <&dpll_per_m2x2_ck>;
845 reg = <0x0108>;
846 ti,dividers = <2>, <4>;
847 };
848
849 init_60m_fclk: init_60m_fclk@104 {
850 #clock-cells = <0>;
851 compatible = "ti,divider-clock";
852 clock-output-names = "init_60m_fclk";
853 clocks = <&dpll_usb_m2_ck>;
854 reg = <0x0104>;
855 ti,dividers = <1>, <8>;
856 };
857
858 per_abe_nc_fclk: per_abe_nc_fclk@108 {
859 #clock-cells = <0>;
860 compatible = "ti,divider-clock";
861 clock-output-names = "per_abe_nc_fclk";
862 clocks = <&dpll_abe_m2_ck>;
863 reg = <0x0108>;
864 ti,max-div = <2>;
865 };
866
867 usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
868 #clock-cells = <0>;
869 compatible = "ti,gate-clock";
870 clock-output-names = "usb_phy_cm_clk32k";
871 clocks = <&sys_32k_ck>;
872 ti,bit-shift = <8>;
873 reg = <0x0640>;
874 };
875};
876
877&cm2_clockdomains {
878 l3_init_clkdm: l3_init_clkdm {
879 compatible = "ti,clockdomain";
880 clock-output-names = "l3_init_clkdm";
881 clocks = <&dpll_usb_ck>;
882 };
883};
884
885&scrm_clocks {
886 auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
887 #clock-cells = <0>;
888 compatible = "ti,composite-no-wait-gate-clock";
889 clock-output-names = "auxclk0_src_gate_ck";
890 clocks = <&dpll_core_m3x2_ck>;
891 ti,bit-shift = <8>;
892 reg = <0x0310>;
893 };
894
895 auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
896 #clock-cells = <0>;
897 compatible = "ti,composite-mux-clock";
898 clock-output-names = "auxclk0_src_mux_ck";
899 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
900 ti,bit-shift = <1>;
901 reg = <0x0310>;
902 };
903
904 auxclk0_src_ck: auxclk0_src_ck {
905 #clock-cells = <0>;
906 compatible = "ti,composite-clock";
907 clock-output-names = "auxclk0_src_ck";
908 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
909 };
910
911 auxclk0_ck: auxclk0_ck@310 {
912 #clock-cells = <0>;
913 compatible = "ti,divider-clock";
914 clock-output-names = "auxclk0_ck";
915 clocks = <&auxclk0_src_ck>;
916 ti,bit-shift = <16>;
917 ti,max-div = <16>;
918 reg = <0x0310>;
919 };
920
921 auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
922 #clock-cells = <0>;
923 compatible = "ti,composite-no-wait-gate-clock";
924 clock-output-names = "auxclk1_src_gate_ck";
925 clocks = <&dpll_core_m3x2_ck>;
926 ti,bit-shift = <8>;
927 reg = <0x0314>;
928 };
929
930 auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
931 #clock-cells = <0>;
932 compatible = "ti,composite-mux-clock";
933 clock-output-names = "auxclk1_src_mux_ck";
934 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
935 ti,bit-shift = <1>;
936 reg = <0x0314>;
937 };
938
939 auxclk1_src_ck: auxclk1_src_ck {
940 #clock-cells = <0>;
941 compatible = "ti,composite-clock";
942 clock-output-names = "auxclk1_src_ck";
943 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
944 };
945
946 auxclk1_ck: auxclk1_ck@314 {
947 #clock-cells = <0>;
948 compatible = "ti,divider-clock";
949 clock-output-names = "auxclk1_ck";
950 clocks = <&auxclk1_src_ck>;
951 ti,bit-shift = <16>;
952 ti,max-div = <16>;
953 reg = <0x0314>;
954 };
955
956 auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
957 #clock-cells = <0>;
958 compatible = "ti,composite-no-wait-gate-clock";
959 clock-output-names = "auxclk2_src_gate_ck";
960 clocks = <&dpll_core_m3x2_ck>;
961 ti,bit-shift = <8>;
962 reg = <0x0318>;
963 };
964
965 auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
966 #clock-cells = <0>;
967 compatible = "ti,composite-mux-clock";
968 clock-output-names = "auxclk2_src_mux_ck";
969 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
970 ti,bit-shift = <1>;
971 reg = <0x0318>;
972 };
973
974 auxclk2_src_ck: auxclk2_src_ck {
975 #clock-cells = <0>;
976 compatible = "ti,composite-clock";
977 clock-output-names = "auxclk2_src_ck";
978 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
979 };
980
981 auxclk2_ck: auxclk2_ck@318 {
982 #clock-cells = <0>;
983 compatible = "ti,divider-clock";
984 clock-output-names = "auxclk2_ck";
985 clocks = <&auxclk2_src_ck>;
986 ti,bit-shift = <16>;
987 ti,max-div = <16>;
988 reg = <0x0318>;
989 };
990
991 auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
992 #clock-cells = <0>;
993 compatible = "ti,composite-no-wait-gate-clock";
994 clock-output-names = "auxclk3_src_gate_ck";
995 clocks = <&dpll_core_m3x2_ck>;
996 ti,bit-shift = <8>;
997 reg = <0x031c>;
998 };
999
1000 auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
1001 #clock-cells = <0>;
1002 compatible = "ti,composite-mux-clock";
1003 clock-output-names = "auxclk3_src_mux_ck";
1004 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1005 ti,bit-shift = <1>;
1006 reg = <0x031c>;
1007 };
1008
1009 auxclk3_src_ck: auxclk3_src_ck {
1010 #clock-cells = <0>;
1011 compatible = "ti,composite-clock";
1012 clock-output-names = "auxclk3_src_ck";
1013 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
1014 };
1015
1016 auxclk3_ck: auxclk3_ck@31c {
1017 #clock-cells = <0>;
1018 compatible = "ti,divider-clock";
1019 clock-output-names = "auxclk3_ck";
1020 clocks = <&auxclk3_src_ck>;
1021 ti,bit-shift = <16>;
1022 ti,max-div = <16>;
1023 reg = <0x031c>;
1024 };
1025
1026 auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
1027 #clock-cells = <0>;
1028 compatible = "ti,composite-no-wait-gate-clock";
1029 clock-output-names = "auxclk4_src_gate_ck";
1030 clocks = <&dpll_core_m3x2_ck>;
1031 ti,bit-shift = <8>;
1032 reg = <0x0320>;
1033 };
1034
1035 auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
1036 #clock-cells = <0>;
1037 compatible = "ti,composite-mux-clock";
1038 clock-output-names = "auxclk4_src_mux_ck";
1039 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1040 ti,bit-shift = <1>;
1041 reg = <0x0320>;
1042 };
1043
1044 auxclk4_src_ck: auxclk4_src_ck {
1045 #clock-cells = <0>;
1046 compatible = "ti,composite-clock";
1047 clock-output-names = "auxclk4_src_ck";
1048 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
1049 };
1050
1051 auxclk4_ck: auxclk4_ck@320 {
1052 #clock-cells = <0>;
1053 compatible = "ti,divider-clock";
1054 clock-output-names = "auxclk4_ck";
1055 clocks = <&auxclk4_src_ck>;
1056 ti,bit-shift = <16>;
1057 ti,max-div = <16>;
1058 reg = <0x0320>;
1059 };
1060
1061 auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
1062 #clock-cells = <0>;
1063 compatible = "ti,composite-no-wait-gate-clock";
1064 clock-output-names = "auxclk5_src_gate_ck";
1065 clocks = <&dpll_core_m3x2_ck>;
1066 ti,bit-shift = <8>;
1067 reg = <0x0324>;
1068 };
1069
1070 auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
1071 #clock-cells = <0>;
1072 compatible = "ti,composite-mux-clock";
1073 clock-output-names = "auxclk5_src_mux_ck";
1074 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1075 ti,bit-shift = <1>;
1076 reg = <0x0324>;
1077 };
1078
1079 auxclk5_src_ck: auxclk5_src_ck {
1080 #clock-cells = <0>;
1081 compatible = "ti,composite-clock";
1082 clock-output-names = "auxclk5_src_ck";
1083 clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
1084 };
1085
1086 auxclk5_ck: auxclk5_ck@324 {
1087 #clock-cells = <0>;
1088 compatible = "ti,divider-clock";
1089 clock-output-names = "auxclk5_ck";
1090 clocks = <&auxclk5_src_ck>;
1091 ti,bit-shift = <16>;
1092 ti,max-div = <16>;
1093 reg = <0x0324>;
1094 };
1095
1096 auxclkreq0_ck: auxclkreq0_ck@210 {
1097 #clock-cells = <0>;
1098 compatible = "ti,mux-clock";
1099 clock-output-names = "auxclkreq0_ck";
1100 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1101 ti,bit-shift = <2>;
1102 reg = <0x0210>;
1103 };
1104
1105 auxclkreq1_ck: auxclkreq1_ck@214 {
1106 #clock-cells = <0>;
1107 compatible = "ti,mux-clock";
1108 clock-output-names = "auxclkreq1_ck";
1109 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1110 ti,bit-shift = <2>;
1111 reg = <0x0214>;
1112 };
1113
1114 auxclkreq2_ck: auxclkreq2_ck@218 {
1115 #clock-cells = <0>;
1116 compatible = "ti,mux-clock";
1117 clock-output-names = "auxclkreq2_ck";
1118 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1119 ti,bit-shift = <2>;
1120 reg = <0x0218>;
1121 };
1122
1123 auxclkreq3_ck: auxclkreq3_ck@21c {
1124 #clock-cells = <0>;
1125 compatible = "ti,mux-clock";
1126 clock-output-names = "auxclkreq3_ck";
1127 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1128 ti,bit-shift = <2>;
1129 reg = <0x021c>;
1130 };
1131
1132 auxclkreq4_ck: auxclkreq4_ck@220 {
1133 #clock-cells = <0>;
1134 compatible = "ti,mux-clock";
1135 clock-output-names = "auxclkreq4_ck";
1136 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1137 ti,bit-shift = <2>;
1138 reg = <0x0220>;
1139 };
1140
1141 auxclkreq5_ck: auxclkreq5_ck@224 {
1142 #clock-cells = <0>;
1143 compatible = "ti,mux-clock";
1144 clock-output-names = "auxclkreq5_ck";
1145 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1146 ti,bit-shift = <2>;
1147 reg = <0x0224>;
1148 };
1149};
1150
1151&cm1 {
1152 mpuss_cm: mpuss_cm@300 {
1153 compatible = "ti,omap4-cm";
1154 clock-output-names = "mpuss_cm";
1155 reg = <0x300 0x100>;
1156 #address-cells = <1>;
1157 #size-cells = <1>;
1158 ranges = <0 0x300 0x100>;
1159
1160 mpuss_clkctrl: clk@20 {
1161 compatible = "ti,clkctrl";
1162 clock-output-names = "mpuss_clkctrl";
1163 reg = <0x20 0x4>;
1164 #clock-cells = <2>;
1165 };
1166 };
1167
1168 tesla_cm: tesla_cm@400 {
1169 compatible = "ti,omap4-cm";
1170 clock-output-names = "tesla_cm";
1171 reg = <0x400 0x100>;
1172 #address-cells = <1>;
1173 #size-cells = <1>;
1174 ranges = <0 0x400 0x100>;
1175
1176 tesla_clkctrl: clk@20 {
1177 compatible = "ti,clkctrl";
1178 clock-output-names = "tesla_clkctrl";
1179 reg = <0x20 0x4>;
1180 #clock-cells = <2>;
1181 };
1182 };
1183
1184 abe_cm: abe_cm@500 {
1185 compatible = "ti,omap4-cm";
1186 clock-output-names = "abe_cm";
1187 reg = <0x500 0x100>;
1188 #address-cells = <1>;
1189 #size-cells = <1>;
1190 ranges = <0 0x500 0x100>;
1191
1192 abe_clkctrl: clk@20 {
1193 compatible = "ti,clkctrl";
1194 clock-output-names = "abe_clkctrl";
1195 reg = <0x20 0x6c>;
1196 #clock-cells = <2>;
1197 };
1198 };
1199
1200};
1201
1202&cm2 {
1203 l4_ao_cm: l4_ao_cm@600 {
1204 compatible = "ti,omap4-cm";
1205 clock-output-names = "l4_ao_cm";
1206 reg = <0x600 0x100>;
1207 #address-cells = <1>;
1208 #size-cells = <1>;
1209 ranges = <0 0x600 0x100>;
1210
1211 l4_ao_clkctrl: clk@20 {
1212 compatible = "ti,clkctrl";
1213 clock-output-names = "l4_ao_clkctrl";
1214 reg = <0x20 0x1c>;
1215 #clock-cells = <2>;
1216 };
1217 };
1218
1219 l3_1_cm: l3_1_cm@700 {
1220 compatible = "ti,omap4-cm";
1221 clock-output-names = "l3_1_cm";
1222 reg = <0x700 0x100>;
1223 #address-cells = <1>;
1224 #size-cells = <1>;
1225 ranges = <0 0x700 0x100>;
1226
1227 l3_1_clkctrl: clk@20 {
1228 compatible = "ti,clkctrl";
1229 clock-output-names = "l3_1_clkctrl";
1230 reg = <0x20 0x4>;
1231 #clock-cells = <2>;
1232 };
1233 };
1234
1235 l3_2_cm: l3_2_cm@800 {
1236 compatible = "ti,omap4-cm";
1237 clock-output-names = "l3_2_cm";
1238 reg = <0x800 0x100>;
1239 #address-cells = <1>;
1240 #size-cells = <1>;
1241 ranges = <0 0x800 0x100>;
1242
1243 l3_2_clkctrl: clk@20 {
1244 compatible = "ti,clkctrl";
1245 clock-output-names = "l3_2_clkctrl";
1246 reg = <0x20 0x14>;
1247 #clock-cells = <2>;
1248 };
1249 };
1250
1251 ducati_cm: ducati_cm@900 {
1252 compatible = "ti,omap4-cm";
1253 clock-output-names = "ducati_cm";
1254 reg = <0x900 0x100>;
1255 #address-cells = <1>;
1256 #size-cells = <1>;
1257 ranges = <0 0x900 0x100>;
1258
1259 ducati_clkctrl: clk@20 {
1260 compatible = "ti,clkctrl";
1261 clock-output-names = "ducati_clkctrl";
1262 reg = <0x20 0x4>;
1263 #clock-cells = <2>;
1264 };
1265 };
1266
1267 l3_dma_cm: l3_dma_cm@a00 {
1268 compatible = "ti,omap4-cm";
1269 clock-output-names = "l3_dma_cm";
1270 reg = <0xa00 0x100>;
1271 #address-cells = <1>;
1272 #size-cells = <1>;
1273 ranges = <0 0xa00 0x100>;
1274
1275 l3_dma_clkctrl: clk@20 {
1276 compatible = "ti,clkctrl";
1277 clock-output-names = "l3_dma_clkctrl";
1278 reg = <0x20 0x4>;
1279 #clock-cells = <2>;
1280 };
1281 };
1282
1283 l3_emif_cm: l3_emif_cm@b00 {
1284 compatible = "ti,omap4-cm";
1285 clock-output-names = "l3_emif_cm";
1286 reg = <0xb00 0x100>;
1287 #address-cells = <1>;
1288 #size-cells = <1>;
1289 ranges = <0 0xb00 0x100>;
1290
1291 l3_emif_clkctrl: clk@20 {
1292 compatible = "ti,clkctrl";
1293 clock-output-names = "l3_emif_clkctrl";
1294 reg = <0x20 0x1c>;
1295 #clock-cells = <2>;
1296 };
1297 };
1298
1299 d2d_cm: d2d_cm@c00 {
1300 compatible = "ti,omap4-cm";
1301 clock-output-names = "d2d_cm";
1302 reg = <0xc00 0x100>;
1303 #address-cells = <1>;
1304 #size-cells = <1>;
1305 ranges = <0 0xc00 0x100>;
1306
1307 d2d_clkctrl: clk@20 {
1308 compatible = "ti,clkctrl";
1309 clock-output-names = "d2d_clkctrl";
1310 reg = <0x20 0x4>;
1311 #clock-cells = <2>;
1312 };
1313 };
1314
1315 l4_cfg_cm: l4_cfg_cm@d00 {
1316 compatible = "ti,omap4-cm";
1317 clock-output-names = "l4_cfg_cm";
1318 reg = <0xd00 0x100>;
1319 #address-cells = <1>;
1320 #size-cells = <1>;
1321 ranges = <0 0xd00 0x100>;
1322
1323 l4_cfg_clkctrl: clk@20 {
1324 compatible = "ti,clkctrl";
1325 clock-output-names = "l4_cfg_clkctrl";
1326 reg = <0x20 0x14>;
1327 #clock-cells = <2>;
1328 };
1329 };
1330
1331 l3_instr_cm: l3_instr_cm@e00 {
1332 compatible = "ti,omap4-cm";
1333 clock-output-names = "l3_instr_cm";
1334 reg = <0xe00 0x100>;
1335 #address-cells = <1>;
1336 #size-cells = <1>;
1337 ranges = <0 0xe00 0x100>;
1338
1339 l3_instr_clkctrl: clk@20 {
1340 compatible = "ti,clkctrl";
1341 clock-output-names = "l3_instr_clkctrl";
1342 reg = <0x20 0x24>;
1343 #clock-cells = <2>;
1344 };
1345 };
1346
1347 ivahd_cm: ivahd_cm@f00 {
1348 compatible = "ti,omap4-cm";
1349 clock-output-names = "ivahd_cm";
1350 reg = <0xf00 0x100>;
1351 #address-cells = <1>;
1352 #size-cells = <1>;
1353 ranges = <0 0xf00 0x100>;
1354
1355 ivahd_clkctrl: clk@20 {
1356 compatible = "ti,clkctrl";
1357 clock-output-names = "ivahd_clkctrl";
1358 reg = <0x20 0xc>;
1359 #clock-cells = <2>;
1360 };
1361 };
1362
1363 iss_cm: iss_cm@1000 {
1364 compatible = "ti,omap4-cm";
1365 clock-output-names = "iss_cm";
1366 reg = <0x1000 0x100>;
1367 #address-cells = <1>;
1368 #size-cells = <1>;
1369 ranges = <0 0x1000 0x100>;
1370
1371 iss_clkctrl: clk@20 {
1372 compatible = "ti,clkctrl";
1373 clock-output-names = "iss_clkctrl";
1374 reg = <0x20 0xc>;
1375 #clock-cells = <2>;
1376 };
1377 };
1378
1379 l3_dss_cm: l3_dss_cm@1100 {
1380 compatible = "ti,omap4-cm";
1381 clock-output-names = "l3_dss_cm";
1382 reg = <0x1100 0x100>;
1383 #address-cells = <1>;
1384 #size-cells = <1>;
1385 ranges = <0 0x1100 0x100>;
1386
1387 l3_dss_clkctrl: clk@20 {
1388 compatible = "ti,clkctrl";
1389 clock-output-names = "l3_dss_clkctrl";
1390 reg = <0x20 0x4>;
1391 #clock-cells = <2>;
1392 };
1393 };
1394
1395 l3_gfx_cm: l3_gfx_cm@1200 {
1396 compatible = "ti,omap4-cm";
1397 clock-output-names = "l3_gfx_cm";
1398 reg = <0x1200 0x100>;
1399 #address-cells = <1>;
1400 #size-cells = <1>;
1401 ranges = <0 0x1200 0x100>;
1402
1403 l3_gfx_clkctrl: clk@20 {
1404 compatible = "ti,clkctrl";
1405 clock-output-names = "l3_gfx_clkctrl";
1406 reg = <0x20 0x4>;
1407 #clock-cells = <2>;
1408 };
1409 };
1410
1411 l3_init_cm: l3_init_cm@1300 {
1412 compatible = "ti,omap4-cm";
1413 clock-output-names = "l3_init_cm";
1414 reg = <0x1300 0x100>;
1415 #address-cells = <1>;
1416 #size-cells = <1>;
1417 ranges = <0 0x1300 0x100>;
1418
1419 l3_init_clkctrl: clk@20 {
1420 compatible = "ti,clkctrl";
1421 clock-output-names = "l3_init_clkctrl";
1422 reg = <0x20 0xc4>;
1423 #clock-cells = <2>;
1424 };
1425 };
1426
1427 l4_per_cm: clock@1400 {
1428 compatible = "ti,omap4-cm";
1429 clock-output-names = "l4_per_cm";
1430 reg = <0x1400 0x200>;
1431 #address-cells = <1>;
1432 #size-cells = <1>;
1433 ranges = <0 0x1400 0x200>;
1434
1435 l4_per_clkctrl: clock@20 {
1436 compatible = "ti,clkctrl";
1437 clock-output-names = "l4_per_clkctrl";
1438 reg = <0x20 0x144>;
1439 #clock-cells = <2>;
1440 };
1441
1442 l4_secure_clkctrl: clock@1a0 {
1443 compatible = "ti,clkctrl";
1444 clock-output-names = "l4_secure_clkctrl";
1445 reg = <0x1a0 0x3c>;
1446 #clock-cells = <2>;
1447 };
1448 };
1449};
1450
1451&prm {
1452 l4_wkup_cm: l4_wkup_cm@1800 {
1453 compatible = "ti,omap4-cm";
1454 clock-output-names = "l4_wkup_cm";
1455 reg = <0x1800 0x100>;
1456 #address-cells = <1>;
1457 #size-cells = <1>;
1458 ranges = <0 0x1800 0x100>;
1459
1460 l4_wkup_clkctrl: clk@20 {
1461 compatible = "ti,clkctrl";
1462 clock-output-names = "l4_wkup_clkctrl";
1463 reg = <0x20 0x5c>;
1464 #clock-cells = <2>;
1465 };
1466 };
1467
1468 emu_sys_cm: emu_sys_cm@1a00 {
1469 compatible = "ti,omap4-cm";
1470 clock-output-names = "emu_sys_cm";
1471 reg = <0x1a00 0x100>;
1472 #address-cells = <1>;
1473 #size-cells = <1>;
1474 ranges = <0 0x1a00 0x100>;
1475
1476 emu_sys_clkctrl: clk@20 {
1477 compatible = "ti,clkctrl";
1478 clock-output-names = "emu_sys_clkctrl";
1479 reg = <0x20 0x4>;
1480 #clock-cells = <2>;
1481 };
1482 };
1483};
1/*
2 * Device Tree Source for OMAP4 clock data
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10&cm1_clocks {
11 extalt_clkin_ck: extalt_clkin_ck {
12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <59000000>;
15 };
16
17 pad_clks_src_ck: pad_clks_src_ck {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <12000000>;
21 };
22
23 pad_clks_ck: pad_clks_ck@108 {
24 #clock-cells = <0>;
25 compatible = "ti,gate-clock";
26 clocks = <&pad_clks_src_ck>;
27 ti,bit-shift = <8>;
28 reg = <0x0108>;
29 };
30
31 pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
32 #clock-cells = <0>;
33 compatible = "fixed-clock";
34 clock-frequency = <12000000>;
35 };
36
37 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
38 #clock-cells = <0>;
39 compatible = "fixed-clock";
40 clock-frequency = <32768>;
41 };
42
43 slimbus_src_clk: slimbus_src_clk {
44 #clock-cells = <0>;
45 compatible = "fixed-clock";
46 clock-frequency = <12000000>;
47 };
48
49 slimbus_clk: slimbus_clk@108 {
50 #clock-cells = <0>;
51 compatible = "ti,gate-clock";
52 clocks = <&slimbus_src_clk>;
53 ti,bit-shift = <10>;
54 reg = <0x0108>;
55 };
56
57 sys_32k_ck: sys_32k_ck {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <32768>;
61 };
62
63 virt_12000000_ck: virt_12000000_ck {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <12000000>;
67 };
68
69 virt_13000000_ck: virt_13000000_ck {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <13000000>;
73 };
74
75 virt_16800000_ck: virt_16800000_ck {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <16800000>;
79 };
80
81 virt_19200000_ck: virt_19200000_ck {
82 #clock-cells = <0>;
83 compatible = "fixed-clock";
84 clock-frequency = <19200000>;
85 };
86
87 virt_26000000_ck: virt_26000000_ck {
88 #clock-cells = <0>;
89 compatible = "fixed-clock";
90 clock-frequency = <26000000>;
91 };
92
93 virt_27000000_ck: virt_27000000_ck {
94 #clock-cells = <0>;
95 compatible = "fixed-clock";
96 clock-frequency = <27000000>;
97 };
98
99 virt_38400000_ck: virt_38400000_ck {
100 #clock-cells = <0>;
101 compatible = "fixed-clock";
102 clock-frequency = <38400000>;
103 };
104
105 tie_low_clock_ck: tie_low_clock_ck {
106 #clock-cells = <0>;
107 compatible = "fixed-clock";
108 clock-frequency = <0>;
109 };
110
111 utmi_phy_clkout_ck: utmi_phy_clkout_ck {
112 #clock-cells = <0>;
113 compatible = "fixed-clock";
114 clock-frequency = <60000000>;
115 };
116
117 xclk60mhsp1_ck: xclk60mhsp1_ck {
118 #clock-cells = <0>;
119 compatible = "fixed-clock";
120 clock-frequency = <60000000>;
121 };
122
123 xclk60mhsp2_ck: xclk60mhsp2_ck {
124 #clock-cells = <0>;
125 compatible = "fixed-clock";
126 clock-frequency = <60000000>;
127 };
128
129 xclk60motg_ck: xclk60motg_ck {
130 #clock-cells = <0>;
131 compatible = "fixed-clock";
132 clock-frequency = <60000000>;
133 };
134
135 dpll_abe_ck: dpll_abe_ck@1e0 {
136 #clock-cells = <0>;
137 compatible = "ti,omap4-dpll-m4xen-clock";
138 clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
139 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
140 };
141
142 dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
143 #clock-cells = <0>;
144 compatible = "ti,omap4-dpll-x2-clock";
145 clocks = <&dpll_abe_ck>;
146 reg = <0x01f0>;
147 };
148
149 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
150 #clock-cells = <0>;
151 compatible = "ti,divider-clock";
152 clocks = <&dpll_abe_x2_ck>;
153 ti,max-div = <31>;
154 ti,autoidle-shift = <8>;
155 reg = <0x01f0>;
156 ti,index-starts-at-one;
157 ti,invert-autoidle-bit;
158 };
159
160 abe_24m_fclk: abe_24m_fclk {
161 #clock-cells = <0>;
162 compatible = "fixed-factor-clock";
163 clocks = <&dpll_abe_m2x2_ck>;
164 clock-mult = <1>;
165 clock-div = <8>;
166 };
167
168 abe_clk: abe_clk@108 {
169 #clock-cells = <0>;
170 compatible = "ti,divider-clock";
171 clocks = <&dpll_abe_m2x2_ck>;
172 ti,max-div = <4>;
173 reg = <0x0108>;
174 ti,index-power-of-two;
175 };
176
177 aess_fclk: aess_fclk@528 {
178 #clock-cells = <0>;
179 compatible = "ti,divider-clock";
180 clocks = <&abe_clk>;
181 ti,bit-shift = <24>;
182 ti,max-div = <2>;
183 reg = <0x0528>;
184 };
185
186 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
187 #clock-cells = <0>;
188 compatible = "ti,divider-clock";
189 clocks = <&dpll_abe_x2_ck>;
190 ti,max-div = <31>;
191 ti,autoidle-shift = <8>;
192 reg = <0x01f4>;
193 ti,index-starts-at-one;
194 ti,invert-autoidle-bit;
195 };
196
197 core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
198 #clock-cells = <0>;
199 compatible = "ti,mux-clock";
200 clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
201 ti,bit-shift = <23>;
202 reg = <0x012c>;
203 };
204
205 dpll_core_ck: dpll_core_ck@120 {
206 #clock-cells = <0>;
207 compatible = "ti,omap4-dpll-core-clock";
208 clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
209 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
210 };
211
212 dpll_core_x2_ck: dpll_core_x2_ck {
213 #clock-cells = <0>;
214 compatible = "ti,omap4-dpll-x2-clock";
215 clocks = <&dpll_core_ck>;
216 };
217
218 dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
219 #clock-cells = <0>;
220 compatible = "ti,divider-clock";
221 clocks = <&dpll_core_x2_ck>;
222 ti,max-div = <31>;
223 ti,autoidle-shift = <8>;
224 reg = <0x0140>;
225 ti,index-starts-at-one;
226 ti,invert-autoidle-bit;
227 };
228
229 dpll_core_m2_ck: dpll_core_m2_ck@130 {
230 #clock-cells = <0>;
231 compatible = "ti,divider-clock";
232 clocks = <&dpll_core_ck>;
233 ti,max-div = <31>;
234 ti,autoidle-shift = <8>;
235 reg = <0x0130>;
236 ti,index-starts-at-one;
237 ti,invert-autoidle-bit;
238 };
239
240 ddrphy_ck: ddrphy_ck {
241 #clock-cells = <0>;
242 compatible = "fixed-factor-clock";
243 clocks = <&dpll_core_m2_ck>;
244 clock-mult = <1>;
245 clock-div = <2>;
246 };
247
248 dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
249 #clock-cells = <0>;
250 compatible = "ti,divider-clock";
251 clocks = <&dpll_core_x2_ck>;
252 ti,max-div = <31>;
253 ti,autoidle-shift = <8>;
254 reg = <0x013c>;
255 ti,index-starts-at-one;
256 ti,invert-autoidle-bit;
257 };
258
259 div_core_ck: div_core_ck@100 {
260 #clock-cells = <0>;
261 compatible = "ti,divider-clock";
262 clocks = <&dpll_core_m5x2_ck>;
263 reg = <0x0100>;
264 ti,max-div = <2>;
265 };
266
267 div_iva_hs_clk: div_iva_hs_clk@1dc {
268 #clock-cells = <0>;
269 compatible = "ti,divider-clock";
270 clocks = <&dpll_core_m5x2_ck>;
271 ti,max-div = <4>;
272 reg = <0x01dc>;
273 ti,index-power-of-two;
274 };
275
276 div_mpu_hs_clk: div_mpu_hs_clk@19c {
277 #clock-cells = <0>;
278 compatible = "ti,divider-clock";
279 clocks = <&dpll_core_m5x2_ck>;
280 ti,max-div = <4>;
281 reg = <0x019c>;
282 ti,index-power-of-two;
283 };
284
285 dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
286 #clock-cells = <0>;
287 compatible = "ti,divider-clock";
288 clocks = <&dpll_core_x2_ck>;
289 ti,max-div = <31>;
290 ti,autoidle-shift = <8>;
291 reg = <0x0138>;
292 ti,index-starts-at-one;
293 ti,invert-autoidle-bit;
294 };
295
296 dll_clk_div_ck: dll_clk_div_ck {
297 #clock-cells = <0>;
298 compatible = "fixed-factor-clock";
299 clocks = <&dpll_core_m4x2_ck>;
300 clock-mult = <1>;
301 clock-div = <2>;
302 };
303
304 dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
305 #clock-cells = <0>;
306 compatible = "ti,divider-clock";
307 clocks = <&dpll_abe_ck>;
308 ti,max-div = <31>;
309 reg = <0x01f0>;
310 ti,index-starts-at-one;
311 };
312
313 dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
314 #clock-cells = <0>;
315 compatible = "ti,composite-no-wait-gate-clock";
316 clocks = <&dpll_core_x2_ck>;
317 ti,bit-shift = <8>;
318 reg = <0x0134>;
319 };
320
321 dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
322 #clock-cells = <0>;
323 compatible = "ti,composite-divider-clock";
324 clocks = <&dpll_core_x2_ck>;
325 ti,max-div = <31>;
326 reg = <0x0134>;
327 ti,index-starts-at-one;
328 };
329
330 dpll_core_m3x2_ck: dpll_core_m3x2_ck {
331 #clock-cells = <0>;
332 compatible = "ti,composite-clock";
333 clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
334 };
335
336 dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
337 #clock-cells = <0>;
338 compatible = "ti,divider-clock";
339 clocks = <&dpll_core_x2_ck>;
340 ti,max-div = <31>;
341 ti,autoidle-shift = <8>;
342 reg = <0x0144>;
343 ti,index-starts-at-one;
344 ti,invert-autoidle-bit;
345 };
346
347 iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
348 #clock-cells = <0>;
349 compatible = "ti,mux-clock";
350 clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
351 ti,bit-shift = <23>;
352 reg = <0x01ac>;
353 };
354
355 dpll_iva_ck: dpll_iva_ck@1a0 {
356 #clock-cells = <0>;
357 compatible = "ti,omap4-dpll-clock";
358 clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
359 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
360 };
361
362 dpll_iva_x2_ck: dpll_iva_x2_ck {
363 #clock-cells = <0>;
364 compatible = "ti,omap4-dpll-x2-clock";
365 clocks = <&dpll_iva_ck>;
366 };
367
368 dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
369 #clock-cells = <0>;
370 compatible = "ti,divider-clock";
371 clocks = <&dpll_iva_x2_ck>;
372 ti,max-div = <31>;
373 ti,autoidle-shift = <8>;
374 reg = <0x01b8>;
375 ti,index-starts-at-one;
376 ti,invert-autoidle-bit;
377 };
378
379 dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
380 #clock-cells = <0>;
381 compatible = "ti,divider-clock";
382 clocks = <&dpll_iva_x2_ck>;
383 ti,max-div = <31>;
384 ti,autoidle-shift = <8>;
385 reg = <0x01bc>;
386 ti,index-starts-at-one;
387 ti,invert-autoidle-bit;
388 };
389
390 dpll_mpu_ck: dpll_mpu_ck@160 {
391 #clock-cells = <0>;
392 compatible = "ti,omap4-dpll-clock";
393 clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
394 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
395 };
396
397 dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
398 #clock-cells = <0>;
399 compatible = "ti,divider-clock";
400 clocks = <&dpll_mpu_ck>;
401 ti,max-div = <31>;
402 ti,autoidle-shift = <8>;
403 reg = <0x0170>;
404 ti,index-starts-at-one;
405 ti,invert-autoidle-bit;
406 };
407
408 per_hs_clk_div_ck: per_hs_clk_div_ck {
409 #clock-cells = <0>;
410 compatible = "fixed-factor-clock";
411 clocks = <&dpll_abe_m3x2_ck>;
412 clock-mult = <1>;
413 clock-div = <2>;
414 };
415
416 usb_hs_clk_div_ck: usb_hs_clk_div_ck {
417 #clock-cells = <0>;
418 compatible = "fixed-factor-clock";
419 clocks = <&dpll_abe_m3x2_ck>;
420 clock-mult = <1>;
421 clock-div = <3>;
422 };
423
424 l3_div_ck: l3_div_ck@100 {
425 #clock-cells = <0>;
426 compatible = "ti,divider-clock";
427 clocks = <&div_core_ck>;
428 ti,bit-shift = <4>;
429 ti,max-div = <2>;
430 reg = <0x0100>;
431 };
432
433 l4_div_ck: l4_div_ck@100 {
434 #clock-cells = <0>;
435 compatible = "ti,divider-clock";
436 clocks = <&l3_div_ck>;
437 ti,bit-shift = <8>;
438 ti,max-div = <2>;
439 reg = <0x0100>;
440 };
441
442 lp_clk_div_ck: lp_clk_div_ck {
443 #clock-cells = <0>;
444 compatible = "fixed-factor-clock";
445 clocks = <&dpll_abe_m2x2_ck>;
446 clock-mult = <1>;
447 clock-div = <16>;
448 };
449
450 mpu_periphclk: mpu_periphclk {
451 #clock-cells = <0>;
452 compatible = "fixed-factor-clock";
453 clocks = <&dpll_mpu_ck>;
454 clock-mult = <1>;
455 clock-div = <2>;
456 };
457
458 ocp_abe_iclk: ocp_abe_iclk@528 {
459 #clock-cells = <0>;
460 compatible = "ti,divider-clock";
461 clocks = <&aess_fclk>;
462 ti,bit-shift = <24>;
463 reg = <0x0528>;
464 ti,dividers = <2>, <1>;
465 };
466
467 per_abe_24m_fclk: per_abe_24m_fclk {
468 #clock-cells = <0>;
469 compatible = "fixed-factor-clock";
470 clocks = <&dpll_abe_m2_ck>;
471 clock-mult = <1>;
472 clock-div = <4>;
473 };
474
475 dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
476 #clock-cells = <0>;
477 compatible = "ti,mux-clock";
478 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
479 ti,bit-shift = <25>;
480 reg = <0x0538>;
481 };
482
483 func_dmic_abe_gfclk: func_dmic_abe_gfclk@538 {
484 #clock-cells = <0>;
485 compatible = "ti,mux-clock";
486 clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
487 ti,bit-shift = <24>;
488 reg = <0x0538>;
489 };
490
491 mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
492 #clock-cells = <0>;
493 compatible = "ti,mux-clock";
494 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
495 ti,bit-shift = <25>;
496 reg = <0x0540>;
497 };
498
499 func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@540 {
500 #clock-cells = <0>;
501 compatible = "ti,mux-clock";
502 clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
503 ti,bit-shift = <24>;
504 reg = <0x0540>;
505 };
506
507 mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 {
508 #clock-cells = <0>;
509 compatible = "ti,mux-clock";
510 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
511 ti,bit-shift = <25>;
512 reg = <0x0548>;
513 };
514
515 func_mcbsp1_gfclk: func_mcbsp1_gfclk@548 {
516 #clock-cells = <0>;
517 compatible = "ti,mux-clock";
518 clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
519 ti,bit-shift = <24>;
520 reg = <0x0548>;
521 };
522
523 mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
524 #clock-cells = <0>;
525 compatible = "ti,mux-clock";
526 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
527 ti,bit-shift = <25>;
528 reg = <0x0550>;
529 };
530
531 func_mcbsp2_gfclk: func_mcbsp2_gfclk@550 {
532 #clock-cells = <0>;
533 compatible = "ti,mux-clock";
534 clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
535 ti,bit-shift = <24>;
536 reg = <0x0550>;
537 };
538
539 mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
540 #clock-cells = <0>;
541 compatible = "ti,mux-clock";
542 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
543 ti,bit-shift = <25>;
544 reg = <0x0558>;
545 };
546
547 func_mcbsp3_gfclk: func_mcbsp3_gfclk@558 {
548 #clock-cells = <0>;
549 compatible = "ti,mux-clock";
550 clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
551 ti,bit-shift = <24>;
552 reg = <0x0558>;
553 };
554
555 slimbus1_fclk_1: slimbus1_fclk_1@560 {
556 #clock-cells = <0>;
557 compatible = "ti,gate-clock";
558 clocks = <&func_24m_clk>;
559 ti,bit-shift = <9>;
560 reg = <0x0560>;
561 };
562
563 slimbus1_fclk_0: slimbus1_fclk_0@560 {
564 #clock-cells = <0>;
565 compatible = "ti,gate-clock";
566 clocks = <&abe_24m_fclk>;
567 ti,bit-shift = <8>;
568 reg = <0x0560>;
569 };
570
571 slimbus1_fclk_2: slimbus1_fclk_2@560 {
572 #clock-cells = <0>;
573 compatible = "ti,gate-clock";
574 clocks = <&pad_clks_ck>;
575 ti,bit-shift = <10>;
576 reg = <0x0560>;
577 };
578
579 slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
580 #clock-cells = <0>;
581 compatible = "ti,gate-clock";
582 clocks = <&slimbus_clk>;
583 ti,bit-shift = <11>;
584 reg = <0x0560>;
585 };
586
587 timer5_sync_mux: timer5_sync_mux@568 {
588 #clock-cells = <0>;
589 compatible = "ti,mux-clock";
590 clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
591 ti,bit-shift = <24>;
592 reg = <0x0568>;
593 };
594
595 timer6_sync_mux: timer6_sync_mux@570 {
596 #clock-cells = <0>;
597 compatible = "ti,mux-clock";
598 clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
599 ti,bit-shift = <24>;
600 reg = <0x0570>;
601 };
602
603 timer7_sync_mux: timer7_sync_mux@578 {
604 #clock-cells = <0>;
605 compatible = "ti,mux-clock";
606 clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
607 ti,bit-shift = <24>;
608 reg = <0x0578>;
609 };
610
611 timer8_sync_mux: timer8_sync_mux@580 {
612 #clock-cells = <0>;
613 compatible = "ti,mux-clock";
614 clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
615 ti,bit-shift = <24>;
616 reg = <0x0580>;
617 };
618
619 dummy_ck: dummy_ck {
620 #clock-cells = <0>;
621 compatible = "fixed-clock";
622 clock-frequency = <0>;
623 };
624};
625&prm_clocks {
626 sys_clkin_ck: sys_clkin_ck@110 {
627 #clock-cells = <0>;
628 compatible = "ti,mux-clock";
629 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
630 reg = <0x0110>;
631 ti,index-starts-at-one;
632 };
633
634 abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
635 #clock-cells = <0>;
636 compatible = "ti,mux-clock";
637 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
638 ti,bit-shift = <24>;
639 reg = <0x0108>;
640 };
641
642 abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
643 #clock-cells = <0>;
644 compatible = "ti,mux-clock";
645 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
646 reg = <0x010c>;
647 };
648
649 dbgclk_mux_ck: dbgclk_mux_ck {
650 #clock-cells = <0>;
651 compatible = "fixed-factor-clock";
652 clocks = <&sys_clkin_ck>;
653 clock-mult = <1>;
654 clock-div = <1>;
655 };
656
657 l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
658 #clock-cells = <0>;
659 compatible = "ti,mux-clock";
660 clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
661 reg = <0x0108>;
662 };
663
664 syc_clk_div_ck: syc_clk_div_ck@100 {
665 #clock-cells = <0>;
666 compatible = "ti,divider-clock";
667 clocks = <&sys_clkin_ck>;
668 reg = <0x0100>;
669 ti,max-div = <2>;
670 };
671
672 gpio1_dbclk: gpio1_dbclk@1838 {
673 #clock-cells = <0>;
674 compatible = "ti,gate-clock";
675 clocks = <&sys_32k_ck>;
676 ti,bit-shift = <8>;
677 reg = <0x1838>;
678 };
679
680 dmt1_clk_mux: dmt1_clk_mux@1840 {
681 #clock-cells = <0>;
682 compatible = "ti,mux-clock";
683 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
684 ti,bit-shift = <24>;
685 reg = <0x1840>;
686 };
687
688 usim_ck: usim_ck@1858 {
689 #clock-cells = <0>;
690 compatible = "ti,divider-clock";
691 clocks = <&dpll_per_m4x2_ck>;
692 ti,bit-shift = <24>;
693 reg = <0x1858>;
694 ti,dividers = <14>, <18>;
695 };
696
697 usim_fclk: usim_fclk@1858 {
698 #clock-cells = <0>;
699 compatible = "ti,gate-clock";
700 clocks = <&usim_ck>;
701 ti,bit-shift = <8>;
702 reg = <0x1858>;
703 };
704
705 pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@1a20 {
706 #clock-cells = <0>;
707 compatible = "ti,mux-clock";
708 clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
709 ti,bit-shift = <20>;
710 reg = <0x1a20>;
711 };
712
713 pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@1a20 {
714 #clock-cells = <0>;
715 compatible = "ti,mux-clock";
716 clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
717 ti,bit-shift = <22>;
718 reg = <0x1a20>;
719 };
720
721 stm_clk_div_ck: stm_clk_div_ck@1a20 {
722 #clock-cells = <0>;
723 compatible = "ti,divider-clock";
724 clocks = <&pmd_stm_clock_mux_ck>;
725 ti,bit-shift = <27>;
726 ti,max-div = <64>;
727 reg = <0x1a20>;
728 ti,index-power-of-two;
729 };
730
731 trace_clk_div_div_ck: trace_clk_div_div_ck@1a20 {
732 #clock-cells = <0>;
733 compatible = "ti,divider-clock";
734 clocks = <&pmd_trace_clk_mux_ck>;
735 ti,bit-shift = <24>;
736 reg = <0x1a20>;
737 ti,dividers = <0>, <1>, <2>, <0>, <4>;
738 };
739
740 trace_clk_div_ck: trace_clk_div_ck {
741 #clock-cells = <0>;
742 compatible = "ti,clkdm-gate-clock";
743 clocks = <&trace_clk_div_div_ck>;
744 };
745};
746
747&prm_clockdomains {
748 emu_sys_clkdm: emu_sys_clkdm {
749 compatible = "ti,clockdomain";
750 clocks = <&trace_clk_div_ck>;
751 };
752};
753
754&cm2_clocks {
755 per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
756 #clock-cells = <0>;
757 compatible = "ti,mux-clock";
758 clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
759 ti,bit-shift = <23>;
760 reg = <0x014c>;
761 };
762
763 dpll_per_ck: dpll_per_ck@140 {
764 #clock-cells = <0>;
765 compatible = "ti,omap4-dpll-clock";
766 clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
767 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
768 };
769
770 dpll_per_m2_ck: dpll_per_m2_ck@150 {
771 #clock-cells = <0>;
772 compatible = "ti,divider-clock";
773 clocks = <&dpll_per_ck>;
774 ti,max-div = <31>;
775 reg = <0x0150>;
776 ti,index-starts-at-one;
777 };
778
779 dpll_per_x2_ck: dpll_per_x2_ck@150 {
780 #clock-cells = <0>;
781 compatible = "ti,omap4-dpll-x2-clock";
782 clocks = <&dpll_per_ck>;
783 reg = <0x0150>;
784 };
785
786 dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
787 #clock-cells = <0>;
788 compatible = "ti,divider-clock";
789 clocks = <&dpll_per_x2_ck>;
790 ti,max-div = <31>;
791 ti,autoidle-shift = <8>;
792 reg = <0x0150>;
793 ti,index-starts-at-one;
794 ti,invert-autoidle-bit;
795 };
796
797 dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
798 #clock-cells = <0>;
799 compatible = "ti,composite-no-wait-gate-clock";
800 clocks = <&dpll_per_x2_ck>;
801 ti,bit-shift = <8>;
802 reg = <0x0154>;
803 };
804
805 dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
806 #clock-cells = <0>;
807 compatible = "ti,composite-divider-clock";
808 clocks = <&dpll_per_x2_ck>;
809 ti,max-div = <31>;
810 reg = <0x0154>;
811 ti,index-starts-at-one;
812 };
813
814 dpll_per_m3x2_ck: dpll_per_m3x2_ck {
815 #clock-cells = <0>;
816 compatible = "ti,composite-clock";
817 clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
818 };
819
820 dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
821 #clock-cells = <0>;
822 compatible = "ti,divider-clock";
823 clocks = <&dpll_per_x2_ck>;
824 ti,max-div = <31>;
825 ti,autoidle-shift = <8>;
826 reg = <0x0158>;
827 ti,index-starts-at-one;
828 ti,invert-autoidle-bit;
829 };
830
831 dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
832 #clock-cells = <0>;
833 compatible = "ti,divider-clock";
834 clocks = <&dpll_per_x2_ck>;
835 ti,max-div = <31>;
836 ti,autoidle-shift = <8>;
837 reg = <0x015c>;
838 ti,index-starts-at-one;
839 ti,invert-autoidle-bit;
840 };
841
842 dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
843 #clock-cells = <0>;
844 compatible = "ti,divider-clock";
845 clocks = <&dpll_per_x2_ck>;
846 ti,max-div = <31>;
847 ti,autoidle-shift = <8>;
848 reg = <0x0160>;
849 ti,index-starts-at-one;
850 ti,invert-autoidle-bit;
851 };
852
853 dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
854 #clock-cells = <0>;
855 compatible = "ti,divider-clock";
856 clocks = <&dpll_per_x2_ck>;
857 ti,max-div = <31>;
858 ti,autoidle-shift = <8>;
859 reg = <0x0164>;
860 ti,index-starts-at-one;
861 ti,invert-autoidle-bit;
862 };
863
864 dpll_usb_ck: dpll_usb_ck@180 {
865 #clock-cells = <0>;
866 compatible = "ti,omap4-dpll-j-type-clock";
867 clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
868 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
869 };
870
871 dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
872 #clock-cells = <0>;
873 compatible = "ti,fixed-factor-clock";
874 clocks = <&dpll_usb_ck>;
875 ti,clock-div = <1>;
876 ti,autoidle-shift = <8>;
877 reg = <0x01b4>;
878 ti,clock-mult = <1>;
879 ti,invert-autoidle-bit;
880 };
881
882 dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
883 #clock-cells = <0>;
884 compatible = "ti,divider-clock";
885 clocks = <&dpll_usb_ck>;
886 ti,max-div = <127>;
887 ti,autoidle-shift = <8>;
888 reg = <0x0190>;
889 ti,index-starts-at-one;
890 ti,invert-autoidle-bit;
891 };
892
893 ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
894 #clock-cells = <0>;
895 compatible = "ti,mux-clock";
896 clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
897 reg = <0x0100>;
898 };
899
900 func_12m_fclk: func_12m_fclk {
901 #clock-cells = <0>;
902 compatible = "fixed-factor-clock";
903 clocks = <&dpll_per_m2x2_ck>;
904 clock-mult = <1>;
905 clock-div = <16>;
906 };
907
908 func_24m_clk: func_24m_clk {
909 #clock-cells = <0>;
910 compatible = "fixed-factor-clock";
911 clocks = <&dpll_per_m2_ck>;
912 clock-mult = <1>;
913 clock-div = <4>;
914 };
915
916 func_24mc_fclk: func_24mc_fclk {
917 #clock-cells = <0>;
918 compatible = "fixed-factor-clock";
919 clocks = <&dpll_per_m2x2_ck>;
920 clock-mult = <1>;
921 clock-div = <8>;
922 };
923
924 func_48m_fclk: func_48m_fclk@108 {
925 #clock-cells = <0>;
926 compatible = "ti,divider-clock";
927 clocks = <&dpll_per_m2x2_ck>;
928 reg = <0x0108>;
929 ti,dividers = <4>, <8>;
930 };
931
932 func_48mc_fclk: func_48mc_fclk {
933 #clock-cells = <0>;
934 compatible = "fixed-factor-clock";
935 clocks = <&dpll_per_m2x2_ck>;
936 clock-mult = <1>;
937 clock-div = <4>;
938 };
939
940 func_64m_fclk: func_64m_fclk@108 {
941 #clock-cells = <0>;
942 compatible = "ti,divider-clock";
943 clocks = <&dpll_per_m4x2_ck>;
944 reg = <0x0108>;
945 ti,dividers = <2>, <4>;
946 };
947
948 func_96m_fclk: func_96m_fclk@108 {
949 #clock-cells = <0>;
950 compatible = "ti,divider-clock";
951 clocks = <&dpll_per_m2x2_ck>;
952 reg = <0x0108>;
953 ti,dividers = <2>, <4>;
954 };
955
956 init_60m_fclk: init_60m_fclk@104 {
957 #clock-cells = <0>;
958 compatible = "ti,divider-clock";
959 clocks = <&dpll_usb_m2_ck>;
960 reg = <0x0104>;
961 ti,dividers = <1>, <8>;
962 };
963
964 per_abe_nc_fclk: per_abe_nc_fclk@108 {
965 #clock-cells = <0>;
966 compatible = "ti,divider-clock";
967 clocks = <&dpll_abe_m2_ck>;
968 reg = <0x0108>;
969 ti,max-div = <2>;
970 };
971
972 aes1_fck: aes1_fck@15a0 {
973 #clock-cells = <0>;
974 compatible = "ti,gate-clock";
975 clocks = <&l3_div_ck>;
976 ti,bit-shift = <1>;
977 reg = <0x15a0>;
978 };
979
980 aes2_fck: aes2_fck@15a8 {
981 #clock-cells = <0>;
982 compatible = "ti,gate-clock";
983 clocks = <&l3_div_ck>;
984 ti,bit-shift = <1>;
985 reg = <0x15a8>;
986 };
987
988 dss_sys_clk: dss_sys_clk@1120 {
989 #clock-cells = <0>;
990 compatible = "ti,gate-clock";
991 clocks = <&syc_clk_div_ck>;
992 ti,bit-shift = <10>;
993 reg = <0x1120>;
994 };
995
996 dss_tv_clk: dss_tv_clk@1120 {
997 #clock-cells = <0>;
998 compatible = "ti,gate-clock";
999 clocks = <&extalt_clkin_ck>;
1000 ti,bit-shift = <11>;
1001 reg = <0x1120>;
1002 };
1003
1004 dss_dss_clk: dss_dss_clk@1120 {
1005 #clock-cells = <0>;
1006 compatible = "ti,gate-clock";
1007 clocks = <&dpll_per_m5x2_ck>;
1008 ti,bit-shift = <8>;
1009 reg = <0x1120>;
1010 ti,set-rate-parent;
1011 };
1012
1013 dss_48mhz_clk: dss_48mhz_clk@1120 {
1014 #clock-cells = <0>;
1015 compatible = "ti,gate-clock";
1016 clocks = <&func_48mc_fclk>;
1017 ti,bit-shift = <9>;
1018 reg = <0x1120>;
1019 };
1020
1021 fdif_fck: fdif_fck@1028 {
1022 #clock-cells = <0>;
1023 compatible = "ti,divider-clock";
1024 clocks = <&dpll_per_m4x2_ck>;
1025 ti,bit-shift = <24>;
1026 ti,max-div = <4>;
1027 reg = <0x1028>;
1028 ti,index-power-of-two;
1029 };
1030
1031 gpio2_dbclk: gpio2_dbclk@1460 {
1032 #clock-cells = <0>;
1033 compatible = "ti,gate-clock";
1034 clocks = <&sys_32k_ck>;
1035 ti,bit-shift = <8>;
1036 reg = <0x1460>;
1037 };
1038
1039 gpio3_dbclk: gpio3_dbclk@1468 {
1040 #clock-cells = <0>;
1041 compatible = "ti,gate-clock";
1042 clocks = <&sys_32k_ck>;
1043 ti,bit-shift = <8>;
1044 reg = <0x1468>;
1045 };
1046
1047 gpio4_dbclk: gpio4_dbclk@1470 {
1048 #clock-cells = <0>;
1049 compatible = "ti,gate-clock";
1050 clocks = <&sys_32k_ck>;
1051 ti,bit-shift = <8>;
1052 reg = <0x1470>;
1053 };
1054
1055 gpio5_dbclk: gpio5_dbclk@1478 {
1056 #clock-cells = <0>;
1057 compatible = "ti,gate-clock";
1058 clocks = <&sys_32k_ck>;
1059 ti,bit-shift = <8>;
1060 reg = <0x1478>;
1061 };
1062
1063 gpio6_dbclk: gpio6_dbclk@1480 {
1064 #clock-cells = <0>;
1065 compatible = "ti,gate-clock";
1066 clocks = <&sys_32k_ck>;
1067 ti,bit-shift = <8>;
1068 reg = <0x1480>;
1069 };
1070
1071 sgx_clk_mux: sgx_clk_mux@1220 {
1072 #clock-cells = <0>;
1073 compatible = "ti,mux-clock";
1074 clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
1075 ti,bit-shift = <24>;
1076 reg = <0x1220>;
1077 };
1078
1079 hsi_fck: hsi_fck@1338 {
1080 #clock-cells = <0>;
1081 compatible = "ti,divider-clock";
1082 clocks = <&dpll_per_m2x2_ck>;
1083 ti,bit-shift = <24>;
1084 ti,max-div = <4>;
1085 reg = <0x1338>;
1086 ti,index-power-of-two;
1087 };
1088
1089 iss_ctrlclk: iss_ctrlclk@1020 {
1090 #clock-cells = <0>;
1091 compatible = "ti,gate-clock";
1092 clocks = <&func_96m_fclk>;
1093 ti,bit-shift = <8>;
1094 reg = <0x1020>;
1095 };
1096
1097 mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@14e0 {
1098 #clock-cells = <0>;
1099 compatible = "ti,mux-clock";
1100 clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
1101 ti,bit-shift = <25>;
1102 reg = <0x14e0>;
1103 };
1104
1105 per_mcbsp4_gfclk: per_mcbsp4_gfclk@14e0 {
1106 #clock-cells = <0>;
1107 compatible = "ti,mux-clock";
1108 clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
1109 ti,bit-shift = <24>;
1110 reg = <0x14e0>;
1111 };
1112
1113 hsmmc1_fclk: hsmmc1_fclk@1328 {
1114 #clock-cells = <0>;
1115 compatible = "ti,mux-clock";
1116 clocks = <&func_64m_fclk>, <&func_96m_fclk>;
1117 ti,bit-shift = <24>;
1118 reg = <0x1328>;
1119 };
1120
1121 hsmmc2_fclk: hsmmc2_fclk@1330 {
1122 #clock-cells = <0>;
1123 compatible = "ti,mux-clock";
1124 clocks = <&func_64m_fclk>, <&func_96m_fclk>;
1125 ti,bit-shift = <24>;
1126 reg = <0x1330>;
1127 };
1128
1129 ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@13e0 {
1130 #clock-cells = <0>;
1131 compatible = "ti,gate-clock";
1132 clocks = <&func_48m_fclk>;
1133 ti,bit-shift = <8>;
1134 reg = <0x13e0>;
1135 };
1136
1137 sha2md5_fck: sha2md5_fck@15c8 {
1138 #clock-cells = <0>;
1139 compatible = "ti,gate-clock";
1140 clocks = <&l3_div_ck>;
1141 ti,bit-shift = <1>;
1142 reg = <0x15c8>;
1143 };
1144
1145 slimbus2_fclk_1: slimbus2_fclk_1@1538 {
1146 #clock-cells = <0>;
1147 compatible = "ti,gate-clock";
1148 clocks = <&per_abe_24m_fclk>;
1149 ti,bit-shift = <9>;
1150 reg = <0x1538>;
1151 };
1152
1153 slimbus2_fclk_0: slimbus2_fclk_0@1538 {
1154 #clock-cells = <0>;
1155 compatible = "ti,gate-clock";
1156 clocks = <&func_24mc_fclk>;
1157 ti,bit-shift = <8>;
1158 reg = <0x1538>;
1159 };
1160
1161 slimbus2_slimbus_clk: slimbus2_slimbus_clk@1538 {
1162 #clock-cells = <0>;
1163 compatible = "ti,gate-clock";
1164 clocks = <&pad_slimbus_core_clks_ck>;
1165 ti,bit-shift = <10>;
1166 reg = <0x1538>;
1167 };
1168
1169 smartreflex_core_fck: smartreflex_core_fck@638 {
1170 #clock-cells = <0>;
1171 compatible = "ti,gate-clock";
1172 clocks = <&l4_wkup_clk_mux_ck>;
1173 ti,bit-shift = <1>;
1174 reg = <0x0638>;
1175 };
1176
1177 smartreflex_iva_fck: smartreflex_iva_fck@630 {
1178 #clock-cells = <0>;
1179 compatible = "ti,gate-clock";
1180 clocks = <&l4_wkup_clk_mux_ck>;
1181 ti,bit-shift = <1>;
1182 reg = <0x0630>;
1183 };
1184
1185 smartreflex_mpu_fck: smartreflex_mpu_fck@628 {
1186 #clock-cells = <0>;
1187 compatible = "ti,gate-clock";
1188 clocks = <&l4_wkup_clk_mux_ck>;
1189 ti,bit-shift = <1>;
1190 reg = <0x0628>;
1191 };
1192
1193 cm2_dm10_mux: cm2_dm10_mux@1428 {
1194 #clock-cells = <0>;
1195 compatible = "ti,mux-clock";
1196 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
1197 ti,bit-shift = <24>;
1198 reg = <0x1428>;
1199 };
1200
1201 cm2_dm11_mux: cm2_dm11_mux@1430 {
1202 #clock-cells = <0>;
1203 compatible = "ti,mux-clock";
1204 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
1205 ti,bit-shift = <24>;
1206 reg = <0x1430>;
1207 };
1208
1209 cm2_dm2_mux: cm2_dm2_mux@1438 {
1210 #clock-cells = <0>;
1211 compatible = "ti,mux-clock";
1212 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
1213 ti,bit-shift = <24>;
1214 reg = <0x1438>;
1215 };
1216
1217 cm2_dm3_mux: cm2_dm3_mux@1440 {
1218 #clock-cells = <0>;
1219 compatible = "ti,mux-clock";
1220 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
1221 ti,bit-shift = <24>;
1222 reg = <0x1440>;
1223 };
1224
1225 cm2_dm4_mux: cm2_dm4_mux@1448 {
1226 #clock-cells = <0>;
1227 compatible = "ti,mux-clock";
1228 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
1229 ti,bit-shift = <24>;
1230 reg = <0x1448>;
1231 };
1232
1233 cm2_dm9_mux: cm2_dm9_mux@1450 {
1234 #clock-cells = <0>;
1235 compatible = "ti,mux-clock";
1236 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
1237 ti,bit-shift = <24>;
1238 reg = <0x1450>;
1239 };
1240
1241 usb_host_fs_fck: usb_host_fs_fck@13d0 {
1242 #clock-cells = <0>;
1243 compatible = "ti,gate-clock";
1244 clocks = <&func_48mc_fclk>;
1245 ti,bit-shift = <1>;
1246 reg = <0x13d0>;
1247 };
1248
1249 utmi_p1_gfclk: utmi_p1_gfclk@1358 {
1250 #clock-cells = <0>;
1251 compatible = "ti,mux-clock";
1252 clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
1253 ti,bit-shift = <24>;
1254 reg = <0x1358>;
1255 };
1256
1257 usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1358 {
1258 #clock-cells = <0>;
1259 compatible = "ti,gate-clock";
1260 clocks = <&utmi_p1_gfclk>;
1261 ti,bit-shift = <8>;
1262 reg = <0x1358>;
1263 };
1264
1265 utmi_p2_gfclk: utmi_p2_gfclk@1358 {
1266 #clock-cells = <0>;
1267 compatible = "ti,mux-clock";
1268 clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
1269 ti,bit-shift = <25>;
1270 reg = <0x1358>;
1271 };
1272
1273 usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1358 {
1274 #clock-cells = <0>;
1275 compatible = "ti,gate-clock";
1276 clocks = <&utmi_p2_gfclk>;
1277 ti,bit-shift = <9>;
1278 reg = <0x1358>;
1279 };
1280
1281 usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1358 {
1282 #clock-cells = <0>;
1283 compatible = "ti,gate-clock";
1284 clocks = <&init_60m_fclk>;
1285 ti,bit-shift = <10>;
1286 reg = <0x1358>;
1287 };
1288
1289 usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1358 {
1290 #clock-cells = <0>;
1291 compatible = "ti,gate-clock";
1292 clocks = <&dpll_usb_m2_ck>;
1293 ti,bit-shift = <13>;
1294 reg = <0x1358>;
1295 };
1296
1297 usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1358 {
1298 #clock-cells = <0>;
1299 compatible = "ti,gate-clock";
1300 clocks = <&init_60m_fclk>;
1301 ti,bit-shift = <11>;
1302 reg = <0x1358>;
1303 };
1304
1305 usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1358 {
1306 #clock-cells = <0>;
1307 compatible = "ti,gate-clock";
1308 clocks = <&init_60m_fclk>;
1309 ti,bit-shift = <12>;
1310 reg = <0x1358>;
1311 };
1312
1313 usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1358 {
1314 #clock-cells = <0>;
1315 compatible = "ti,gate-clock";
1316 clocks = <&dpll_usb_m2_ck>;
1317 ti,bit-shift = <14>;
1318 reg = <0x1358>;
1319 };
1320
1321 usb_host_hs_func48mclk: usb_host_hs_func48mclk@1358 {
1322 #clock-cells = <0>;
1323 compatible = "ti,gate-clock";
1324 clocks = <&func_48mc_fclk>;
1325 ti,bit-shift = <15>;
1326 reg = <0x1358>;
1327 };
1328
1329 usb_host_hs_fck: usb_host_hs_fck@1358 {
1330 #clock-cells = <0>;
1331 compatible = "ti,gate-clock";
1332 clocks = <&init_60m_fclk>;
1333 ti,bit-shift = <1>;
1334 reg = <0x1358>;
1335 };
1336
1337 otg_60m_gfclk: otg_60m_gfclk@1360 {
1338 #clock-cells = <0>;
1339 compatible = "ti,mux-clock";
1340 clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
1341 ti,bit-shift = <24>;
1342 reg = <0x1360>;
1343 };
1344
1345 usb_otg_hs_xclk: usb_otg_hs_xclk@1360 {
1346 #clock-cells = <0>;
1347 compatible = "ti,gate-clock";
1348 clocks = <&otg_60m_gfclk>;
1349 ti,bit-shift = <8>;
1350 reg = <0x1360>;
1351 };
1352
1353 usb_otg_hs_ick: usb_otg_hs_ick@1360 {
1354 #clock-cells = <0>;
1355 compatible = "ti,gate-clock";
1356 clocks = <&l3_div_ck>;
1357 ti,bit-shift = <0>;
1358 reg = <0x1360>;
1359 };
1360
1361 usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
1362 #clock-cells = <0>;
1363 compatible = "ti,gate-clock";
1364 clocks = <&sys_32k_ck>;
1365 ti,bit-shift = <8>;
1366 reg = <0x0640>;
1367 };
1368
1369 usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1368 {
1370 #clock-cells = <0>;
1371 compatible = "ti,gate-clock";
1372 clocks = <&init_60m_fclk>;
1373 ti,bit-shift = <10>;
1374 reg = <0x1368>;
1375 };
1376
1377 usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1368 {
1378 #clock-cells = <0>;
1379 compatible = "ti,gate-clock";
1380 clocks = <&init_60m_fclk>;
1381 ti,bit-shift = <8>;
1382 reg = <0x1368>;
1383 };
1384
1385 usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1368 {
1386 #clock-cells = <0>;
1387 compatible = "ti,gate-clock";
1388 clocks = <&init_60m_fclk>;
1389 ti,bit-shift = <9>;
1390 reg = <0x1368>;
1391 };
1392
1393 usb_tll_hs_ick: usb_tll_hs_ick@1368 {
1394 #clock-cells = <0>;
1395 compatible = "ti,gate-clock";
1396 clocks = <&l4_div_ck>;
1397 ti,bit-shift = <0>;
1398 reg = <0x1368>;
1399 };
1400};
1401
1402&cm2_clockdomains {
1403 l3_init_clkdm: l3_init_clkdm {
1404 compatible = "ti,clockdomain";
1405 clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>;
1406 };
1407};
1408
1409&scrm_clocks {
1410 auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
1411 #clock-cells = <0>;
1412 compatible = "ti,composite-no-wait-gate-clock";
1413 clocks = <&dpll_core_m3x2_ck>;
1414 ti,bit-shift = <8>;
1415 reg = <0x0310>;
1416 };
1417
1418 auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
1419 #clock-cells = <0>;
1420 compatible = "ti,composite-mux-clock";
1421 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1422 ti,bit-shift = <1>;
1423 reg = <0x0310>;
1424 };
1425
1426 auxclk0_src_ck: auxclk0_src_ck {
1427 #clock-cells = <0>;
1428 compatible = "ti,composite-clock";
1429 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
1430 };
1431
1432 auxclk0_ck: auxclk0_ck@310 {
1433 #clock-cells = <0>;
1434 compatible = "ti,divider-clock";
1435 clocks = <&auxclk0_src_ck>;
1436 ti,bit-shift = <16>;
1437 ti,max-div = <16>;
1438 reg = <0x0310>;
1439 };
1440
1441 auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
1442 #clock-cells = <0>;
1443 compatible = "ti,composite-no-wait-gate-clock";
1444 clocks = <&dpll_core_m3x2_ck>;
1445 ti,bit-shift = <8>;
1446 reg = <0x0314>;
1447 };
1448
1449 auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
1450 #clock-cells = <0>;
1451 compatible = "ti,composite-mux-clock";
1452 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1453 ti,bit-shift = <1>;
1454 reg = <0x0314>;
1455 };
1456
1457 auxclk1_src_ck: auxclk1_src_ck {
1458 #clock-cells = <0>;
1459 compatible = "ti,composite-clock";
1460 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
1461 };
1462
1463 auxclk1_ck: auxclk1_ck@314 {
1464 #clock-cells = <0>;
1465 compatible = "ti,divider-clock";
1466 clocks = <&auxclk1_src_ck>;
1467 ti,bit-shift = <16>;
1468 ti,max-div = <16>;
1469 reg = <0x0314>;
1470 };
1471
1472 auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
1473 #clock-cells = <0>;
1474 compatible = "ti,composite-no-wait-gate-clock";
1475 clocks = <&dpll_core_m3x2_ck>;
1476 ti,bit-shift = <8>;
1477 reg = <0x0318>;
1478 };
1479
1480 auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
1481 #clock-cells = <0>;
1482 compatible = "ti,composite-mux-clock";
1483 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1484 ti,bit-shift = <1>;
1485 reg = <0x0318>;
1486 };
1487
1488 auxclk2_src_ck: auxclk2_src_ck {
1489 #clock-cells = <0>;
1490 compatible = "ti,composite-clock";
1491 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
1492 };
1493
1494 auxclk2_ck: auxclk2_ck@318 {
1495 #clock-cells = <0>;
1496 compatible = "ti,divider-clock";
1497 clocks = <&auxclk2_src_ck>;
1498 ti,bit-shift = <16>;
1499 ti,max-div = <16>;
1500 reg = <0x0318>;
1501 };
1502
1503 auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
1504 #clock-cells = <0>;
1505 compatible = "ti,composite-no-wait-gate-clock";
1506 clocks = <&dpll_core_m3x2_ck>;
1507 ti,bit-shift = <8>;
1508 reg = <0x031c>;
1509 };
1510
1511 auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
1512 #clock-cells = <0>;
1513 compatible = "ti,composite-mux-clock";
1514 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1515 ti,bit-shift = <1>;
1516 reg = <0x031c>;
1517 };
1518
1519 auxclk3_src_ck: auxclk3_src_ck {
1520 #clock-cells = <0>;
1521 compatible = "ti,composite-clock";
1522 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
1523 };
1524
1525 auxclk3_ck: auxclk3_ck@31c {
1526 #clock-cells = <0>;
1527 compatible = "ti,divider-clock";
1528 clocks = <&auxclk3_src_ck>;
1529 ti,bit-shift = <16>;
1530 ti,max-div = <16>;
1531 reg = <0x031c>;
1532 };
1533
1534 auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
1535 #clock-cells = <0>;
1536 compatible = "ti,composite-no-wait-gate-clock";
1537 clocks = <&dpll_core_m3x2_ck>;
1538 ti,bit-shift = <8>;
1539 reg = <0x0320>;
1540 };
1541
1542 auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
1543 #clock-cells = <0>;
1544 compatible = "ti,composite-mux-clock";
1545 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1546 ti,bit-shift = <1>;
1547 reg = <0x0320>;
1548 };
1549
1550 auxclk4_src_ck: auxclk4_src_ck {
1551 #clock-cells = <0>;
1552 compatible = "ti,composite-clock";
1553 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
1554 };
1555
1556 auxclk4_ck: auxclk4_ck@320 {
1557 #clock-cells = <0>;
1558 compatible = "ti,divider-clock";
1559 clocks = <&auxclk4_src_ck>;
1560 ti,bit-shift = <16>;
1561 ti,max-div = <16>;
1562 reg = <0x0320>;
1563 };
1564
1565 auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
1566 #clock-cells = <0>;
1567 compatible = "ti,composite-no-wait-gate-clock";
1568 clocks = <&dpll_core_m3x2_ck>;
1569 ti,bit-shift = <8>;
1570 reg = <0x0324>;
1571 };
1572
1573 auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
1574 #clock-cells = <0>;
1575 compatible = "ti,composite-mux-clock";
1576 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1577 ti,bit-shift = <1>;
1578 reg = <0x0324>;
1579 };
1580
1581 auxclk5_src_ck: auxclk5_src_ck {
1582 #clock-cells = <0>;
1583 compatible = "ti,composite-clock";
1584 clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
1585 };
1586
1587 auxclk5_ck: auxclk5_ck@324 {
1588 #clock-cells = <0>;
1589 compatible = "ti,divider-clock";
1590 clocks = <&auxclk5_src_ck>;
1591 ti,bit-shift = <16>;
1592 ti,max-div = <16>;
1593 reg = <0x0324>;
1594 };
1595
1596 auxclkreq0_ck: auxclkreq0_ck@210 {
1597 #clock-cells = <0>;
1598 compatible = "ti,mux-clock";
1599 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1600 ti,bit-shift = <2>;
1601 reg = <0x0210>;
1602 };
1603
1604 auxclkreq1_ck: auxclkreq1_ck@214 {
1605 #clock-cells = <0>;
1606 compatible = "ti,mux-clock";
1607 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1608 ti,bit-shift = <2>;
1609 reg = <0x0214>;
1610 };
1611
1612 auxclkreq2_ck: auxclkreq2_ck@218 {
1613 #clock-cells = <0>;
1614 compatible = "ti,mux-clock";
1615 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1616 ti,bit-shift = <2>;
1617 reg = <0x0218>;
1618 };
1619
1620 auxclkreq3_ck: auxclkreq3_ck@21c {
1621 #clock-cells = <0>;
1622 compatible = "ti,mux-clock";
1623 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1624 ti,bit-shift = <2>;
1625 reg = <0x021c>;
1626 };
1627
1628 auxclkreq4_ck: auxclkreq4_ck@220 {
1629 #clock-cells = <0>;
1630 compatible = "ti,mux-clock";
1631 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1632 ti,bit-shift = <2>;
1633 reg = <0x0220>;
1634 };
1635
1636 auxclkreq5_ck: auxclkreq5_ck@224 {
1637 #clock-cells = <0>;
1638 compatible = "ti,mux-clock";
1639 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1640 ti,bit-shift = <2>;
1641 reg = <0x0224>;
1642 };
1643};