1// SPDX-License-Identifier: GPL-2.0 OR MIT
 2/*
 3 * Copyright 2014 Carlo Caione <carlo@caione.org>
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 4 */
 5
 6#include "meson.dtsi"
 7
 8/ {
 9	model = "Amlogic Meson6 SoC";
10	compatible = "amlogic,meson6";
11
 
 
12	cpus {
13		#address-cells = <1>;
14		#size-cells = <0>;
15
16		cpu@200 {
17			device_type = "cpu";
18			compatible = "arm,cortex-a9";
19			next-level-cache = <&L2>;
20			reg = <0x200>;
21		};
22
23		cpu@201 {
24			device_type = "cpu";
25			compatible = "arm,cortex-a9";
26			next-level-cache = <&L2>;
27			reg = <0x201>;
28		};
29	};
30
31	apb2: bus@d0000000 {
32		compatible = "simple-bus";
33		reg = <0xd0000000 0x40000>;
34		#address-cells = <1>;
35		#size-cells = <1>;
36		ranges = <0x0 0xd0000000 0x40000>;
37	};
38
39	clk81: clk@0 {
40		#clock-cells = <0>;
41		compatible = "fixed-clock";
42		clock-frequency = <200000000>;
43	};
44}; /* end of / */
45
46&efuse {
47	status = "disabled";
48};
49
50&timer_abcde {
51	clocks = <&xtal>, <&clk81>;
52	clock-names = "xtal", "pclk";
53};
54
55&uart_AO {
56	clocks = <&xtal>, <&clk81>, <&clk81>;
57	clock-names = "xtal", "pclk", "baud";
58};
59
60&uart_A {
61	clocks = <&xtal>, <&clk81>, <&clk81>;
62	clock-names = "xtal", "pclk", "baud";
63};
64
65&uart_B {
66	clocks = <&xtal>, <&clk81>, <&clk81>;
67	clock-names = "xtal", "pclk", "baud";
68};
69
70&uart_C {
71	clocks = <&xtal>, <&clk81>, <&clk81>;
72	clock-names = "xtal", "pclk", "baud";
73};

 
 1/*
 2 * Copyright 2014 Carlo Caione <carlo@caione.org>
 3 *
 4 * This file is dual-licensed: you can use it either under the terms
 5 * of the GPL or the X11 license, at your option. Note that this dual
 6 * licensing only applies to this file, and not this project as a
 7 * whole.
 8 *
 9 *  a) This library is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License as
11 *     published by the Free Software Foundation; either version 2 of the
12 *     License, or (at your option) any later version.
13 *
14 *     This library is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 *     You should have received a copy of the GNU General Public
20 *     License along with this library; if not, write to the Free
21 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 *     MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 *  b) Permission is hereby granted, free of charge, to any person
27 *     obtaining a copy of this software and associated documentation
28 *     files (the "Software"), to deal in the Software without
29 *     restriction, including without limitation the rights to use,
30 *     copy, modify, merge, publish, distribute, sublicense, and/or
31 *     sell copies of the Software, and to permit persons to whom the
32 *     Software is furnished to do so, subject to the following
33 *     conditions:
34 *
35 *     The above copyright notice and this permission notice shall be
36 *     included in all copies or substantial portions of the Software.
37 *
38 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 *     OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/include/ "meson.dtsi"
49
50/ {
51	model = "Amlogic Meson6 SoC";
52	compatible = "amlogic,meson6";
53
54	interrupt-parent = <&gic>;
55
56	cpus {
57		#address-cells = <1>;
58		#size-cells = <0>;
59
60		cpu@200 {
61			device_type = "cpu";
62			compatible = "arm,cortex-a9";
63			next-level-cache = <&L2>;
64			reg = <0x200>;
65		};
66
67		cpu@201 {
68			device_type = "cpu";
69			compatible = "arm,cortex-a9";
70			next-level-cache = <&L2>;
71			reg = <0x201>;
72		};
73	};
74
 
 
 
 
 
 
 
 
75	clk81: clk@0 {
76		#clock-cells = <0>;
77		compatible = "fixed-clock";
78		clock-frequency = <200000000>;
79	};
80}; /* end of / */