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1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Copyright (C) 2016 Amarula Solutions B.V.
4 * Copyright (C) 2016 Engicam S.r.l.
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/sound/fsl-imx-audmux.h>
10
11/ {
12 memory@10000000 {
13 device_type = "memory";
14 reg = <0x10000000 0x80000000>;
15 };
16
17 chosen {
18 stdout-path = &uart4;
19 };
20
21 backlight_lvds: backlight-lvds {
22 compatible = "pwm-backlight";
23 pwms = <&pwm3 0 100000>;
24 brightness-levels = <0 4 8 16 32 64 128 255>;
25 default-brightness-level = <7>;
26 };
27
28 reg_1p8v: regulator-1p8v {
29 compatible = "regulator-fixed";
30 regulator-name = "1P8V";
31 regulator-min-microvolt = <1800000>;
32 regulator-max-microvolt = <1800000>;
33 regulator-boot-on;
34 regulator-always-on;
35 };
36
37 reg_2p5v: regulator-2p5v {
38 compatible = "regulator-fixed";
39 regulator-name = "2P5V";
40 regulator-min-microvolt = <2500000>;
41 regulator-max-microvolt = <2500000>;
42 regulator-boot-on;
43 regulator-always-on;
44 };
45
46 reg_3p3v: regulator-3p3v {
47 compatible = "regulator-fixed";
48 regulator-name = "3P3V";
49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
51 regulator-boot-on;
52 regulator-always-on;
53 };
54
55 reg_usb_h1_vbus: regulator-usb-h1-vbus {
56 compatible = "regulator-fixed";
57 regulator-name = "usb_h1_vbus";
58 regulator-min-microvolt = <5000000>;
59 regulator-max-microvolt = <5000000>;
60 regulator-boot-on;
61 regulator-always-on;
62 };
63
64 reg_usb_otg_vbus: regulator-usb-otg-vbus {
65 compatible = "regulator-fixed";
66 regulator-name = "usb_otg_vbus";
67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>;
69 regulator-boot-on;
70 regulator-always-on;
71 };
72
73 rmii_clk: clock-rmii-clk {
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <25000000>; /* 25MHz for example */
77 };
78
79 sound {
80 compatible = "simple-audio-card";
81 simple-audio-card,name = "imx6qdl-icore-sgtl5000";
82 simple-audio-card,format = "i2s";
83 simple-audio-card,bitclock-master = <&dailink_master>;
84 simple-audio-card,frame-master = <&dailink_master>;
85 simple-audio-card,widgets =
86 "Microphone", "Mic Jack",
87 "Headphone", "Headphone Jack",
88 "Line", "Line In Jack",
89 "Speaker", "Line Out Jack",
90 "Speaker", "Ext Spk";
91 simple-audio-card,routing =
92 "MIC_IN", "Mic Jack",
93 "Mic Jack", "Mic Bias",
94 "Headphone Jack", "HP_OUT";
95
96 simple-audio-card,cpu {
97 sound-dai = <&ssi1>;
98 };
99
100 dailink_master: simple-audio-card,codec {
101 sound-dai = <&sgtl5000>;
102 };
103 };
104};
105
106&audmux {
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_audmux>;
109 status = "okay";
110
111
112 audmux_ssi1 {
113 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
114 fsl,port-config = <
115 (IMX_AUDMUX_V2_PTCR_TFSDIR |
116 IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
117 IMX_AUDMUX_V2_PTCR_TCLKDIR |
118 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
119 IMX_AUDMUX_V2_PTCR_SYN)
120 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
121 >;
122 };
123
124 audmux_aud4 {
125 fsl,audmux-port = <MX51_AUDMUX_PORT4>;
126 fsl,port-config = <
127 IMX_AUDMUX_V2_PTCR_SYN
128 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
129 >;
130 };
131};
132
133&can1 {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_flexcan1>;
136 xceiver-supply = <®_3p3v>;
137};
138
139&can2 {
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_flexcan2>;
142 xceiver-supply = <®_3p3v>;
143};
144
145&clks {
146 assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
147 assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
148};
149
150&fec {
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_enet>;
153 clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
154 phy-mode = "rmii";
155 phy-handle = <ð_phy>;
156 status = "okay";
157
158 mdio {
159 #address-cells = <1>;
160 #size-cells = <0>;
161
162 eth_phy: ethernet-phy@0 {
163 compatible = "ethernet-phy-ieee802.3-c22";
164 reg = <0>;
165 reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
166 reset-assert-us = <4000>;
167 reset-deassert-us = <4000>;
168 };
169 };
170};
171
172&gpmi {
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_gpmi_nand>;
175 nand-on-flash-bbt;
176 status = "okay";
177};
178
179&i2c1 {
180 clock-frequency = <100000>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_i2c1>;
183 status = "okay";
184};
185
186&i2c2 {
187 clock-frequency = <100000>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_i2c2>;
190 status = "okay";
191};
192
193&i2c3 {
194 clock-frequency = <100000>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_i2c3>;
197 status = "okay";
198
199 ov5640: camera@3c {
200 compatible = "ovti,ov5640";
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_ov5640>;
203 reg = <0x3c>;
204 clocks = <&clks IMX6QDL_CLK_CKO>;
205 clock-names = "xclk";
206 DOVDD-supply = <®_1p8v>;
207 AVDD-supply = <®_3p3v>;
208 DVDD-supply = <®_3p3v>;
209 powerdown-gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
210 reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
211 status = "disabled";
212
213 port {
214 ov5640_to_mipi_csi2: endpoint {
215 remote-endpoint = <&mipi_csi2_in>;
216 clock-lanes = <0>;
217 data-lanes = <1 2>;
218 };
219 };
220 };
221
222 sgtl5000: codec@a {
223 #sound-dai-cells = <0>;
224 compatible = "fsl,sgtl5000";
225 reg = <0x0a>;
226 clocks = <&clks IMX6QDL_CLK_CKO>;
227 VDDA-supply = <®_2p5v>;
228 VDDIO-supply = <®_3p3v>;
229 VDDD-supply = <®_1p8v>;
230 };
231};
232
233&mipi_csi {
234 status = "disabled";
235
236 port@0 {
237 reg = <0>;
238
239 mipi_csi2_in: endpoint {
240 remote-endpoint = <&ov5640_to_mipi_csi2>;
241 clock-lanes = <0>;
242 data-lanes = <1 2>;
243 };
244 };
245};
246
247&pwm3 {
248 #pwm-cells = <2>;
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_pwm3>;
251 status = "okay";
252};
253
254&ssi1 {
255 fsl,mode = "i2s-slave";
256 status = "okay";
257};
258
259&uart4 {
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_uart4>;
262 status = "okay";
263};
264
265&usbh1 {
266 vbus-supply = <®_usb_h1_vbus>;
267 disable-over-current;
268 status = "okay";
269};
270
271&usbotg {
272 vbus-supply = <®_usb_otg_vbus>;
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_usbotg>;
275 disable-over-current;
276 status = "okay";
277};
278
279&usdhc1 {
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_usdhc1>;
282 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
283 no-1-8-v;
284 status = "okay";
285};
286
287&usdhc3 {
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_usdhc3>;
290 no-1-8-v;
291 non-removable;
292 status = "disabled";
293};
294
295&iomuxc {
296 pinctrl_audmux: audmuxgrp {
297 fsl,pins = <
298 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
299 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
300 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
301 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
302 >;
303 };
304
305 pinctrl_enet: enetgrp {
306 fsl,pins = <
307 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
308 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1
309 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
310 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
311 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
312 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
313 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
314 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
315 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
316 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
317 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
318 >;
319 };
320
321 pinctrl_flexcan1: flexcan1grp {
322 fsl,pins = <
323 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
324 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
325 >;
326 };
327
328 pinctrl_flexcan2: flexcan2grp {
329 fsl,pins = <
330 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
331 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
332 >;
333 };
334
335 pinctrl_gpmi_nand: gpminandgrp {
336 fsl,pins = <
337 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
338 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
339 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
340 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
341 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
342 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
343 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
344 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
345 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
346 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
347 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
348 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
349 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
350 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
351 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
352 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
353 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
354 >;
355 };
356
357 pinctrl_i2c1: i2c1grp {
358 fsl,pins = <
359 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
360 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
361 >;
362 };
363
364 pinctrl_i2c2: i2c2grp {
365 fsl,pins = <
366 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
367 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
368 >;
369 };
370
371 pinctrl_i2c3: i2c3grp {
372 fsl,pins = <
373 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
374 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
375 >;
376 };
377
378 pinctrl_ov5640: ov5640grp {
379 fsl,pins = <
380 MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0
381 MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0
382 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
383 >;
384 };
385
386 pinctrl_uart4: uart4grp {
387 fsl,pins = <
388 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
389 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
390 >;
391 };
392
393 pinctrl_pwm3: pwm3grp {
394 fsl,pins = <
395 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
396 >;
397 };
398
399 pinctrl_usbotg: usbotggrp {
400 fsl,pins = <
401 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
402 >;
403 };
404
405 pinctrl_usdhc1: usdhc1grp {
406 fsl,pins = <
407 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
408 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070
409 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
410 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
411 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
412 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
413 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
414 >;
415 };
416
417 pinctrl_usdhc3: usdhc3grp {
418 fsl,pins = <
419 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
420 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
421 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
422 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
423 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
424 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
425 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
426 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
427 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
428 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
429 >;
430 };
431};
1/*
2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/gpio/gpio.h>
44#include <dt-bindings/input/input.h>
45
46/ {
47 memory {
48 reg = <0x10000000 0x80000000>;
49 };
50
51 reg_3p3v: regulator-3p3v {
52 compatible = "regulator-fixed";
53 regulator-name = "3P3V";
54 regulator-min-microvolt = <3300000>;
55 regulator-max-microvolt = <3300000>;
56 regulator-boot-on;
57 regulator-always-on;
58 };
59
60 reg_usb_h1_vbus: regulator-usb-h1-vbus {
61 compatible = "regulator-fixed";
62 regulator-name = "usb_h1_vbus";
63 regulator-min-microvolt = <5000000>;
64 regulator-max-microvolt = <5000000>;
65 regulator-boot-on;
66 regulator-always-on;
67 };
68
69 reg_usb_otg_vbus: regulator-usb-otg-vbus {
70 compatible = "regulator-fixed";
71 regulator-name = "usb_otg_vbus";
72 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <5000000>;
74 regulator-boot-on;
75 regulator-always-on;
76 };
77
78 rmii_clk: clock-rmii-clk {
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <25000000>; /* 25MHz for example */
82 };
83};
84
85&can1 {
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_flexcan1>;
88 xceiver-supply = <®_3p3v>;
89};
90
91&can2 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_flexcan2>;
94 xceiver-supply = <®_3p3v>;
95};
96
97&clks {
98 assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
99 assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
100};
101
102&fec {
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_enet>;
105 phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
106 clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
107 phy-mode = "rmii";
108 status = "okay";
109};
110
111&gpmi {
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_gpmi_nand>;
114 nand-on-flash-bbt;
115 status = "okay";
116};
117
118&i2c1 {
119 clock-frequency = <100000>;
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_i2c1>;
122 status = "okay";
123};
124
125&i2c2 {
126 clock-frequency = <100000>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_i2c2>;
129 status = "okay";
130};
131
132&i2c3 {
133 clock-frequency = <100000>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_i2c3>;
136 status = "okay";
137};
138
139&uart4 {
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_uart4>;
142 status = "okay";
143};
144
145&usbh1 {
146 vbus-supply = <®_usb_h1_vbus>;
147 disable-over-current;
148 status = "okay";
149};
150
151&usbotg {
152 vbus-supply = <®_usb_otg_vbus>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_usbotg>;
155 disable-over-current;
156 status = "okay";
157};
158
159&usdhc1 {
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_usdhc1>;
162 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
163 no-1-8-v;
164 status = "okay";
165};
166
167&iomuxc {
168 pinctrl_enet: enetgrp {
169 fsl,pins = <
170 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
171 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1
172 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
173 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
174 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
175 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
176 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
177 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
178 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
179 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
180 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
181 >;
182 };
183
184 pinctrl_flexcan1: flexcan1grp {
185 fsl,pins = <
186 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
187 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
188 >;
189 };
190
191 pinctrl_flexcan2: flexcan2grp {
192 fsl,pins = <
193 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
194 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
195 >;
196 };
197
198 pinctrl_gpmi_nand: gpmi-nand {
199 fsl,pins = <
200 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
201 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
202 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
203 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
204 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
205 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
206 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
207 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
208 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
209 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
210 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
211 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
212 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
213 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
214 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
215 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
216 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
217 >;
218 };
219
220 pinctrl_i2c1: i2c1grp {
221 fsl,pins = <
222 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
223 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
224 >;
225 };
226
227 pinctrl_i2c2: i2c2grp {
228 fsl,pins = <
229 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
230 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
231 >;
232 };
233
234 pinctrl_i2c3: i2c3grp {
235 fsl,pins = <
236 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
237 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
238 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
239 >;
240 };
241
242 pinctrl_uart4: uart4grp {
243 fsl,pins = <
244 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
245 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
246 >;
247 };
248
249 pinctrl_usbotg: usbotggrp {
250 fsl,pins = <
251 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
252 >;
253 };
254
255 pinctrl_usdhc1: usdhc1grp {
256 fsl,pins = <
257 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
258 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070
259 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
260 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
261 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
262 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
263 >;
264 };
265};