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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2011 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include "imx53-pinfunc.h"
7#include <dt-bindings/clock/imx5-clock.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 /*
16 * The decompressor and also some bootloaders rely on a
17 * pre-existing /chosen node to be available to insert the
18 * command line and merge other ATAGS info.
19 */
20 chosen {};
21
22 aliases {
23 ethernet0 = &fec;
24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 gpio4 = &gpio5;
29 gpio5 = &gpio6;
30 gpio6 = &gpio7;
31 i2c0 = &i2c1;
32 i2c1 = &i2c2;
33 i2c2 = &i2c3;
34 ipu0 = &ipu;
35 mmc0 = &esdhc1;
36 mmc1 = &esdhc2;
37 mmc2 = &esdhc3;
38 mmc3 = &esdhc4;
39 serial0 = &uart1;
40 serial1 = &uart2;
41 serial2 = &uart3;
42 serial3 = &uart4;
43 serial4 = &uart5;
44 spi0 = &ecspi1;
45 spi1 = &ecspi2;
46 spi2 = &cspi;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52 cpu0: cpu@0 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a8";
55 reg = <0x0>;
56 clocks = <&clks IMX5_CLK_ARM>;
57 clock-latency = <61036>;
58 voltage-tolerance = <5>;
59 operating-points = <
60 /* kHz */
61 166666 850000
62 400000 900000
63 800000 1050000
64 1000000 1200000
65 1200000 1300000
66 >;
67 };
68 };
69
70 display-subsystem {
71 compatible = "fsl,imx-display-subsystem";
72 ports = <&ipu_di0>, <&ipu_di1>;
73 };
74
75 capture_subsystem {
76 compatible = "fsl,imx-capture-subsystem";
77 ports = <&ipu_csi0>, <&ipu_csi1>;
78 };
79
80 tzic: tz-interrupt-controller@fffc000 {
81 compatible = "fsl,imx53-tzic", "fsl,tzic";
82 interrupt-controller;
83 #interrupt-cells = <1>;
84 reg = <0x0fffc000 0x4000>;
85 };
86
87 clocks {
88 ckil {
89 compatible = "fixed-clock";
90 #clock-cells = <0>;
91 clock-frequency = <32768>;
92 };
93
94 ckih1 {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <22579200>;
98 };
99
100 ckih2 {
101 compatible = "fixed-clock";
102 #clock-cells = <0>;
103 clock-frequency = <0>;
104 };
105
106 osc {
107 compatible = "fixed-clock";
108 #clock-cells = <0>;
109 clock-frequency = <24000000>;
110 };
111 };
112
113 pmu: pmu {
114 compatible = "arm,cortex-a8-pmu";
115 interrupt-parent = <&tzic>;
116 interrupts = <77>;
117 };
118
119 usbphy0: usbphy-0 {
120 compatible = "usb-nop-xceiv";
121 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
122 clock-names = "main_clk";
123 #phy-cells = <0>;
124 status = "okay";
125 };
126
127 usbphy1: usbphy-1 {
128 compatible = "usb-nop-xceiv";
129 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
130 clock-names = "main_clk";
131 #phy-cells = <0>;
132 status = "okay";
133 };
134
135 soc: soc {
136 #address-cells = <1>;
137 #size-cells = <1>;
138 compatible = "simple-bus";
139 interrupt-parent = <&tzic>;
140 ranges;
141
142 sata: sata@10000000 {
143 compatible = "fsl,imx53-ahci";
144 reg = <0x10000000 0x1000>;
145 interrupts = <28>;
146 clocks = <&clks IMX5_CLK_SATA_GATE>,
147 <&clks IMX5_CLK_SATA_REF>,
148 <&clks IMX5_CLK_AHB>;
149 clock-names = "sata", "sata_ref", "ahb";
150 status = "disabled";
151 };
152
153 ipu: ipu@18000000 {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 compatible = "fsl,imx53-ipu";
157 reg = <0x18000000 0x08000000>;
158 interrupts = <11 10>;
159 clocks = <&clks IMX5_CLK_IPU_GATE>,
160 <&clks IMX5_CLK_IPU_DI0_GATE>,
161 <&clks IMX5_CLK_IPU_DI1_GATE>;
162 clock-names = "bus", "di0", "di1";
163 resets = <&src 2>;
164
165 ipu_csi0: port@0 {
166 reg = <0>;
167
168 ipu_csi0_from_parallel_sensor: endpoint {
169 };
170 };
171
172 ipu_csi1: port@1 {
173 reg = <1>;
174
175 ipu_csi1_from_parallel_sensor: endpoint {
176 };
177 };
178
179 ipu_di0: port@2 {
180 #address-cells = <1>;
181 #size-cells = <0>;
182 reg = <2>;
183
184 ipu_di0_disp0: endpoint@0 {
185 reg = <0>;
186 };
187
188 ipu_di0_lvds0: endpoint@1 {
189 reg = <1>;
190 remote-endpoint = <&lvds0_in>;
191 };
192 };
193
194 ipu_di1: port@3 {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 reg = <3>;
198
199 ipu_di1_disp1: endpoint@0 {
200 reg = <0>;
201 };
202
203 ipu_di1_lvds1: endpoint@1 {
204 reg = <1>;
205 remote-endpoint = <&lvds1_in>;
206 };
207
208 ipu_di1_tve: endpoint@2 {
209 reg = <2>;
210 remote-endpoint = <&tve_in>;
211 };
212 };
213 };
214
215 gpu: gpu@30000000 {
216 compatible = "amd,imageon-200.0", "amd,imageon";
217 reg = <0x30000000 0x20000>;
218 reg-names = "kgsl_3d0_reg_memory";
219 interrupts = <12>;
220 interrupt-names = "kgsl_3d0_irq";
221 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
222 clock-names = "core_clk", "mem_iface_clk";
223 };
224
225 aips1: bus@50000000 { /* AIPS1 */
226 compatible = "fsl,aips-bus", "simple-bus";
227 #address-cells = <1>;
228 #size-cells = <1>;
229 reg = <0x50000000 0x10000000>;
230 ranges;
231
232 spba-bus@50000000 {
233 compatible = "fsl,spba-bus", "simple-bus";
234 #address-cells = <1>;
235 #size-cells = <1>;
236 reg = <0x50000000 0x40000>;
237 ranges;
238
239 esdhc1: mmc@50004000 {
240 compatible = "fsl,imx53-esdhc";
241 reg = <0x50004000 0x4000>;
242 interrupts = <1>;
243 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
244 <&clks IMX5_CLK_DUMMY>,
245 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
246 clock-names = "ipg", "ahb", "per";
247 bus-width = <4>;
248 status = "disabled";
249 };
250
251 esdhc2: mmc@50008000 {
252 compatible = "fsl,imx53-esdhc";
253 reg = <0x50008000 0x4000>;
254 interrupts = <2>;
255 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
256 <&clks IMX5_CLK_DUMMY>,
257 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
258 clock-names = "ipg", "ahb", "per";
259 bus-width = <4>;
260 status = "disabled";
261 };
262
263 uart3: serial@5000c000 {
264 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
265 reg = <0x5000c000 0x4000>;
266 interrupts = <33>;
267 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
268 <&clks IMX5_CLK_UART3_PER_GATE>;
269 clock-names = "ipg", "per";
270 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
271 dma-names = "rx", "tx";
272 status = "disabled";
273 };
274
275 ecspi1: spi@50010000 {
276 #address-cells = <1>;
277 #size-cells = <0>;
278 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
279 reg = <0x50010000 0x4000>;
280 interrupts = <36>;
281 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
282 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
283 clock-names = "ipg", "per";
284 status = "disabled";
285 };
286
287 ssi2: ssi@50014000 {
288 #sound-dai-cells = <0>;
289 compatible = "fsl,imx53-ssi",
290 "fsl,imx51-ssi",
291 "fsl,imx21-ssi";
292 reg = <0x50014000 0x4000>;
293 interrupts = <30>;
294 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
295 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
296 clock-names = "ipg", "baud";
297 dmas = <&sdma 24 1 0>,
298 <&sdma 25 1 0>;
299 dma-names = "rx", "tx";
300 fsl,fifo-depth = <15>;
301 status = "disabled";
302 };
303
304 esdhc3: mmc@50020000 {
305 compatible = "fsl,imx53-esdhc";
306 reg = <0x50020000 0x4000>;
307 interrupts = <3>;
308 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
309 <&clks IMX5_CLK_DUMMY>,
310 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
311 clock-names = "ipg", "ahb", "per";
312 bus-width = <4>;
313 status = "disabled";
314 };
315
316 esdhc4: mmc@50024000 {
317 compatible = "fsl,imx53-esdhc";
318 reg = <0x50024000 0x4000>;
319 interrupts = <4>;
320 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
321 <&clks IMX5_CLK_DUMMY>,
322 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
323 clock-names = "ipg", "ahb", "per";
324 bus-width = <4>;
325 status = "disabled";
326 };
327 };
328
329 aipstz1: bridge@53f00000 {
330 compatible = "fsl,imx53-aipstz";
331 reg = <0x53f00000 0x60>;
332 };
333
334 usbotg: usb@53f80000 {
335 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
336 reg = <0x53f80000 0x0200>;
337 interrupts = <18>;
338 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
339 fsl,usbmisc = <&usbmisc 0>;
340 fsl,usbphy = <&usbphy0>;
341 status = "disabled";
342 };
343
344 usbh1: usb@53f80200 {
345 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
346 reg = <0x53f80200 0x0200>;
347 interrupts = <14>;
348 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
349 fsl,usbmisc = <&usbmisc 1>;
350 fsl,usbphy = <&usbphy1>;
351 dr_mode = "host";
352 status = "disabled";
353 };
354
355 usbh2: usb@53f80400 {
356 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
357 reg = <0x53f80400 0x0200>;
358 interrupts = <16>;
359 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
360 fsl,usbmisc = <&usbmisc 2>;
361 dr_mode = "host";
362 status = "disabled";
363 };
364
365 usbh3: usb@53f80600 {
366 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
367 reg = <0x53f80600 0x0200>;
368 interrupts = <17>;
369 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
370 fsl,usbmisc = <&usbmisc 3>;
371 dr_mode = "host";
372 status = "disabled";
373 };
374
375 usbmisc: usbmisc@53f80800 {
376 #index-cells = <1>;
377 compatible = "fsl,imx53-usbmisc";
378 reg = <0x53f80800 0x200>;
379 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
380 };
381
382 gpio1: gpio@53f84000 {
383 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
384 reg = <0x53f84000 0x4000>;
385 interrupts = <50 51>;
386 gpio-controller;
387 #gpio-cells = <2>;
388 interrupt-controller;
389 #interrupt-cells = <2>;
390 };
391
392 gpio2: gpio@53f88000 {
393 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
394 reg = <0x53f88000 0x4000>;
395 interrupts = <52 53>;
396 gpio-controller;
397 #gpio-cells = <2>;
398 interrupt-controller;
399 #interrupt-cells = <2>;
400 };
401
402 gpio3: gpio@53f8c000 {
403 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
404 reg = <0x53f8c000 0x4000>;
405 interrupts = <54 55>;
406 gpio-controller;
407 #gpio-cells = <2>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 };
411
412 gpio4: gpio@53f90000 {
413 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
414 reg = <0x53f90000 0x4000>;
415 interrupts = <56 57>;
416 gpio-controller;
417 #gpio-cells = <2>;
418 interrupt-controller;
419 #interrupt-cells = <2>;
420 };
421
422 kpp: kpp@53f94000 {
423 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
424 reg = <0x53f94000 0x4000>;
425 interrupts = <60>;
426 clocks = <&clks IMX5_CLK_DUMMY>;
427 status = "disabled";
428 };
429
430 wdog1: watchdog@53f98000 {
431 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
432 reg = <0x53f98000 0x4000>;
433 interrupts = <58>;
434 clocks = <&clks IMX5_CLK_DUMMY>;
435 };
436
437 wdog2: watchdog@53f9c000 {
438 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
439 reg = <0x53f9c000 0x4000>;
440 interrupts = <59>;
441 clocks = <&clks IMX5_CLK_DUMMY>;
442 status = "disabled";
443 };
444
445 gpt: timer@53fa0000 {
446 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
447 reg = <0x53fa0000 0x4000>;
448 interrupts = <39>;
449 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
450 <&clks IMX5_CLK_GPT_HF_GATE>;
451 clock-names = "ipg", "per";
452 };
453
454 srtc: rtc@53fa4000 {
455 compatible = "fsl,imx53-rtc";
456 reg = <0x53fa4000 0x4000>;
457 interrupts = <24>;
458 clocks = <&clks IMX5_CLK_SRTC_GATE>;
459 };
460
461 iomuxc: iomuxc@53fa8000 {
462 compatible = "fsl,imx53-iomuxc";
463 reg = <0x53fa8000 0x4000>;
464 };
465
466 gpr: iomuxc-gpr@53fa8000 {
467 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
468 reg = <0x53fa8000 0xc>;
469 };
470
471 ldb: ldb@53fa8008 {
472 #address-cells = <1>;
473 #size-cells = <0>;
474 compatible = "fsl,imx53-ldb";
475 reg = <0x53fa8008 0x4>;
476 gpr = <&gpr>;
477 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
478 <&clks IMX5_CLK_LDB_DI1_SEL>,
479 <&clks IMX5_CLK_IPU_DI0_SEL>,
480 <&clks IMX5_CLK_IPU_DI1_SEL>,
481 <&clks IMX5_CLK_LDB_DI0_GATE>,
482 <&clks IMX5_CLK_LDB_DI1_GATE>;
483 clock-names = "di0_pll", "di1_pll",
484 "di0_sel", "di1_sel",
485 "di0", "di1";
486 status = "disabled";
487
488 lvds-channel@0 {
489 #address-cells = <1>;
490 #size-cells = <0>;
491 reg = <0>;
492 status = "disabled";
493
494 port@0 {
495 reg = <0>;
496
497 lvds0_in: endpoint {
498 remote-endpoint = <&ipu_di0_lvds0>;
499 };
500 };
501
502 port@2 {
503 reg = <2>;
504 };
505 };
506
507 lvds-channel@1 {
508 #address-cells = <1>;
509 #size-cells = <0>;
510 reg = <1>;
511 status = "disabled";
512
513 port@1 {
514 reg = <1>;
515
516 lvds1_in: endpoint {
517 remote-endpoint = <&ipu_di1_lvds1>;
518 };
519 };
520
521 port@2 {
522 reg = <2>;
523 };
524 };
525 };
526
527 pwm1: pwm@53fb4000 {
528 #pwm-cells = <3>;
529 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
530 reg = <0x53fb4000 0x4000>;
531 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
532 <&clks IMX5_CLK_PWM1_HF_GATE>;
533 clock-names = "ipg", "per";
534 interrupts = <61>;
535 };
536
537 pwm2: pwm@53fb8000 {
538 #pwm-cells = <3>;
539 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
540 reg = <0x53fb8000 0x4000>;
541 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
542 <&clks IMX5_CLK_PWM2_HF_GATE>;
543 clock-names = "ipg", "per";
544 interrupts = <94>;
545 };
546
547 uart1: serial@53fbc000 {
548 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
549 reg = <0x53fbc000 0x4000>;
550 interrupts = <31>;
551 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
552 <&clks IMX5_CLK_UART1_PER_GATE>;
553 clock-names = "ipg", "per";
554 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
555 dma-names = "rx", "tx";
556 status = "disabled";
557 };
558
559 uart2: serial@53fc0000 {
560 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
561 reg = <0x53fc0000 0x4000>;
562 interrupts = <32>;
563 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
564 <&clks IMX5_CLK_UART2_PER_GATE>;
565 clock-names = "ipg", "per";
566 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
567 dma-names = "rx", "tx";
568 status = "disabled";
569 };
570
571 can1: can@53fc8000 {
572 compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
573 reg = <0x53fc8000 0x4000>;
574 interrupts = <82>;
575 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
576 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
577 clock-names = "ipg", "per";
578 status = "disabled";
579 };
580
581 can2: can@53fcc000 {
582 compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
583 reg = <0x53fcc000 0x4000>;
584 interrupts = <83>;
585 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
586 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
587 clock-names = "ipg", "per";
588 status = "disabled";
589 };
590
591 src: reset-controller@53fd0000 {
592 compatible = "fsl,imx53-src", "fsl,imx51-src";
593 reg = <0x53fd0000 0x4000>;
594 interrupts = <75>;
595 #reset-cells = <1>;
596 };
597
598 clks: ccm@53fd4000{
599 compatible = "fsl,imx53-ccm";
600 reg = <0x53fd4000 0x4000>;
601 interrupts = <0 71 0x04 0 72 0x04>;
602 #clock-cells = <1>;
603 };
604
605 gpio5: gpio@53fdc000 {
606 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
607 reg = <0x53fdc000 0x4000>;
608 interrupts = <103 104>;
609 gpio-controller;
610 #gpio-cells = <2>;
611 interrupt-controller;
612 #interrupt-cells = <2>;
613 };
614
615 gpio6: gpio@53fe0000 {
616 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
617 reg = <0x53fe0000 0x4000>;
618 interrupts = <105 106>;
619 gpio-controller;
620 #gpio-cells = <2>;
621 interrupt-controller;
622 #interrupt-cells = <2>;
623 };
624
625 gpio7: gpio@53fe4000 {
626 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
627 reg = <0x53fe4000 0x4000>;
628 interrupts = <107 108>;
629 gpio-controller;
630 #gpio-cells = <2>;
631 interrupt-controller;
632 #interrupt-cells = <2>;
633 };
634
635 i2c3: i2c@53fec000 {
636 #address-cells = <1>;
637 #size-cells = <0>;
638 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
639 reg = <0x53fec000 0x4000>;
640 interrupts = <64>;
641 clocks = <&clks IMX5_CLK_I2C3_GATE>;
642 status = "disabled";
643 };
644
645 uart4: serial@53ff0000 {
646 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
647 reg = <0x53ff0000 0x4000>;
648 interrupts = <13>;
649 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
650 <&clks IMX5_CLK_UART4_PER_GATE>;
651 clock-names = "ipg", "per";
652 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
653 dma-names = "rx", "tx";
654 status = "disabled";
655 };
656 };
657
658 aips2: bus@60000000 { /* AIPS2 */
659 compatible = "fsl,aips-bus", "simple-bus";
660 #address-cells = <1>;
661 #size-cells = <1>;
662 reg = <0x60000000 0x10000000>;
663 ranges;
664
665 aipstz2: bridge@63f00000 {
666 compatible = "fsl,imx53-aipstz";
667 reg = <0x63f00000 0x60>;
668 };
669
670 iim: efuse@63f98000 {
671 compatible = "fsl,imx53-iim", "fsl,imx27-iim", "syscon";
672 reg = <0x63f98000 0x4000>;
673 interrupts = <69>;
674 clocks = <&clks IMX5_CLK_IIM_GATE>;
675 };
676
677 uart5: serial@63f90000 {
678 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
679 reg = <0x63f90000 0x4000>;
680 interrupts = <86>;
681 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
682 <&clks IMX5_CLK_UART5_PER_GATE>;
683 clock-names = "ipg", "per";
684 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
685 dma-names = "rx", "tx";
686 status = "disabled";
687 };
688
689 tigerp: tigerp@63fa0000 {
690 compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp";
691 reg = <0x63fa0000 0x28>;
692 };
693
694 owire: owire@63fa4000 {
695 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
696 reg = <0x63fa4000 0x4000>;
697 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
698 status = "disabled";
699 };
700
701 ecspi2: spi@63fac000 {
702 #address-cells = <1>;
703 #size-cells = <0>;
704 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
705 reg = <0x63fac000 0x4000>;
706 interrupts = <37>;
707 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
708 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
709 clock-names = "ipg", "per";
710 status = "disabled";
711 };
712
713 sdma: dma-controller@63fb0000 {
714 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
715 reg = <0x63fb0000 0x4000>;
716 interrupts = <6>;
717 clocks = <&clks IMX5_CLK_SDMA_GATE>,
718 <&clks IMX5_CLK_AHB>;
719 clock-names = "ipg", "ahb";
720 #dma-cells = <3>;
721 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
722 };
723
724 cspi: spi@63fc0000 {
725 #address-cells = <1>;
726 #size-cells = <0>;
727 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
728 reg = <0x63fc0000 0x4000>;
729 interrupts = <38>;
730 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
731 <&clks IMX5_CLK_CSPI_IPG_GATE>;
732 clock-names = "ipg", "per";
733 status = "disabled";
734 };
735
736 i2c2: i2c@63fc4000 {
737 #address-cells = <1>;
738 #size-cells = <0>;
739 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
740 reg = <0x63fc4000 0x4000>;
741 interrupts = <63>;
742 clocks = <&clks IMX5_CLK_I2C2_GATE>;
743 status = "disabled";
744 };
745
746 i2c1: i2c@63fc8000 {
747 #address-cells = <1>;
748 #size-cells = <0>;
749 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
750 reg = <0x63fc8000 0x4000>;
751 interrupts = <62>;
752 clocks = <&clks IMX5_CLK_I2C1_GATE>;
753 status = "disabled";
754 };
755
756 ssi1: ssi@63fcc000 {
757 #sound-dai-cells = <0>;
758 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
759 "fsl,imx21-ssi";
760 reg = <0x63fcc000 0x4000>;
761 interrupts = <29>;
762 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
763 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
764 clock-names = "ipg", "baud";
765 dmas = <&sdma 28 0 0>,
766 <&sdma 29 0 0>;
767 dma-names = "rx", "tx";
768 fsl,fifo-depth = <15>;
769 status = "disabled";
770 };
771
772 audmux: audmux@63fd0000 {
773 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
774 reg = <0x63fd0000 0x4000>;
775 status = "disabled";
776 };
777
778 nfc: nand@63fdb000 {
779 compatible = "fsl,imx53-nand";
780 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
781 interrupts = <8>;
782 clocks = <&clks IMX5_CLK_NFC_GATE>;
783 status = "disabled";
784 };
785
786 ssi3: ssi@63fe8000 {
787 #sound-dai-cells = <0>;
788 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
789 "fsl,imx21-ssi";
790 reg = <0x63fe8000 0x4000>;
791 interrupts = <96>;
792 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
793 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
794 clock-names = "ipg", "baud";
795 dmas = <&sdma 46 0 0>,
796 <&sdma 47 0 0>;
797 dma-names = "rx", "tx";
798 fsl,fifo-depth = <15>;
799 status = "disabled";
800 };
801
802 fec: ethernet@63fec000 {
803 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
804 reg = <0x63fec000 0x4000>;
805 interrupts = <87>;
806 clocks = <&clks IMX5_CLK_FEC_GATE>,
807 <&clks IMX5_CLK_FEC_GATE>,
808 <&clks IMX5_CLK_FEC_GATE>;
809 clock-names = "ipg", "ahb", "ptp";
810 status = "disabled";
811 };
812
813 tve: tve@63ff0000 {
814 compatible = "fsl,imx53-tve";
815 reg = <0x63ff0000 0x1000>;
816 interrupts = <92>;
817 clocks = <&clks IMX5_CLK_TVE_GATE>,
818 <&clks IMX5_CLK_IPU_DI1_SEL>;
819 clock-names = "tve", "di_sel";
820 status = "disabled";
821
822 port {
823 tve_in: endpoint {
824 remote-endpoint = <&ipu_di1_tve>;
825 };
826 };
827 };
828
829 vpu: vpu@63ff4000 {
830 compatible = "fsl,imx53-vpu", "cnm,coda7541";
831 reg = <0x63ff4000 0x1000>;
832 interrupts = <9>;
833 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
834 <&clks IMX5_CLK_VPU_GATE>;
835 clock-names = "per", "ahb";
836 resets = <&src 1>;
837 iram = <&ocram>;
838 };
839
840 sahara: crypto@63ff8000 {
841 compatible = "fsl,imx53-sahara";
842 reg = <0x63ff8000 0x4000>;
843 interrupts = <19 20>;
844 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
845 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
846 clock-names = "ipg", "ahb";
847 };
848 };
849
850 ocram: sram@f8000000 {
851 compatible = "mmio-sram";
852 reg = <0xf8000000 0x20000>;
853 clocks = <&clks IMX5_CLK_OCRAM>;
854 };
855 };
856};
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include "imx53-pinfunc.h"
14#include <dt-bindings/clock/imx5-clock.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/input/input.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18
19/ {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 /*
23 * The decompressor and also some bootloaders rely on a
24 * pre-existing /chosen node to be available to insert the
25 * command line and merge other ATAGS info.
26 * Also for U-Boot there must be a pre-existing /memory node.
27 */
28 chosen {};
29 memory { device_type = "memory"; reg = <0 0>; };
30
31 aliases {
32 ethernet0 = &fec;
33 gpio0 = &gpio1;
34 gpio1 = &gpio2;
35 gpio2 = &gpio3;
36 gpio3 = &gpio4;
37 gpio4 = &gpio5;
38 gpio5 = &gpio6;
39 gpio6 = &gpio7;
40 i2c0 = &i2c1;
41 i2c1 = &i2c2;
42 i2c2 = &i2c3;
43 mmc0 = &esdhc1;
44 mmc1 = &esdhc2;
45 mmc2 = &esdhc3;
46 mmc3 = &esdhc4;
47 serial0 = &uart1;
48 serial1 = &uart2;
49 serial2 = &uart3;
50 serial3 = &uart4;
51 serial4 = &uart5;
52 spi0 = &ecspi1;
53 spi1 = &ecspi2;
54 spi2 = &cspi;
55 };
56
57 cpus {
58 #address-cells = <1>;
59 #size-cells = <0>;
60 cpu0: cpu@0 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a8";
63 reg = <0x0>;
64 clocks = <&clks IMX5_CLK_ARM>;
65 clock-latency = <61036>;
66 voltage-tolerance = <5>;
67 operating-points = <
68 /* kHz */
69 166666 850000
70 400000 900000
71 800000 1050000
72 1000000 1200000
73 1200000 1300000
74 >;
75 };
76 };
77
78 display-subsystem {
79 compatible = "fsl,imx-display-subsystem";
80 ports = <&ipu_di0>, <&ipu_di1>;
81 };
82
83 tzic: tz-interrupt-controller@0fffc000 {
84 compatible = "fsl,imx53-tzic", "fsl,tzic";
85 interrupt-controller;
86 #interrupt-cells = <1>;
87 reg = <0x0fffc000 0x4000>;
88 };
89
90 clocks {
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 ckil {
95 compatible = "fsl,imx-ckil", "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <32768>;
98 };
99
100 ckih1 {
101 compatible = "fsl,imx-ckih1", "fixed-clock";
102 #clock-cells = <0>;
103 clock-frequency = <22579200>;
104 };
105
106 ckih2 {
107 compatible = "fsl,imx-ckih2", "fixed-clock";
108 #clock-cells = <0>;
109 clock-frequency = <0>;
110 };
111
112 osc {
113 compatible = "fsl,imx-osc", "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <24000000>;
116 };
117 };
118
119 soc {
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "simple-bus";
123 interrupt-parent = <&tzic>;
124 ranges;
125
126 sata: sata@10000000 {
127 compatible = "fsl,imx53-ahci";
128 reg = <0x10000000 0x1000>;
129 interrupts = <28>;
130 clocks = <&clks IMX5_CLK_SATA_GATE>,
131 <&clks IMX5_CLK_SATA_REF>,
132 <&clks IMX5_CLK_AHB>;
133 clock-names = "sata", "sata_ref", "ahb";
134 status = "disabled";
135 };
136
137 ipu: ipu@18000000 {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 compatible = "fsl,imx53-ipu";
141 reg = <0x18000000 0x08000000>;
142 interrupts = <11 10>;
143 clocks = <&clks IMX5_CLK_IPU_GATE>,
144 <&clks IMX5_CLK_IPU_DI0_GATE>,
145 <&clks IMX5_CLK_IPU_DI1_GATE>;
146 clock-names = "bus", "di0", "di1";
147 resets = <&src 2>;
148
149 ipu_csi0: port@0 {
150 reg = <0>;
151 };
152
153 ipu_csi1: port@1 {
154 reg = <1>;
155 };
156
157 ipu_di0: port@2 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 reg = <2>;
161
162 ipu_di0_disp0: endpoint@0 {
163 reg = <0>;
164 };
165
166 ipu_di0_lvds0: endpoint@1 {
167 reg = <1>;
168 remote-endpoint = <&lvds0_in>;
169 };
170 };
171
172 ipu_di1: port@3 {
173 #address-cells = <1>;
174 #size-cells = <0>;
175 reg = <3>;
176
177 ipu_di1_disp1: endpoint@0 {
178 reg = <0>;
179 };
180
181 ipu_di1_lvds1: endpoint@1 {
182 reg = <1>;
183 remote-endpoint = <&lvds1_in>;
184 };
185
186 ipu_di1_tve: endpoint@2 {
187 reg = <2>;
188 remote-endpoint = <&tve_in>;
189 };
190 };
191 };
192
193 aips@50000000 { /* AIPS1 */
194 compatible = "fsl,aips-bus", "simple-bus";
195 #address-cells = <1>;
196 #size-cells = <1>;
197 reg = <0x50000000 0x10000000>;
198 ranges;
199
200 spba@50000000 {
201 compatible = "fsl,spba-bus", "simple-bus";
202 #address-cells = <1>;
203 #size-cells = <1>;
204 reg = <0x50000000 0x40000>;
205 ranges;
206
207 esdhc1: esdhc@50004000 {
208 compatible = "fsl,imx53-esdhc";
209 reg = <0x50004000 0x4000>;
210 interrupts = <1>;
211 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
212 <&clks IMX5_CLK_DUMMY>,
213 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
214 clock-names = "ipg", "ahb", "per";
215 bus-width = <4>;
216 status = "disabled";
217 };
218
219 esdhc2: esdhc@50008000 {
220 compatible = "fsl,imx53-esdhc";
221 reg = <0x50008000 0x4000>;
222 interrupts = <2>;
223 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
224 <&clks IMX5_CLK_DUMMY>,
225 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
226 clock-names = "ipg", "ahb", "per";
227 bus-width = <4>;
228 status = "disabled";
229 };
230
231 uart3: serial@5000c000 {
232 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
233 reg = <0x5000c000 0x4000>;
234 interrupts = <33>;
235 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
236 <&clks IMX5_CLK_UART3_PER_GATE>;
237 clock-names = "ipg", "per";
238 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
239 dma-names = "rx", "tx";
240 status = "disabled";
241 };
242
243 ecspi1: ecspi@50010000 {
244 #address-cells = <1>;
245 #size-cells = <0>;
246 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
247 reg = <0x50010000 0x4000>;
248 interrupts = <36>;
249 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
250 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
251 clock-names = "ipg", "per";
252 status = "disabled";
253 };
254
255 ssi2: ssi@50014000 {
256 #sound-dai-cells = <0>;
257 compatible = "fsl,imx53-ssi",
258 "fsl,imx51-ssi",
259 "fsl,imx21-ssi";
260 reg = <0x50014000 0x4000>;
261 interrupts = <30>;
262 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
263 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
264 clock-names = "ipg", "baud";
265 dmas = <&sdma 24 1 0>,
266 <&sdma 25 1 0>;
267 dma-names = "rx", "tx";
268 fsl,fifo-depth = <15>;
269 status = "disabled";
270 };
271
272 esdhc3: esdhc@50020000 {
273 compatible = "fsl,imx53-esdhc";
274 reg = <0x50020000 0x4000>;
275 interrupts = <3>;
276 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
277 <&clks IMX5_CLK_DUMMY>,
278 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
279 clock-names = "ipg", "ahb", "per";
280 bus-width = <4>;
281 status = "disabled";
282 };
283
284 esdhc4: esdhc@50024000 {
285 compatible = "fsl,imx53-esdhc";
286 reg = <0x50024000 0x4000>;
287 interrupts = <4>;
288 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
289 <&clks IMX5_CLK_DUMMY>,
290 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
291 clock-names = "ipg", "ahb", "per";
292 bus-width = <4>;
293 status = "disabled";
294 };
295 };
296
297 aipstz1: bridge@53f00000 {
298 compatible = "fsl,imx53-aipstz";
299 reg = <0x53f00000 0x60>;
300 };
301
302 usbphy0: usbphy@0 {
303 compatible = "usb-nop-xceiv";
304 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
305 clock-names = "main_clk";
306 status = "okay";
307 };
308
309 usbphy1: usbphy@1 {
310 compatible = "usb-nop-xceiv";
311 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
312 clock-names = "main_clk";
313 status = "okay";
314 };
315
316 usbotg: usb@53f80000 {
317 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
318 reg = <0x53f80000 0x0200>;
319 interrupts = <18>;
320 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
321 fsl,usbmisc = <&usbmisc 0>;
322 fsl,usbphy = <&usbphy0>;
323 status = "disabled";
324 };
325
326 usbh1: usb@53f80200 {
327 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
328 reg = <0x53f80200 0x0200>;
329 interrupts = <14>;
330 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
331 fsl,usbmisc = <&usbmisc 1>;
332 fsl,usbphy = <&usbphy1>;
333 dr_mode = "host";
334 status = "disabled";
335 };
336
337 usbh2: usb@53f80400 {
338 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
339 reg = <0x53f80400 0x0200>;
340 interrupts = <16>;
341 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
342 fsl,usbmisc = <&usbmisc 2>;
343 dr_mode = "host";
344 status = "disabled";
345 };
346
347 usbh3: usb@53f80600 {
348 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
349 reg = <0x53f80600 0x0200>;
350 interrupts = <17>;
351 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
352 fsl,usbmisc = <&usbmisc 3>;
353 dr_mode = "host";
354 status = "disabled";
355 };
356
357 usbmisc: usbmisc@53f80800 {
358 #index-cells = <1>;
359 compatible = "fsl,imx53-usbmisc";
360 reg = <0x53f80800 0x200>;
361 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
362 };
363
364 gpio1: gpio@53f84000 {
365 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
366 reg = <0x53f84000 0x4000>;
367 interrupts = <50 51>;
368 gpio-controller;
369 #gpio-cells = <2>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 };
373
374 gpio2: gpio@53f88000 {
375 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
376 reg = <0x53f88000 0x4000>;
377 interrupts = <52 53>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
382 };
383
384 gpio3: gpio@53f8c000 {
385 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
386 reg = <0x53f8c000 0x4000>;
387 interrupts = <54 55>;
388 gpio-controller;
389 #gpio-cells = <2>;
390 interrupt-controller;
391 #interrupt-cells = <2>;
392 };
393
394 gpio4: gpio@53f90000 {
395 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
396 reg = <0x53f90000 0x4000>;
397 interrupts = <56 57>;
398 gpio-controller;
399 #gpio-cells = <2>;
400 interrupt-controller;
401 #interrupt-cells = <2>;
402 };
403
404 kpp: kpp@53f94000 {
405 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
406 reg = <0x53f94000 0x4000>;
407 interrupts = <60>;
408 clocks = <&clks IMX5_CLK_DUMMY>;
409 status = "disabled";
410 };
411
412 wdog1: wdog@53f98000 {
413 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
414 reg = <0x53f98000 0x4000>;
415 interrupts = <58>;
416 clocks = <&clks IMX5_CLK_DUMMY>;
417 };
418
419 wdog2: wdog@53f9c000 {
420 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
421 reg = <0x53f9c000 0x4000>;
422 interrupts = <59>;
423 clocks = <&clks IMX5_CLK_DUMMY>;
424 status = "disabled";
425 };
426
427 gpt: timer@53fa0000 {
428 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
429 reg = <0x53fa0000 0x4000>;
430 interrupts = <39>;
431 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
432 <&clks IMX5_CLK_GPT_HF_GATE>;
433 clock-names = "ipg", "per";
434 };
435
436 iomuxc: iomuxc@53fa8000 {
437 compatible = "fsl,imx53-iomuxc";
438 reg = <0x53fa8000 0x4000>;
439 };
440
441 gpr: iomuxc-gpr@53fa8000 {
442 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
443 reg = <0x53fa8000 0xc>;
444 };
445
446 ldb: ldb@53fa8008 {
447 #address-cells = <1>;
448 #size-cells = <0>;
449 compatible = "fsl,imx53-ldb";
450 reg = <0x53fa8008 0x4>;
451 gpr = <&gpr>;
452 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
453 <&clks IMX5_CLK_LDB_DI1_SEL>,
454 <&clks IMX5_CLK_IPU_DI0_SEL>,
455 <&clks IMX5_CLK_IPU_DI1_SEL>,
456 <&clks IMX5_CLK_LDB_DI0_GATE>,
457 <&clks IMX5_CLK_LDB_DI1_GATE>;
458 clock-names = "di0_pll", "di1_pll",
459 "di0_sel", "di1_sel",
460 "di0", "di1";
461 status = "disabled";
462
463 lvds-channel@0 {
464 #address-cells = <1>;
465 #size-cells = <0>;
466 reg = <0>;
467 status = "disabled";
468
469 port@0 {
470 reg = <0>;
471
472 lvds0_in: endpoint {
473 remote-endpoint = <&ipu_di0_lvds0>;
474 };
475 };
476 };
477
478 lvds-channel@1 {
479 #address-cells = <1>;
480 #size-cells = <0>;
481 reg = <1>;
482 status = "disabled";
483
484 port@1 {
485 reg = <1>;
486
487 lvds1_in: endpoint {
488 remote-endpoint = <&ipu_di1_lvds1>;
489 };
490 };
491 };
492 };
493
494 pwm1: pwm@53fb4000 {
495 #pwm-cells = <2>;
496 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
497 reg = <0x53fb4000 0x4000>;
498 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
499 <&clks IMX5_CLK_PWM1_HF_GATE>;
500 clock-names = "ipg", "per";
501 interrupts = <61>;
502 };
503
504 pwm2: pwm@53fb8000 {
505 #pwm-cells = <2>;
506 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
507 reg = <0x53fb8000 0x4000>;
508 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
509 <&clks IMX5_CLK_PWM2_HF_GATE>;
510 clock-names = "ipg", "per";
511 interrupts = <94>;
512 };
513
514 uart1: serial@53fbc000 {
515 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
516 reg = <0x53fbc000 0x4000>;
517 interrupts = <31>;
518 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
519 <&clks IMX5_CLK_UART1_PER_GATE>;
520 clock-names = "ipg", "per";
521 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
522 dma-names = "rx", "tx";
523 status = "disabled";
524 };
525
526 uart2: serial@53fc0000 {
527 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
528 reg = <0x53fc0000 0x4000>;
529 interrupts = <32>;
530 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
531 <&clks IMX5_CLK_UART2_PER_GATE>;
532 clock-names = "ipg", "per";
533 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
534 dma-names = "rx", "tx";
535 status = "disabled";
536 };
537
538 can1: can@53fc8000 {
539 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
540 reg = <0x53fc8000 0x4000>;
541 interrupts = <82>;
542 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
543 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
544 clock-names = "ipg", "per";
545 status = "disabled";
546 };
547
548 can2: can@53fcc000 {
549 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
550 reg = <0x53fcc000 0x4000>;
551 interrupts = <83>;
552 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
553 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
554 clock-names = "ipg", "per";
555 status = "disabled";
556 };
557
558 src: src@53fd0000 {
559 compatible = "fsl,imx53-src", "fsl,imx51-src";
560 reg = <0x53fd0000 0x4000>;
561 #reset-cells = <1>;
562 };
563
564 clks: ccm@53fd4000{
565 compatible = "fsl,imx53-ccm";
566 reg = <0x53fd4000 0x4000>;
567 interrupts = <0 71 0x04 0 72 0x04>;
568 #clock-cells = <1>;
569 };
570
571 gpio5: gpio@53fdc000 {
572 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
573 reg = <0x53fdc000 0x4000>;
574 interrupts = <103 104>;
575 gpio-controller;
576 #gpio-cells = <2>;
577 interrupt-controller;
578 #interrupt-cells = <2>;
579 };
580
581 gpio6: gpio@53fe0000 {
582 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
583 reg = <0x53fe0000 0x4000>;
584 interrupts = <105 106>;
585 gpio-controller;
586 #gpio-cells = <2>;
587 interrupt-controller;
588 #interrupt-cells = <2>;
589 };
590
591 gpio7: gpio@53fe4000 {
592 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
593 reg = <0x53fe4000 0x4000>;
594 interrupts = <107 108>;
595 gpio-controller;
596 #gpio-cells = <2>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
599 };
600
601 i2c3: i2c@53fec000 {
602 #address-cells = <1>;
603 #size-cells = <0>;
604 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
605 reg = <0x53fec000 0x4000>;
606 interrupts = <64>;
607 clocks = <&clks IMX5_CLK_I2C3_GATE>;
608 status = "disabled";
609 };
610
611 uart4: serial@53ff0000 {
612 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
613 reg = <0x53ff0000 0x4000>;
614 interrupts = <13>;
615 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
616 <&clks IMX5_CLK_UART4_PER_GATE>;
617 clock-names = "ipg", "per";
618 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
619 dma-names = "rx", "tx";
620 status = "disabled";
621 };
622 };
623
624 aips@60000000 { /* AIPS2 */
625 compatible = "fsl,aips-bus", "simple-bus";
626 #address-cells = <1>;
627 #size-cells = <1>;
628 reg = <0x60000000 0x10000000>;
629 ranges;
630
631 aipstz2: bridge@63f00000 {
632 compatible = "fsl,imx53-aipstz";
633 reg = <0x63f00000 0x60>;
634 };
635
636 iim: iim@63f98000 {
637 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
638 reg = <0x63f98000 0x4000>;
639 interrupts = <69>;
640 clocks = <&clks IMX5_CLK_IIM_GATE>;
641 };
642
643 uart5: serial@63f90000 {
644 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
645 reg = <0x63f90000 0x4000>;
646 interrupts = <86>;
647 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
648 <&clks IMX5_CLK_UART5_PER_GATE>;
649 clock-names = "ipg", "per";
650 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
651 dma-names = "rx", "tx";
652 status = "disabled";
653 };
654
655 owire: owire@63fa4000 {
656 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
657 reg = <0x63fa4000 0x4000>;
658 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
659 status = "disabled";
660 };
661
662 ecspi2: ecspi@63fac000 {
663 #address-cells = <1>;
664 #size-cells = <0>;
665 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
666 reg = <0x63fac000 0x4000>;
667 interrupts = <37>;
668 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
669 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
670 clock-names = "ipg", "per";
671 status = "disabled";
672 };
673
674 sdma: sdma@63fb0000 {
675 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
676 reg = <0x63fb0000 0x4000>;
677 interrupts = <6>;
678 clocks = <&clks IMX5_CLK_SDMA_GATE>,
679 <&clks IMX5_CLK_SDMA_GATE>;
680 clock-names = "ipg", "ahb";
681 #dma-cells = <3>;
682 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
683 };
684
685 cspi: cspi@63fc0000 {
686 #address-cells = <1>;
687 #size-cells = <0>;
688 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
689 reg = <0x63fc0000 0x4000>;
690 interrupts = <38>;
691 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
692 <&clks IMX5_CLK_CSPI_IPG_GATE>;
693 clock-names = "ipg", "per";
694 status = "disabled";
695 };
696
697 i2c2: i2c@63fc4000 {
698 #address-cells = <1>;
699 #size-cells = <0>;
700 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
701 reg = <0x63fc4000 0x4000>;
702 interrupts = <63>;
703 clocks = <&clks IMX5_CLK_I2C2_GATE>;
704 status = "disabled";
705 };
706
707 i2c1: i2c@63fc8000 {
708 #address-cells = <1>;
709 #size-cells = <0>;
710 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
711 reg = <0x63fc8000 0x4000>;
712 interrupts = <62>;
713 clocks = <&clks IMX5_CLK_I2C1_GATE>;
714 status = "disabled";
715 };
716
717 ssi1: ssi@63fcc000 {
718 #sound-dai-cells = <0>;
719 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
720 "fsl,imx21-ssi";
721 reg = <0x63fcc000 0x4000>;
722 interrupts = <29>;
723 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
724 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
725 clock-names = "ipg", "baud";
726 dmas = <&sdma 28 0 0>,
727 <&sdma 29 0 0>;
728 dma-names = "rx", "tx";
729 fsl,fifo-depth = <15>;
730 status = "disabled";
731 };
732
733 audmux: audmux@63fd0000 {
734 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
735 reg = <0x63fd0000 0x4000>;
736 status = "disabled";
737 };
738
739 nfc: nand@63fdb000 {
740 compatible = "fsl,imx53-nand";
741 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
742 interrupts = <8>;
743 clocks = <&clks IMX5_CLK_NFC_GATE>;
744 status = "disabled";
745 };
746
747 ssi3: ssi@63fe8000 {
748 #sound-dai-cells = <0>;
749 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
750 "fsl,imx21-ssi";
751 reg = <0x63fe8000 0x4000>;
752 interrupts = <96>;
753 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
754 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
755 clock-names = "ipg", "baud";
756 dmas = <&sdma 46 0 0>,
757 <&sdma 47 0 0>;
758 dma-names = "rx", "tx";
759 fsl,fifo-depth = <15>;
760 status = "disabled";
761 };
762
763 fec: ethernet@63fec000 {
764 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
765 reg = <0x63fec000 0x4000>;
766 interrupts = <87>;
767 clocks = <&clks IMX5_CLK_FEC_GATE>,
768 <&clks IMX5_CLK_FEC_GATE>,
769 <&clks IMX5_CLK_FEC_GATE>;
770 clock-names = "ipg", "ahb", "ptp";
771 status = "disabled";
772 };
773
774 tve: tve@63ff0000 {
775 compatible = "fsl,imx53-tve";
776 reg = <0x63ff0000 0x1000>;
777 interrupts = <92>;
778 clocks = <&clks IMX5_CLK_TVE_GATE>,
779 <&clks IMX5_CLK_IPU_DI1_SEL>;
780 clock-names = "tve", "di_sel";
781 status = "disabled";
782
783 port {
784 tve_in: endpoint {
785 remote-endpoint = <&ipu_di1_tve>;
786 };
787 };
788 };
789
790 vpu: vpu@63ff4000 {
791 compatible = "fsl,imx53-vpu", "cnm,coda7541";
792 reg = <0x63ff4000 0x1000>;
793 interrupts = <9>;
794 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
795 <&clks IMX5_CLK_VPU_GATE>;
796 clock-names = "per", "ahb";
797 resets = <&src 1>;
798 iram = <&ocram>;
799 };
800
801 sahara: crypto@63ff8000 {
802 compatible = "fsl,imx53-sahara";
803 reg = <0x63ff8000 0x4000>;
804 interrupts = <19 20>;
805 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
806 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
807 clock-names = "ipg", "ahb";
808 };
809 };
810
811 ocram: sram@f8000000 {
812 compatible = "mmio-sram";
813 reg = <0xf8000000 0x20000>;
814 clocks = <&clks IMX5_CLK_OCRAM>;
815 };
816
817 pmu {
818 compatible = "arm,cortex-a8-pmu";
819 interrupts = <77>;
820 };
821 };
822};